yaxpeax-x86-1.2.2/.cargo_vcs_info.json0000644000000001360000000000100131400ustar { "git": { "sha1": "9a120cc76a49e5aadb0454f3ec4e89a6bff15a5d" }, "path_in_vcs": "" }yaxpeax-x86-1.2.2/.gitignore000064400000000000000000000000231046102023000137130ustar 00000000000000target/ Cargo.lock yaxpeax-x86-1.2.2/CHANGELOG000064400000000000000000000544231046102023000131520ustar 00000000000000## 1.2.2 * fix `hreset` reporting two operands, with a second operand of `Nothing`. this is not exactly a *bug*, there is in fact no second operand and libraries probably ought to handle `Nothing` identically to having no operand reported at all. but `yaxpeax-x86` intends to not report superfluous operands. ## 1.2.1 * fix incorrect register numbers used in `RegSpec::r12()` and `RegSpec::r13()` and smaller-size variants (thank you @tokatoka!) * fix synonyms of registers from `rex.w` on byte-size operands with register number <4 * adjust misleading docs on `register_class::B` and `register_class::RB`: being in register class `B` does not imply that there was no `rex.w` on the instruction - `rex.w` may have been present but the register number may have been <4 such that `B` was an appropriate register class anyway. * fix missing memory access size text for 128-bit keylocker instructions (would have text like "aesdec128kl xmm0, BUG [rcx]" rather than "..., m384b [rcx]". instructions are otherwise decoded correctly.) * fix incorrect register selection for `vpmovm2*` with `rex.b` set (would select registers "k8" through "k15", but should be masked down to "k0".."k7".) * fix incorrect register selection for `vpbroadcastm{b2q,w2d}` with `rex.b` set. basically the same bug as `vpmovm2*`; would select registers "k8".."k15", but should have been masked to "k0".."k7". * fix incorrect register selection for `vpmov*2m` with `rex.r` set. similar to above, except 64-bit only: in 32- and 16-bit modes, this case was and continues to be a `bound` instruction. in 64-bit mode, this would disassemble as a `vpmov*2m` with nonsense `k8..k15` selected. to real hardware, this bit sequence is an invalid instruction, and so it is now invalid to yaxpeax-x86 as well. * fix incorrect `RegisterBank` names in `long_mode`. in a previous reorganization register bank numbers were changed and the names were updated to match for `protected_mode` and `real_mode`, but `long_mode` was overlooked. ## 1.2.0 * fix incorrect old yaxpeax-arch version selection for ffi crates * address incorrect behavior of `Prefixes::cs()` * this "getter" would in fact set the selected segment to `cs`. it has never actually returned a `bool`, like other selector-checking methods on `Prefixes`. * add `Opcode::is_jcc`, `Opcode::is_setcc`, and `Opcode::is_cmovcc` helpers * discovered that `jna` and `jnb` are named what they are, instead of `jbe`/`jae` like their `setcc` an `cmovcc` counterparts. sorry. these will become `jbe` and `jae` in 2.x. * fix incorrect decode of a0/a1/a2/a3 mov register when rex.b is set (rex.b would select register 8, but the register is unconditionally A) * fix incorrect handling of some variants of gather instructions, vpgatherdq, vpgatherqq, vgatherdps, vgatherdpd, vgatherqps, vgatherqpd. errors were any of: * reporting qword loads when loads are dword-wide * reporting dword loads when loads are qword-wide * reporting ymm register sizes when sizes are actually xmm * reporting xmm register sizes when sizes are actually ymm * reporting index register as ymm when it is actually xmm * extended support for some newer instructions (pconfig, movdir64b) from just 64-bit to all decode modes * fix cvttsd2si/cvtsd2si reporting xmm registers as destinations in 64-bit mode * fix inconsistently-reported memory access size of vcvt{,t}{sd,si} across encodings and bitness * in some cases, instructions loading a single-precision float reported 8-byte loads * in some cases, instructions loading a double-precision float reported 4-byte loads * fix register sizes for lar/lsl * 16 bits are read from the source register, but x86 docs state that the source register is written as 16-bit, 32-bit, or 64-bit, as prefixes dictate. memory is always written as `word [addr]`, which was correct before and remains the case. ## 1.1.5 * fix several typos across crate docs - thank you Bruce! (aka github user waywardmonkeys) * optimizations (mostly code motion) for hot codepaths - large `match`-based decode tables have been outlined to 256-entry arrays. this makes for slicely nicer inlining in `read_with_annotations`. - vex/evex decoding in 64-bit decoding now shares more code. this seems to aid code cache friendliness when prefixes must be read. - added a fast path for operand reading for the more-likely cases of [64-bit]: {0x66,rex}{,0x0f-} [32-bit]: {0x66}{,0x0f-} [16-bit]: {0x66}{,0x0f-} in particular, this avoids checking for instruction length overflows and some bounds checks when we aren't handling a pessimal case of many-prefixed instructions. if an instruction has multiple prefixes, decoders fall back to normal read-in-a-loop-until-length-limit-reached decoding. * `Makefile` at the crate root now exercises `yaxpeax-x86` builds and tests under: - default features (fmt, std) - no-std + fmt - no-std and no-fmt * fix several issues prohibiting builds of the crate with no-std +fmt configurations; the required Display impl for field annotation would simply not compile in no-fmt builds. it is now a minimal implementation to comply with the goals of `no-fmt`: "avoid as much extra code and data for formatting instructions as possible". two dozen bytes for a likely-DCE'd codepath should be ok. * adjust test structure so that exhaustive tests can be `#[ignored]` and explicitly run anyway for completeness. this means the ignored at&t tests now are both ignored and appear to succeed when run. * support `9a` encoding of `callf` with absolute segment/address operand - this encoding is only present in 32-bit and 16-bit modes ## 1.1.4 * fix reachable unreachable under `DisplayStyle::C` in 64-, 32-, and 16-bit modes * add fuzz target to cover `DisplayStyle::C` formatter for 64-, 32-, and 16-bit modes ## 1.1.3 * fix reachable unsoundness via `RegSpec` helper functions - helpers should only permit creating valid `RegSpec` structs, but three helpers would permit out-of-range register numbers; `mask` registers in 16- and 32-bit modes, and `rex byte` registers in 64-bit modes. - when displaying an invalid `RegSpec`, for some out-of-range mask registers, the displayed register name could be chosen as arbitrary const data interpreted as a pointer/length pair * fix incorrect (non-present!) memory size for f30f1e-style `nop`. - this would decode without error, but produce an instruction with memory operand and memory size of `0`. if formatted, yaxpeax-x86 panics. * add in-tree `cargo fuzz` targets for decoding and displaying instructions. neither of these operations should ever panic. * fix incorrect disassembler used in x86-16 doc comments and thank you to @5225225 (https://github.com/5225225) for the bug reports handled in 1.1.2 and 1.1.3, as well as the nudge to start using `cargo fuzz`. ## 1.1.2 * fix panic when evex instructions with compressed displacements are decoded in debug builds ## 1.1.1 * support `endbr64` and `endbr32` - these are interpretations of `nop` (`0f1e` wide nop), so the only issue with for users <1.1.1 will be `yaxpeax-86` decoding `nop` instead. * export `InstructionDisplayer` this fixes an issue where crate docs would have dead links for the return value of public APIs. it also allows callers to write name of what `display_with` returns in their code, which hopefully isn't too useful but shouldn't be impossible. ## 1.1.0 * implement `AnnotatingDecoder` from `yaxpeax-arch=0.2.6` and later. this is a relatively involved addition. for rustc reasons, there are several additional `inline(always)` attributes applied to keep non-annotating decoder calls yielding the same generated code (and performance) as before. annotations are produced for much but not all of 16-, 32-, and 64-bit x86, describing prefixes, opcodes, operand encoding, and for more common instructions, operand encoding as well. descriptions provided are described by the `FieldDescription` struct in all architectures. `id` generally matches some kind of parse order for the instruction, typically the order that `yaxpeax-x86` considers bit fields in decoding an instruction. prefixes will have lower id than opcodes, opcodes will have lower id than operands, immediates will have the highest id due to being last values read in an instruction. between prefixes, opcodes, and operands, "Boundary" field descriptions are reported as a hint to library clients that a logical grouping of descriptions has ended. * `pub const fn` builders for all general-purpose registers, segment registers, and ip/flags registers. - this corrects a spotty and inconsistent set of builders filled in on-demand. * `DisplayStyle::Intel` now shows relative offsets as `$+0xXX`, rather than `0xXX`. - this corrects an ambiguity with instructions like `jz 0x1234`, where `jz` on x86 is _only_ relative branches, but the displayed syntax is ambiguous about being a relative or absolute address. - `DisplayStyle::Intel` is how `impl Display for Instruction` works, so typical `Display` use is also fixed. * `push`, `pop`, `call`, and `ret` now report `mem_size` in all cases. - earlier, these instructions only reported a `mem_size` if their operand was a memory access. - for `call`, in 32- and 16-bit modes the reported memory size may describe the *read*, not the corresponding write of pushing `{e}ip` to the stack. documentation has been added to `mem_size` more specifically describing this circumstance. * correct `rex.b` incorrectly applying to the `*ax` register - `4f91` is `xchg rax, r9`, not `xchg r8, r9`. * correct `nop` incorrectly ignoring `rex.b` - `4190` is `xchg rax, r8`, not `nop`. * `DisplayStyle::C` now has rules to nicely display `jCC`, `jmp`, `call`, `loop*`, and `j*cxz` instructions. ## 1.0.4 in 64-, 32-, and 16-bit modes: * fix incorrect decoding of `scas`; memory access is through `*di` not `*si`. * fix incorrect segment register for `scas` memory operand; `es` segment is always used. * fix incorrect decoding of some 67-prefixed string instructions: `movs`, `scas`, `lods`, `stos`, `cmps`. - a 67-prefix selects an alternate addressing mode. in 64-bit mode, this selects 32-bit registers for addressing, 32-bit selects 16-bit registers, and 16-bit selects 32-bit registers. the decoder had ignored the 67 prefix on these instructions. in 32- and 16-bit modes: * fix incorrect decoding of 16-bit memory accesses with modrm where mod=00 and mmm=110. - the memory access from this modrm is a disp16 memory access, which the decoder reports. the decoder would then not read the subsequent 16-bit displacement. this would typically result in a `Displacement(0)` operand, and incorrect following instructions. ## 1.0.3 * fix a few broken doc links, added example of yaxpeax-x86 usage through yaxpeax-arch traits ## 1.0.2 * remove a stale line from README ## 1.0.1 * fix a broken docs link in README ## 1.0.0 * `avx512` support * `avx2` support * `avx` support * real-mode (x86_16) support * ffi-friendly packaging of decoders for 16-bit, 32-bit, and multi-arch uses * added `Instruction::mem_size()` to query the size of an instruction's memory access * `xacquire`/`xrelease` support * `AMD` `sev_snp` support * `pconfig`/Total Memory Encryption support * `Intel` `keylocker` support * removed `MOVSX_b`, `MOVSX_w`, `MOVZX_b`, and `MOVZX_w` - these differentiations are now described by `mem_size` and the `MOVSX`/`MOVZX` opcodes generally * `PartialEq` impl for `Instruction` and all contained structures * expose more details of an instruction's prefixes, and which prefixes are actually present on the instruction ## 0.2.2 * fix rendering error in `ShowContextual` impl with `&[Option]` overrides - would in some circumstances incorrectly print stale data if an `Instruction` was reused for decoding. no impact on logical correctness, but certainly made for awkward disassembly in some cases. ## 0.2.1 * update `yaxpeax-arch` dep to 0.0.5 - no external-facing changes for this, but `yaxpeax-arch 0.0.5` uses `crossterm` for cross-platform terminal coloring * clean up a few warnings that made it into 0.2.0? ## 0.2.0 ### features! * fuzz against mishegos and fix many bugs that made obvious - duplicate and redundant f2, f3, and 66 prefixes on 0f-type opcodes are now handled "right", assuming xed as a source of truth. almost all of these cases are undefined by the intel and AMD manuals, but it seems unlikely that capstone is correct with respect to cpu interpretation while xed is incorrect. * public `enum`s are now `#[non_exhaustive]`. these are `Operand`, `Opcode`, and `DecodeError`. - `Operand` is not expected to vary, but might. - `Opcode` will grow new variants for every extension. - `DecodeError` will probably not change, but no guarantees. * add a notion of display styles for instructions, see `Instruction::display_with`. currently there are two styles: - `DisplayStyle::Intel` produces intel-like syntax for instructions - `DisplayStyle::C` produces C pseudocode-ish syntax for instructions - as an example, `xor eax, [rax]` is rendered as `eax ^= [rax]`. - `DisplayStyle::Att` is one potential future style, but not yet implemented * `fmt`-related code and the `display` module are now optional on the `fmt` feature - this is to support minimal builds for decoders in non-formatting circumstances. `yaxpeax-x86` long mode is still 65kb there. * improved packaging of ffi-friendly bindings in `ffi/` - architectures have standalone libraries for each of `long_mode`, `protected_mode`, and `real_mode` (last still to be implemented) - improved `ffi/` build instructions to describe how to build minimal-size `.so` and `.a` archives for linking * `ffi/multiarch` is intended to be a single package for all architectures, but currently does not fulfil this role ### decode fixes * segment prefixes (`cs`, `ds`, `ss`, `es`) are now properly ignored in long mode * `lock xchg` now decodes correctly (operands were in reversed order and so memory "destinations" were treated as memory sources) * some missing sse instructions are now supported (`blendps`, `blendpd`, `pclmulqdq`) * some missing avx instructions are now supported (`vorpd`, `vorps`, `vandpd`, `vandps`, `vandnpd`, `vandnps`, `vpmaxuw`) * prefetch instructions with register operand are interpreted as `nop`, not `#UD` * `mov` to control or debug registers that are statically known to `#UD` now produce `DecodeError::InvalidOperand` * `salc` is now rejected. it was accepted on a whim, and i am fickle. - realistically, this should be behind a decoder flag and accepted by default, but this makes fuzzing somewhat easier and isn't an instruction you'd expect to see in a modern x86 binary. see the summary at the end of this section for some thoughts on decoder flags... ### new ISA extension support! * 3dnow is 3d-supported-now * `sse4a` is now supported * `gfni` extensions are now supported * `ptwrite` extensions are now supported * `cet` (`c`ontrol-flow `e`nforcement `t`echnology) extensions are now supported * `invpcid` extensions are now supported * `tdx` extensions are now supported * `waitpkg` extensions are now supported * `uintr` extensions are now supported * `tsxldtrk` extensions are now supported * `ud0`, `ud1`, and `ud2` are now supported - `ud2e` which was never real, is actually `ud1` * `movdir` extensions are now supported * `key locker` extensions are now supported * `enqcmd` extensions are now supported ### architecture support * all above changes apply both to `long_mode` and `protected_mode`. `protected_mode` may accept some 64bit-only instructions incorrectly. beware. ### thoughts? folks, i'm out of feature bits in `InstDecoder`. there are too dang many x86 extensions. in the happy case, rustc knows that the provided decoder always compares equal to `InstDecoder::default()` so it can be made an arbitrarily large byte array. but i continue to be in awe of how much they put in the computer. as things stand, new extensions are not categorized into `InstDecoder` flags, but since there is a way to implement additional bits without causing overhead in the happy path, this feature will probably continue being supported in the future. ### unsafe there are still a handful of `unsafe {}` uses in `yaxpeax-x86` for performance reasons. i tried removing arms in matches by making the last meaningful arm, often something like: ``` 8 => { /* handle 8-byte operand */ } ``` into a general catchall arm and deleting the `unreachable_unchecked`, like: ``` _ => { /* handle 8-byte operand */ } ``` but this also caused a ~5% regression in performance. this makes sense, since `unreachable_unchecked` is stronger in saying that other values (`3`, `5`, `6`, `7`, ...) will _not_ occur, but `_` doesn't disallow them and likely produces jump tables for no good reason. maybe this can be solved some other way, one day... ## 0.1.5 * fix several issues around 0f01* opcode decoding; - AMD-only `monitorx`, `mwaitx`, `clzero`, and `rdpru` are now supported - `swapgs` is invalid in non-64-bit modes - `rdpkru` and `wrpkru` were incorrectly decoded when modrm bits were not `11` * small performance tweaks. read_imm_signed is now inline(always) and some pre-decode initialization is a bit better-packed * `xchg {r,e,}ax, reg` was not supported! it's supported now. ## 0.1.4 * [long mode only]: fix decoding of rex-prefixed modrm+sib operands selecting index 0b100 and base 0b101 - for memory operands with a base, index, and displacement either the wrong base would be selected (register number ignored, so only `*ax` or `r8*` would be reported), or yaxpeax-x86 would report a base register is present when it is not (`RegIndexBaseScaleDisp` when the operand is actually `RegScaleDisp`) thank you to Evan Johnson for catching and reporting this bug! ## 0.1.3 * fix 0x80-opcode instructions not having an opcode - this meant that for example `lock xorb [rax], 0` would decode as invalid ## 0.1.2 * expose constructors for `RegSpec` in both `long_mode` and `protected_mode` * expose a const `RegSpec::RIP` - most useful for matching `Operand::RegDisp(RegSpec::RIP, disp)` in patterns, really ## 0.1.1 * add `long_mode::register_class` and `protected_mode::register_class` where `RegisterClass` constants for each register class are defined. - without these, the only way to distinguish register classes would be string compares. bad. sorry! ## 0.1.0 * port `long_mode` improvements to `protected_mode` decoder - real mode will wait until another day * support undocumented instruction `salc` * fix segment registers being numbered wrong - this is relevant only for mov to/from segments * support x86_32 `push ``/`pop ` * support x86_32 `pusha`/`popa` * support x86_32 BCD instructions - for `aam`/`aad`, the undocumented `amx` and `adx` forms are used in all cases, including when the base is 10 * begin some proper documentation for public items /!\ BREAKING CHANGES /!\ * `RegisterBank` is no longer public. `RegisterClass` should be a suitable replacement, accessible via `reg.class()`, with the register class name available by `reg.class().name`, and size available by `reg.class().width()`. `reg.width()` still works, and just forwards to `reg.class().width()`. * the field `opcode` of `Instruction` is no longer public. it can now be accessed by `inst.opcode()`. ## 0.0.15 * the `x87` instruction set is now fully supported - textual disassembly differs slightly from other decoders in that yaxpeax-x86 does not prefer using `st` in place of `st(0)` * do not decode `into` in 64-bit mode * support `vmread`, `vmwrite` * support `iret`/`iretd`/`iretq` * support `enter` * support `cmc` and `int1` * support `loopz`, `loopnz`, `jecxz` * support `maskmovq`, `movnti`, and `movntq` - this brings full support to non-vex-coded x86 instructions * reject excessively-long instructions * reject reg-reg encodings where instructions forbid those operands * correctly handle `mov [0xoffset], ax` and `mov ax, [0xoffset]` - offset had been read with incorrect size * `vpsrlw`, `vpermq`, `vpminsq`, `vpsrlq`, `vextractf128`, `vinserti128` * reorganize likely decoding paths for a smidge more speed ## 0.0.14 * `netburst` supported `cmpxchg16b` from its first x86_64 incarnation. since no uarch in `long_mode` had declared `cmpxchg16b` support, no uarch-specific Intel decoder supported `cmpxchg16b`. ## 0.0.13 * the Intel microarchitecture is named `Penryn`, not `Peryn`. ## 0.0.12 * fix improper decode of `sib` memory operand when `rex.x` is set and index is `0b100` - functionally: instructions which should have had a memory operand like `[rax + r12 + disp]` were missing `r12` * add instruction set extensions: `SHA`, `BMI1`, `BMI2`, `XSAVE`, `RDRAND`, `RDSEED`, `CMPXCHG{8,16}B` `ADX`, `SVM`, `MOVBE`, `PREFETCHW`, `TSX`, and `F16C` * add `RDFSBASE`, `RDGSBASE`, `WRFSBASE`, `WRGSBASE` * builders for per-uarch x86_64 instruction decoders, see `yaxpeax_x86::long_mode::uarch::{intel, amd}` * builders for per-uarch x86_32 instruction decoders, see `yaxpeax_x86::protected_mode::uarch::{intel, amd}` ## 0.0.11 * fix mis-named 'cbd' instruction, which should be 'cwd' * add `Operand::width` to query the width of an x86 access - this is wrong for many memory operands, which require deeper changes * bump `yaxpeax-arch` to 0.0.4, which yields a breaking change in `Self::Unit` of `LengthedInstruction * `Prefixes::rep` is now public, allowing users to query if a decoded instruction has a rep prefix ## 0.0.10 same as 0.0.9, but with a warning fixed. ## 0.0.9 added `protected_mode` for 32-bit instruction decoding. BCD instructions not yet supported. ## 0.0.8 same as 0.0.7, but with a readme in the crates.io page. ## 0.0.7 `sse` and `sse2` support are mostly complete. `jmp reg` erroneously decoded to 32-bit registers without `rex.w`. `callf` could erroneously decode as having a register operand. more comprehensive, if yet insufficiently tested, avx decoding. support `vmclear` and `vmxon`, vmx still incomplete. ## 0.0.6 addressing modes using a sib byte with displacement != 0 were wrongly reported as having no displacement. ## 0.0.5 history basically starts here. * impl Ord and PartialOrd on RegSpec and RegisterBank * `RegSpec::name` to get `&'static str` labels for registers * support `in` and `out` instructions ## 0.0.4 - 0.0.2 seriously stop, just don't use these versions just bumps to use newer `yaxpeax-arch` since this is all wildly unstable yaxpeax-x86-1.2.2/Cargo.toml0000644000000030220000000000100111330ustar # THIS FILE IS AUTOMATICALLY GENERATED BY CARGO # # When uploading crates to the registry Cargo will automatically # "normalize" Cargo.toml files for maximal compatibility # with all versions of Cargo and also rewrite `path` dependencies # to registry (e.g., crates.io) dependencies. # # If you are reading this file be aware that the original Cargo.toml # will likely look very different (and much more reasonable). # See Cargo.toml.orig for the original contents. [package] edition = "2018" name = "yaxpeax-x86" version = "1.2.2" authors = ["iximeow "] description = "x86 decoders for the yaxpeax project" readme = "README.md" license = "0BSD" repository = "http://git.iximeow.net/yaxpeax-x86/" [profile.bench] opt-level = 3 lto = true [profile.release] opt-level = 3 lto = true [[test]] name = "test" path = "test/test.rs" [[bench]] name = "bench" path = "test/bench.rs" [dependencies.cfg-if] version = "1.0.0" [dependencies.num-traits] version = "0.2" default-features = false [dependencies.serde] version = "1.0" optional = true [dependencies.serde_derive] version = "1.0" optional = true [dependencies.serde_json] version = "1.0" optional = true [dependencies.yaxpeax-arch] version = "0.2.7" features = [] default-features = false [dev-dependencies.rand] version = "0.8.4" [features] capstone_bench = [] colors = ["yaxpeax-arch/colors"] default = [ "std", "colors", "use-serde", "fmt", ] fmt = [] std = ["yaxpeax-arch/std"] use-serde = [ "yaxpeax-arch/use-serde", "serde", "serde_derive", ] yaxpeax-x86-1.2.2/Cargo.toml.orig000064400000000000000000000023171046102023000146220ustar 00000000000000[package] name = "yaxpeax-x86" version = "1.2.2" authors = [ "iximeow " ] license = "0BSD" repository = "http://git.iximeow.net/yaxpeax-x86/" description = "x86 decoders for the yaxpeax project" readme = "README.md" edition = "2018" [dependencies] yaxpeax-arch = { version = "0.2.7", default-features = false, features = [] } "num-traits" = { version = "0.2", default-features = false } "serde" = { version = "1.0", optional = true } "serde_json" = { version = "1.0", optional = true } "serde_derive" = { version = "1.0", optional = true } "cfg-if" = "1.0.0" [dev-dependencies] rand = "0.8.4" [[test]] name = "test" path = "test/test.rs" [[bench]] name = "bench" path = "test/bench.rs" [profile.bench] opt-level = 3 lto = true [profile.release] opt-level = 3 lto = true [features] default = ["std", "colors", "use-serde", "fmt"] # opt-in for some apis that are really much nicer with String std = ["yaxpeax-arch/std"] # feature for formatting instructions and their components fmt = [] use-serde = ["yaxpeax-arch/use-serde", "serde", "serde_derive"] colors = ["yaxpeax-arch/colors"] # This enables some capstone benchmarks over the same # instruction bytes used to bench this code. capstone_bench = [] yaxpeax-x86-1.2.2/LICENSE000064400000000000000000000011731046102023000127370ustar 00000000000000Copyright (c) 2020 iximeow Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted. THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. yaxpeax-x86-1.2.2/Makefile000064400000000000000000000004651046102023000133750ustar 00000000000000test: test-fast test-exhaustive test-fast: test-std test-no-std test-fmt-no-std test-exhaustive: cargo test -- --ignored cargo test --no-default-features -- --ignored test-std: cargo test test-no-std: cargo test --no-default-features test-fmt-no-std: cargo test --no-default-features --features "fmt" yaxpeax-x86-1.2.2/README.md000064400000000000000000000146501046102023000132150ustar 00000000000000## yaxpeax-x86 [![crate](https://img.shields.io/crates/v/yaxpeax-x86.svg?logo=rust)](https://crates.io/crates/yaxpeax-x86) [![documentation](https://docs.rs/yaxpeax-x86/badge.svg)](https://docs.rs/yaxpeax-x86) x86 decoders implemented as part of the yaxpeax project, implementing traits provided by `yaxpeax-arch`. Rust users of this library will either want to use the [quick and dirty APIs](https://docs.rs/yaxpeax-x86/latest/yaxpeax_x86/long_mode/struct.InstDecoder.html#method.decode_slice), or more [generic decode interfaces](https://docs.rs/yaxpeax-arch/latest/yaxpeax_arch/trait.Decoder.html#method.decode) from `yaxpeax-arch` - appropriate when mixing `yaxpeax-x86` usage with other `yaxpeax` decoders, such as `yaxpeax-arm`. examples of both styles are provided [in the documentation](https://docs.rs/yaxpeax-x86/). the `ffi/` directory provides a repackaging of `yaxpeax-x86` suitable for use by non-Rust callers, such as C or C++. see the `examples` directory for FFI usage of this library. ### features * `#[no_std]` * configurable instruction set extensions * very fast * pretty small? ### `#[no_std]` the decoders provided by `yaxpeax-x86` are designed to be usable in a `no_std` setting, and does so by default. to build `yaxpeax_x86` without `std`, add the parameter `default-features = false` to your `yaxpeax-x86` dependency; the [ffi packaging](https://git.iximeow.net/yaxpeax-x86/tree/ffi) of `yaxpeax_x86` does this and builds without the Rust standard library as well. serde can be enabled without `std`, but json serialization/deserialization [need some careful attention](https://serde.rs/no-std.html) in that mode. as well as the `colors` feature to render instructions with default (eg terminal-friendly) syntax highlighting. ### instruction set extensions `yaxpeax-x86` decoders provide the option to specify what [instruction set extensions](http://git.iximeow.net/yaxpeax-x86/tree/src/long_mode/mod.rs#n1297) are eligible when decoding, to support decoding x86 instructions as understood by a particular microarchitecture. the default impls of decoders in `yaxpeax_x86` take an optimistic approach to decoding and assumes all feature sets are available, as well as accepting both intel-specific and amd-specific quirks around undefined encodings. yaxpeax-x86 decodes long-mode (`amd64`/`x86_64`), protected-mode (`x86`/`x86_32`), and real-mode (`x86_16`) instructions. the most part, ISA extensions decode equivalently across modes; this is the full list of extensions that are supported: `3dnow`\*, `sse`\*, `sse2`\*, `sse3`, `ssse3`, `sse4.1`, `sse4.2`, `sse4a`, `avx`, `avx2`, `avx512`\*\*, `syscall`, `cmpxchg16b`, `fma3`, `aesni`, `popcnt`, `rdrand`, `xsave`, `sgx`, `monitor`, `movbe`, `sgx`, `bmi1`, `bmi2`, `invpcid`, `mpx`, `adx`, `clflushopt`, `pcommit`, `sha`, `gfni`, `pclmulqdq`, `rdtscp`, `abm`, `xop`, `skinit`, `tbm`, `svm`, `f16c`, `fma4`, `tsx`, `enqcmd`\*\*\*, `uintr`\*\*\*, `keylocker`\*\*\*, `store_direct`\*\*\*, `cet`\*\*\*, `sev/snp`\*\*\* \*: `3dnow`, `sse`, and `sse2` are non-optional in `x86_64`, so it is not permitted to construct a decoder that rejects them. `x86_32` and `x86_16` could have features to reject these instructions for true `8086` and `i386` compatibility, but currently do not. \*\*: `avx512` is fully supported, but decoders rejecting subgroups of the `avx512` family are not. if you need granular `avx512` compatibility controls, please file an issue. \*\*\*: i ran out of space for feature bits. `InstDecoder` is currently a `u64` and all 64 bits are used for x86 features mapping to `cpuid` bits. supporting these as optional instructions would require growing this to a pair of `u64`. since the typical case is to decode everything, these are decoded regardless of `InstDecoder` settings. growing `InstDecoder` to an `u128` is likely acceptable, but has not yet been profiled. ### very fast when hooked up to [`disas-bench`](https://github.com/iximeow/disas-bench#results), `yaxpeax_x86::long_mode` has shown roughly 250mb/s decode throughput and on some hardware is the fastest software x86 decoder available. the likely path through the decoder, through `::decode_into``, is an average of 58 cycles on a zen2 core. while there is an in-repo benchmark, i've decided it's so unrealistic as to be unuseful, and prefer `disas-bench` until it can be made more informative. ### pretty small? `yaxpeax_x86::long_mode` built on its own is around 143kb of code and data. with data for instruction formatting, this grows to 249kb. while code size can be shrunk some, most of the crate is a few lookup tables - the hot path through `yaxpeax-x86`'s decode logic stays in functions coming out to ~5 kilobytes of code, and lots of supporting logic for less likely instructions. `yaxpeax_x86` may be the smallest library for tasks focused entirely on decoding and instruction formatting, but this crate doesn't have extensive testing to that end. ### mirrors the canonical copy of `yaxpeax-x86` is at [https://git.iximeow.net/yaxpeax-x86/](https://git.iximeow.net/yaxpeax-x86/). `yaxpeax-x86` is also mirrored on GitHub at [https://www.github.com/iximeow/yaxpeax-x86](https://www.github.com/iximeow/yaxpeax-x86). ### unsafety `yaxpeax_x86` makes regular use of `unsafe { unreachable_unchecked(); }` and occasional use of `unsafe { _.get_unchecked() }` for purely performance reasons. `yaxpeax_x86` is fuzzed via `mishegos` and has passed multiple days of fuzzing without issue. ### changelog a changelog across crate versions is maintained in the `CHANGELOG` file located in the repo, as well as [online](https://git.iximeow.net/yaxpeax-x86/tree/CHANGELOG). ### contributing unfortunately, pushing commits to the canonical repo at `git.iximeow.net` is impossible. if you'd like to contribute - thank you! - please send patches to emails iximeow has committed under or by opening PRs against the [GitHub mirror](https://www.github.com/iximeow/yaxpeax-x86). both remotes are kept in sync. ### see also [`iced`](https://github.com/0xd4d/iced) is another very good `x86_64` decoder, also written in rust. it provides additional information about instruction semantics as part of the crate, as well as the ability to re-encode instructions. [`disas-bench`](https://github.com/athre0z/disas-bench), a handy benchmark of several `x86_64` decoders including `yaxpeax-x86`. [`mishegos`](https://github.com/trailofbits/mishegos/), a differential fuzzer that has made testing the correctness of `yaxpeax-x86` _much_ easier. yaxpeax-x86-1.2.2/build.rs000064400000000000000000000002371046102023000133770ustar 00000000000000fn main() { #[cfg(capstone_bench)] { println!("cargo:rustc-link-search=/usr/lib/"); println!("cargo:rustc-link-lib=capstone"); } } yaxpeax-x86-1.2.2/goodfile000064400000000000000000000047161046102023000134530ustar 00000000000000Build.dependencies({"git", "make", "rustc", "cargo"}) Build.metric( "nightly version", string.gsub(Build.check_output({"rustc", "--version"}).stdout, '^%s*(.*)%s*$', '%1') ) Step.start("crate") Step.push("build") Build.run({"cargo", "build"}) -- `run` automatically records stdout and stderr to log files named after the command Step.advance("test") Build.run({"cargo", "test"}, {name="test stdlib/fmt"}) -- artifacts are stored under `name` if that's present Build.run({"cargo", "test", "--no-default-features"}, {name="test nostdlib/nofmt"}) Build.run({"cargo", "test", "--no-default-features", "--features", "fmt"}, {name="test nostdlib/fmt"}) Step.start("ffi") Step.push("build") Build.run({"cargo", "+nightly", "build", "-Z", "build-std", "--release", "--no-default-features", "--target", Build.environment.vars.native_rust_triple}, {cwd="ffi/"}) Step.advance("validate") sopath = "ffi/target/" .. Build.environment.vars.native_rust_triple .. "/release/libyaxpeax_x86_ffi_long_mode.so" Build.run({"ls", sopath}) Build.metric( "libyaxpeax_x86_ffi_long_mode.so size (bytes)", Build.environment.size(sopath) ) Build.artifact(sopath) -- now run some perf numbers... Step.start("perf") Build.run({"git", "clone", "https://github.com/athre0z/disas-bench.git", "disas-bench"}) Build.run({"git", "submodule", "update", "--recursive", "--init"}, {cwd="disas-bench"}) Build.run({"git", "remote", "add", "dev", "../../.."}, {cwd="disas-bench/libs/yaxpeax"}) Build.run({"git", "fetch", "-a", "dev"}, {cwd="disas-bench/libs/yaxpeax"}) Build.run({"git", "checkout", Build.sha}, {cwd="disas-bench/libs/yaxpeax"}) Step.push("build") Build.run({"make", "make-bench-yaxpeax"}, {cwd="disas-bench/bench/yaxpeax"}) Build.metric( "bench-yaxpeax-fmt size (bytes)", Build.environment.size("disas-bench/bench/yaxpeax/bench-yaxpeax-fmt") ) Build.metric( "bench-yaxpeax-no-fmt size (bytes)", Build.environment.size("disas-bench/bench/yaxpeax/bench-yaxpeax-no-fmt") ) -- fmt Step.advance("fmt") bench_start = Build.now_ms() Build.run({"./bench-yaxpeax-fmt", "20", "0x400", "0x2460400", "../../input/xul.dll"}, {cwd="disas-bench/bench/yaxpeax"}) bench_end = Build.now_ms() Build.metric("fmt runtime (ms)", bench_end - bench_start) -- no-fmt Step.advance("no-fmt") bench_start = Build.now_ms() Build.run({"./bench-yaxpeax-no-fmt", "20", "0x400", "0x2460400", "../../input/xul.dll"}, {cwd="disas-bench/bench/yaxpeax"}) bench_end = Build.now_ms() Build.metric("no-fmt runtime (ms)", bench_end - bench_start) yaxpeax-x86-1.2.2/src/lib.rs000064400000000000000000000171631046102023000136430ustar 00000000000000//! # `yaxpeax-x86`, a decoder for x86-family instruction sets //! //! `yaxpeax-x86` provides x86 decoders, for 64-, 32-, and 16-bit modes. `yaxpeax-x86` also //! implements traits defined by `yaxpeax_arch`, making it suitable for interchangeable use with //! other `yaxpeax`-family instruction decoders. //! //! ## usage //! //! the fastest way to decode an x86 instruction is through [`amd64::InstDecoder::decode_slice()`]: //! ``` //! let decoder = yaxpeax_x86::amd64::InstDecoder::default(); //! //! let inst = decoder.decode_slice(&[0x33, 0xc0]).unwrap(); //! //! #[cfg(features="fmt")] //! assert_eq!("xor eax, eax", inst.to_string()); //! ``` //! //! instructions, operands, registers, and generally all decoding structures, are in their mode's //! respective submodule: //! * `x86_64`/`amd64` decoding is under [`long_mode`] //! * `x86_32`/`x86` decoding is under [`protected_mode`] //! * `x86_16`/`8086` decoding is under [`real_mode`] //! //! all modes have equivalent data available in a decoded instruction. for example, all modes have //! library-friendly `Operand` and `RegSpec` types: //! //! ``` //! use yaxpeax_x86::amd64::{InstDecoder, Operand, RegSpec}; //! //! let decoder = yaxpeax_x86::amd64::InstDecoder::default(); //! //! let inst = decoder.decode_slice(&[0x33, 0x01]).unwrap(); //! //! #[cfg(features="fmt")] //! assert_eq!("xor eax, dword [rcx]", inst.to_string()); //! //! assert_eq!(Operand::Register(RegSpec::eax()), inst.operand(0)); //! #[cfg(features="fmt")] //! assert_eq!("eax", inst.operand(0).to_string()); //! assert_eq!(Operand::RegDeref(RegSpec::rcx()), inst.operand(1)); //! //! // an operand in isolation does not know the size of memory it references, if any //! #[cfg(features="fmt")] //! assert_eq!("[rcx]", inst.operand(1).to_string()); //! //! // and for memory operands, the size must be read from the instruction itself: //! let mem_size: yaxpeax_x86::amd64::MemoryAccessSize = inst.mem_size().unwrap(); //! assert_eq!("dword", mem_size.size_name()); //! //! // `MemoryAccessSize::size_name()` is how its `Display` impl works, as well: //! #[cfg(features="fmt")] //! assert_eq!("dword", mem_size.to_string()); //! ``` //! //! `yaxpeax-x86` can also be used to decode instructions generically through the `yaxpeax-arch` //! traits: //! ``` //! mod decoder { //! use yaxpeax_arch::{Arch, AddressDisplay, Decoder, Reader, ReaderBuilder}; //! //! // have to play some games so this example works right even without `fmt` enabled! //! #[cfg(feature="fmt")] //! trait InstBound: std::fmt::Display {} //! #[cfg(not(feature="fmt"))] //! trait InstBound {} //! //! #[cfg(feature="fmt")] //! impl InstBound for T {} //! #[cfg(not(feature="fmt"))] //! impl InstBound for T {} //! //! pub fn decode_stream< //! 'data, //! A: yaxpeax_arch::Arch, //! U: ReaderBuilder, //! >(data: U) where //! A::Instruction: InstBound, //! { //! let mut reader = ReaderBuilder::read_from(data); //! let mut address: A::Address = reader.total_offset(); //! //! let decoder = A::Decoder::default(); //! let mut decode_res = decoder.decode(&mut reader); //! loop { //! match decode_res { //! Ok(ref inst) => { //! #[cfg(feature="fmt")] //! println!("{}: {}", address.show(), inst); //! decode_res = decoder.decode(&mut reader); //! address = reader.total_offset(); //! } //! Err(e) => { //! println!("{}: decode error: {}", address.show(), e); //! break; //! } //! } //! } //! } //! } //! //! use yaxpeax_x86::amd64::{Arch as x86_64}; //! use yaxpeax_arch::{ReaderBuilder, U8Reader}; //! let data: &[u8] = &[0x55, 0x33, 0xc0, 0x48, 0x8b, 0x02, 0x5d, 0xc3]; //! decoder::decode_stream::(data); //! ``` //! //! ## `#![no_std]` //! //! `yaxpeax-x86` supports `no_std` usage. to be built `no_std`, `yaxpeax-x86` only needs //! `default-features = false` in the corresponding `Cargo.toml` dependency. if formatting is //! needed with `std` disabled, it can be re-enabled by explicitly requesting the `fmt` features //! like: //! ```text //! yaxpeax-x86 = { version = "*", default-features = false, features = ["fmt"] } //! ``` //! //! this is how the `.so` and `.a` packaging in //! [`ffi/`](https://github.com/iximeow/yaxpeax-x86/tree/no-gods-no-/ffi) is performed. #![no_std] #[cfg(feature="use-serde")] #[macro_use] extern crate serde_derive; #[cfg(feature="use-serde")] extern crate serde; #[cfg(feature="std")] extern crate alloc; pub mod long_mode; pub use long_mode as amd64; pub use long_mode::Arch as x86_64; pub mod protected_mode; pub use protected_mode::Arch as x86_32; pub mod real_mode; pub use real_mode::Arch as x86_16; mod safer_unchecked; const MEM_SIZE_STRINGS: [&'static str; 64] = [ "byte", "word", "BUG", "dword", "ptr", "far", "BUG", "qword", "BUG", "mword", "BUG", "BUG", "BUG", "BUG", "BUG", "xmmword", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "ymmword", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "m384b", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "ptr", "zmmword", ]; pub struct MemoryAccessSize { size: u8, } impl MemoryAccessSize { /// return the number of bytes referenced by this memory access. /// /// if the number of bytes cannot be confidently known by the instruction in isolation (as is /// the case for `xsave`/`xrstor`-style "operate on all processor state" instructions), this /// function will return `None`. pub fn bytes_size(&self) -> Option { if self.size == 63 { None } else { Some(self.size) } } /// a human-friendly label for the number of bytes this memory access references. /// /// there are some differences from size names that may be expected elsewhere; `yaxpeax-x86` /// prefers to use consistent names for a width even if the way those bytes are used varies. /// /// the sizes `yaxpeax-x86` knows are as follows: /// | size (bytes) | name | /// |--------------|------------| /// | 1 | `byte` | /// | 2 | `word` | /// | 4 | `dword` | /// | 6 | `far` | /// | 8 | `qword` | /// | 10 | `mword` | /// | 16 | `xmmword` | /// | 32 | `ymmword` | /// | 64 | `zmmword` | /// | variable | `ptr` | /// /// "mword" refers to an mmx-sized access - 80 bits, or 10 bytes. `mword` is also used for /// 64-bit far calls, because they reference a contiguous ten bytes; two bytes of segment /// selector and eight bytes of address. /// /// "variable" accesses access a number of bytes dependent on the physical processor and its /// operating mode. this is particularly relevant for `xsave`/`xrstor`-style instructions. pub fn size_name(&self) -> &'static str { MEM_SIZE_STRINGS[self.size as usize - 1] } } #[cfg(feature = "fmt")] impl core::fmt::Display for MemoryAccessSize { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { f.write_str(self.size_name()) } } #[cfg(feature = "fmt")] impl core::fmt::Debug for MemoryAccessSize { fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result { core::fmt::Display::fmt(self, f) } } yaxpeax-x86-1.2.2/src/long_mode/display.rs000064400000000000000000003213651046102023000165070ustar 00000000000000use core::fmt; use yaxpeax_arch::{Colorize, ShowContextual, NoColors, YaxColors}; use yaxpeax_arch::display::*; use crate::safer_unchecked::GetSaferUnchecked as _; use crate::MEM_SIZE_STRINGS; use crate::long_mode::{RegSpec, Opcode, Operand, MergeMode, InstDecoder, Instruction, Segment, PrefixRex, OperandSpec}; impl fmt::Display for InstDecoder { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self == &InstDecoder::default() { return write!(f, ""); } else if self == &InstDecoder::minimal() { return write!(f, ""); } if self.sse3() { write!(f, "sse3 ")? } if self.ssse3() { write!(f, "ssse3 ")? } if self.monitor() { write!(f, "monitor ")? } if self.vmx() { write!(f, "vmx ")? } if self.fma3() { write!(f, "fma3 ")? } if self.cmpxchg16b() { write!(f, "cmpxchg16b ")? } if self.sse4_1() { write!(f, "sse4_1 ")? } if self.sse4_2() { write!(f, "sse4_2 ")? } if self.movbe() { write!(f, "movbe ")? } if self.popcnt() { write!(f, "popcnt ")? } if self.aesni() { write!(f, "aesni ")? } if self.xsave() { write!(f, "xsave ")? } if self.rdrand() { write!(f, "rdrand ")? } if self.sgx() { write!(f, "sgx ")? } if self.bmi1() { write!(f, "bmi1 ")? } if self.avx2() { write!(f, "avx2 ")? } if self.bmi2() { write!(f, "bmi2 ")? } if self.invpcid() { write!(f, "invpcid ")? } if self.mpx() { write!(f, "mpx ")? } if self.avx512_f() { write!(f, "avx512_f ")? } if self.avx512_dq() { write!(f, "avx512_dq ")? } if self.rdseed() { write!(f, "rdseed ")? } if self.adx() { write!(f, "adx ")? } if self.avx512_fma() { write!(f, "avx512_fma ")? } if self.pcommit() { write!(f, "pcommit ")? } if self.clflushopt() { write!(f, "clflushopt ")? } if self.clwb() { write!(f, "clwb ")? } if self.avx512_pf() { write!(f, "avx512_pf ")? } if self.avx512_er() { write!(f, "avx512_er ")? } if self.avx512_cd() { write!(f, "avx512_cd ")? } if self.sha() { write!(f, "sha ")? } if self.avx512_bw() { write!(f, "avx512_bw ")? } if self.avx512_vl() { write!(f, "avx512_vl ")? } if self.prefetchwt1() { write!(f, "prefetchwt1 ")? } if self.avx512_vbmi() { write!(f, "avx512_vbmi ")? } if self.avx512_vbmi2() { write!(f, "avx512_vbmi2 ")? } if self.gfni() { write!(f, "gfni ")? } if self.vaes() { write!(f, "vaes ")? } if self.pclmulqdq() { write!(f, "pclmulqdq ")? } if self.avx_vnni() { write!(f, "avx_vnni ")? } if self.avx512_bitalg() { write!(f, "avx512_bitalg ")? } if self.avx512_vpopcntdq() { write!(f, "avx512_vpopcntdq ")? } if self.avx512_4vnniw() { write!(f, "avx512_4vnniw ")? } if self.avx512_4fmaps() { write!(f, "avx512_4fmaps ")? } if self.cx8() { write!(f, "cx8 ")? } if self.syscall() { write!(f, "syscall ")? } if self.rdtscp() { write!(f, "rdtscp ")? } if self.abm() { write!(f, "abm ")? } if self.sse4a() { write!(f, "sse4a ")? } if self._3dnowprefetch() { write!(f, "_3dnowprefetch ")? } if self.xop() { write!(f, "xop ")? } if self.skinit() { write!(f, "skinit ")? } if self.tbm() { write!(f, "tbm ")? } if self.intel_quirks() { write!(f, "intel_quirks ")? } if self.amd_quirks() { write!(f, "amd_quirks ")? } if self.avx() { write!(f, "avx ")? } Ok(()) } } impl fmt::Display for PrefixRex { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self.present() { write!(f, "rex:{}{}{}{}", if self.w() { "w" } else { "-" }, if self.r() { "r" } else { "-" }, if self.x() { "x" } else { "-" }, if self.b() { "b" } else { "-" }, ) } else { write!(f, "rex:none") } } } impl fmt::Display for Segment { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { Segment::CS => write!(f, "cs"), Segment::DS => write!(f, "ds"), Segment::ES => write!(f, "es"), Segment::FS => write!(f, "fs"), Segment::GS => write!(f, "gs"), Segment::SS => write!(f, "ss"), } } } // register names are grouped by indices scaled by 16. // xmm, ymm, zmm all get two indices. const REG_NAMES: &[&'static str] = &[ "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w", "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d", "BUG", "BUG", "BUG", "BUG", "spl", "bpl", "sil", "dil", "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b", "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "cr8", "cr9", "cr10", "cr11", "cr12", "cr13", "cr14", "cr15", "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", "dr8", "dr9", "dr10", "dr11", "dr12", "dr13", "dr14", "dr15", "es", "cs", "ss", "ds", "fs", "gs", "", "", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "st(0)", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", "eip", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "rip", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "eflags", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "rflags", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", ]; pub(crate) fn regspec_label(spec: &RegSpec) -> &'static str { unsafe { REG_NAMES.get_kinda_unchecked((spec.num as u16 + ((spec.bank as u16) << 3)) as usize) } } impl fmt::Display for RegSpec { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(regspec_label(self)) } } impl fmt::Display for Operand { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } impl Colorize for Operand { fn colorize(&self, colors: &Y, f: &mut T) -> fmt::Result { match self { &Operand::ImmediateU8(imm) => { write!(f, "{}", colors.number(u8_hex(imm))) } &Operand::ImmediateI8(imm) => { write!(f, "{}", colors.number(signed_i8_hex(imm))) }, &Operand::ImmediateU16(imm) => { write!(f, "{}", colors.number(u16_hex(imm))) } &Operand::ImmediateI16(imm) => { write!(f, "{}", colors.number(signed_i16_hex(imm))) }, &Operand::ImmediateU32(imm) => { write!(f, "{}", colors.number(u32_hex(imm))) } &Operand::ImmediateI32(imm) => { write!(f, "{}", colors.number(signed_i32_hex(imm))) }, &Operand::ImmediateU64(imm) => { write!(f, "{}", colors.number(u64_hex(imm))) } &Operand::ImmediateI64(imm) => { write!(f, "{}", colors.number(signed_i64_hex(imm))) }, &Operand::Register(ref spec) => { f.write_str(regspec_label(spec)) } &Operand::RegisterMaskMerge(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } Ok(()) } &Operand::RegisterMaskMergeSae(ref spec, ref mask, merge_mode, sae_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str(sae_mode.label())?; Ok(()) } &Operand::RegisterMaskMergeSaeNoround(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str("{sae}")?; Ok(()) } &Operand::DisplacementU32(imm) => { write!(f, "[{}]", colors.address(u32_hex(imm))) } &Operand::DisplacementU64(imm) => { write!(f, "[{}]", colors.address(u64_hex(imm))) } &Operand::RegDisp(ref spec, disp) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDeref(ref spec) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]") }, &Operand::RegScale(ref spec, scale) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) ) }, &Operand::RegScaleDisp(ref spec, scale, disp) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBase(ref base, ref index) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]") } &Operand::RegIndexBaseDisp(ref base, ref index, disp) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBaseScale(ref base, ref index, scale) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) ) } &Operand::RegIndexBaseScaleDisp(ref base, ref index, scale, disp) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDispMasked(ref spec, disp, ref mask_reg) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegDerefMasked(ref spec, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleMasked(ref spec, scale, ref mask_reg) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleDispMasked(ref spec, scale, disp, ref mask_reg) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseMasked(ref base, ref index, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseDispMasked(ref base, ref index, disp, ref mask_reg) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseScaleMasked(ref base, ref index, scale, ref mask_reg) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseScaleDispMasked(ref base, ref index, scale, disp, ref mask_reg) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::Nothing => { Ok(()) }, } } } impl fmt::Display for Opcode { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.name()) } } const MNEMONICS: &[&'static str] = &[ "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp", "rol", "ror", "rcl", "rcr", "shl", "shr", "sal", "sar", "btc", "btr", "bts", "cmpxchg", "cmpxchg8b", "cmpxchg16b", "dec", "inc", "neg", "not", "xadd", "xchg", "invalid", "bt", "bsf", "bsr", "tzcnt", "movss", "addss", "subss", "mulss", "divss", "minss", "maxss", "sqrtss", "movsd", "sqrtsd", "addsd", "subsd", "mulsd", "divsd", "minsd", "maxsd", "movsldup", "movshdup", "movddup", "haddps", "hsubps", "addsubpd", "addsubps", "cvtsi2ss", "cvtsi2sd", "cvttsd2si", "cvttps2dq", "cvtpd2dq", "cvtpd2ps", "cvtps2dq", "cvtsd2si", "cvtsd2ss", "cvttss2si", "cvtss2si", "cvtss2sd", "cvtdq2pd", "lddqu", "movzx", "movsx", "movsxd", "shrd", // "inc", // "dec", "hlt", "call", "callf", "jmp", "jmpf", "push", "pop", "lea", "nop", "prefetchnta", "prefetch0", "prefetch1", "prefetch2", // "xchg", "popf", "int", "into", "iret", "iretd", "iretq", "retf", "enter", "leave", "mov", "ret", "pushf", "wait", "cbw", "cwde", "cdqe", "cwd", "cdq", "cqo", "lods", "stos", "lahf", "sahf", "cmps", "scas", "movs", "test", "ins", "in", "outs", "out", "imul", "jo", "jno", "jb", "jnb", "jz", "jnz", "ja", "jna", "js", "jns", "jp", "jnp", "jl", "jge", "jle", "jg", "cmova", "cmovb", "cmovg", "cmovge", "cmovl", "cmovle", "cmovna", "cmovnb", "cmovno", "cmovnp", "cmovns", "cmovnz", "cmovo", "cmovp", "cmovs", "cmovz", "div", "idiv", "mul", // "neg", // "not", // "cmpxchg", "seto", "setno", "setb", "setae", "setz", "setnz", "setbe", "seta", "sets", "setns", "setp", "setnp", "setl", "setge", "setle", "setg", "cpuid", "ud0", "ud1", "ud2", "wbinvd", "invd", "sysret", "clts", "syscall", "lsl", "lar", "sgdt", "sidt", "lgdt", "lidt", "smsw", "lmsw", "swapgs", "rdtscp", "invlpg", "fxsave", "fxrstor", "ldmxcsr", "stmxcsr", "xsave", "xrstor", "xsaveopt", "lfence", "mfence", "sfence", "clflush", "clflushopt", "clwb", "wrmsr", "rdtsc", "rdmsr", "rdpmc", "sldt", "str", "lldt", "ltr", "verr", "verw", "cmc", "clc", "stc", "cli", "sti", "cld", "std", "jmpe", "popcnt", "movdqu", "movdqa", "movq", "cmpss", "cmpsd", "unpcklps", "unpcklpd", "unpckhps", "unpckhpd", "pshufhw", "pshuflw", "movups", "movq2dq", "movdq2q", "rsqrtss", "rcpss", "andn", "bextr", "blsi", "blsmsk", "blsr", "vmclear", "vmxon", "vmcall", "vmlaunch", "vmresume", "vmxoff", "pconfig", "monitor", "mwait", "monitorx", "mwaitx", "clac", "stac", "encls", "enclv", "xgetbv", "xsetbv", "vmfunc", "xabort", "xbegin", "xend", "xtest", "enclu", "rdpkru", "wrpkru", "rdpru", "clzero", "rdseed", "rdrand", "addps", "addpd", "andnps", "andnpd", "andps", "andpd", "bswap", "cmppd", "cmpps", "comisd", "comiss", "cvtdq2ps", "cvtpi2ps", "cvtpi2pd", "cvtps2pd", "cvtps2pi", "cvtpd2pi", "cvttps2pi", "cvttpd2pi", "cvttpd2dq", "divps", "divpd", "emms", "getsec", "lfs", "lgs", "lss", "maskmovq", "maskmovdqu", "maxps", "maxpd", "minps", "minpd", "movaps", "movapd", "movd", "movlps", "movlpd", "movhps", "movhpd", "movlhps", "movhlps", "movupd", "movmskps", "movmskpd", "movnti", "movntps", "movntpd", "extrq", "insertq", "movntss", "movntsd", "movntq", "movntdq", "mulps", "mulpd", "orps", "orpd", "packssdw", "packsswb", "packuswb", "paddb", "paddd", "paddq", "paddsb", "paddsw", "paddusb", "paddusw", "paddw", "pand", "pandn", "pavgb", "pavgw", "pcmpeqb", "pcmpeqd", "pcmpeqw", "pcmpgtb", "pcmpgtd", "pcmpgtw", "pinsrw", "pmaddwd", "pmaxsw", "pmaxub", "pminsw", "pminub", "pmovmskb", "pmulhuw", "pmulhw", "pmullw", "pmuludq", "por", "psadbw", "pshufw", "pshufd", "pslld", "pslldq", "psllq", "psllw", "psrad", "psraw", "psrld", "psrldq", "psrlq", "psrlw", "psubb", "psubd", "psubq", "psubsb", "psubsw", "psubusb", "psubusw", "psubw", "punpckhbw", "punpckhdq", "punpckhwd", "punpcklbw", "punpckldq", "punpcklwd", "punpcklqdq", "punpckhqdq", "pxor", "rcpps", "rsm", "rsqrtps", "shld", "shufpd", "shufps", "slhd", "sqrtps", "sqrtpd", "subps", "subpd", "sysenter", "sysexit", "ucomisd", "ucomiss", "vmread", "vmwrite", "xorps", "xorpd", "vmovddup", "vpshuflw", "vpshufhw", "vhaddps", "vhsubps", "vaddsubps", "vcvtpd2dq", "vlddqu", "vcomisd", "vcomiss", "vucomisd", "vucomiss", "vaddpd", "vaddps", "vaddsd", "vaddss", "vaddsubpd", "vaesdec", "vaesdeclast", "vaesenc", "vaesenclast", "vaesimc", "vaeskeygenassist", "vblendpd", "vblendps", "vblendvpd", "vblendvps", "vbroadcastf128", "vbroadcasti128", "vbroadcastsd", "vbroadcastss", "vcmpsd", "vcmpss", "vcmppd", "vcmpps", "vcvtdq2pd", "vcvtdq2ps", "vcvtpd2ps", "vcvtph2ps", "vcvtps2dq", "vcvtps2pd", "vcvtss2sd", "vcvtsi2ss", "vcvtsi2sd", "vcvtsd2si", "vcvtsd2ss", "vcvtps2ph", "vcvtss2si", "vcvttpd2dq", "vcvttps2dq", "vcvttss2si", "vcvttsd2si", "vdivpd", "vdivps", "vdivsd", "vdivss", "vdppd", "vdpps", "vextractf128", "vextracti128", "vextractps", "vfmadd132pd", "vfmadd132ps", "vfmadd132sd", "vfmadd132ss", "vfmadd213pd", "vfmadd213ps", "vfmadd213sd", "vfmadd213ss", "vfmadd231pd", "vfmadd231ps", "vfmadd231sd", "vfmadd231ss", "vfmaddsub132pd", "vfmaddsub132ps", "vfmaddsub213pd", "vfmaddsub213ps", "vfmaddsub231pd", "vfmaddsub231ps", "vfmsub132pd", "vfmsub132ps", "vfmsub132sd", "vfmsub132ss", "vfmsub213pd", "vfmsub213ps", "vfmsub213sd", "vfmsub213ss", "vfmsub231pd", "vfmsub231ps", "vfmsub231sd", "vfmsub231ss", "vfmsubadd132pd", "vfmsubadd132ps", "vfmsubadd213pd", "vfmsubadd213ps", "vfmsubadd231pd", "vfmsubadd231ps", "vfnmadd132pd", "vfnmadd132ps", "vfnmadd132sd", "vfnmadd132ss", "vfnmadd213pd", "vfnmadd213ps", "vfnmadd213sd", "vfnmadd213ss", "vfnmadd231pd", "vfnmadd231ps", "vfnmadd231sd", "vfnmadd231ss", "vfnmsub132pd", "vfnmsub132ps", "vfnmsub132sd", "vfnmsub132ss", "vfnmsub213pd", "vfnmsub213ps", "vfnmsub213sd", "vfnmsub213ss", "vfnmsub231pd", "vfnmsub231ps", "vfnmsub231sd", "vfnmsub231ss", "vgatherdpd", "vgatherdps", "vgatherqpd", "vgatherqps", "vhaddpd", "vhsubpd", "vinsertf128", "vinserti128", "vinsertps", "vmaskmovdqu", "vmaskmovpd", "vmaskmovps", "vmaxpd", "vmaxps", "vmaxsd", "vmaxss", "vminpd", "vminps", "vminsd", "vminss", "vmovapd", "vmovaps", "vmovd", "vmovdqa", "vmovdqu", "vmovhlps", "vmovhpd", "vmovhps", "vmovlhps", "vmovlpd", "vmovlps", "vmovmskpd", "vmovmskps", "vmovntdq", "vmovntdqa", "vmovntpd", "vmovntps", "vmovq", "vmovss", "vmovsd", "vmovshdup", "vmovsldup", "vmovupd", "vmovups", "vmpsadbw", "vmulpd", "vmulps", "vmulsd", "vmulss", "vpabsb", "vpabsd", "vpabsw", "vpackssdw", "vpackusdw", "vpacksswb", "vpackuswb", "vpaddb", "vpaddd", "vpaddq", "vpaddsb", "vpaddsw", "vpaddusb", "vpaddusw", "vpaddw", "vpalignr", "vandpd", "vandps", "vorpd", "vorps", "vandnpd", "vandnps", "vpand", "vpandn", "vpavgb", "vpavgw", "vpblendd", "vpblendvb", "vpblendw", "vpbroadcastb", "vpbroadcastd", "vpbroadcastq", "vpbroadcastw", "vpclmulqdq", "vpcmpeqb", "vpcmpeqd", "vpcmpeqq", "vpcmpeqw", "vpcmpgtb", "vpcmpgtd", "vpcmpgtq", "vpcmpgtw", "vpcmpestri", "vpcmpestrm", "vpcmpistri", "vpcmpistrm", "vperm2f128", "vperm2i128", "vpermd", "vpermilpd", "vpermilps", "vpermpd", "vpermps", "vpermq", "vpextrb", "vpextrd", "vpextrq", "vpextrw", "vpgatherdd", "vpgatherdq", "vpgatherqd", "vpgatherqq", "vphaddd", "vphaddsw", "vphaddw", "vpmaddubsw", "vphminposuw", "vphsubd", "vphsubsw", "vphsubw", "vpinsrb", "vpinsrd", "vpinsrq", "vpinsrw", "vpmaddwd", "vpmaskmovd", "vpmaskmovq", "vpmaxsb", "vpmaxsd", "vpmaxsw", "vpmaxub", "vpmaxuw", "vpmaxud", "vpminsb", "vpminsw", "vpminsd", "vpminub", "vpminuw", "vpminud", "vpmovmskb", "vpmovsxbd", "vpmovsxbq", "vpmovsxbw", "vpmovsxdq", "vpmovsxwd", "vpmovsxwq", "vpmovzxbd", "vpmovzxbq", "vpmovzxbw", "vpmovzxdq", "vpmovzxwd", "vpmovzxwq", "vpmuldq", "vpmulhrsw", "vpmulhuw", "vpmulhw", "vpmullq", "vpmulld", "vpmullw", "vpmuludq", "vpor", "vpsadbw", "vpshufb", "vpshufd", "vpsignb", "vpsignd", "vpsignw", "vpslld", "vpslldq", "vpsllq", "vpsllvd", "vpsllvq", "vpsllw", "vpsrad", "vpsravd", "vpsraw", "vpsrld", "vpsrldq", "vpsrlq", "vpsrlvd", "vpsrlvq", "vpsrlw", "vpsubb", "vpsubd", "vpsubq", "vpsubsb", "vpsubsw", "vpsubusb", "vpsubusw", "vpsubw", "vptest", "vpunpckhbw", "vpunpckhdq", "vpunpckhqdq", "vpunpckhwd", "vpunpcklbw", "vpunpckldq", "vpunpcklqdq", "vpunpcklwd", "vpxor", "vrcpps", "vroundpd", "vroundps", "vroundsd", "vroundss", "vrsqrtps", "vrsqrtss", "vrcpss", "vshufpd", "vshufps", "vsqrtpd", "vsqrtps", "vsqrtss", "vsqrtsd", "vsubpd", "vsubps", "vsubsd", "vsubss", "vtestpd", "vtestps", "vunpckhpd", "vunpckhps", "vunpcklpd", "vunpcklps", "vxorpd", "vxorps", "vzeroupper", "vzeroall", "vldmxcsr", "vstmxcsr", "pclmulqdq", "aeskeygenassist", "aesimc", "aesenc", "aesenclast", "aesdec", "aesdeclast", "pcmpgtq", "pcmpistrm", "pcmpistri", "pcmpestri", "packusdw", "pcmpestrm", "pcmpeqq", "ptest", "phminposuw", "dpps", "dppd", "mpsadbw", "pmovzxdq", "pmovsxdq", "pmovzxbd", "pmovsxbd", "pmovzxwq", "pmovsxwq", "pmovzxbq", "pmovsxbq", "pmovsxwd", "pmovzxwd", "pextrq", "pextrd", "pextrw", "pextrb", "pmovsxbw", "pmovzxbw", "pinsrq", "pinsrd", "pinsrb", "extractps", "insertps", "roundss", "roundsd", "roundps", "roundpd", "pmaxsb", "pmaxsd", "pmaxuw", "pmaxud", "pminsd", "pminsb", "pminud", "pminuw", "blendw", "pblendvb", "pblendw", "blendvps", "blendvpd", "blendps", "blendpd", "pmuldq", "movntdqa", "pmulld", "palignr", "psignw", "psignd", "psignb", "pshufb", "pmulhrsw", "pmaddubsw", "pabsd", "pabsw", "pabsb", "phsubsw", "phsubw", "phsubd", "phaddd", "phaddsw", "phaddw", "hsubpd", "haddpd", "sha1rnds4", "sha1nexte", "sha1msg1", "sha1msg2", "sha256rnds2", "sha256msg1", "sha256msg2", "lzcnt", "clgi", "stgi", "skinit", "vmload", "vmmcall", "vmsave", "vmrun", "invlpga", "invlpgb", "tlbsync", "movbe", "adcx", "adox", "prefetchw", "rdpid", // "cmpxchg8b", // "cmpxchg16b", "vmptrld", "vmptrst", "bzhi", "mulx", "shlx", "shrx", "sarx", "pdep", "pext", "rorx", "xrstors", "xrstors64", "xsavec", "xsavec64", "xsaves", "xsaves64", "rdfsbase", "rdgsbase", "wrfsbase", "wrgsbase", "crc32", "salc", "xlat", "f2xm1", "fabs", "fadd", "faddp", "fbld", "fbstp", "fchs", "fcmovb", "fcmovbe", "fcmove", "fcmovnb", "fcmovnbe", "fcmovne", "fcmovnu", "fcmovu", "fcom", "fcomi", "fcomip", "fcomp", "fcompp", "fcos", "fdecstp", "fdisi8087_nop", "fdiv", "fdivp", "fdivr", "fdivrp", "feni8087_nop", "ffree", "ffreep", "fiadd", "ficom", "ficomp", "fidiv", "fidivr", "fild", "fimul", "fincstp", "fist", "fistp", "fisttp", "fisub", "fisubr", "fld", "fld1", "fldcw", "fldenv", "fldl2e", "fldl2t", "fldlg2", "fldln2", "fldpi", "fldz", "fmul", "fmulp", "fnclex", "fninit", "fnop", "fnsave", "fnstcw", "fnstenv", "fnstor", "fnstsw", "fpatan", "fprem", "fprem1", "fptan", "frndint", "frstor", "fscale", "fsetpm287_nop", "fsin", "fsincos", "fsqrt", "fst", "fstp", "fstpnce", "fsub", "fsubp", "fsubr", "fsubrp", "ftst", "fucom", "fucomi", "fucomip", "fucomp", "fucompp", "fxam", "fxch", "fxtract", "fyl2x", "fyl2xp1", "loopnz", "loopz", "loop", "jrcxz", // started shipping in Tremont, 2020 sept 23 "movdir64b", "movdiri", // started shipping in Tiger Lake, 2020 sept 2 "aesdec128kl", "aesdec256kl", "aesdecwide128kl", "aesdecwide256kl", "aesenc128kl", "aesenc256kl", "aesencwide128kl", "aesencwide256kl", "encodekey128", "encodekey256", "loadiwkey", // unsure "hreset", // 3dnow "femms", "pi2fw", "pi2fd", "pf2iw", "pf2id", "pmulhrw", "pfcmpge", "pfmin", "pfrcp", "pfrsqrt", "pfsub", "pfadd", "pfcmpgt", "pfmax", "pfrcpit1", "pfrsqit1", "pfsubr", "pfacc", "pfcmpeq", "pfmul", "pfmulhrw", "pfrcpit2", "pfnacc", "pfpnacc", "pswapd", "pavgusb", // ENQCMD "enqcmd", "enqcmds", // INVPCID "invept", "invvpid", "invpcid", // PTWRITE "ptwrite", // GFNI "gf2p8affineqb", "gf2p8affineinvqb", "gf2p8mulb", // CET "wruss", "wrss", "incssp", "saveprevssp", "setssbsy", "clrssbsy", "rstorssp", "endbr64", "endbr32", // TDX "tdcall", "seamret", "seamops", "seamcall", // WAITPKG "tpause", "umonitor", "umwait", // UINTR "uiret", "testui", "clui", "stui", "senduipi", // TSXLDTRK "xsusldtrk", "xresldtrk", // AVX512F "valignd", "valignq", "vblendmpd", "vblendmps", "vcompresspd", "vcompressps", "vcvtpd2udq", "vcvttpd2udq", "vcvtps2udq", "vcvttps2udq", "vcvtqq2pd", "vcvtqq2ps", "vcvtsd2usi", "vcvttsd2usi", "vcvtss2usi", "vcvttss2usi", "vcvtudq2pd", "vcvtudq2ps", "vcvtusi2usd", "vcvtusi2uss", "vexpandpd", "vexpandps", "vextractf32x4", "vextractf64x4", "vextracti32x4", "vextracti64x4", "vfixupimmpd", "vfixupimmps", "vfixupimmsd", "vfixupimmss", "vgetexppd", "vgetexpps", "vgetexpsd", "vgetexpss", "vgetmantpd", "vgetmantps", "vgetmantsd", "vgetmantss", "vinsertf32x4", "vinsertf64x4", "vinserti64x4", "vmovdqa32", "vmovdqa64", "vmovdqu32", "vmovdqu64", "vpblendmd", "vpblendmq", "vpcmpd", "vpcmpud", "vpcmpq", "vpcmpuq", "vpcompressq", "vpcompressd", "vpermi2d", "vpermi2q", "vpermi2pd", "vpermi2ps", "vpermt2d", "vpermt2q", "vpermt2pd", "vpermt2ps", "vpmaxsq", "vpmaxuq", "vpminsq", "vpminuq", "vpmovsqb", "vpmovusqb", "vpmovsqw", "vpmovusqw", "vpmovsqd", "vpmovusqd", "vpmovsdb", "vpmovusdb", "vpmovsdw", "vpmovusdw", "vprold", "vprolq", "vprolvd", "vprolvq", "vprord", "vprorq", "vprorrd", "vprorrq", "vpscatterdd", "vpscatterdq", "vpscatterqd", "vpscatterqq", "vpsraq", "vpsravq", "vptestnmd", "vptestnmq", "vpternlogd", "vpternlogq", "vptestmd", "vptestmq", "vrcp14pd", "vrcp14ps", "vrcp14sd", "vrcp14ss", "vrndscalepd", "vrndscaleps", "vrndscalesd", "vrndscaless", "vrsqrt14pd", "vrsqrt14ps", "vrsqrt14sd", "vrsqrt14ss", "vscaledpd", "vscaledps", "vscaledsd", "vscaledss", "vscatterdd", "vscatterdq", "vscatterqd", "vscatterqq", "vshuff32x4", "vshuff64x2", "vshufi32x4", "vshufi64x2", // AVX512DQ "vcvttpd2qq", "vcvtpd2qq", "vcvttpd2uqq", "vcvtpd2uqq", "vcvttps2qq", "vcvtps2qq", "vcvttps2uqq", "vcvtps2uqq", "vcvtuqq2pd", "vcvtuqq2ps", "vextractf64x2", "vextracti64x2", "vfpclasspd", "vfpclassps", "vfpclasssd", "vfpclassss", "vinsertf64x2", "vinserti64x2", "vpmovm2d", "vpmovm2q", "vpmovb2d", "vpmovq2m", "vrangepd", "vrangeps", "vrangesd", "vrangess", "vreducepd", "vreduceps", "vreducesd", "vreducess", // AVX512BW "vdbpsadbw", "vmovdqu8", "vmovdqu16", "vpblendmb", "vpblendmw", "vpcmpb", "vpcmpub", "vpcmpw", "vpcmpuw", "vpermw", "vpermi2b", "vpermi2w", "vpmovm2b", "vpmovm2w", "vpmovb2m", "vpmovw2m", "vpmovswb", "vpmovuswb", "vpsllvw", "vpsravw", "vpsrlvw", "vptestnmb", "vptestnmw", "vptestmb", "vptestmw", // AVX512CD "vpbroadcastm", "vpconflictd", "vpconflictq", "vplzcntd", "vplzcntq", "kunpckbw", "kunpckwd", "kunpckdq", "kaddb", "kandb", "kandnb", "kmovb", "knotb", "korb", "kortestb", "kshiftlb", "kshiftrb", "ktestb", "kxnorb", "kxorb", "kaddw", "kandw", "kandnw", "kmovw", "knotw", "korw", "kortestw", "kshiftlw", "kshiftrw", "ktestw", "kxnorw", "kxorw", "kaddd", "kandd", "kandnd", "kmovd", "knotd", "kord", "kortestd", "kshiftld", "kshiftrd", "ktestd", "kxnord", "kxord", "kaddq", "kandq", "kandnq", "kmovq", "knotq", "korq", "kortestq", "kshiftlq", "kshiftrq", "ktestq", "kxnorq", "kxorq", // AVX512ER "vexp2pd", "vexp2ps", "vexp2sd", "vexp2ss", "vrcp28pd", "vrcp28ps", "vrcp28sd", "vrcp28ss", "vrsqrt28pd", "vrsqrt28ps", "vrsqrt28sd", "vrsqrt28ss", // AVX512PF "vgatherpf0dpd", "vgatherpf0dps", "vgatherpf0qpd", "vgatherpf0qps", "vgatherpf1dpd", "vgatherpf1dps", "vgatherpf1qpd", "vgatherpf1qps", "vscatterpf0dpd", "vscatterpf0dps", "vscatterpf0qpd", "vscatterpf0qps", "vscatterpf1dpd", "vscatterpf1dps", "vscatterpf1qpd", "vscatterpf1qps", // MPX "bndmk", "bndcl", "bndcu", "bndcn", "bndmov", "bndldx", "bndstx", "vgf2p8affineqb", "vgf2p8affineinvqb", "vpshrdq", "vpshrdd", "vpshrdw", "vpshldq", "vpshldd", "vpshldw", "vbroadcastf32x8", "vbroadcastf64x4", "vbroadcastf32x4", "vbroadcastf64x2", "vbroadcastf32x2", "vbroadcasti32x8", "vbroadcasti64x4", "vbroadcasti32x4", "vbroadcasti64x2", "vbroadcasti32x2", "vextracti32x8", "vextractf32x8", "vinserti32x8", "vinsertf32x8", "vinserti32x4", "v4fnmaddss", "v4fnmaddps", "vcvtneps2bf16", "v4fmaddss", "v4fmaddps", "vcvtne2ps2bf16", "vp2intersectd", "vp2intersectq", "vp4dpwssds", "vp4dpwssd", "vpdpwssds", "vpdpwssd", "vpdpbusds", "vdpbf16ps", "vpbroadcastmw2d", "vpbroadcastmb2q", "vpmovd2m", "vpmovqd", "vpmovwb", "vpmovdb", "vpmovdw", "vpmovqb", "vpmovqw", "vgf2p8mulb", "vpmadd52huq", "vpmadd52luq", "vpshufbitqmb", "vpermb", "vpexpandd", "vpexpandq", "vpabsq", "vprorvd", "vprorvq", "vpmultishiftqb", "vpermt2b", "vpermt2w", "vpshrdvq", "vpshrdvd", "vpshrdvw", "vpshldvq", "vpshldvd", "vpshldvw", "vpcompressb", "vpcompressw", "vpexpandb", "vpexpandw", "vpopcntd", "vpopcntq", "vpopcntb", "vpopcntw", "vscalefss", "vscalefsd", "vscalefps", "vscalefpd", "vpdpbusd", "vcvtusi2sd", "vcvtusi2ss", "vpxord", "vpxorq", "vpord", "vporq", "vpandnd", "vpandnq", "vpandd", "vpandq", "psmash", "pvalidate", "rmpadjust", "rmpupdate", ]; impl Opcode { fn name(&self) -> &'static str { unsafe { MNEMONICS.get_kinda_unchecked((*self as usize) & 0xfff) } } } impl Colorize for Opcode { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { match self { Opcode::VGF2P8AFFINEQB | Opcode::VGF2P8AFFINEINVQB | Opcode::VPSHRDQ | Opcode::VPSHRDD | Opcode::VPSHRDW | Opcode::VPSHLDQ | Opcode::VPSHLDD | Opcode::VPSHLDW | Opcode::VBROADCASTF32X8 | Opcode::VBROADCASTF64X4 | Opcode::VBROADCASTF32X4 | Opcode::VBROADCASTF64X2 | Opcode::VBROADCASTF32X2 | Opcode::VBROADCASTI32X8 | Opcode::VBROADCASTI64X4 | Opcode::VBROADCASTI32X4 | Opcode::VBROADCASTI64X2 | Opcode::VBROADCASTI32X2 | Opcode::VEXTRACTI32X8 | Opcode::VEXTRACTF32X8 | Opcode::VINSERTI32X8 | Opcode::VINSERTF32X8 | Opcode::VINSERTI32X4 | Opcode::V4FNMADDSS | Opcode::V4FNMADDPS | Opcode::VCVTNEPS2BF16 | Opcode::V4FMADDSS | Opcode::V4FMADDPS | Opcode::VCVTNE2PS2BF16 | Opcode::VP2INTERSECTD | Opcode::VP2INTERSECTQ | Opcode::VP4DPWSSDS | Opcode::VP4DPWSSD | Opcode::VPDPWSSDS | Opcode::VPDPWSSD | Opcode::VPDPBUSDS | Opcode::VDPBF16PS | Opcode::VPBROADCASTMW2D | Opcode::VPBROADCASTMB2Q | Opcode::VPMOVD2M | Opcode::VPMOVQD | Opcode::VPMOVWB | Opcode::VPMOVDB | Opcode::VPMOVDW | Opcode::VPMOVQB | Opcode::VPMOVQW | Opcode::VGF2P8MULB | Opcode::VPMADD52HUQ | Opcode::VPMADD52LUQ | Opcode::VPSHUFBITQMB | Opcode::VPERMB | Opcode::VPEXPANDD | Opcode::VPEXPANDQ | Opcode::VPABSQ | Opcode::VPRORVD | Opcode::VPRORVQ | Opcode::VPMULTISHIFTQB | Opcode::VPERMT2B | Opcode::VPERMT2W | Opcode::VPSHRDVQ | Opcode::VPSHRDVD | Opcode::VPSHRDVW | Opcode::VPSHLDVQ | Opcode::VPSHLDVD | Opcode::VPSHLDVW | Opcode::VPCOMPRESSB | Opcode::VPCOMPRESSW | Opcode::VPEXPANDB | Opcode::VPEXPANDW | Opcode::VPOPCNTD | Opcode::VPOPCNTQ | Opcode::VPOPCNTB | Opcode::VPOPCNTW | Opcode::VSCALEFSS | Opcode::VSCALEFSD | Opcode::VSCALEFPS | Opcode::VSCALEFPD | Opcode::VPDPBUSD | Opcode::VCVTUSI2SD | Opcode::VCVTUSI2SS | Opcode::VPXORD | Opcode::VPXORQ | Opcode::VPORD | Opcode::VPORQ | Opcode::VPANDND | Opcode::VPANDNQ | Opcode::VPANDD | Opcode::VPANDQ | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::HADDPD | Opcode::HSUBPD | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::PABSB | Opcode::PABSD | Opcode::PABSW | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::PSIGNB | Opcode::PSIGND | Opcode::PSIGNW | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::PCLMULQDQ | Opcode::PMULDQ | Opcode::PMULHRSW | Opcode::PMULLD | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VEXP2PD | Opcode::VEXP2PS | Opcode::VEXP2SD | Opcode::VEXP2SS | Opcode::VRCP28PD | Opcode::VRCP28PS | Opcode::VRCP28SD | Opcode::VRCP28SS | Opcode::VRCP14PD | Opcode::VRCP14PS | Opcode::VRCP14SD | Opcode::VRCP14SS | Opcode::VRNDSCALEPD | Opcode::VRNDSCALEPS | Opcode::VRNDSCALESD | Opcode::VRNDSCALESS | Opcode::VRSQRT14PD | Opcode::VRSQRT14PS | Opcode::VRSQRT14SD | Opcode::VRSQRT14SS | Opcode::VSCALEDPD | Opcode::VSCALEDPS | Opcode::VSCALEDSD | Opcode::VSCALEDSS | Opcode::VRSQRT28PD | Opcode::VRSQRT28PS | Opcode::VRSQRT28SD | Opcode::VRSQRT28SS | Opcode::VRSQRTPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VRCPSS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::ROUNDPD | Opcode::ROUNDPS | Opcode::ROUNDSD | Opcode::ROUNDSS | Opcode::VRSQRTSS | Opcode::VSQRTSD | Opcode::VSQRTSS | Opcode::VPSADBW | Opcode::VMPSADBW | Opcode::VDBPSADBW | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPMADDUBSW | Opcode::VPMADDWD | Opcode::VDPPD | Opcode::VDPPS | Opcode::VRCPPS | Opcode::VORPD | Opcode::VORPS | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VPAND | Opcode::VPANDN | Opcode::VPOR | Opcode::VPXOR | Opcode::VXORPD | Opcode::VXORPS | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPROLD | Opcode::VPROLQ | Opcode::VPROLVD | Opcode::VPROLVQ | Opcode::VPRORD | Opcode::VPRORQ | Opcode::VPRORRD | Opcode::VPRORRQ | Opcode::VPSLLVW | Opcode::VPSRAQ | Opcode::VPSRAVQ | Opcode::VPSRAVW | Opcode::VPSRLVW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::PHADDD | Opcode::PHADDSW | Opcode::PHADDW | Opcode::PHSUBD | Opcode::PHSUBSW | Opcode::PHSUBW | Opcode::PMADDUBSW | Opcode::ADDSUBPD | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::RCPSS | Opcode::RSQRTSS | Opcode::SQRTSD | Opcode::ADDSD | Opcode::SUBSD | Opcode::MULSD | Opcode::DIVSD | Opcode::SQRTSS | Opcode::ADDSS | Opcode::SUBSS | Opcode::MULSS | Opcode::DIVSS | Opcode::HADDPS | Opcode::HSUBPS | Opcode::ADDSUBPS | Opcode::PMULHRW | Opcode::PFRCP | Opcode::PFRSQRT | Opcode::PFSUB | Opcode::PFADD | Opcode::PFRCPIT1 | Opcode::PFRSQIT1 | Opcode::PFSUBR | Opcode::PFACC | Opcode::PFMUL | Opcode::PFMULHRW | Opcode::PFRCPIT2 | Opcode::PFNACC | Opcode::PFPNACC | Opcode::PSWAPD | Opcode::PAVGUSB | Opcode::XADD| Opcode::DIV | Opcode::IDIV | Opcode::MUL | Opcode::MULX | Opcode::NEG | Opcode::NOT | Opcode::SAR | Opcode::SAL | Opcode::SHR | Opcode::SARX | Opcode::SHLX | Opcode::SHRX | Opcode::SHRD | Opcode::SHL | Opcode::RCR | Opcode::RCL | Opcode::ROR | Opcode::RORX | Opcode::ROL | Opcode::INC | Opcode::DEC | Opcode::SBB | Opcode::AND | Opcode::XOR | Opcode::OR | Opcode::LEA | Opcode::ADD | Opcode::ADC | Opcode::ADCX | Opcode::ADOX | Opcode::SUB | Opcode::POPCNT | Opcode::LZCNT | Opcode::VPLZCNTD | Opcode::VPLZCNTQ | Opcode::BT | Opcode::BTS | Opcode::BTR | Opcode::BTC | Opcode::BSF | Opcode::BSR | Opcode::BZHI | Opcode::PDEP | Opcode::PEXT | Opcode::TZCNT | Opcode::ANDN | Opcode::BEXTR | Opcode::BLSI | Opcode::BLSMSK | Opcode::BLSR | Opcode::ADDPS | Opcode::ADDPD | Opcode::ANDNPS | Opcode::ANDNPD | Opcode::ANDPS | Opcode::ANDPD | Opcode::COMISD | Opcode::COMISS | Opcode::DIVPS | Opcode::DIVPD | Opcode::MULPS | Opcode::MULPD | Opcode::ORPS | Opcode::ORPD | Opcode::PADDB | Opcode::PADDD | Opcode::PADDQ | Opcode::PADDSB | Opcode::PADDSW | Opcode::PADDUSB | Opcode::PADDUSW | Opcode::PADDW | Opcode::PAND | Opcode::PANDN | Opcode::PAVGB | Opcode::PAVGW | Opcode::PMADDWD | Opcode::PMULHUW | Opcode::PMULHW | Opcode::PMULLW | Opcode::PMULUDQ | Opcode::POR | Opcode::PSADBW | Opcode::PSHUFD | Opcode::PSHUFW | Opcode::PSHUFB | Opcode::PSLLD | Opcode::PSLLDQ | Opcode::PSLLQ | Opcode::PSLLW | Opcode::PSRAD | Opcode::PSRAW | Opcode::PSRLD | Opcode::PSRLDQ | Opcode::PSRLQ | Opcode::PSRLW | Opcode::PSUBB | Opcode::PSUBD | Opcode::PSUBQ | Opcode::PSUBSB | Opcode::PSUBSW | Opcode::PSUBUSB | Opcode::PSUBUSW | Opcode::PSUBW | Opcode::PXOR | Opcode::RSQRTPS | Opcode::SQRTPS | Opcode::SQRTPD | Opcode::SUBPS | Opcode::SUBPD | Opcode::XORPS | Opcode::XORPD | Opcode::RCPPS | Opcode::SHLD | Opcode::SLHD | Opcode::UCOMISD | Opcode::UCOMISS | Opcode::F2XM1 | Opcode::FABS | Opcode::FADD | Opcode::FADDP | Opcode::FCHS | Opcode::FCOS | Opcode::FDIV | Opcode::FDIVP | Opcode::FDIVR | Opcode::FDIVRP | Opcode::FIADD | Opcode::FIDIV | Opcode::FIDIVR | Opcode::FIMUL | Opcode::FISUB | Opcode::FISUBR | Opcode::FMUL | Opcode::FMULP | Opcode::FNCLEX | Opcode::FNINIT | Opcode::FPATAN | Opcode::FPREM | Opcode::FPREM1 | Opcode::FPTAN | Opcode::FRNDINT | Opcode::FSCALE | Opcode::FSIN | Opcode::FSINCOS | Opcode::FSQRT | Opcode::FSUB | Opcode::FSUBP | Opcode::FSUBR | Opcode::FSUBRP | Opcode::FXTRACT | Opcode::FYL2X | Opcode::FYL2XP1 | Opcode::KADDB | Opcode::KANDB | Opcode::KANDNB | Opcode::KNOTB | Opcode::KORB | Opcode::KSHIFTLB | Opcode::KSHIFTRB | Opcode::KXNORB | Opcode::KXORB | Opcode::KADDW | Opcode::KANDW | Opcode::KANDNW | Opcode::KNOTW | Opcode::KORW | Opcode::KSHIFTLW | Opcode::KSHIFTRW | Opcode::KXNORW | Opcode::KXORW | Opcode::KADDD | Opcode::KANDD | Opcode::KANDND | Opcode::KNOTD | Opcode::KORD | Opcode::KSHIFTLD | Opcode::KSHIFTRD | Opcode::KXNORD | Opcode::KXORD | Opcode::KADDQ | Opcode::KANDQ | Opcode::KANDNQ | Opcode::KNOTQ | Opcode::KORQ | Opcode::KSHIFTLQ | Opcode::KSHIFTRQ | Opcode::KXNORQ | Opcode::KXORQ | Opcode::IMUL => { write!(out, "{}", colors.arithmetic_op(self)) } Opcode::POPF | Opcode::PUSHF | Opcode::ENTER | Opcode::LEAVE | Opcode::PUSH | Opcode::POP => { write!(out, "{}", colors.stack_op(self)) } Opcode::WAIT | Opcode::FNOP | Opcode::FDISI8087_NOP | Opcode::FENI8087_NOP | Opcode::FSETPM287_NOP | Opcode::PREFETCHNTA | Opcode::PREFETCH0 | Opcode::PREFETCH1 | Opcode::PREFETCH2 | Opcode::PREFETCHW | Opcode::NOP => { write!(out, "{}", colors.nop_op(self)) } /* Control flow */ Opcode::HLT | Opcode::INT | Opcode::INTO | Opcode::IRET | Opcode::IRETD | Opcode::IRETQ | Opcode::RETF | Opcode::RETURN => { write!(out, "{}", colors.stop_op(self)) } Opcode::LOOPNZ | Opcode::LOOPZ | Opcode::LOOP | Opcode::JRCXZ | Opcode::CALL | Opcode::CALLF | Opcode::JMP | Opcode::JMPF | Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JLE | Opcode::JG => { write!(out, "{}", colors.control_flow_op(self)) } /* Data transfer */ Opcode::PI2FW | Opcode::PI2FD | Opcode::PF2ID | Opcode::PF2IW | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2DQ | Opcode::VCVTPD2PS | Opcode::VCVTPH2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTPS2PH | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSI2SD | Opcode::VCVTSI2SS | Opcode::VCVTSS2SD | Opcode::VCVTSS2SI | Opcode::VCVTTSD2SI | Opcode::VCVTTSS2SI | Opcode::VCVTPD2UDQ | Opcode::VCVTTPD2UDQ | Opcode::VCVTPS2UDQ | Opcode::VCVTTPS2UDQ | Opcode::VCVTQQ2PD | Opcode::VCVTQQ2PS | Opcode::VCVTSD2USI | Opcode::VCVTTSD2USI | Opcode::VCVTSS2USI | Opcode::VCVTTSS2USI | Opcode::VCVTUDQ2PD | Opcode::VCVTUDQ2PS | Opcode::VCVTUSI2USD | Opcode::VCVTUSI2USS | Opcode::VCVTTPD2QQ | Opcode::VCVTPD2QQ | Opcode::VCVTTPD2UQQ | Opcode::VCVTPD2UQQ | Opcode::VCVTTPS2QQ | Opcode::VCVTPS2QQ | Opcode::VCVTTPS2UQQ | Opcode::VCVTPS2UQQ | Opcode::VCVTUQQ2PD | Opcode::VCVTUQQ2PS | Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VBLENDMPD | Opcode::VBLENDMPS | Opcode::VPBLENDMD | Opcode::VPBLENDMQ | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VPBLENDMB | Opcode::VPBLENDMW | Opcode::PBLENDVB | Opcode::PBLENDW | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::BLENDW | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VPBROADCASTM | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::EXTRACTPS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VGATHERPF0DPD | Opcode::VGATHERPF0DPS | Opcode::VGATHERPF0QPD | Opcode::VGATHERPF0QPS | Opcode::VGATHERPF1DPD | Opcode::VGATHERPF1DPS | Opcode::VGATHERPF1QPD | Opcode::VGATHERPF1QPS | Opcode::VSCATTERDD | Opcode::VSCATTERDQ | Opcode::VSCATTERQD | Opcode::VSCATTERQQ | Opcode::VPSCATTERDD | Opcode::VPSCATTERDQ | Opcode::VPSCATTERQD | Opcode::VPSCATTERQQ | Opcode::VSCATTERPF0DPD | Opcode::VSCATTERPF0DPS | Opcode::VSCATTERPF0QPD | Opcode::VSCATTERPF0QPS | Opcode::VSCATTERPF1DPD | Opcode::VSCATTERPF1DPS | Opcode::VSCATTERPF1QPD | Opcode::VSCATTERPF1QPS | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::INSERTPS | Opcode::VEXTRACTF32X4 | Opcode::VEXTRACTF64X2 | Opcode::VEXTRACTF64X4 | Opcode::VEXTRACTI32X4 | Opcode::VEXTRACTI64X2 | Opcode::VEXTRACTI64X4 | Opcode::VINSERTF32X4 | Opcode::VINSERTF64X2 | Opcode::VINSERTF64X4 | Opcode::VINSERTI64X2 | Opcode::VINSERTI64X4 | Opcode::VSHUFF32X4 | Opcode::VSHUFF64X2 | Opcode::VSHUFI32X4 | Opcode::VSHUFI64X2 | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::MOVDIR64B | Opcode::MOVDIRI | Opcode::MOVNTDQA | Opcode::VMOVQ | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMOVSD | Opcode::VMOVSS | Opcode::VMOVDQA32 | Opcode::VMOVDQA64 | Opcode::VMOVDQU32 | Opcode::VMOVDQU64 | Opcode::VPMOVM2B | Opcode::VPMOVM2W | Opcode::VPMOVB2M | Opcode::VPMOVW2M | Opcode::VPMOVSWB | Opcode::VPMOVUSWB | Opcode::VPMOVSQB | Opcode::VPMOVUSQB | Opcode::VPMOVSQW | Opcode::VPMOVUSQW | Opcode::VPMOVSQD | Opcode::VPMOVUSQD | Opcode::VPMOVSDB | Opcode::VPMOVUSDB | Opcode::VPMOVSDW | Opcode::VPMOVUSDW | Opcode::VPMOVM2D | Opcode::VPMOVM2Q | Opcode::VPMOVB2D | Opcode::VPMOVQ2M | Opcode::VMOVDQU8 | Opcode::VMOVDQU16 | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPCLMULQDQ | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::PMOVSXBD | Opcode::PMOVSXBQ | Opcode::PMOVSXBW | Opcode::PMOVSXDQ | Opcode::PMOVSXWD | Opcode::PMOVSXWQ | Opcode::PMOVZXBD | Opcode::PMOVZXBQ | Opcode::PMOVZXBW | Opcode::PMOVZXDQ | Opcode::PMOVZXWD | Opcode::PMOVZXWQ | Opcode::KUNPCKBW | Opcode::KUNPCKWD | Opcode::KUNPCKDQ | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::PACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VALIGND | Opcode::VALIGNQ | Opcode::VPALIGNR | Opcode::PALIGNR | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPERMI2D | Opcode::VPERMI2Q | Opcode::VPERMI2PD | Opcode::VPERMI2PS | Opcode::VPERMT2D | Opcode::VPERMT2Q | Opcode::VPERMT2PD | Opcode::VPERMT2PS | Opcode::VPERMI2B | Opcode::VPERMI2W | Opcode::VPERMW | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::PEXTRB | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::EXTRQ | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::INSERTQ | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VCOMPRESSPD | Opcode::VCOMPRESSPS | Opcode::VPCOMPRESSQ | Opcode::VPCOMPRESSD | Opcode::VEXPANDPD | Opcode::VEXPANDPS | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPHMINPOSUW | Opcode::PHMINPOSUW | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VFIXUPIMMPD | Opcode::VFIXUPIMMPS | Opcode::VFIXUPIMMSD | Opcode::VFIXUPIMMSS | Opcode::VREDUCEPD | Opcode::VREDUCEPS | Opcode::VREDUCESD | Opcode::VREDUCESS | Opcode::VGETEXPPD | Opcode::VGETEXPPS | Opcode::VGETEXPSD | Opcode::VGETEXPSS | Opcode::VGETMANTPD | Opcode::VGETMANTPS | Opcode::VGETMANTSD | Opcode::VGETMANTSS | Opcode::VLDDQU | Opcode::BSWAP | Opcode::CVTDQ2PD | Opcode::CVTDQ2PS | Opcode::CVTPS2DQ | Opcode::CVTPD2DQ | Opcode::CVTPI2PS | Opcode::CVTPI2PD | Opcode::CVTPS2PD | Opcode::CVTPD2PS | Opcode::CVTPS2PI | Opcode::CVTPD2PI | Opcode::CVTSD2SI | Opcode::CVTSD2SS | Opcode::CVTSI2SD | Opcode::CVTSI2SS | Opcode::CVTSS2SD | Opcode::CVTSS2SI | Opcode::CVTTPD2DQ | Opcode::CVTTPS2DQ | Opcode::CVTTPS2PI | Opcode::CVTTPD2PI | Opcode::CVTTSD2SI | Opcode::CVTTSS2SI | Opcode::MASKMOVQ | Opcode::MASKMOVDQU | Opcode::MOVAPS | Opcode::MOVAPD | Opcode::MOVD | Opcode::MOVHPS | Opcode::MOVHPD | Opcode::MOVHLPS | Opcode::MOVLPS | Opcode::MOVLPD | Opcode::MOVLHPS | Opcode::MOVMSKPS | Opcode::MOVMSKPD | Opcode::MOVNTI | Opcode::MOVNTPS | Opcode::MOVNTPD | Opcode::MOVNTSS | Opcode::MOVNTSD | Opcode::MOVNTQ | Opcode::MOVNTDQ | Opcode::MOVSD | Opcode::MOVSS | Opcode::MOVUPD | Opcode::PSHUFHW | Opcode::PSHUFLW | Opcode::PUNPCKHBW | Opcode::PUNPCKHDQ | Opcode::PUNPCKHWD | Opcode::PUNPCKLBW | Opcode::PUNPCKLDQ | Opcode::PUNPCKLWD | Opcode::PUNPCKLQDQ | Opcode::PUNPCKHQDQ | Opcode::PACKSSDW | Opcode::PACKSSWB | Opcode::PACKUSWB | Opcode::UNPCKHPS | Opcode::UNPCKHPD | Opcode::UNPCKLPS | Opcode::UNPCKLPD | Opcode::SHUFPD | Opcode::SHUFPS | Opcode::PMOVMSKB | Opcode::KMOVB | Opcode::KMOVW | Opcode::KMOVD | Opcode::KMOVQ | Opcode::BNDMOV | Opcode::LDDQU | Opcode::CMC | Opcode::CLC | Opcode::CLI | Opcode::CLD | Opcode::STC | Opcode::STI | Opcode::STD | Opcode::CBW | Opcode::CWDE | Opcode::CDQE | Opcode::CWD | Opcode::CDQ | Opcode::CQO | Opcode::MOVDDUP | Opcode::MOVSLDUP | Opcode::MOVDQ2Q | Opcode::MOVDQU | Opcode::MOVDQA | Opcode::MOVQ | Opcode::MOVQ2DQ | Opcode::MOVSHDUP | Opcode::MOVUPS | Opcode::PEXTRW | Opcode::PINSRW | Opcode::MOV | Opcode::MOVBE | Opcode::LODS | Opcode::STOS | Opcode::LAHF | Opcode::SAHF | Opcode::MOVS | Opcode::INS | Opcode::IN | Opcode::OUTS | Opcode::OUT | Opcode::MOVZX | Opcode::MOVSX | Opcode::MOVSXD | Opcode::FILD | Opcode::FBLD | Opcode::FBSTP | Opcode::FIST | Opcode::FISTP | Opcode::FISTTP | Opcode::FLD | Opcode::FLD1 | Opcode::FLDCW | Opcode::FLDENV | Opcode::FLDL2E | Opcode::FLDL2T | Opcode::FLDLG2 | Opcode::FLDLN2 | Opcode::FLDPI | Opcode::FLDZ | Opcode::FST | Opcode::FSTP | Opcode::FSTPNCE | Opcode::FNSAVE | Opcode::FNSTCW | Opcode::FNSTENV | Opcode::FNSTOR | Opcode::FNSTSW | Opcode::FRSTOR | Opcode::FXCH | Opcode::XCHG | Opcode::XLAT | Opcode::CMOVA | Opcode::CMOVB | Opcode::CMOVG | Opcode::CMOVGE | Opcode::CMOVL | Opcode::CMOVLE | Opcode::CMOVNA | Opcode::CMOVNB | Opcode::CMOVNO | Opcode::CMOVNP | Opcode::CMOVNS | Opcode::CMOVNZ | Opcode::CMOVO | Opcode::CMOVP | Opcode::CMOVS | Opcode::CMOVZ | Opcode::FCMOVB | Opcode::FCMOVBE | Opcode::FCMOVE | Opcode::FCMOVNB | Opcode::FCMOVNBE | Opcode::FCMOVNE | Opcode::FCMOVNU | Opcode::FCMOVU | Opcode::SALC | Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETBE | Opcode::SETA | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETLE | Opcode::SETG => { write!(out, "{}", colors.data_op(self)) } Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::KORTESTB | Opcode::KTESTB | Opcode::KORTESTW | Opcode::KTESTW | Opcode::KORTESTD | Opcode::KTESTD | Opcode::KORTESTQ | Opcode::KTESTQ | Opcode::VPTESTNMD | Opcode::VPTESTNMQ | Opcode::VPTERNLOGD | Opcode::VPTERNLOGQ | Opcode::VPTESTMD | Opcode::VPTESTMQ | Opcode::VPTESTNMB | Opcode::VPTESTNMW | Opcode::VPTESTMB | Opcode::VPTESTMW | Opcode::VPCMPD | Opcode::VPCMPUD | Opcode::VPCMPQ | Opcode::VPCMPUQ | Opcode::VPCMPB | Opcode::VPCMPUB | Opcode::VPCMPW | Opcode::VPCMPUW | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VPMAXSQ | Opcode::VPMAXUQ | Opcode::VPMINSQ | Opcode::VPMINUQ | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VFPCLASSPD | Opcode::VFPCLASSPS | Opcode::VFPCLASSSD | Opcode::VFPCLASSSS | Opcode::VRANGEPD | Opcode::VRANGEPS | Opcode::VRANGESD | Opcode::VRANGESS | Opcode::VPCONFLICTD | Opcode::VPCONFLICTQ | Opcode::VPTEST | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::PCMPEQB | Opcode::PCMPEQD | Opcode::PCMPEQQ | Opcode::PCMPEQW | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPGTB | Opcode::PCMPGTD | Opcode::PCMPGTQ | Opcode::PCMPGTW | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PTEST | Opcode::MAXPD | Opcode::MAXPS | Opcode::MAXSD | Opcode::MAXSS | Opcode::MINPD | Opcode::MINPS | Opcode::MINSD | Opcode::MINSS | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::PMAXSW | Opcode::PMAXUB | Opcode::PMAXUD | Opcode::PMAXUW | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMINSW | Opcode::PMINUB | Opcode::PMINUD | Opcode::PMINUW | Opcode::PFCMPGE | Opcode::PFMIN | Opcode::PFCMPGT | Opcode::PFMAX | Opcode::PFCMPEQ | Opcode::CMPS | Opcode::SCAS | Opcode::TEST | Opcode::FTST | Opcode::FXAM | Opcode::FUCOM | Opcode::FUCOMI | Opcode::FUCOMIP | Opcode::FUCOMP | Opcode::FUCOMPP | Opcode::FCOM | Opcode::FCOMI | Opcode::FCOMIP | Opcode::FCOMP | Opcode::FCOMPP | Opcode::FICOM | Opcode::FICOMP | Opcode::CMPSD | Opcode::CMPSS | Opcode::CMP | Opcode::CMPPS | Opcode::CMPPD | Opcode::CMPXCHG8B | Opcode::CMPXCHG16B | Opcode::CMPXCHG => { write!(out, "{}", colors.comparison_op(self)) } Opcode::WRMSR | Opcode::RDMSR | Opcode::RDTSC | Opcode::RDPMC | Opcode::RDPID | Opcode::RDFSBASE | Opcode::RDGSBASE | Opcode::WRFSBASE | Opcode::WRGSBASE | Opcode::FXSAVE | Opcode::FXRSTOR | Opcode::LDMXCSR | Opcode::STMXCSR | Opcode::VLDMXCSR | Opcode::VSTMXCSR | Opcode::XSAVE | Opcode::XSAVEC | Opcode::XSAVES | Opcode::XSAVEC64 | Opcode::XSAVES64 | Opcode::XRSTOR | Opcode::XRSTORS | Opcode::XRSTORS64 | Opcode::XSAVEOPT | Opcode::LFENCE | Opcode::MFENCE | Opcode::SFENCE | Opcode::CLFLUSH | Opcode::CLFLUSHOPT | Opcode::CLWB | Opcode::SGDT | Opcode::SIDT | Opcode::LGDT | Opcode::LIDT | Opcode::SMSW | Opcode::LMSW | Opcode::SWAPGS | Opcode::RDTSCP | Opcode::INVEPT | Opcode::INVVPID | Opcode::INVPCID | Opcode::INVLPG | Opcode::INVLPGA | Opcode::INVLPGB | Opcode::TLBSYNC | Opcode::PSMASH | Opcode::PVALIDATE | Opcode::RMPADJUST | Opcode::RMPUPDATE | Opcode::CPUID | Opcode::WBINVD | Opcode::INVD | Opcode::SYSRET | Opcode::CLTS | Opcode::SYSCALL | Opcode::TDCALL | Opcode::SEAMRET | Opcode::SEAMOPS | Opcode::SEAMCALL | Opcode::TPAUSE | Opcode::UMONITOR | Opcode::UMWAIT | Opcode::LSL | Opcode::SLDT | Opcode::STR | Opcode::LLDT | Opcode::LTR | Opcode::VERR | Opcode::VERW | Opcode::JMPE | Opcode::EMMS | Opcode::FEMMS | Opcode::GETSEC | Opcode::LFS | Opcode::LGS | Opcode::LSS | Opcode::RSM | Opcode::SYSENTER | Opcode::SYSEXIT | Opcode::VMREAD | Opcode::VMWRITE | Opcode::VMCLEAR | Opcode::VMPTRLD | Opcode::VMPTRST | Opcode::VMXON | Opcode::VMCALL | Opcode::VMLAUNCH | Opcode::VMRESUME | Opcode::VMLOAD | Opcode::VMMCALL | Opcode::VMSAVE | Opcode::VMRUN | Opcode::VMXOFF | Opcode::PCONFIG | Opcode::MONITOR | Opcode::MWAIT | Opcode::MONITORX | Opcode::MWAITX | Opcode::SKINIT | Opcode::CLGI | Opcode::STGI | Opcode::CLAC | Opcode::STAC | Opcode::ENCLS | Opcode::ENCLV | Opcode::XGETBV | Opcode::XSETBV | Opcode::VMFUNC | Opcode::XEND | Opcode::XTEST | Opcode::XABORT | Opcode::XBEGIN | Opcode::ENCLU | Opcode::RDPKRU | Opcode::WRPKRU | Opcode::RDPRU | Opcode::CLZERO | Opcode::ENQCMD | Opcode::ENQCMDS | Opcode::PTWRITE | Opcode::UIRET | Opcode::TESTUI | Opcode::CLUI | Opcode::STUI | Opcode::SENDUIPI | Opcode::XSUSLDTRK | Opcode::XRESLDTRK | Opcode::BNDMK | Opcode::BNDCL | Opcode::BNDCU | Opcode::BNDCN | Opcode::BNDLDX | Opcode::BNDSTX | Opcode::LAR => { write!(out, "{}", colors.platform_op(self)) } Opcode::CRC32 | Opcode::RDSEED | Opcode::RDRAND | Opcode::SHA1RNDS4 | Opcode::SHA1NEXTE | Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA256RNDS2 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::FFREE | Opcode::FFREEP | Opcode::FDECSTP | Opcode::FINCSTP | Opcode::GF2P8MULB | Opcode::GF2P8AFFINEQB | Opcode::GF2P8AFFINEINVQB | Opcode::AESDEC128KL | Opcode::AESDEC256KL | Opcode::AESDECWIDE128KL | Opcode::AESDECWIDE256KL | Opcode::AESENC128KL | Opcode::AESENC256KL | Opcode::AESENCWIDE128KL | Opcode::AESENCWIDE256KL | Opcode::ENCODEKEY128 | Opcode::ENCODEKEY256 | Opcode::LOADIWKEY | Opcode::HRESET | Opcode::WRUSS | Opcode::WRSS | Opcode::INCSSP | Opcode::SAVEPREVSSP | Opcode::SETSSBSY | Opcode::CLRSSBSY | Opcode::RSTORSSP | Opcode::ENDBR64 | Opcode::ENDBR32 | Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST | Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { write!(out, "{}", colors.misc_op(self)) } Opcode::UD0 | Opcode::UD1 | Opcode::UD2 | Opcode::Invalid => { write!(out, "{}", colors.invalid_op(self)) } } } } impl fmt::Display for Instruction { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.display_with(DisplayStyle::Intel).colorize(&NoColors, fmt) } } impl<'instr> fmt::Display for InstructionDisplayer<'instr> { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } /// enum controlling how `Instruction::display_with` renders instructions. `Intel` is more or less /// intel syntax, though memory operand sizes are elided if they can be inferred from other /// operands. #[derive(Copy, Clone)] pub enum DisplayStyle { /// intel-style syntax for instructions, like /// `add rax, [rdx + rcx * 2 + 0x1234]` Intel, /// C-style syntax for instructions, like /// `rax += [rdx + rcx * 2 + 0x1234]` C, // one might imagine an ATT style here, which is mostly interesting for reversing operand // order. // well. // it also complicates memory operands in an offset-only operand, and is just kind of awful, so // it's just not implemented yet. // ATT, } /// implementation of [`Display`](fmt::Display) that renders instructions using a specified display /// style. pub struct InstructionDisplayer<'instr> { pub(crate) instr: &'instr Instruction, pub(crate) style: DisplayStyle, } /* * Can't implement this as accepting a formatter because rust * doesn't let me build one outside println! or write! or whatever. * * can't write this as an intermediate struct because i refuse to copy * all data into the struct, and having a function producing a struct with * some lifetimes gets really hairy if it's from a trait - same GAT kind * of nonsense as i saw with ContextRead, because someone could hold onto * the dang intermediate struct forever. * * so write to some Write thing i guess. bite me. i really just want to * stop thinking about how to support printing instructions... */ impl <'instr, T: fmt::Write, Y: YaxColors> Colorize for InstructionDisplayer<'instr> { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { // TODO: I DONT LIKE THIS, there is no address i can give contextualize here, // the address operand maybe should be optional.. self.contextualize(colors, 0, Some(&NoContext), out) } } /// No per-operand context when contextualizing an instruction! struct NoContext; impl Instruction { pub fn write_to(&self, out: &mut T) -> fmt::Result { self.display_with(DisplayStyle::Intel).contextualize(&NoColors, 0, Some(&NoContext), out) } } fn contextualize_intel(instr: &Instruction, colors: &Y, _address: u64, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { if instr.xacquire() { out.write_str("xacquire ")?; } if instr.xrelease() { out.write_str("xrelease ")?; } if instr.prefixes.lock() { out.write_str("lock ")?; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { if instr.prefixes.rep() { write!(out, "rep ")?; } else if instr.prefixes.repnz() { write!(out, "repnz ")?; } } } out.write_str(instr.opcode.name())?; if instr.opcode == Opcode::XBEGIN { if (instr.imm as i32) >= 0 { return write!(out, " $+{}", colors.number(signed_i32_hex(instr.imm as i32))); } else { return write!(out, " ${}", colors.number(signed_i32_hex(instr.imm as i32))); } } if instr.operand_count > 0 { out.write_str(" ")?; let x = Operand::from_spec(instr, instr.operands[0]); const RELATIVE_BRANCHES: [Opcode; 21] = [ Opcode::JMP, Opcode::JRCXZ, Opcode::LOOP, Opcode::LOOPZ, Opcode::LOOPNZ, Opcode::JO, Opcode::JNO, Opcode::JB, Opcode::JNB, Opcode::JZ, Opcode::JNZ, Opcode::JNA, Opcode::JA, Opcode::JS, Opcode::JNS, Opcode::JP, Opcode::JNP, Opcode::JL, Opcode::JGE, Opcode::JLE, Opcode::JG, ]; if instr.operands[0] == OperandSpec::ImmI8 || instr.operands[0] == OperandSpec::ImmI32 { if RELATIVE_BRANCHES.contains(&instr.opcode) { return match x { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } _ => { unreachable!() } }; } } if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; for i in 1..instr.operand_count { match instr.opcode { _ => { match &instr.operands[i as usize] { &OperandSpec::Nothing => { return Ok(()); }, _ => { out.write_str(", ")?; let x = Operand::from_spec(instr, instr.operands[i as usize]); if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(i) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; if let Some(evex) = instr.prefixes.evex() { if evex.broadcast() && x.is_memory() { let scale = if instr.opcode == Opcode::VCVTPD2PS || instr.opcode == Opcode::VCVTTPD2UDQ || instr.opcode == Opcode::VCVTPD2UDQ || instr.opcode == Opcode::VCVTUDQ2PD || instr.opcode == Opcode::VCVTPS2PD || instr.opcode == Opcode::VCVTQQ2PS || instr.opcode == Opcode::VCVTDQ2PD || instr.opcode == Opcode::VCVTTPD2DQ || instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VFPCLASSPD || instr.opcode == Opcode::VCVTNEPS2BF16 || instr.opcode == Opcode::VCVTUQQ2PS || instr.opcode == Opcode::VCVTPD2DQ || instr.opcode == Opcode::VCVTTPS2UQQ || instr.opcode == Opcode::VCVTPS2UQQ || instr.opcode == Opcode::VCVTTPS2QQ || instr.opcode == Opcode::VCVTPS2QQ { if instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VCVTNEPS2BF16 { if evex.vex().l() { 8 } else if evex.lp() { 16 } else { 4 } } else if instr.opcode == Opcode::VFPCLASSPD { if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } else { // vcvtpd2ps is "cool": in broadcast mode, it can read a // double-precision float (qword), resize to single-precision, // then broadcast that to the whole destination register. this // means we need to show `xmm, qword [addr]{1to4}` if vector // size is 256. likewise, scale of 8 for the same truncation // reason if vector size is 512. // vcvtudq2pd is the same story. // vfpclassp{s,d} is a mystery to me. if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } } else { // this should never be `None` - that would imply two // memory operands for a broadcasted operation. if let Some(width) = Operand::from_spec(instr, instr.operands[i as usize - 1]).width() { width / instr.mem_size } else { 0 } }; write!(out, "{{1to{}}}", scale)?; } } } } } } } } Ok(()) } fn contextualize_c(instr: &Instruction, colors: &Y, _address: u64, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { let mut brace_count = 0; let mut prefixed = false; if instr.xacquire() { out.write_str("xacquire ")?; prefixed = true; } if instr.xrelease() { out.write_str("xrelease ")?; prefixed = true; } if instr.prefixes.lock() { out.write_str("lock ")?; prefixed = true; } if prefixed { out.write_str("{ ")?; brace_count += 1; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { let word_str = match instr.mem_size { 1 => "byte", 2 => "word", 4 => "dword", 8 => "qword", _ => { unreachable!("invalid word size") } }; // only a few of you actually use the prefix... if instr.prefixes.rep() { out.write_str("rep ")?; } else if instr.prefixes.repnz() { out.write_str("repnz ")?; } // TODO: other rep kinds? out.write_str(word_str)?; out.write_str(" { ")?; brace_count += 1; } } fn write_jmp_operand(op: Operand, colors: &Y, out: &mut T) -> fmt::Result { match op { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } other => { write!(out, "{}", other) } } } match instr.opcode { Opcode::Invalid => { out.write_str("invalid")?; }, Opcode::MOVS => { out.write_str("es:[rdi++] = ds:[rsi++]")?; }, Opcode::CMPS => { out.write_str("rflags = flags(ds:[rsi++] - es:[rdi++])")?; }, Opcode::LODS => { // TODO: size out.write_str("rax = ds:[rsi++]")?; }, Opcode::STOS => { // TODO: size out.write_str("es:[rdi++] = rax")?; }, Opcode::INS => { // TODO: size out.write_str("es:[rdi++] = port(dx)")?; }, Opcode::OUTS => { // TODO: size out.write_str("port(dx) = ds:[rsi++]")?; } Opcode::ADD => { write!(out, "{} += {}", instr.operand(0), instr.operand(1))?; } Opcode::OR => { write!(out, "{} |= {}", instr.operand(0), instr.operand(1))?; } Opcode::ADC => { write!(out, "{} += {} + rflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADCX => { write!(out, "{} += {} + rflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADOX => { write!(out, "{} += {} + rflags.of", instr.operand(0), instr.operand(1))?; } Opcode::SBB => { write!(out, "{} -= {} + rflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::AND => { write!(out, "{} &= {}", instr.operand(0), instr.operand(1))?; } Opcode::XOR => { write!(out, "{} ^= {}", instr.operand(0), instr.operand(1))?; } Opcode::SUB => { write!(out, "{} -= {}", instr.operand(0), instr.operand(1))?; } Opcode::CMP => { write!(out, "rflags = flags({} - {})", instr.operand(0), instr.operand(1))?; } Opcode::TEST => { write!(out, "rflags = flags({} & {})", instr.operand(0), instr.operand(1))?; } Opcode::XADD => { write!(out, "({}, {}) = ({} + {}, {})", instr.operand(0), instr.operand(1), instr.operand(0), instr.operand(1), instr.operand(0))?; } Opcode::BT => { write!(out, "bt")?; } Opcode::BTS => { write!(out, "bts")?; } Opcode::BTC => { write!(out, "btc")?; } Opcode::BSR => { write!(out, "{} = msb({})", instr.operand(0), instr.operand(1))?; } Opcode::BSF => { write!(out, "{} = lsb({}) (x86 bsf)", instr.operand(0), instr.operand(1))?; } Opcode::TZCNT => { write!(out, "{} = lsb({})", instr.operand(0), instr.operand(1))?; } Opcode::MOV => { write!(out, "{} = {}", instr.operand(0), instr.operand(1))?; } Opcode::SAR => { write!(out, "{} = {} >>> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SAL => { write!(out, "{} = {} <<< {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHR => { write!(out, "{} = {} >> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHRX => { write!(out, "{} = {} >> {} (x86 shrx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::SHL => { write!(out, "{} = {} << {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHLX => { write!(out, "{} = {} << {} (x86 shlx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROR => { write!(out, "{} = {} ror {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RORX => { write!(out, "{} = {} ror {} (x86 rorx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROL => { write!(out, "{} = {} rol {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCR => { write!(out, "{} = {} rcr {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCL => { write!(out, "{} = {} rcl {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::PUSH => { write!(out, "push({})", instr.operand(0))?; } Opcode::POP => { write!(out, "{} = pop()", instr.operand(0))?; } Opcode::MOVD => { write!(out, "{} = movd({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVQ => { write!(out, "{} = movq({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVNTQ => { write!(out, "{} = movntq({})", instr.operand(0), instr.operand(1))?; } Opcode::INC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}++", instr.operand(0))?; }, 2 => { write!(out, "word {}++", instr.operand(0))?; }, 4 => { write!(out, "dword {}++", instr.operand(0))?; }, _ => { write!(out, "qword {}++", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}++", instr.operand(0))?; } } Opcode::DEC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}--", instr.operand(0))?; }, 2 => { write!(out, "word {}--", instr.operand(0))?; }, 4 => { write!(out, "dword {}--", instr.operand(0))?; }, _ => { write!(out, "qword {}--", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}--", instr.operand(0))?; } } Opcode::JMP => { out.write_str("jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JRCXZ => { out.write_str("if rcx == 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOP => { out.write_str("rcx--; if rcx != 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPZ => { out.write_str("rcx--; if rcx != 0 and zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPNZ => { out.write_str("rcx--; if rcx != 0 and !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JB => { out.write_str("if /* unsigned */ below(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNB => { out.write_str("if /* unsigned */ above_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JZ => { out.write_str("if zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNZ => { out.write_str("if !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNA => { out.write_str("if /* unsigned */ below_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JA => { out.write_str("if /* unsigned */ above(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JS => { out.write_str("if signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNS => { out.write_str("if !signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JP => { out.write_str("if parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNP => { out.write_str("if !parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JL => { out.write_str("if /* signed */ less(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JGE => { out.write_str("if /* signed */ greater_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JLE => { out.write_str("if /* signed */ less_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JG => { out.write_str("if /* signed */ greater(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::NOP => { write!(out, "nop")?; } _ => { if instr.operand_count() == 0 { write!(out, "{}()", instr.opcode())?; } else { write!(out, "{} = {}({}", instr.operand(0), instr.opcode(), instr.operand(0))?; let mut comma = true; for i in 1..instr.operand_count() { if comma { write!(out, ", ")?; } write!(out, "{}", instr.operand(i))?; comma = true; } write!(out, ")")?; } } } while brace_count > 0 { out.write_str(" }")?; brace_count -= 1; } Ok(()) } impl <'instr, T: fmt::Write, Y: YaxColors> ShowContextual for InstructionDisplayer<'instr> { fn contextualize(&self, colors: &Y, address: u64, context: Option<&NoContext>, out: &mut T) -> fmt::Result { let InstructionDisplayer { instr, style, } = self; match style { DisplayStyle::Intel => { contextualize_intel(instr, colors, address, context, out) } DisplayStyle::C => { contextualize_c(instr, colors, address, context, out) } } } } #[cfg(feature="std")] impl ShowContextual], T, Y> for Instruction { fn contextualize(&self, colors: &Y, _address: u64, context: Option<&[Option]>, out: &mut T) -> fmt::Result { if self.prefixes.lock() { write!(out, "lock ")?; } if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&self.opcode) { // only a few of you actually use the prefix... if self.prefixes.rep() { write!(out, "rep ")?; } else if self.prefixes.repnz() { write!(out, "repnz ")?; } } self.opcode.colorize(colors, out)?; match context.and_then(|xs| xs[0].as_ref()) { Some(s) => { write!(out, " {}", s)?; }, None => { match self.operands[0] { OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, " ")?; if let Some(prefix) = self.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } } } let x = Operand::from_spec(self, self.operands[0]); x.colorize(colors, out)?; } }; for i in 1..self.operand_count { let i = i as usize; match context.and_then(|xs| xs[i].as_ref()) { Some(s) => { write!(out, ", {}", s)? } None => { match &self.operands[i] { &OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, ", ")?; if let Some(prefix) = self.segment_override_for_op(1) { write!(out, "{}:", prefix)?; } let x = Operand::from_spec(self, self.operands[i]); x.colorize(colors, out)? } } } } } Ok(()) } } yaxpeax-x86-1.2.2/src/long_mode/evex/generated.rs000064400000000000000000002641761046102023000177550ustar 00000000000000use crate::long_mode::Opcode; use crate::long_mode::evex::EVEXOperandCode; pub(crate) const TABLES: [&'static [[(Opcode, EVEXOperandCode); 8]; 256]; 12] = [ &DUMMY, &DUMMY, &DUMMY, &DUMMY, &DUMMY, &DUMMY, &DUMMY, &DUMMY, &DUMMY, &EVEX_66_0f3a, &DUMMY, &DUMMY, ]; pub(crate) const DUMMY: [[(Opcode, EVEXOperandCode); 8]; 256] = [ [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], [(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing),(Opcode::Invalid, EVEXOperandCode::Nothing)], ]; yaxpeax-x86-1.2.2/src/long_mode/evex.rs000064400000000000000000000007661046102023000160100ustar 00000000000000// use crate::long_mode::{OperandSpec, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::long_mode::{Arch, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::long_mode::{read_modrm, read_E_vex, read_imm_unsigned}; use yaxpeax_arch::Reader; const DEFAULT_EVEX_REGISTER_SIZE: RegisterBank = RegisterBank::Q; const DEFAULT_EVEX_REGISTER_WIDTH: u8 = 8; fn isa_has_qwords() -> bool { true } include!("../shared/generated_evex.in"); include!("../shared/evex.in"); yaxpeax-x86-1.2.2/src/long_mode/mod.rs000064400000000000000000020311641046102023000156160ustar 00000000000000mod vex; mod evex; #[cfg(feature = "fmt")] mod display; pub mod uarch; pub use crate::MemoryAccessSize; #[cfg(feature = "fmt")] pub use self::display::{DisplayStyle, InstructionDisplayer}; use core::cmp::PartialEq; use crate::safer_unchecked::unreachable_kinda_unchecked as unreachable_unchecked; use yaxpeax_arch::{AddressDiff, Decoder, Reader, LengthedInstruction}; use yaxpeax_arch::annotation::{AnnotatingDecoder, DescriptionSink, NullSink}; use yaxpeax_arch::{DecodeError as ArchDecodeError}; use core::fmt; impl fmt::Display for DecodeError { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.description()) } } /// an `x86_64` register, including its number and type. if `fmt` is enabled, name too. /// /// ``` /// use yaxpeax_x86::long_mode::{RegSpec, register_class}; /// /// assert_eq!(RegSpec::ecx().num(), 1); /// assert_eq!(RegSpec::ecx().class(), register_class::D); /// ``` /// /// some registers have classes of their own, and only one member: `rip`, `eip`, `rflags`, and /// `eflags`. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, PartialOrd, Ord, Eq, PartialEq)] pub struct RegSpec { num: u8, bank: RegisterBank } use core::hash::Hash; use core::hash::Hasher; impl Hash for RegSpec { fn hash(&self, state: &mut H) { let code = ((self.bank as u16) << 8) | (self.num as u16); code.hash(state); } } /// the condition for a conditional instruction. /// /// these are only obtained through [`Opcode::condition()`]: /// ``` /// use yaxpeax_x86::long_mode::{Opcode, ConditionCode}; /// /// assert_eq!(Opcode::JB.condition(), Some(ConditionCode::B)); /// ``` #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] pub enum ConditionCode { O, NO, B, AE, Z, NZ, A, BE, S, NS, P, NP, L, GE, G, LE, } macro_rules! register { ($bank:ident, $name:ident => $num:expr, $($tail:tt)+) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } register!($bank, $($tail)*); }; ($bank:ident, $name:ident => $num:expr) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } }; } #[allow(non_snake_case)] impl RegSpec { /// the register `rip`. this register is in the class `rip`, which contains only it. pub const RIP: RegSpec = RegSpec::rip(); /// the number of this register in its `RegisterClass`. /// /// for many registers this is a number in the name, but for registers harkening back to /// `x86_32`, the first eight registers are `rax`, `rcx`, `rdx`, `rbx`, `rsp`, `rbp`, `rsi`, /// and `rdi` (or `eXX` for the 32-bit forms, `XX` for 16-bit forms). pub fn num(&self) -> u8 { self.num } /// the class of register this register is in. /// /// this corresponds to the register's size, but is by the register's usage in the instruction /// set; `rax` and `mm0` are the same size, but different classes (`Q`(word) and `MM` (mmx) /// respectively). pub fn class(&self) -> RegisterClass { RegisterClass { kind: self.bank } } #[cfg(feature = "fmt")] /// return a human-friendly name for this register. the returned name is the same as would be /// used to render this register in an instruction. pub fn name(&self) -> &'static str { display::regspec_label(self) } /// construct a `RegSpec` for x87 register `st(num)` #[inline] pub fn st(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x87 reg st({})", num); } RegSpec { num, bank: RegisterBank::ST } } /// construct a `RegSpec` for xmm reg `num` #[inline] pub fn xmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 xmm reg {}", num); } RegSpec { num, bank: RegisterBank::X } } /// construct a `RegSpec` for ymm reg `num` #[inline] pub fn ymm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 ymm reg {}", num); } RegSpec { num, bank: RegisterBank::Y } } /// construct a `RegSpec` for zmm reg `num` #[inline] pub fn zmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 zmm reg {}", num); } RegSpec { num, bank: RegisterBank::Z } } /// construct a `RegSpec` for qword reg `num` #[inline] pub fn q(num: u8) -> RegSpec { if num >= 16 { panic!("invalid x86 qword reg {}", num); } RegSpec { num, bank: RegisterBank::Q } } /// construct a `RegSpec` for mask reg `num` #[inline] pub fn mask(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 mask reg {}", num); } RegSpec { num, bank: RegisterBank::K } } /// construct a `RegSpec` for dword reg `num` #[inline] pub fn d(num: u8) -> RegSpec { if num >= 16 { panic!("invalid x86 dword reg {}", num); } RegSpec { num, bank: RegisterBank::D } } /// construct a `RegSpec` for word reg `num` #[inline] pub fn w(num: u8) -> RegSpec { if num >= 16 { panic!("invalid x86 word reg {}", num); } RegSpec { num, bank: RegisterBank::W } } /// construct a `RegSpec` for non-rex byte reg `num` #[inline] pub fn rb(num: u8) -> RegSpec { if num >= 16 { panic!("invalid x86 rex-byte reg {}", num); } let bank = if num < 4 { RegisterBank::B } else { RegisterBank::rB }; RegSpec { num, bank, } } /// construct a `RegSpec` for non-rex byte reg `num` #[inline] pub fn b(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 non-rex byte reg {}", num); } RegSpec { num, bank: RegisterBank::B } } #[inline] fn from_parts(num: u8, extended: bool, bank: RegisterBank) -> RegSpec { RegSpec { num: num + if extended { 0b1000 } else { 0 }, bank: bank } } #[inline] fn gp_from_parts_non_byte(num: u8, extended: bool, bank: RegisterBank) -> RegSpec { RegSpec { num: num + if extended { 0b1000 } else { 0 }, bank } } register!(RIP, rip => 0); register!(EIP, eip => 0); register!(RFlags, rflags => 0); register!(EFlags, eflags => 0); register!(S, es => 0, cs => 1, ss => 2, ds => 3, fs => 4, gs => 5); register!(Q, rax => 0, rcx => 1, rdx => 2, rbx => 3, rsp => 4, rbp => 5, rsi => 6, rdi => 7, r8 => 8, r9 => 9, r10 => 10, r11 => 11, r12 => 12, r13 => 13, r14 => 14, r15 => 15 ); register!(D, eax => 0, ecx => 1, edx => 2, ebx => 3, esp => 4, ebp => 5, esi => 6, edi => 7, r8d => 8, r9d => 9, r10d => 10, r11d => 11, r12d => 12, r13d => 13, r14d => 14, r15d => 15 ); register!(W, ax => 0, cx => 1, dx => 2, bx => 3, sp => 4, bp => 5, si => 6, di => 7, r8w => 8, r9w => 9, r10w => 10, r11w => 11, r12w => 12, r13w => 13, r14w => 14, r15w => 15 ); register!(B, al => 0, cl => 1, dl => 2, bl => 3, ah => 4, ch => 5, dh => 6, bh => 7 ); register!(rB, spl => 4, bpl => 5, sil => 6, dil => 7, r8b => 8, r9b => 9, r10b => 10, r11b => 11, r12b => 12, r13b => 13, r14b => 14, r15b => 15 ); #[inline] pub const fn zmm0() -> RegSpec { RegSpec { bank: RegisterBank::Z, num: 0 } } #[inline] pub const fn ymm0() -> RegSpec { RegSpec { bank: RegisterBank::Y, num: 0 } } #[inline] pub const fn xmm0() -> RegSpec { RegSpec { bank: RegisterBank::X, num: 0 } } #[inline] pub const fn st0() -> RegSpec { RegSpec { bank: RegisterBank::ST, num: 0 } } #[inline] pub const fn mm0() -> RegSpec { RegSpec { bank: RegisterBank::MM, num: 0 } } /// return the size of this register, in bytes. #[inline] pub fn width(&self) -> u8 { self.class().width() } } #[allow(non_camel_case_types)] #[allow(dead_code)] enum SizeCode { b, vd, vq, vqp } /// an operand for an `x86_64` instruction. /// /// `Operand::Nothing` should be unreachable in practice; any such instructions should have an /// operand count of 0 (or at least one fewer than the `Nothing` operand's position). #[derive(Clone, Debug, PartialEq, Eq)] #[non_exhaustive] pub enum Operand { /// a sign-extended byte ImmediateI8(i8), /// a zero-extended byte ImmediateU8(u8), /// a sign-extended word ImmediateI16(i16), /// a zero-extended word ImmediateU16(u16), /// a sign-extended dword ImmediateI32(i32), /// a zero-extended dword ImmediateU32(u32), /// a sign-extended qword ImmediateI64(i64), /// a zero-extended qword ImmediateU64(u64), /// a bare register operand, such as `rcx`. Register(RegSpec), /// an `avx512` register operand with optional mask register and merge mode, such as /// `zmm3{k4}{z}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMerge(RegSpec, RegSpec, MergeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, such as `zmm3{k4}{z}{rd-sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSae(RegSpec, RegSpec, MergeMode, SaeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, with no overridden rounding mode, such as `zmm3{k4}{z}{sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSaeNoround(RegSpec, RegSpec, MergeMode), /// a memory access to a literal dword address. it's extremely rare that a well-formed x86 /// instruction uses this mode. as an example, `[0x1133]` DisplacementU32(u32), /// a memory access to a literal qword address. it's relatively rare that a well-formed x86 /// instruction uses this mode, but plausible. for example, `gs:[0x14]`. segment overrides, /// however, are maintained on the instruction itself. DisplacementU64(u64), /// a simple dereference of the address held in some register. for example: `[rsi]`. RegDeref(RegSpec), /// a dereference of the address held in some register with offset. for example: `[rsi + 0x14]`. RegDisp(RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8. this is almost always used with the `lea` instruction. for example: `[rdx * 4]`. RegScale(RegSpec, u8), /// a dereference of the address from summing two registers. for example: `[rbp + rax]` RegIndexBase(RegSpec, RegSpec), /// a dereference of the address from summing two registers with offset. for example: `[rdi + rcx + 0x40]` RegIndexBaseDisp(RegSpec, RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8 with offset. this is almost always used with the `lea` instruction. for example: `[rax * 4 + 0x30]`. RegScaleDisp(RegSpec, u8, i32), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8. for /// example: `[rsi + rcx * 4]` RegIndexBaseScale(RegSpec, RegSpec, u8), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8, with offset. for /// example: `[rsi + rcx * 4 + 0x1234]` RegIndexBaseScaleDisp(RegSpec, RegSpec, u8, i32), /// an `avx512` dereference of register with optional masking. for example: `[rdx]{k3}` RegDerefMasked(RegSpec, RegSpec), /// an `avx512` dereference of register plus offset, with optional masking. for example: `[rsp + 0x40]{k3}` RegDispMasked(RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8, with optional masking. this /// seems extraordinarily unlikely to occur in practice. for example: `[rsi * 4]{k2}` RegScaleMasked(RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional masking. /// for example: `[rsi + rax * 4]{k6}` RegIndexBaseMasked(RegSpec, RegSpec, RegSpec), /// an `avx512` dereference of a register plus offset, with optional masking. for example: /// `[rsi + rax + 0x1313]{k6}` RegIndexBaseDispMasked(RegSpec, RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8 plus offset, with optional /// masking. this seems extraordinarily unlikely to occur in practice. for example: `[rsi * /// 4 + 0x1357]{k2}` RegScaleDispMasked(RegSpec, u8, i32, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional /// masking. for example: `[rsi + rax * 4]{k6}` RegIndexBaseScaleMasked(RegSpec, RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8 and offset, with /// optional masking. for example: `[rsi + rax * 4 + 0x1313]{k6}` RegIndexBaseScaleDispMasked(RegSpec, RegSpec, u8, i32, RegSpec), /// no operand. it is a bug for `yaxpeax-x86` to construct an `Operand` of this kind for public /// use; the instruction's `operand_count` should be reduced so as to make this invisible to /// library clients. Nothing, } impl OperandSpec { fn masked(self) -> Self { match self { OperandSpec::RegRRR => OperandSpec::RegRRR_maskmerge, OperandSpec::RegMMM => OperandSpec::RegMMM_maskmerge, OperandSpec::RegVex => OperandSpec::RegVex_maskmerge, OperandSpec::Deref => OperandSpec::Deref_mask, OperandSpec::RegDisp => OperandSpec::RegDisp_mask, OperandSpec::RegScale => OperandSpec::RegScale_mask, OperandSpec::RegScaleDisp => OperandSpec::RegScaleDisp_mask, OperandSpec::RegIndexBaseScale => OperandSpec::RegIndexBaseScale_mask, OperandSpec::RegIndexBaseScaleDisp => OperandSpec::RegIndexBaseScaleDisp_mask, o => o, } } fn is_memory(&self) -> bool { (*self as u8) & 0x80 != 0 } } /// an `avx512` merging mode. /// /// the behavior for non-`avx512` instructions is equivalent to `merge`. `zero` is only useful in /// conjunction with a mask register, where bits specified in the mask register correspond to /// unmodified items in the instruction's destination. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum MergeMode { Merge, Zero, } impl From for MergeMode { fn from(b: bool) -> Self { if b { MergeMode::Zero } else { MergeMode::Merge } } } /// an `avx512` custom rounding mode. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum SaeMode { RoundNearest, RoundDown, RoundUp, RoundZero, } const SAE_MODES: [SaeMode; 4] = [ SaeMode::RoundNearest, SaeMode::RoundDown, SaeMode::RoundUp, SaeMode::RoundZero, ]; impl SaeMode { /// a human-friendly label for this `SaeMode`: /// /// ``` /// use yaxpeax_x86::long_mode::SaeMode; /// /// assert_eq!(SaeMode::RoundNearest.label(), "{rne-sae}"); /// assert_eq!(SaeMode::RoundDown.label(), "{rd-sae}"); /// assert_eq!(SaeMode::RoundUp.label(), "{ru-sae}"); /// assert_eq!(SaeMode::RoundZero.label(), "{rz-sae}"); /// ``` pub fn label(&self) -> &'static str { match self { SaeMode::RoundNearest => "{rne-sae}", SaeMode::RoundDown => "{rd-sae}", SaeMode::RoundUp => "{ru-sae}", SaeMode::RoundZero => "{rz-sae}", } } fn from(l: bool, lp: bool) -> Self { let mut idx = 0; if l { idx |= 1; } if lp { idx |= 2; } SAE_MODES[idx] } } impl Operand { fn from_spec(inst: &Instruction, spec: OperandSpec) -> Operand { match spec { OperandSpec::Nothing => { Operand::Nothing } // the register in modrm_rrr OperandSpec::RegRRR => { Operand::Register(inst.regs[0]) } OperandSpec::RegRRR_maskmerge => { Operand::RegisterMaskMerge( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegRRR_maskmerge_sae => { Operand::RegisterMaskMergeSae( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), SaeMode::from(inst.prefixes.evex_unchecked().vex().l(), inst.prefixes.evex_unchecked().lp()), ) } OperandSpec::RegRRR_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } // the register in modrm_mmm (eg modrm mod bits were 11) OperandSpec::RegMMM => { Operand::Register(inst.regs[1]) } OperandSpec::RegMMM_maskmerge => { Operand::RegisterMaskMerge( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegMMM_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegVex => { Operand::Register(inst.regs[3]) } OperandSpec::RegVex_maskmerge => { Operand::RegisterMaskMerge( inst.regs[3], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::Reg4 => { Operand::Register(RegSpec { num: inst.imm as u8, bank: inst.regs[3].bank }) } OperandSpec::ImmI8 => Operand::ImmediateI8(inst.imm as i8), OperandSpec::ImmU8 => Operand::ImmediateU8(inst.imm as u8), OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16), OperandSpec::ImmU16 => Operand::ImmediateU16(inst.imm as u16), OperandSpec::ImmI32 => Operand::ImmediateI32(inst.imm as i32), OperandSpec::ImmI64 => Operand::ImmediateI64(inst.imm as i64), OperandSpec::ImmInDispField => Operand::ImmediateU16(inst.disp as u16), OperandSpec::DispU32 => Operand::DisplacementU32(inst.disp as u32), OperandSpec::DispU64 => Operand::DisplacementU64(inst.disp as u64), OperandSpec::Deref => { Operand::RegDeref(inst.regs[1]) } OperandSpec::Deref_esi => { Operand::RegDeref(RegSpec::esi()) } OperandSpec::Deref_edi => { Operand::RegDeref(RegSpec::edi()) } OperandSpec::Deref_rsi => { Operand::RegDeref(RegSpec::rsi()) } OperandSpec::Deref_rdi => { Operand::RegDeref(RegSpec::rdi()) } OperandSpec::RegDisp => { Operand::RegDisp(inst.regs[1], inst.disp as i32) } OperandSpec::RegScale => { Operand::RegScale(inst.regs[2], inst.scale) } OperandSpec::RegScaleDisp => { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::RegIndexBaseScale => { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } OperandSpec::RegIndexBaseScaleDisp => { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::Deref_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDerefMasked(inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDeref(inst.regs[1]) } } OperandSpec::RegDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDispMasked(inst.regs[1], inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDisp(inst.regs[1], inst.disp as i32) } } OperandSpec::RegScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleMasked(inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScale(inst.regs[2], inst.scale) } } OperandSpec::RegScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleDispMasked(inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } } OperandSpec::RegIndexBaseScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleMasked(inst.regs[1], inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } } OperandSpec::RegIndexBaseScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleDispMasked(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } } } } /// returns `true` if this operand implies a memory access, `false` otherwise. /// /// notably, the `lea` instruction uses a memory operand without actually ever accessing /// memory. pub fn is_memory(&self) -> bool { match self { Operand::DisplacementU32(_) | Operand::DisplacementU64(_) | Operand::RegDeref(_) | Operand::RegDisp(_, _) | Operand::RegScale(_, _) | Operand::RegIndexBase(_, _) | Operand::RegIndexBaseDisp(_, _, _) | Operand::RegScaleDisp(_, _, _) | Operand::RegIndexBaseScale(_, _, _) | Operand::RegIndexBaseScaleDisp(_, _, _, _) | Operand::RegDerefMasked(_, _) | Operand::RegDispMasked(_, _, _) | Operand::RegScaleMasked(_, _, _) | Operand::RegIndexBaseMasked(_, _, _) | Operand::RegIndexBaseDispMasked(_, _, _, _) | Operand::RegScaleDispMasked(_, _, _, _) | Operand::RegIndexBaseScaleMasked(_, _, _, _) | Operand::RegIndexBaseScaleDispMasked(_, _, _, _, _) => { true }, Operand::ImmediateI8(_) | Operand::ImmediateU8(_) | Operand::ImmediateI16(_) | Operand::ImmediateU16(_) | Operand::ImmediateU32(_) | Operand::ImmediateI32(_) | Operand::ImmediateU64(_) | Operand::ImmediateI64(_) | Operand::Register(_) | Operand::RegisterMaskMerge(_, _, _) | Operand::RegisterMaskMergeSae(_, _, _, _) | Operand::RegisterMaskMergeSaeNoround(_, _, _) | Operand::Nothing => { false } } } /// return the width of this operand, in bytes. register widths are determined by the /// register's class. the widths of memory operands are recorded on the instruction this /// `Operand` came from; `None` here means the authoritative width is `instr.mem_size()`. pub fn width(&self) -> Option { match self { Operand::Register(reg) => { Some(reg.width()) } Operand::RegisterMaskMerge(reg, _, _) => { Some(reg.width()) } Operand::ImmediateI8(_) | Operand::ImmediateU8(_) => { Some(1) } Operand::ImmediateI16(_) | Operand::ImmediateU16(_) => { Some(2) } Operand::ImmediateI32(_) | Operand::ImmediateU32(_) => { Some(4) } Operand::ImmediateI64(_) | Operand::ImmediateU64(_) => { Some(8) } // memory operands or `Nothing` _ => { None } } } } #[test] fn operand_size() { assert_eq!(core::mem::size_of::(), 1); assert_eq!(core::mem::size_of::(), 2); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 8); // assert_eq!(core::mem::size_of::(), 4); // assert_eq!(core::mem::size_of::(), 40); } /// an `x86_64` register class - `qword`, `dword`, `xmmword`, `segment`, and so on. /// /// this is mostly useful for comparing a `RegSpec`'s [`RegSpec::class()`] with a constant out of /// [`register_class`]. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] pub struct RegisterClass { kind: RegisterBank, } const REGISTER_CLASS_NAMES: &[&'static str] = &[ "BUG. PLEASE REPORT.", "byte", "word", "BUG. PLEASE REPORT.", "dword", "BUG. PLEASE REPORT.", "rex-byte", "BUG. PLEASE REPORT.", "qword", "BUG. PLEASE REPORT.", "cr", "BUG. PLEASE REPORT.", "dr", "BUG. PLEASE REPORT.", "segment", "xmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "ymm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "zmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "x87-stack", "mmx", "k", "eip", "rip", "eflags", "rflags", ]; /// high-level register classes in an x86 machine, such as "8-byte general purpose", "xmm", "x87", /// and so on. constants in this module are useful for inspecting the register class of a decoded /// instruction. as an example: /// ``` /// use yaxpeax_x86::long_mode::{self as amd64}; /// use yaxpeax_x86::long_mode::{Opcode, Operand, RegisterClass}; /// use yaxpeax_arch::{Decoder, U8Reader}; /// /// let movsx_eax_cl = &[0x0f, 0xbe, 0xc1]; /// let decoder = amd64::InstDecoder::default(); /// let instruction = decoder /// .decode(&mut U8Reader::new(movsx_eax_cl)) /// .expect("can decode"); /// /// assert_eq!(instruction.opcode(), Opcode::MOVSX); /// /// fn show_register_class_info(regclass: RegisterClass) { /// match regclass { /// amd64::register_class::D => { /// println!(" and is a dword register"); /// } /// amd64::register_class::B => { /// println!(" and is a byte register"); /// } /// other => { /// panic!("unexpected and invalid register class {:?}", other); /// } /// } /// } /// /// if let Operand::Register(regspec) = instruction.operand(0) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// /// if let Operand::Register(regspec) = instruction.operand(1) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// ``` /// /// this is preferable to alternatives like checking register names against a known list: a /// register class is one byte and "is qword general-purpose" can then be a simple one-byte /// compare, instead of 16 string compares. /// /// `yaxpeax-x86` does not attempt to further distinguish between, for example, register /// suitability as operands. as an example, `cl` is only a byte register, with no additional /// register class to describe its use as an implicit shift operand. pub mod register_class { use super::{RegisterBank, RegisterClass}; /// quadword registers: rax through r15 pub const Q: RegisterClass = RegisterClass { kind: RegisterBank::Q }; /// doubleword registers: eax through r15d pub const D: RegisterClass = RegisterClass { kind: RegisterBank::D }; /// word registers: ax through r15w pub const W: RegisterClass = RegisterClass { kind: RegisterBank::W }; /// byte registers: al, cl, dl, bl, ah, ch, dh, bh. pub const B: RegisterClass = RegisterClass { kind: RegisterBank::B }; /// byte registers added in x86_64: spl through r15b. pub const RB: RegisterClass = RegisterClass { kind: RegisterBank::rB }; /// control registers cr0 through cr15. pub const CR: RegisterClass = RegisterClass { kind: RegisterBank::CR}; /// debug registers dr0 through dr15. pub const DR: RegisterClass = RegisterClass { kind: RegisterBank::DR }; /// segment registers es, cs, ss, ds, fs, gs. pub const S: RegisterClass = RegisterClass { kind: RegisterBank::S }; /// xmm registers xmm0 through xmm31. pub const X: RegisterClass = RegisterClass { kind: RegisterBank::X }; /// ymm registers ymm0 through ymm31. pub const Y: RegisterClass = RegisterClass { kind: RegisterBank::Y }; /// zmm registers zmm0 through zmm31. pub const Z: RegisterClass = RegisterClass { kind: RegisterBank::Z }; /// x87 floating point stack entries st(0) through st(7). pub const ST: RegisterClass = RegisterClass { kind: RegisterBank::ST }; /// mmx registers mm0 through mm7. pub const MM: RegisterClass = RegisterClass { kind: RegisterBank::MM }; /// `avx512` mask registers k0 through k7. pub const K: RegisterClass = RegisterClass { kind: RegisterBank::K }; /// the full instruction pointer register. pub const RIP: RegisterClass = RegisterClass { kind: RegisterBank::RIP }; /// the low 32 bits of `rip`. pub const EIP: RegisterClass = RegisterClass { kind: RegisterBank::EIP }; /// the full cpu flags register. pub const RFLAGS: RegisterClass = RegisterClass { kind: RegisterBank::RFlags }; /// the low 32 bits of rflags. pub const EFLAGS: RegisterClass = RegisterClass { kind: RegisterBank::EFlags }; } impl RegisterClass { /// return a human-friendly name for this register class pub fn name(&self) -> &'static str { REGISTER_CLASS_NAMES[self.kind as usize] } /// return the size of this register class, in bytes pub fn width(&self) -> u8 { match self.kind { RegisterBank::Q => self.kind as u8, RegisterBank::D => self.kind as u8, RegisterBank::W => self.kind as u8, RegisterBank::B | RegisterBank::rB => { 1 }, RegisterBank::CR | RegisterBank::DR => { 8 }, RegisterBank::S => { 2 }, RegisterBank::EIP => { 4 } RegisterBank::RIP => { 8 } RegisterBank::EFlags => { 4 } RegisterBank::RFlags => { 8 } RegisterBank::X => { 16 } RegisterBank::Y => { 32 } RegisterBank::Z => { 64 } RegisterBank::ST => { 10 } RegisterBank::MM => { 8 } RegisterBank::K => { 8 } } } } #[allow(non_camel_case_types)] #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] enum RegisterBank { Q = 8, D = 4, W = 2, B = 1, rB = 6, // Quadword, Dword, Word, Byte CR = 10, DR = 12, S = 14, EIP = 30, RIP = 31, EFlags = 32, RFlags = 33, // Control reg, Debug reg, Selector, ... X = 15, Y = 19, Z = 23, // XMM, YMM, ZMM ST = 27, MM = 28, // ST, MM regs (x87, mmx) K = 29, // AVX512 mask registers } /// the segment register used by the corresponding instruction. /// /// typically this will be `ds` but can be overridden. some instructions have specific segment /// registers used regardless of segment prefixes, and in these cases `yaxpeax-x86` will report the /// actual segment register a physical processor would use. #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)] pub enum Segment { DS = 0, CS, ES, FS, GS, SS } const BMI1: [Opcode; 6] = [ Opcode::ANDN, Opcode::BEXTR, Opcode::BLSI, Opcode::BLSMSK, Opcode::BLSR, Opcode::TZCNT, ]; const BMI2: [Opcode; 8] = [ Opcode::BZHI, Opcode::MULX, Opcode::PDEP, Opcode::PEXT, Opcode::RORX, Opcode::SARX, Opcode::SHRX, Opcode::SHLX, ]; #[allow(dead_code)] const XSAVE: [Opcode; 10] = [ Opcode::XGETBV, Opcode::XRSTOR, Opcode::XRSTORS, Opcode::XSAVE, Opcode::XSAVEC, Opcode::XSAVEC64, Opcode::XSAVEOPT, Opcode::XSAVES, Opcode::XSAVES64, Opcode::XSETBV, ]; //struct OpcodeBuilder { // variant_specifier: OpcodeVariantInfo /// an `x86_64` opcode. there sure are a lot of these. #[allow(non_camel_case_types)] #[derive(Copy, Clone, Debug, Eq, PartialEq)] #[non_exhaustive] #[repr(u32)] pub enum Opcode { ADD = 0x1000, OR = 0x1001, ADC = 0x1002, SBB = 0x1003, AND = 0x1004, SUB = 0x1005, XOR = 0x1006, CMP = 7, ROL = 8, ROR, RCL, RCR, SHL, SHR, SAL, SAR = 0x0f, BTC = 0x1010, BTR = 0x1011, BTS = 0x1012, CMPXCHG = 0x1013, CMPXCHG8B = 0x1014, CMPXCHG16B = 0x1015, DEC = 0x1016, INC = 0x1017, NEG = 0x1018, NOT = 0x1019, XADD = 0x101a, XCHG = 0x101b, Invalid = 0x1c, // XADD, BT, // BTS, // BTC, // BTR, BSF, BSR, TZCNT, MOVSS, ADDSS, SUBSS, MULSS, DIVSS, MINSS, MAXSS, SQRTSS, MOVSD, SQRTSD, ADDSD, SUBSD, MULSD, DIVSD, MINSD, MAXSD, MOVSLDUP, MOVSHDUP, MOVDDUP, HADDPS, HSUBPS, ADDSUBPD, ADDSUBPS, CVTSI2SS, CVTSI2SD, CVTTSD2SI, CVTTPS2DQ, CVTPD2DQ, CVTPD2PS, CVTPS2DQ, CVTSD2SI, CVTSD2SS, CVTTSS2SI, CVTSS2SI, CVTSS2SD, CVTDQ2PD, LDDQU, MOVZX, MOVSX, MOVSXD, SHRD, // INC, // DEC, HLT, CALL, CALLF, JMP, JMPF, PUSH, POP, LEA, NOP, PREFETCHNTA, PREFETCH0, PREFETCH1, PREFETCH2, // XCHG, POPF, INT, INTO, IRET, IRETD, IRETQ, RETF, ENTER, LEAVE, MOV, RETURN, PUSHF, WAIT, CBW, CWDE, CDQE, CWD, CDQ, CQO, LODS, STOS, LAHF, SAHF, CMPS, SCAS, MOVS, TEST, INS, IN, OUTS, OUT, IMUL, JO, JNO, JB, JNB, JZ, JNZ, JA, JNA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, CMOVA, CMOVB, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNB, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVS, CMOVZ, DIV, IDIV, MUL, // NEG, // NOT, // CMPXCHG, SETO, SETNO, SETB, SETAE, SETZ, SETNZ, SETBE, SETA, SETS, SETNS, SETP, SETNP, SETL, SETGE, SETLE, SETG, CPUID, UD0, UD1, UD2, WBINVD, INVD, SYSRET, CLTS, SYSCALL, LSL, LAR, SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, SWAPGS, RDTSCP, INVLPG, FXSAVE, FXRSTOR, LDMXCSR, STMXCSR, XSAVE, XRSTOR, XSAVEOPT, LFENCE, MFENCE, SFENCE, CLFLUSH, CLFLUSHOPT, CLWB, WRMSR, RDTSC, RDMSR, RDPMC, SLDT, STR, LLDT, LTR, VERR, VERW, CMC, CLC, STC, CLI, STI, CLD, STD, JMPE, POPCNT, MOVDQU, MOVDQA, MOVQ, CMPSS, CMPSD, UNPCKLPS, UNPCKLPD, UNPCKHPS, UNPCKHPD, PSHUFHW, PSHUFLW, MOVUPS, MOVQ2DQ, MOVDQ2Q, RSQRTSS, RCPSS, ANDN, BEXTR, BLSI, BLSMSK, BLSR, VMCLEAR, VMXON, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, PCONFIG, MONITOR, MWAIT, MONITORX, MWAITX, CLAC, STAC, ENCLS, ENCLV, XGETBV, XSETBV, VMFUNC, XABORT, XBEGIN, XEND, XTEST, ENCLU, RDPKRU, WRPKRU, RDPRU, CLZERO, RDSEED, RDRAND, ADDPS, ADDPD, ANDNPS, ANDNPD, ANDPS, ANDPD, BSWAP, CMPPD, CMPPS, COMISD, COMISS, CVTDQ2PS, CVTPI2PS, CVTPI2PD, CVTPS2PD, CVTPS2PI, CVTPD2PI, CVTTPS2PI, CVTTPD2PI, CVTTPD2DQ, DIVPS, DIVPD, EMMS, GETSEC, LFS, LGS, LSS, MASKMOVQ, MASKMOVDQU, MAXPS, MAXPD, MINPS, MINPD, MOVAPS, MOVAPD, MOVD, MOVLPS, MOVLPD, MOVHPS, MOVHPD, MOVLHPS, MOVHLPS, MOVUPD, MOVMSKPS, MOVMSKPD, MOVNTI, MOVNTPS, MOVNTPD, EXTRQ, INSERTQ, MOVNTSS, MOVNTSD, MOVNTQ, MOVNTDQ, MULPS, MULPD, ORPS, ORPD, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PAVGB, PAVGW, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PINSRW, PMADDWD, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PMULHW, PMULLW, PMULUDQ, POR, PSADBW, PSHUFW, PSHUFD, PSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PUNPCKLQDQ, PUNPCKHQDQ, PXOR, RCPPS, RSM, RSQRTPS, SHLD, SHUFPD, SHUFPS, SLHD, SQRTPS, SQRTPD, SUBPS, SUBPD, SYSENTER, SYSEXIT, UCOMISD, UCOMISS, VMREAD, VMWRITE, XORPS, XORPD, VMOVDDUP, VPSHUFLW, VPSHUFHW, VHADDPS, VHSUBPS, VADDSUBPS, VCVTPD2DQ, VLDDQU, VCOMISD, VCOMISS, VUCOMISD, VUCOMISS, VADDPD, VADDPS, VADDSD, VADDSS, VADDSUBPD, VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST, VBLENDPD, VBLENDPS, VBLENDVPD, VBLENDVPS, VBROADCASTF128, VBROADCASTI128, VBROADCASTSD, VBROADCASTSS, VCMPSD, VCMPSS, VCMPPD, VCMPPS, VCVTDQ2PD, VCVTDQ2PS, VCVTPD2PS, VCVTPH2PS, VCVTPS2DQ, VCVTPS2PD, VCVTSS2SD, VCVTSI2SS, VCVTSI2SD, VCVTSD2SI, VCVTSD2SS, VCVTPS2PH, VCVTSS2SI, VCVTTPD2DQ, VCVTTPS2DQ, VCVTTSS2SI, VCVTTSD2SI, VDIVPD, VDIVPS, VDIVSD, VDIVSS, VDPPD, VDPPS, VEXTRACTF128, VEXTRACTI128, VEXTRACTPS, VFMADD132PD, VFMADD132PS, VFMADD132SD, VFMADD132SS, VFMADD213PD, VFMADD213PS, VFMADD213SD, VFMADD213SS, VFMADD231PD, VFMADD231PS, VFMADD231SD, VFMADD231SS, VFMADDSUB132PD, VFMADDSUB132PS, VFMADDSUB213PD, VFMADDSUB213PS, VFMADDSUB231PD, VFMADDSUB231PS, VFMSUB132PD, VFMSUB132PS, VFMSUB132SD, VFMSUB132SS, VFMSUB213PD, VFMSUB213PS, VFMSUB213SD, VFMSUB213SS, VFMSUB231PD, VFMSUB231PS, VFMSUB231SD, VFMSUB231SS, VFMSUBADD132PD, VFMSUBADD132PS, VFMSUBADD213PD, VFMSUBADD213PS, VFMSUBADD231PD, VFMSUBADD231PS, VFNMADD132PD, VFNMADD132PS, VFNMADD132SD, VFNMADD132SS, VFNMADD213PD, VFNMADD213PS, VFNMADD213SD, VFNMADD213SS, VFNMADD231PD, VFNMADD231PS, VFNMADD231SD, VFNMADD231SS, VFNMSUB132PD, VFNMSUB132PS, VFNMSUB132SD, VFNMSUB132SS, VFNMSUB213PD, VFNMSUB213PS, VFNMSUB213SD, VFNMSUB213SS, VFNMSUB231PD, VFNMSUB231PS, VFNMSUB231SD, VFNMSUB231SS, VGATHERDPD, VGATHERDPS, VGATHERQPD, VGATHERQPS, VHADDPD, VHSUBPD, VINSERTF128, VINSERTI128, VINSERTPS, VMASKMOVDQU, VMASKMOVPD, VMASKMOVPS, VMAXPD, VMAXPS, VMAXSD, VMAXSS, VMINPD, VMINPS, VMINSD, VMINSS, VMOVAPD, VMOVAPS, VMOVD, VMOVDQA, VMOVDQU, VMOVHLPS, VMOVHPD, VMOVHPS, VMOVLHPS, VMOVLPD, VMOVLPS, VMOVMSKPD, VMOVMSKPS, VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS, VMOVQ, VMOVSS, VMOVSD, VMOVSHDUP, VMOVSLDUP, VMOVUPD, VMOVUPS, VMPSADBW, VMULPD, VMULPS, VMULSD, VMULSS, VPABSB, VPABSD, VPABSW, VPACKSSDW, VPACKUSDW, VPACKSSWB, VPACKUSWB, VPADDB, VPADDD, VPADDQ, VPADDSB, VPADDSW, VPADDUSB, VPADDUSW, VPADDW, VPALIGNR, VANDPD, VANDPS, VORPD, VORPS, VANDNPD, VANDNPS, VPAND, VPANDN, VPAVGB, VPAVGW, VPBLENDD, VPBLENDVB, VPBLENDW, VPBROADCASTB, VPBROADCASTD, VPBROADCASTQ, VPBROADCASTW, VPCLMULQDQ, VPCMPEQB, VPCMPEQD, VPCMPEQQ, VPCMPEQW, VPCMPGTB, VPCMPGTD, VPCMPGTQ, VPCMPGTW, VPCMPESTRI, VPCMPESTRM, VPCMPISTRI, VPCMPISTRM, VPERM2F128, VPERM2I128, VPERMD, VPERMILPD, VPERMILPS, VPERMPD, VPERMPS, VPERMQ, VPEXTRB, VPEXTRD, VPEXTRQ, VPEXTRW, VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ, VPHADDD, VPHADDSW, VPHADDW, VPMADDUBSW, VPHMINPOSUW, VPHSUBD, VPHSUBSW, VPHSUBW, VPINSRB, VPINSRD, VPINSRQ, VPINSRW, VPMADDWD, VPMASKMOVD, VPMASKMOVQ, VPMAXSB, VPMAXSD, VPMAXSW, VPMAXUB, VPMAXUW, VPMAXUD, VPMINSB, VPMINSW, VPMINSD, VPMINUB, VPMINUW, VPMINUD, VPMOVMSKB, VPMOVSXBD, VPMOVSXBQ, VPMOVSXBW, VPMOVSXDQ, VPMOVSXWD, VPMOVSXWQ, VPMOVZXBD, VPMOVZXBQ, VPMOVZXBW, VPMOVZXDQ, VPMOVZXWD, VPMOVZXWQ, VPMULDQ, VPMULHRSW, VPMULHUW, VPMULHW, VPMULLQ, VPMULLD, VPMULLW, VPMULUDQ, VPOR, VPSADBW, VPSHUFB, VPSHUFD, VPSIGNB, VPSIGND, VPSIGNW, VPSLLD, VPSLLDQ, VPSLLQ, VPSLLVD, VPSLLVQ, VPSLLW, VPSRAD, VPSRAVD, VPSRAW, VPSRLD, VPSRLDQ, VPSRLQ, VPSRLVD, VPSRLVQ, VPSRLW, VPSUBB, VPSUBD, VPSUBQ, VPSUBSB, VPSUBSW, VPSUBUSB, VPSUBUSW, VPSUBW, VPTEST, VPUNPCKHBW, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLDQ, VPUNPCKLQDQ, VPUNPCKLWD, VPXOR, VRCPPS, VROUNDPD, VROUNDPS, VROUNDSD, VROUNDSS, VRSQRTPS, VRSQRTSS, VRCPSS, VSHUFPD, VSHUFPS, VSQRTPD, VSQRTPS, VSQRTSS, VSQRTSD, VSUBPD, VSUBPS, VSUBSD, VSUBSS, VTESTPD, VTESTPS, VUNPCKHPD, VUNPCKHPS, VUNPCKLPD, VUNPCKLPS, VXORPD, VXORPS, VZEROUPPER, VZEROALL, VLDMXCSR, VSTMXCSR, PCLMULQDQ, AESKEYGENASSIST, AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST, PCMPGTQ, PCMPISTRM, PCMPISTRI, PCMPESTRI, PACKUSDW, PCMPESTRM, PCMPEQQ, PTEST, PHMINPOSUW, DPPS, DPPD, MPSADBW, PMOVZXDQ, PMOVSXDQ, PMOVZXBD, PMOVSXBD, PMOVZXWQ, PMOVSXWQ, PMOVZXBQ, PMOVSXBQ, PMOVSXWD, PMOVZXWD, PEXTRQ, PEXTRD, PEXTRW, PEXTRB, PMOVSXBW, PMOVZXBW, PINSRQ, PINSRD, PINSRB, EXTRACTPS, INSERTPS, ROUNDSS, ROUNDSD, ROUNDPS, ROUNDPD, PMAXSB, PMAXSD, PMAXUW, PMAXUD, PMINSD, PMINSB, PMINUD, PMINUW, BLENDW, PBLENDVB, PBLENDW, BLENDVPS, BLENDVPD, BLENDPS, BLENDPD, PMULDQ, MOVNTDQA, PMULLD, PALIGNR, PSIGNW, PSIGND, PSIGNB, PSHUFB, PMULHRSW, PMADDUBSW, PABSD, PABSW, PABSB, PHSUBSW, PHSUBW, PHSUBD, PHADDD, PHADDSW, PHADDW, HSUBPD, HADDPD, SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2, SHA256RNDS2, SHA256MSG1, SHA256MSG2, LZCNT, CLGI, STGI, SKINIT, VMLOAD, VMMCALL, VMSAVE, VMRUN, INVLPGA, INVLPGB, TLBSYNC, MOVBE, ADCX, ADOX, PREFETCHW, RDPID, // CMPXCHG8B, // CMPXCHG16B, VMPTRLD, VMPTRST, BZHI, MULX, SHLX, SHRX, SARX, PDEP, PEXT, RORX, XRSTORS, XRSTORS64, XSAVEC, XSAVEC64, XSAVES, XSAVES64, RDFSBASE, RDGSBASE, WRFSBASE, WRGSBASE, CRC32, SALC, XLAT, F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU, FCOM, FCOMI, FCOMIP, FCOMP, FCOMPP, FCOS, FDECSTP, FDISI8087_NOP, FDIV, FDIVP, FDIVR, FDIVRP, FENI8087_NOP, FFREE, FFREEP, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNINIT, FNOP, FNSAVE, FNSTCW, FNSTENV, FNSTOR, FNSTSW, FPATAN, FPREM, FPREM1, FPTAN, FRNDINT, FRSTOR, FSCALE, FSETPM287_NOP, FSIN, FSINCOS, FSQRT, FST, FSTP, FSTPNCE, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FUCOM, FUCOMI, FUCOMIP, FUCOMP, FUCOMPP, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1, LOOPNZ, LOOPZ, LOOP, JRCXZ, // started shipping in Tremont, 2020 sept 23 MOVDIR64B, MOVDIRI, // started shipping in Tiger Lake, 2020 sept 2 AESDEC128KL, AESDEC256KL, AESDECWIDE128KL, AESDECWIDE256KL, AESENC128KL, AESENC256KL, AESENCWIDE128KL, AESENCWIDE256KL, ENCODEKEY128, ENCODEKEY256, LOADIWKEY, // unsure HRESET, // 3dnow FEMMS, PI2FW, PI2FD, PF2IW, PF2ID, PMULHRW, PFCMPGE, PFMIN, PFRCP, PFRSQRT, PFSUB, PFADD, PFCMPGT, PFMAX, PFRCPIT1, PFRSQIT1, PFSUBR, PFACC, PFCMPEQ, PFMUL, PFMULHRW, PFRCPIT2, PFNACC, PFPNACC, PSWAPD, PAVGUSB, // ENQCMD ENQCMD, ENQCMDS, // INVPCID INVEPT, INVVPID, INVPCID, // PTWRITE PTWRITE, // GFNI GF2P8AFFINEQB, GF2P8AFFINEINVQB, GF2P8MULB, // CET WRUSS, WRSS, INCSSP, SAVEPREVSSP, SETSSBSY, CLRSSBSY, RSTORSSP, ENDBR64, ENDBR32, // TDX TDCALL, SEAMRET, SEAMOPS, SEAMCALL, // WAITPKG TPAUSE, UMONITOR, UMWAIT, // UINTR UIRET, TESTUI, CLUI, STUI, SENDUIPI, // TSXLDTRK XSUSLDTRK, XRESLDTRK, // AVX512F VALIGND, VALIGNQ, VBLENDMPD, VBLENDMPS, VCOMPRESSPD, VCOMPRESSPS, VCVTPD2UDQ, VCVTTPD2UDQ, VCVTPS2UDQ, VCVTTPS2UDQ, VCVTQQ2PD, VCVTQQ2PS, VCVTSD2USI, VCVTTSD2USI, VCVTSS2USI, VCVTTSS2USI, VCVTUDQ2PD, VCVTUDQ2PS, VCVTUSI2USD, VCVTUSI2USS, VEXPANDPD, VEXPANDPS, VEXTRACTF32X4, VEXTRACTF64X4, VEXTRACTI32X4, VEXTRACTI64X4, VFIXUPIMMPD, VFIXUPIMMPS, VFIXUPIMMSD, VFIXUPIMMSS, VGETEXPPD, VGETEXPPS, VGETEXPSD, VGETEXPSS, VGETMANTPD, VGETMANTPS, VGETMANTSD, VGETMANTSS, VINSERTF32X4, VINSERTF64X4, VINSERTI64X4, VMOVDQA32, VMOVDQA64, VMOVDQU32, VMOVDQU64, VPBLENDMD, VPBLENDMQ, VPCMPD, VPCMPUD, VPCMPQ, VPCMPUQ, VPCOMPRESSQ, VPCOMPRESSD, VPERMI2D, VPERMI2Q, VPERMI2PD, VPERMI2PS, VPERMT2D, VPERMT2Q, VPERMT2PD, VPERMT2PS, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ, VPMOVSQB, VPMOVUSQB, VPMOVSQW, VPMOVUSQW, VPMOVSQD, VPMOVUSQD, VPMOVSDB, VPMOVUSDB, VPMOVSDW, VPMOVUSDW, VPROLD, VPROLQ, VPROLVD, VPROLVQ, VPRORD, VPRORQ, VPRORRD, VPRORRQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, VPSRAQ, VPSRAVQ, VPTESTNMD, VPTESTNMQ, VPTERNLOGD, VPTERNLOGQ, VPTESTMD, VPTESTMQ, VRCP14PD, VRCP14PS, VRCP14SD, VRCP14SS, VRNDSCALEPD, VRNDSCALEPS, VRNDSCALESD, VRNDSCALESS, VRSQRT14PD, VRSQRT14PS, VRSQRT14SD, VRSQRT14SS, VSCALEDPD, VSCALEDPS, VSCALEDSD, VSCALEDSS, VSCATTERDD, VSCATTERDQ, VSCATTERQD, VSCATTERQQ, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2, // AVX512DQ VCVTTPD2QQ, VCVTPD2QQ, VCVTTPD2UQQ, VCVTPD2UQQ, VCVTTPS2QQ, VCVTPS2QQ, VCVTTPS2UQQ, VCVTPS2UQQ, VCVTUQQ2PD, VCVTUQQ2PS, VEXTRACTF64X2, VEXTRACTI64X2, VFPCLASSPD, VFPCLASSPS, VFPCLASSSD, VFPCLASSSS, VINSERTF64X2, VINSERTI64X2, VPMOVM2D, VPMOVM2Q, VPMOVB2D, VPMOVQ2M, VRANGEPD, VRANGEPS, VRANGESD, VRANGESS, VREDUCEPD, VREDUCEPS, VREDUCESD, VREDUCESS, // AVX512BW VDBPSADBW, VMOVDQU8, VMOVDQU16, VPBLENDMB, VPBLENDMW, VPCMPB, VPCMPUB, VPCMPW, VPCMPUW, VPERMW, VPERMI2B, VPERMI2W, VPMOVM2B, VPMOVM2W, VPMOVB2M, VPMOVW2M, VPMOVSWB, VPMOVUSWB, VPSLLVW, VPSRAVW, VPSRLVW, VPTESTNMB, VPTESTNMW, VPTESTMB, VPTESTMW, // AVX512CD VPBROADCASTM, VPCONFLICTD, VPCONFLICTQ, VPLZCNTD, VPLZCNTQ, KUNPCKBW, KUNPCKWD, KUNPCKDQ, KADDB, KANDB, KANDNB, KMOVB, KNOTB, KORB, KORTESTB, KSHIFTLB, KSHIFTRB, KTESTB, KXNORB, KXORB, KADDW, KANDW, KANDNW, KMOVW, KNOTW, KORW, KORTESTW, KSHIFTLW, KSHIFTRW, KTESTW, KXNORW, KXORW, KADDD, KANDD, KANDND, KMOVD, KNOTD, KORD, KORTESTD, KSHIFTLD, KSHIFTRD, KTESTD, KXNORD, KXORD, KADDQ, KANDQ, KANDNQ, KMOVQ, KNOTQ, KORQ, KORTESTQ, KSHIFTLQ, KSHIFTRQ, KTESTQ, KXNORQ, KXORQ, // AVX512ER VEXP2PD, VEXP2PS, VEXP2SD, VEXP2SS, VRCP28PD, VRCP28PS, VRCP28SD, VRCP28SS, VRSQRT28PD, VRSQRT28PS, VRSQRT28SD, VRSQRT28SS, // AVX512PF VGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS, VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD, VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTERPF1DPS, VSCATTERPF1QPD, VSCATTERPF1QPS, // MPX BNDMK, BNDCL, BNDCU, BNDCN, BNDMOV, BNDLDX, BNDSTX, VGF2P8AFFINEQB, VGF2P8AFFINEINVQB, VPSHRDQ, VPSHRDD, VPSHRDW, VPSHLDQ, VPSHLDD, VPSHLDW, VBROADCASTF32X8, VBROADCASTF64X4, VBROADCASTF32X4, VBROADCASTF64X2, VBROADCASTF32X2, VBROADCASTI32X8, VBROADCASTI64X4, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X2, VEXTRACTI32X8, VEXTRACTF32X8, VINSERTI32X8, VINSERTF32X8, VINSERTI32X4, V4FNMADDSS, V4FNMADDPS, VCVTNEPS2BF16, V4FMADDSS, V4FMADDPS, VCVTNE2PS2BF16, VP2INTERSECTD, VP2INTERSECTQ, VP4DPWSSDS, VP4DPWSSD, VPDPWSSDS, VPDPWSSD, VPDPBUSDS, VDPBF16PS, VPBROADCASTMW2D, VPBROADCASTMB2Q, VPMOVD2M, VPMOVQD, VPMOVWB, VPMOVDB, VPMOVDW, VPMOVQB, VPMOVQW, VGF2P8MULB, VPMADD52HUQ, VPMADD52LUQ, VPSHUFBITQMB, VPERMB, VPEXPANDD, VPEXPANDQ, VPABSQ, VPRORVD, VPRORVQ, VPMULTISHIFTQB, VPERMT2B, VPERMT2W, VPSHRDVQ, VPSHRDVD, VPSHRDVW, VPSHLDVQ, VPSHLDVD, VPSHLDVW, VPCOMPRESSB, VPCOMPRESSW, VPEXPANDB, VPEXPANDW, VPOPCNTD, VPOPCNTQ, VPOPCNTB, VPOPCNTW, VSCALEFSS, VSCALEFSD, VSCALEFPS, VSCALEFPD, VPDPBUSD, VCVTUSI2SD, VCVTUSI2SS, VPXORD, VPXORQ, VPORD, VPORQ, VPANDND, VPANDNQ, VPANDD, VPANDQ, PSMASH, PVALIDATE, RMPADJUST, RMPUPDATE, } impl PartialEq for Instruction { fn eq(&self, other: &Self) -> bool { if self.prefixes != other.prefixes { return false; } if self.opcode != other.opcode { return false; } if self.operand_count != other.operand_count { return false; } if self.mem_size != other.mem_size { return false; } for i in 0..self.operand_count { if self.operands[i as usize] != other.operands[i as usize] { return false; } if self.operand(i) != other.operand(i) { return false; } } true } } /// an `x86_64` instruction. /// /// typically an opcode will be inspected by [`Instruction::opcode()`], and an instruction has /// [`Instruction::operand_count()`] many operands. operands are provided by /// [`Instruction::operand()`]. #[derive(Debug, Clone, Copy, Eq)] pub struct Instruction { pub prefixes: Prefixes, regs: [RegSpec; 4], scale: u8, length: u8, operand_count: u8, operands: [OperandSpec; 4], imm: u64, disp: u64, opcode: Opcode, mem_size: u8, } impl yaxpeax_arch::Instruction for Instruction { fn well_defined(&self) -> bool { // TODO: this is incorrect! true } } #[derive(Debug, PartialEq, Eq, Copy, Clone)] #[non_exhaustive] pub enum DecodeError { ExhaustedInput, InvalidOpcode, InvalidOperand, InvalidPrefixes, TooLong, IncompleteDecoder, } impl yaxpeax_arch::DecodeError for DecodeError { fn data_exhausted(&self) -> bool { self == &DecodeError::ExhaustedInput } fn bad_opcode(&self) -> bool { self == &DecodeError::InvalidOpcode } fn bad_operand(&self) -> bool { self == &DecodeError::InvalidOperand } fn description(&self) -> &'static str { match self { DecodeError::ExhaustedInput => { "exhausted input" }, DecodeError::InvalidOpcode => { "invalid opcode" }, DecodeError::InvalidOperand => { "invalid operand" }, DecodeError::InvalidPrefixes => { "invalid prefixes" }, DecodeError::TooLong => { "too long" }, DecodeError::IncompleteDecoder => { "the decoder is incomplete" }, } } } #[cfg(feature = "std")] extern crate std; #[cfg(feature = "std")] impl std::error::Error for DecodeError { fn description(&self) -> &str { ::description(self) } } #[allow(non_camel_case_types)] #[derive(Debug, Copy, Clone, Eq, PartialEq)] #[repr(u8)] enum OperandSpec { Nothing = 0, // the register in regs[0] RegRRR = 0x01, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed) RegRRR_maskmerge = 0x41, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed with a potentially // custom rounding mode. RegRRR_maskmerge_sae = 0x58, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed. RegRRR_maskmerge_sae_noround = 0x59, // the register in modrm_mmm (eg modrm mod bits were 11) RegMMM = 0x02, // same as `RegRRR`: the register is modrm's `mmm` bits, and may be masked. RegMMM_maskmerge = 0x42, RegMMM_maskmerge_sae_noround = 0x5a, // the register selected by vex-vvvv bits RegVex = 0x03, RegVex_maskmerge = 0x43, // the register selected by a handful of avx2 vex-coded instructions, // stuffed in imm4. Reg4 = 0x04, ImmI8 = 0x05, ImmI16 = 0x06, ImmI32 = 0x07, ImmI64 = 0x08, ImmU8 = 0x09, ImmU16 = 0x0a, // ENTER is a two-immediate instruction, where the first immediate is stored in the disp field. // for this case, a second immediate-style operand is needed. // turns out `insertq` and `extrq` are also two-immediate instructions, so this is generalized // to cover them too. ImmInDispField = 0x0b, DispU32 = 0x8c, DispU64 = 0x8d, Deref = 0x8e, Deref_esi = 0x8f, Deref_edi = 0x90, Deref_rsi = 0x91, Deref_rdi = 0x92, RegDisp = 0x93, RegScale = 0x94, RegScaleDisp = 0x95, RegIndexBaseScale = 0x96, RegIndexBaseScaleDisp = 0x97, Deref_mask = 0xce, RegDisp_mask = 0xd3, RegScale_mask = 0xd4, RegScaleDisp_mask = 0xd5, RegIndexBaseScale_mask = 0xd6, RegIndexBaseScaleDisp_mask = 0xd7, } // the Hash, Eq, and PartialEq impls here are possibly misleading. // They exist because downstream some structs are spelled like // Foo for T == x86_64. This is only to access associated types // which themselves are bounded, but their #[derive] require T to // implement these traits. /// a trivial struct for `yaxpeax_arch::Arch` to be implemented on. it's only interesting for the /// associated type parameters. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Hash, Eq, PartialEq, Debug, Copy, Clone)] #[allow(non_camel_case_types)] pub struct Arch; impl yaxpeax_arch::Arch for Arch { type Address = u64; type Word = u8; type Instruction = Instruction; type DecodeError = DecodeError; type Decoder = InstDecoder; type Operand = Operand; } impl LengthedInstruction for Instruction { type Unit = AddressDiff; #[inline] fn len(&self) -> Self::Unit { AddressDiff::from_const(self.length.into()) } #[inline] fn min_size() -> Self::Unit { AddressDiff::from_const(1) } } /// an `x86_64` instruction decoder. /// /// fundamentally this is one or two primitives with no additional state kept during decoding. it /// can be copied cheaply, hashed cheaply, compared cheaply. if you really want to share an /// `InstDecoder` between threads, you could - but you might want to clone it instead. /// /// unless you're using an `Arc>`, which is _fine_ but i'd be very curious about /// the design requiring that. #[derive(PartialEq, Copy, Clone, Eq, Hash, PartialOrd, Ord)] pub struct InstDecoder { // extensions tracked here: // 0. SSE3 // 1. SSSE3 // 2. monitor (intel-only?) // 3. vmx (some atom chips still lack it) // 4. fma3 (intel haswell/broadwell+, amd piledriver+) // 5. cmpxchg16b (some amd are missing this one) // 6. sse4.1 // 7. sse4.2 // 8. movbe // 9. popcnt (independent of BMI) // 10. aesni // 11. xsave (xsave, xrestor, xsetbv, xgetbv) // 12. rdrand (intel ivybridge+, amd ..??) // 13. sgx (eadd, eblock, ecreate, edbgrd, edbgwr, einit, eldb, eldu, epa, eremove, etrace, // ewb, eenter, eexit, egetkey, ereport, eresume) // 14. bmi1 (intel haswell+, amd jaguar+) // 15. avx2 (intel haswell+, amd excavator+) // 16. bmi2 (intel ?, amd ?) // 17. invpcid // 18. mpx // 19. avx512_f // 20. avx512_dq // 21. rdseed // 22. adx // 23. avx512_fma // 24. pcommit // 25. clflushopt // 26. clwb // 27. avx512_pf // 28. avx512_er // 29. avx512_cd // 30. sha // 31. avx512_bw // 32. avx512_vl // 33. prefetchwt1 // 34. avx512_vbmi // 35. avx512_vbmi2 // 36. gfni (galois field instructions) // 37. vaes // 38. pclmulqdq // 39. avx_vnni // 40. avx512_bitalg // 41. avx512_vpopcntdq // 42. avx512_4vnniw // 43. avx512_4fmaps // 44. cx8 // cmpxchg8 - is this actually optional in x86_64? // 45. syscall // syscall/sysret - actually optional in x86_64? // 46. rdtscp // actually optional in x86_64? // 47. abm (lzcnt, popcnt) // 48. sse4a // 49. 3dnowprefetch // actually optional? // 50. xop // 51. skinit // 52. tbm // 53. intel quirks // 54. amd quirks // 55. avx (intel ?, amd ?) // 56. amd-v/svm // 57. lahfsahf // 58. cmov // 59. f16c // 60. fma4 // 61. prefetchw // 62. tsx // 63. lzcnt flags: u64, } impl InstDecoder { /// instantiates an x86_64 decoder that decodes the bare minimum of x86_64. /// /// pedantic and only decodes what the spec says is well-defined, rejecting undefined sequences /// and any instructions defined by extensions. pub fn minimal() -> Self { InstDecoder { flags: 0, } } /// helper to decode an instruction directly from a byte slice. /// /// this lets callers avoid the work of setting up a [`yaxpeax_arch::U8Reader`] for the slice /// to decode. pub fn decode_slice(&self, data: &[u8]) -> Result { let mut reader = yaxpeax_arch::U8Reader::new(data); self.decode(&mut reader) } pub fn sse3(&self) -> bool { self.flags & (1 << 0) != 0 } pub fn with_sse3(mut self) -> Self { self.flags |= 1 << 0; self } pub fn ssse3(&self) -> bool { self.flags & (1 << 1) != 0 } pub fn with_ssse3(mut self) -> Self { self.flags |= 1 << 1; self } pub fn monitor(&self) -> bool { self.flags & (1 << 2) != 0 } pub fn with_monitor(mut self) -> Self { self.flags |= 1 << 2; self } pub fn vmx(&self) -> bool { self.flags & (1 << 3) != 0 } pub fn with_vmx(mut self) -> Self { self.flags |= 1 << 3; self } pub fn fma3(&self) -> bool { self.flags & (1 << 4) != 0 } pub fn with_fma3(mut self) -> Self { self.flags |= 1 << 4; self } pub fn cmpxchg16b(&self) -> bool { self.flags & (1 << 5) != 0 } pub fn with_cmpxchg16b(mut self) -> Self { self.flags |= 1 << 5; self } pub fn sse4_1(&self) -> bool { self.flags & (1 << 6) != 0 } pub fn with_sse4_1(mut self) -> Self { self.flags |= 1 << 6; self } pub fn sse4_2(&self) -> bool { self.flags & (1 << 7) != 0 } pub fn with_sse4_2(mut self) -> Self { self.flags |= 1 << 7; self } pub fn with_sse4(self) -> Self { self .with_sse4_1() .with_sse4_2() } pub fn movbe(&self) -> bool { self.flags & (1 << 8) != 0 } pub fn with_movbe(mut self) -> Self { self.flags |= 1 << 8; self } pub fn popcnt(&self) -> bool { self.flags & (1 << 9) != 0 } pub fn with_popcnt(mut self) -> Self { self.flags |= 1 << 9; self } pub fn aesni(&self) -> bool { self.flags & (1 << 10) != 0 } pub fn with_aesni(mut self) -> Self { self.flags |= 1 << 10; self } pub fn xsave(&self) -> bool { self.flags & (1 << 11) != 0 } pub fn with_xsave(mut self) -> Self { self.flags |= 1 << 11; self } pub fn rdrand(&self) -> bool { self.flags & (1 << 12) != 0 } pub fn with_rdrand(mut self) -> Self { self.flags |= 1 << 12; self } pub fn sgx(&self) -> bool { self.flags & (1 << 13) != 0 } pub fn with_sgx(mut self) -> Self { self.flags |= 1 << 13; self } pub fn bmi1(&self) -> bool { self.flags & (1 << 14) != 0 } pub fn with_bmi1(mut self) -> Self { self.flags |= 1 << 14; self } pub fn avx2(&self) -> bool { self.flags & (1 << 15) != 0 } pub fn with_avx2(mut self) -> Self { self.flags |= 1 << 15; self } /// `bmi2` indicates support for the `BZHI`, `MULX`, `PDEP`, `PEXT`, `RORX`, `SARX`, `SHRX`, /// and `SHLX` instructions. `bmi2` is implemented in all x86_64 chips that implement `bmi`, /// except the amd `piledriver` and `steamroller` microarchitectures. pub fn bmi2(&self) -> bool { self.flags & (1 << 16) != 0 } pub fn with_bmi2(mut self) -> Self { self.flags |= 1 << 16; self } pub fn invpcid(&self) -> bool { self.flags & (1 << 17) != 0 } pub fn with_invpcid(mut self) -> Self { self.flags |= 1 << 17; self } pub fn mpx(&self) -> bool { self.flags & (1 << 18) != 0 } pub fn with_mpx(mut self) -> Self { self.flags |= 1 << 18; self } pub fn avx512_f(&self) -> bool { self.flags & (1 << 19) != 0 } pub fn with_avx512_f(mut self) -> Self { self.flags |= 1 << 19; self } pub fn avx512_dq(&self) -> bool { self.flags & (1 << 20) != 0 } pub fn with_avx512_dq(mut self) -> Self { self.flags |= 1 << 20; self } pub fn rdseed(&self) -> bool { self.flags & (1 << 21) != 0 } pub fn with_rdseed(mut self) -> Self { self.flags |= 1 << 21; self } pub fn adx(&self) -> bool { self.flags & (1 << 22) != 0 } pub fn with_adx(mut self) -> Self { self.flags |= 1 << 22; self } pub fn avx512_fma(&self) -> bool { self.flags & (1 << 23) != 0 } pub fn with_avx512_fma(mut self) -> Self { self.flags |= 1 << 23; self } pub fn pcommit(&self) -> bool { self.flags & (1 << 24) != 0 } pub fn with_pcommit(mut self) -> Self { self.flags |= 1 << 24; self } pub fn clflushopt(&self) -> bool { self.flags & (1 << 25) != 0 } pub fn with_clflushopt(mut self) -> Self { self.flags |= 1 << 25; self } pub fn clwb(&self) -> bool { self.flags & (1 << 26) != 0 } pub fn with_clwb(mut self) -> Self { self.flags |= 1 << 26; self } pub fn avx512_pf(&self) -> bool { self.flags & (1 << 27) != 0 } pub fn with_avx512_pf(mut self) -> Self { self.flags |= 1 << 27; self } pub fn avx512_er(&self) -> bool { self.flags & (1 << 28) != 0 } pub fn with_avx512_er(mut self) -> Self { self.flags |= 1 << 28; self } pub fn avx512_cd(&self) -> bool { self.flags & (1 << 29) != 0 } pub fn with_avx512_cd(mut self) -> Self { self.flags |= 1 << 29; self } pub fn sha(&self) -> bool { self.flags & (1 << 30) != 0 } pub fn with_sha(mut self) -> Self { self.flags |= 1 << 30; self } pub fn avx512_bw(&self) -> bool { self.flags & (1 << 31) != 0 } pub fn with_avx512_bw(mut self) -> Self { self.flags |= 1 << 31; self } pub fn avx512_vl(&self) -> bool { self.flags & (1 << 32) != 0 } pub fn with_avx512_vl(mut self) -> Self { self.flags |= 1 << 32; self } pub fn prefetchwt1(&self) -> bool { self.flags & (1 << 33) != 0 } pub fn with_prefetchwt1(mut self) -> Self { self.flags |= 1 << 33; self } pub fn avx512_vbmi(&self) -> bool { self.flags & (1 << 34) != 0 } pub fn with_avx512_vbmi(mut self) -> Self { self.flags |= 1 << 34; self } pub fn avx512_vbmi2(&self) -> bool { self.flags & (1 << 35) != 0 } pub fn with_avx512_vbmi2(mut self) -> Self { self.flags |= 1 << 35; self } pub fn gfni(&self) -> bool { self.flags & (1 << 36) != 0 } pub fn with_gfni(mut self) -> Self { self.flags |= 1 << 36; self } pub fn vaes(&self) -> bool { self.flags & (1 << 37) != 0 } pub fn with_vaes(mut self) -> Self { self.flags |= 1 << 37; self } pub fn pclmulqdq(&self) -> bool { self.flags & (1 << 38) != 0 } pub fn with_pclmulqdq(mut self) -> Self { self.flags |= 1 << 38; self } pub fn avx_vnni(&self) -> bool { self.flags & (1 << 39) != 0 } pub fn with_avx_vnni(mut self) -> Self { self.flags |= 1 << 39; self } pub fn avx512_bitalg(&self) -> bool { self.flags & (1 << 40) != 0 } pub fn with_avx512_bitalg(mut self) -> Self { self.flags |= 1 << 40; self } pub fn avx512_vpopcntdq(&self) -> bool { self.flags & (1 << 41) != 0 } pub fn with_avx512_vpopcntdq(mut self) -> Self { self.flags |= 1 << 41; self } pub fn avx512_4vnniw(&self) -> bool { self.flags & (1 << 42) != 0 } pub fn with_avx512_4vnniw(mut self) -> Self { self.flags |= 1 << 42; self } pub fn avx512_4fmaps(&self) -> bool { self.flags & (1 << 43) != 0 } pub fn with_avx512_4fmaps(mut self) -> Self { self.flags |= 1 << 43; self } /// returns `true` if this `InstDecoder` has **all** `avx512` features enabled. pub fn avx512(&self) -> bool { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); (self.flags & avx512_mask) == avx512_mask } /// enable all `avx512` features on this `InstDecoder`. no real CPU, at time of writing, /// actually has such a feature combination, but this is a useful overestimate for `avx512` /// generally. pub fn with_avx512(mut self) -> Self { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); self.flags |= avx512_mask; self } pub fn cx8(&self) -> bool { self.flags & (1 << 44) != 0 } pub fn with_cx8(mut self) -> Self { self.flags |= 1 << 44; self } pub fn syscall(&self) -> bool { self.flags & (1 << 45) != 0 } pub fn with_syscall(mut self) -> Self { self.flags |= 1 << 45; self } pub fn rdtscp(&self) -> bool { self.flags & (1 << 46) != 0 } pub fn with_rdtscp(mut self) -> Self { self.flags |= 1 << 46; self } pub fn abm(&self) -> bool { self.flags & (1 << 47) != 0 } pub fn with_abm(mut self) -> Self { self.flags |= 1 << 47; self } pub fn sse4a(&self) -> bool { self.flags & (1 << 48) != 0 } pub fn with_sse4a(mut self) -> Self { self.flags |= 1 << 48; self } pub fn _3dnowprefetch(&self) -> bool { self.flags & (1 << 49) != 0 } pub fn with_3dnowprefetch(mut self) -> Self { self.flags |= 1 << 49; self } pub fn xop(&self) -> bool { self.flags & (1 << 50) != 0 } pub fn with_xop(mut self) -> Self { self.flags |= 1 << 50; self } pub fn skinit(&self) -> bool { self.flags & (1 << 51) != 0 } pub fn with_skinit(mut self) -> Self { self.flags |= 1 << 51; self } pub fn tbm(&self) -> bool { self.flags & (1 << 52) != 0 } pub fn with_tbm(mut self) -> Self { self.flags |= 1 << 52; self } pub fn intel_quirks(&self) -> bool { self.flags & (1 << 53) != 0 } pub fn with_intel_quirks(mut self) -> Self { self.flags |= 1 << 53; self } pub fn amd_quirks(&self) -> bool { self.flags & (1 << 54) != 0 } pub fn with_amd_quirks(mut self) -> Self { self.flags |= 1 << 54; self } pub fn avx(&self) -> bool { self.flags & (1 << 55) != 0 } pub fn with_avx(mut self) -> Self { self.flags |= 1 << 55; self } pub fn svm(&self) -> bool { self.flags & (1 << 56) != 0 } pub fn with_svm(mut self) -> Self { self.flags |= 1 << 56; self } /// `lahfsahf` is only unset for early revisions of 64-bit amd and intel chips. unfortunately /// the clearest documentation on when these instructions were reintroduced into 64-bit /// architectures seems to be /// [wikipedia](https://en.wikipedia.org/wiki/X86-64#Older_implementations): /// ```text /// Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD /// introduced these instructions (also in 64-bit mode) with their Athlon 64, Opteron and /// Turion 64 revision D processors in March 2005[48][49][50] while Intel introduced the /// instructions with the Pentium 4 G1 stepping in December 2005. The 64-bit version of Windows /// 8.1 requires this feature.[47] /// ``` /// /// this puts reintroduction of these instructions somewhere in the middle of prescott and k8 /// lifecycles, for intel and amd respectively. because there is no specific uarch where these /// features become enabled, prescott and k8 default to not supporting these instructions, /// where later uarches support these instructions. pub fn lahfsahf(&self) -> bool { self.flags & (1 << 57) != 0 } pub fn with_lahfsahf(mut self) -> Self { self.flags |= 1 << 57; self } pub fn cmov(&self) -> bool { self.flags & (1 << 58) != 0 } pub fn with_cmov(mut self) -> Self { self.flags |= 1 << 58; self } pub fn f16c(&self) -> bool { self.flags & (1 << 59) != 0 } pub fn with_f16c(mut self) -> Self { self.flags |= 1 << 59; self } pub fn fma4(&self) -> bool { self.flags & (1 << 60) != 0 } pub fn with_fma4(mut self) -> Self { self.flags |= 1 << 60; self } pub fn prefetchw(&self) -> bool { self.flags & (1 << 61) != 0 } pub fn with_prefetchw(mut self) -> Self { self.flags |= 1 << 61; self } pub fn tsx(&self) -> bool { self.flags & (1 << 62) != 0 } pub fn with_tsx(mut self) -> Self { self.flags |= 1 << 62; self } pub fn lzcnt(&self) -> bool { self.flags & (1 << 63) != 0 } pub fn with_lzcnt(mut self) -> Self { self.flags |= 1 << 63; self } /// optionally reject or reinterpret instruction according to the decoder's /// declared extensions. fn revise_instruction(&self, inst: &mut Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex().is_some() { if !self.avx512() { return Err(DecodeError::InvalidOpcode); } else { return Ok(()); } } match inst.opcode { Opcode::TZCNT => { if !self.bmi1() { // tzcnt is only supported if bmi1 is enabled. without bmi1, this decodes as // bsf. inst.opcode = Opcode::BSF; } } Opcode::LDDQU | Opcode::ADDSUBPS | Opcode::ADDSUBPD | Opcode::HADDPS | Opcode::HSUBPS | Opcode::HADDPD | Opcode::HSUBPD | Opcode::MOVSHDUP | Opcode::MOVSLDUP | Opcode::MOVDDUP | Opcode::MONITOR | Opcode::MWAIT => { // via Intel section 5.7, SSE3 Instructions if !self.sse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PHADDW | Opcode::PHADDSW | Opcode::PHADDD | Opcode::PHSUBW | Opcode::PHSUBSW | Opcode::PHSUBD | Opcode::PABSB | Opcode::PABSW | Opcode::PABSD | Opcode::PMADDUBSW | Opcode::PMULHRSW | Opcode::PSHUFB | Opcode::PSIGNB | Opcode::PSIGNW | Opcode::PSIGND | Opcode::PALIGNR => { // via Intel section 5.8, SSSE3 Instructions if !self.ssse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PMULLD | Opcode::PMULDQ | Opcode::MOVNTDQA | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::PBLENDVB | Opcode::BLENDW | Opcode::PMINUW | Opcode::PMINUD | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMAXUW | Opcode::PMAXUD | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::ROUNDPS | Opcode::ROUNDPD | Opcode::ROUNDSS | Opcode::ROUNDSD | Opcode::PBLENDW | Opcode::EXTRACTPS | Opcode::INSERTPS | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::PMOVSXBW | Opcode::PMOVZXBW | Opcode::PMOVSXBD | Opcode::PMOVZXBD | Opcode::PMOVSXWD | Opcode::PMOVZXWD | Opcode::PMOVSXBQ | Opcode::PMOVZXBQ | Opcode::PMOVSXWQ | Opcode::PMOVZXWQ | Opcode::PMOVSXDQ | Opcode::PMOVZXDQ | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::PHMINPOSUW | Opcode::PTEST | Opcode::PCMPEQQ | Opcode::PEXTRB | Opcode::PEXTRW | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::PACKUSDW => { // via Intel section 5.10, SSE4.1 Instructions if !self.sse4_1() { return Err(DecodeError::InvalidOpcode); } } Opcode::EXTRQ | Opcode::INSERTQ | Opcode::MOVNTSS | Opcode::MOVNTSD => { if !self.sse4a() { return Err(DecodeError::InvalidOpcode); } } Opcode::CRC32 | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PCMPGTQ => { // via Intel section 5.11, SSE4.2 Instructions if !self.sse4_2() { return Err(DecodeError::InvalidOpcode); } } Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::PCLMULQDQ => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.pclmulqdq() { return Err(DecodeError::InvalidOpcode); } } Opcode::XABORT | Opcode::XBEGIN | Opcode::XEND | Opcode::XTEST => { if !self.tsx() { return Err(DecodeError::InvalidOpcode); } } Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA1NEXTE | Opcode::SHA1RNDS4 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::SHA256RNDS2 => { if !self.sha() { return Err(DecodeError::InvalidOpcode); } } Opcode::ENCLV | Opcode::ENCLS | Opcode::ENCLU => { if !self.sgx() { return Err(DecodeError::InvalidOpcode); } } // AVX... Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VCVTPD2DQ | Opcode::VLDDQU | Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTSS2SD | Opcode::VCVTSI2SS | Opcode::VCVTSI2SD | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSS2SI | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTTSS2SI | Opcode::VCVTTSD2SI | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VDPPD | Opcode::VDPPS | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::VMOVQ | Opcode::VMOVSS | Opcode::VMOVSD | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMPSADBW | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPALIGNR | Opcode::VPAND | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VORPD | Opcode::VORPS | Opcode::VPANDN | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPCLMULQDQ | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPMADDUBSW | Opcode::VPHMINPOSUW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMADDWD | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::VPOR | Opcode::VPSADBW | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VPTEST | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VPXOR | Opcode::VRCPPS | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::VRSQRTPS | Opcode::VRSQRTSS | Opcode::VRCPSS | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSQRTSS | Opcode::VSQRTSD | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VXORPD | Opcode::VXORPS | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VLDMXCSR | Opcode::VSTMXCSR => { // TODO: check a table for these if !self.avx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { // TODO: check a table for these if !self.avx() || !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::MOVBE => { if !self.movbe() { return Err(DecodeError::InvalidOpcode); } } Opcode::POPCNT => { /* * from the intel SDM: * ``` * Before an application attempts to use the POPCNT instruction, it must check that * the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1) and POPCNT * (if CPUID.01H:ECX.POPCNT[bit 23] = 1). * ``` */ if self.intel_quirks() && (self.sse4_2() || self.popcnt()) { return Ok(()); } else if !self.popcnt() { /* * elsewhere from the amd APM: * `Instruction Subsets and CPUID Feature Flags` on page 507 indicates that * popcnt is present when the popcnt bit is reported by cpuid. this seems to be * the less quirky default, so `intel_quirks` is considered the outlier, and * before this default. * */ return Err(DecodeError::InvalidOpcode); } } Opcode::LZCNT => { /* * amd APM, `LZCNT` page 212: * LZCNT is an Advanced Bit Manipulation (ABM) instruction. Support for the LZCNT * instruction is indicated by CPUID Fn8000_0001_ECX[ABM] = 1. * * meanwhile the intel SDM simply states: * ``` * CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the * LZCNT instruction. * ``` * * so that's considered the less-quirky (default) case here. * */ if self.amd_quirks() && !self.abm() { return Err(DecodeError::InvalidOpcode); } else if !self.lzcnt() { return Err(DecodeError::InvalidOpcode); } } Opcode::ADCX | Opcode::ADOX => { if !self.adx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VMRUN | Opcode::VMLOAD | Opcode::VMSAVE | Opcode::CLGI | Opcode::VMMCALL | Opcode::INVLPGA => { if !self.svm() { return Err(DecodeError::InvalidOpcode); } } Opcode::STGI | Opcode::SKINIT => { if !self.svm() || !self.skinit() { return Err(DecodeError::InvalidOpcode); } } Opcode::LAHF | Opcode::SAHF => { if !self.lahfsahf() { return Err(DecodeError::InvalidOpcode); } } Opcode::VCVTPS2PH | Opcode::VCVTPH2PS => { /* * from intel SDM: * ``` * 14.4.1 Detection of F16C Instructions Application using float 16 instruction * must follow a detection sequence similar to AVX to ensure: • The OS has * enabled YMM state management support, • The processor support AVX as * indicated by the CPUID feature flag, i.e. CPUID.01H:ECX.AVX[bit 28] = 1. • * The processor support 16-bit floating-point conversion instructions via a * CPUID feature flag (CPUID.01H:ECX.F16C[bit 29] = 1). * ``` * * TODO: only the VEX-coded variant of this instruction should be gated on `f16c`. * the EVEX-coded variant should be gated on `avx512f` or `avx512vl` if not * EVEX.512-coded. */ if !self.avx() || !self.f16c() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDRAND => { if !self.rdrand() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDSEED => { if !self.rdseed() { return Err(DecodeError::InvalidOpcode); } } Opcode::MONITORX | Opcode::MWAITX | // these are gated on the `monitorx` and `mwaitx` cpuid bits, but are AMD-only. Opcode::CLZERO | Opcode::RDPRU => { // again, gated on specific cpuid bits, but AMD-only. if !self.amd_quirks() { return Err(DecodeError::InvalidOpcode); } } other => { if !self.bmi1() { if BMI1.contains(&other) { return Err(DecodeError::InvalidOpcode); } } if !self.bmi2() { if BMI2.contains(&other) { return Err(DecodeError::InvalidOpcode); } } } } Ok(()) } } impl Default for InstDecoder { /// Instantiates an x86_64 decoder that probably decodes what you want. /// /// Attempts to match real processors in interpretation of undefined sequences, and decodes any /// instruction defined in any extension. fn default() -> Self { Self { flags: 0xffffffff_ffffffff, } } } impl Decoder for InstDecoder { fn decode::Address, ::Word>>(&self, words: &mut T) -> Result::DecodeError> { let mut instr = Instruction::invalid(); DecodeCtx::new().read_with_annotations(self, words, &mut instr, &mut NullSink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(&mut instr)?; } Ok(instr) } #[inline(always)] fn decode_into::Address, ::Word>>(&self, instr: &mut Instruction, words: &mut T) -> Result<(), ::DecodeError> { self.decode_with_annotation(instr, words, &mut NullSink) } } impl AnnotatingDecoder for InstDecoder { type FieldDescription = FieldDescription; #[inline(always)] fn decode_with_annotation< T: Reader<::Address, ::Word>, S: DescriptionSink >(&self, instr: &mut Instruction, words: &mut T, sink: &mut S) -> Result<(), ::DecodeError> { DecodeCtx::new().read_with_annotations(self, words, instr, sink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(instr)?; } Ok(()) } } impl Opcode { /// check if the instruction is one of x86's sixteen conditional jump instructions. use this /// rather than `opcode.to_string().starts_with("j") && opcode != Opcode::JMP`, thank you. pub fn is_jcc(&self) -> bool { match self { Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JG | Opcode::JLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional move instructions. pub fn is_cmovcc(&self) -> bool { match self { Opcode::CMOVO | Opcode::CMOVNO | Opcode::CMOVB | Opcode::CMOVNB | Opcode::CMOVZ | Opcode::CMOVNZ | Opcode::CMOVA | Opcode::CMOVNA | Opcode::CMOVS | Opcode::CMOVNS | Opcode::CMOVP | Opcode::CMOVNP | Opcode::CMOVL | Opcode::CMOVGE | Opcode::CMOVG | Opcode::CMOVLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional set instructions. pub fn is_setcc(&self) -> bool { match self { Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETA | Opcode::SETBE | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETG | Opcode::SETLE => true, _ => false } } /// get the [`ConditionCode`] for this instruction, if it is in fact conditional. x86's /// conditional instructions are `Jcc`, `CMOVcc`, andd `SETcc`. pub fn condition(&self) -> Option { match self { Opcode::JO | Opcode::CMOVO | Opcode::SETO => { Some(ConditionCode::O) }, Opcode::JNO | Opcode::CMOVNO | Opcode::SETNO => { Some(ConditionCode::NO) }, Opcode::JB | Opcode::CMOVB | Opcode::SETB => { Some(ConditionCode::B) }, Opcode::JNB | Opcode::CMOVNB | Opcode::SETAE => { Some(ConditionCode::AE) }, Opcode::JZ | Opcode::CMOVZ | Opcode::SETZ => { Some(ConditionCode::Z) }, Opcode::JNZ | Opcode::CMOVNZ | Opcode::SETNZ => { Some(ConditionCode::NZ) }, Opcode::JA | Opcode::CMOVA | Opcode::SETA => { Some(ConditionCode::A) }, Opcode::JNA | Opcode::CMOVNA | Opcode::SETBE => { Some(ConditionCode::BE) }, Opcode::JS | Opcode::CMOVS | Opcode::SETS => { Some(ConditionCode::S) }, Opcode::JNS | Opcode::CMOVNS | Opcode::SETNS => { Some(ConditionCode::NS) }, Opcode::JP | Opcode::CMOVP | Opcode::SETP => { Some(ConditionCode::P) }, Opcode::JNP | Opcode::CMOVNP | Opcode::SETNP => { Some(ConditionCode::NP) }, Opcode::JL | Opcode::CMOVL | Opcode::SETL => { Some(ConditionCode::L) }, Opcode::JGE | Opcode::CMOVGE | Opcode::SETGE => { Some(ConditionCode::GE) }, Opcode::JG | Opcode::CMOVG | Opcode::SETG => { Some(ConditionCode::G) }, Opcode::JLE | Opcode::CMOVLE | Opcode::SETLE => { Some(ConditionCode::LE) }, _ => None, } } } impl Default for Instruction { fn default() -> Self { Instruction::invalid() } } impl Instruction { /// get the `Opcode` of this instruction. pub fn opcode(&self) -> Opcode { self.opcode } /// get the `Operand` at the provided index. /// /// panics if the index is `>= 4`. pub fn operand(&self, i: u8) -> Operand { assert!(i < 4); Operand::from_spec(self, self.operands[i as usize]) } /// get the number of operands in this instruction. useful in iterating an instruction's /// operands generically. pub fn operand_count(&self) -> u8 { self.operand_count } /// check if operand `i` is an actual operand or not. will be `false` for `i >= /// inst.operand_count()`. pub fn operand_present(&self, i: u8) -> bool { assert!(i < 4); if i >= self.operand_count { return false; } if let OperandSpec::Nothing = self.operands[i as usize] { false } else { true } } /// get the memory access information for this instruction, if it accesses memory. /// /// the corresponding `MemoryAccessSize` may report that the size of accessed memory is /// indeterminate; this is the case for `xsave/xrestor`-style instructions whose operation size /// varies based on physical processor. pub fn mem_size(&self) -> Option { if self.mem_size != 0 { Some(MemoryAccessSize { size: self.mem_size }) } else { None } } /// build a new instruction representing nothing in particular. this is primarily useful as a /// default to pass to `decode_into`. pub fn invalid() -> Instruction { Instruction { prefixes: Prefixes::new(0), opcode: Opcode::NOP, mem_size: 0, regs: [RegSpec::rax(); 4], scale: 0, length: 0, disp: 0, imm: 0, operand_count: 0, operands: [OperandSpec::Nothing; 4], } } /// get the `Segment` that will *actually* be used for accessing the operand at index `i`. /// /// `stos`, `lods`, `movs`, and `cmps` specifically name some segments for use regardless of /// prefixes. pub fn segment_override_for_op(&self, op: u8) -> Option { match self.opcode { Opcode::STOS | Opcode::SCAS => { if op == 0 { Some(Segment::ES) } else { None } } Opcode::LODS => { if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::MOVS => { if op == 0 { Some(Segment::ES) } else if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::CMPS => { if op == 0 { Some(self.prefixes.segment) } else if op == 1 { Some(Segment::ES) } else { None } }, _ => { // most operands are pretty simple: if self.operands[op as usize].is_memory() && self.prefixes.segment != Segment::DS { Some(self.prefixes.segment) } else { None } } } } #[cfg(feature = "fmt")] /// wrap a reference to this instruction with a `DisplayStyle` to format the instruction with /// later. see the documentation on [`display::DisplayStyle`] for more. /// /// ``` /// use yaxpeax_x86::long_mode::{InstDecoder, DisplayStyle}; /// /// let decoder = InstDecoder::default(); /// let inst = decoder.decode_slice(&[0x33, 0xc1]).unwrap(); /// /// assert_eq!("eax ^= ecx", inst.display_with(DisplayStyle::C).to_string()); /// assert_eq!("xor eax, ecx", inst.display_with(DisplayStyle::Intel).to_string()); /// ``` pub fn display_with<'a>(&'a self, style: display::DisplayStyle) -> display::InstructionDisplayer<'a> { display::InstructionDisplayer { style, instr: self, } } /// does this instruction include the `xacquire` hint for hardware lock elision? pub fn xacquire(&self) -> bool { if self.prefixes.repnz() { // xacquire is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else { false } } else { false } } /// does this instruction include the `xrelease` hint for hardware lock elision? pub fn xrelease(&self) -> bool { if self.prefixes.rep() { // xrelease is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. additionally, xrelease is permitted on some forms of mov. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else if self.opcode == Opcode::MOV { self.operands[0] != OperandSpec::RegMMM && ( self.operands[1] == OperandSpec::RegRRR || self.operands[1] == OperandSpec::ImmI8 || self.operands[1] == OperandSpec::ImmI16 || self.operands[1] == OperandSpec::ImmI32 || self.operands[1] == OperandSpec::ImmI64 ) } else { false } } else { false } } } #[derive(Debug, Copy, Clone, Eq, PartialEq)] struct EvexData { // data: present, z, b, Lp, Rp. aaa bits: u8, } /// the prefixes on an instruction. /// /// `rep`, `repnz`, `lock`, and segment override prefixes are directly accessible here. `rex`, /// `vex`, and `evex` prefixes are available through their associated helpers. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct Prefixes { bits: u8, rex: PrefixRex, segment: Segment, evex_data: EvexData, } /// the `avx512`-related data from an [`evex`](https://en.wikipedia.org/wiki/EVEX_prefix) prefix. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixEvex { vex: PrefixVex, evex_data: EvexData, } impl PrefixEvex { fn present(&self) -> bool { self.evex_data.present() } /// the `evex` prefix's parts that overlap with `vex` definitions - `L`, `W`, `R`, `X`, and `B` /// bits. pub fn vex(&self) -> PrefixVex { self.vex } /// the `avx512` mask register in use. `0` indicates "no mask register". pub fn mask_reg(&self) -> u8 { self.evex_data.aaa() } pub fn broadcast(&self) -> bool { self.evex_data.b() } pub fn merge(&self) -> bool { self.evex_data.z() } /// the `evex` `L'` bit. pub fn lp(&self) -> bool { self.evex_data.lp() } /// the `evex` `R'` bit. pub fn rp(&self) -> bool { self.evex_data.rp() } } /// bits specified in an avx/avx2 [`vex`](https://en.wikipedia.org/wiki/VEX_prefix) prefix, `L`, `W`, `R`, `X`, and `B`. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixVex { bits: u8, } #[allow(dead_code)] impl PrefixVex { #[inline] fn present(&self) -> bool { (self.bits & 0x80) == 0x80 } #[inline] pub fn b(&self) -> bool { (self.bits & 0x01) == 0x01 } #[inline] pub fn x(&self) -> bool { (self.bits & 0x02) == 0x02 } #[inline] pub fn r(&self) -> bool { (self.bits & 0x04) == 0x04 } #[inline] pub fn w(&self) -> bool { (self.bits & 0x08) == 0x08 } #[inline] pub fn l(&self) -> bool { (self.bits & 0x10) == 0x10 } #[inline] fn compressed_disp(&self) -> bool { (self.bits & 0x20) == 0x20 } } /// bits specified in an x86_64 /// [`rex`](https://wiki.osdev.org/X86-64_Instruction_Encoding#REX_prefix) prefix. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixRex { bits: u8 } impl Prefixes { fn new(bits: u8) -> Prefixes { Prefixes { bits: bits, rex: PrefixRex { bits: 0 }, segment: Segment::DS, evex_data: EvexData { bits: 0 }, } } #[inline] pub fn rep(&self) -> bool { self.bits & 0x30 == 0x10 } #[inline] fn set_rep(&mut self) { self.bits = (self.bits & 0xcf) | 0x10 } #[inline] pub fn repnz(&self) -> bool { self.bits & 0x30 == 0x30 } #[inline] fn set_repnz(&mut self) { self.bits = (self.bits & 0xcf) | 0x30 } #[inline] pub fn rep_any(&self) -> bool { self.bits & 0x30 != 0x00 } #[inline] fn operand_size(&self) -> bool { self.bits & 0x1 == 1 } #[inline] fn set_operand_size(&mut self) { self.bits = self.bits | 0x1; } #[inline] fn unset_operand_size(&mut self) { self.bits = self.bits & !0x1; } #[inline] fn address_size(&self) -> bool { self.bits & 0x2 == 2 } #[inline] fn set_address_size(&mut self) { self.bits = self.bits | 0x2 } #[inline] fn set_lock(&mut self) { self.bits |= 0x4 } #[inline] pub fn lock(&self) -> bool { self.bits & 0x4 == 4 } #[deprecated(since = "0.0.1", note = "pub fn cs has never returned `bool` indicating the current selector is `cs`. use `selects_cs` for this purpose, until 2.x that will correct `pub fn cs`.")] #[inline] pub fn cs(&mut self) {} #[inline] pub fn selects_cs(&self) -> bool { self.segment == Segment::CS } #[inline] pub fn ds(&self) -> bool { self.segment == Segment::DS } #[inline] pub fn es(&self) -> bool { self.segment == Segment::ES } #[inline] pub fn fs(&self) -> bool { self.segment == Segment::FS } #[inline] fn set_fs(&mut self) { self.segment = Segment::FS } #[inline] pub fn gs(&self) -> bool { self.segment == Segment::GS } #[inline] fn set_gs(&mut self) { self.segment = Segment::GS } #[inline] pub fn ss(&self) -> bool { self.segment == Segment::SS } #[inline] fn rex_unchecked(&self) -> PrefixRex { self.rex } #[inline] pub fn rex(&self) -> Option { let rex = self.rex_unchecked(); if rex.present() { Some(rex) } else { None } } #[inline] fn vex_unchecked(&self) -> PrefixVex { PrefixVex { bits: self.rex.bits } } #[inline] fn vex_invalid(&self) -> bool { /* * if instruction.prefixes.rex_unchecked().present() * || instruction.prefixes.lock() * || instruction.prefixes.operand_size() * || instruction.prefixes.rep() * || instruction.prefixes.repnz() { */ (self.bits & 0b1100_0101) > 0 || (self.rex.bits > 0) } #[inline] pub fn vex(&self) -> Option { let vex = self.vex_unchecked(); if vex.present() { Some(vex) } else { None } } #[inline] fn evex_unchecked(&self) -> PrefixEvex { PrefixEvex { vex: PrefixVex { bits: self.rex.bits }, evex_data: self.evex_data } } #[inline] pub fn evex(&self) -> Option { let evex = self.evex_unchecked(); if evex.present() { Some(evex) } else { None } } #[inline] fn apply_compressed_disp(&mut self, state: bool) { if state { self.rex.bits |= 0x20; } else { self.rex.bits &= 0xdf; } } #[inline] fn rex_from(&mut self, bits: u8) { self.rex.bits = bits; } #[inline] fn vex_from_c5(&mut self, bits: u8) { // collect rex bits let r = bits & 0x80; let wrxb = (r >> 5) ^ 0x04; let l = (bits & 0x04) << 2; let synthetic_rex = wrxb | l | 0x80; self.rex.from(synthetic_rex); } #[inline] fn vex_from_c4(&mut self, high: u8, low: u8) { let w = low & 0x80; let rxb = (high >> 5) ^ 0x07; let wrxb = rxb | (w >> 4); let l = (low & 0x04) << 2; let synthetic_rex = wrxb | l | 0x80; self.rex.from(synthetic_rex); } #[inline] fn evex_from(&mut self, b1: u8, b2: u8, b3: u8) { let w = b2 & 0x80; let rxb = ((b1 >> 5) & 0b111) ^ 0b111; // `rxb` is provided in inverted form let wrxb = rxb | (w >> 4); let l = (b3 & 0x20) >> 1; let synthetic_rex = wrxb | l | 0x80; self.rex.from(synthetic_rex); // R' is provided in inverted form let rp = ((b1 & 0x10) >> 4) ^ 1; let lp = (b3 & 0x40) >> 6; let aaa = b3 & 0b111; let z = (b3 & 0x80) >> 7; let b = (b3 & 0x10) >> 4; self.evex_data.from(rp, lp, z, b, aaa); } } impl EvexData { fn from(&mut self, rp: u8, lp: u8, z: u8, b: u8, aaa: u8) { let mut bits = 0; bits |= aaa; bits |= b << 3; bits |= z << 4; bits |= lp << 5; bits |= rp << 6; bits |= 0x80; self.bits = bits; } } impl EvexData { pub(crate) fn present(&self) -> bool { self.bits & 0b1000_0000 != 0 } pub(crate) fn aaa(&self) -> u8 { self.bits & 0b111 } pub(crate) fn b(&self) -> bool { (self.bits & 0b0000_1000) != 0 } pub(crate) fn z(&self) -> bool { (self.bits & 0b0001_0000) != 0 } pub(crate) fn lp(&self) -> bool { (self.bits & 0b0010_0000) != 0 } pub(crate) fn rp(&self) -> bool { (self.bits & 0b0100_0000) != 0 } } impl PrefixRex { #[inline] fn present(&self) -> bool { (self.bits & 0xc0) == 0x40 } #[inline] pub fn b(&self) -> bool { (self.bits & 0x01) == 0x01 } #[inline] pub fn x(&self) -> bool { (self.bits & 0x02) == 0x02 } #[inline] pub fn r(&self) -> bool { (self.bits & 0x04) == 0x04 } #[inline] pub fn w(&self) -> bool { (self.bits & 0x08) == 0x08 } #[inline] fn from(&mut self, prefix: u8) { self.bits = prefix; } } #[derive(Debug, Copy, Clone)] struct OperandCodeBuilder { bits: u16 } #[allow(non_camel_case_types)] enum ZOperandCategory { Zv_R = 0, Zv_AX = 1, Zb_Ib_R = 2, Zv_Ivq_R = 3, } struct ZOperandInstructions { bits: u16 } impl ZOperandInstructions { fn category(&self) -> u8 { (self.bits >> 4) as u8 & 0b11 } fn reg(&self) -> u8 { (self.bits & 0b111) as u8 } } struct EmbeddedOperandInstructions { bits: u16 } impl EmbeddedOperandInstructions { #[allow(unused)] fn bits(&self) -> u16 { self.bits } } #[allow(non_snake_case)] impl OperandCodeBuilder { const fn new() -> Self { OperandCodeBuilder { bits: 0 } } const fn bits(&self) -> u16 { self.bits as u16 } const fn from_bits(bits: u16) -> Self { Self { bits } } const fn read_modrm(mut self) -> Self { self.bits |= 0x8000; self } // deny ModRM `mod=11` const fn deny_regmmm(mut self) -> Self { self.bits |= 0x2000; self } const fn denies_regmmm(&self) -> bool { self.bits & 0x2000 != 0 } const fn set_embedded_instructions(mut self) -> Self { self.bits |= 0x4000; self } fn has_embedded_instructions(&self) -> bool { self.bits & 0x4000 != 0 } fn get_embedded_instructions(&self) -> Option { // 0x4000 indicates embedded instructions // 0x3fff > 0x0080 indicates the embedded instructions are a Z-style operand if self.has_embedded_instructions() { Some(ZOperandInstructions { bits: self.bits }) } else { None } } fn operand_case_handler_index(&self) -> OperandCase { unsafe { core::mem::transmute(self.bits as u8) } } const fn operand_case(mut self, case: OperandCase) -> Self { // leave 0x4000 unset self.bits |= case as u8 as u16; self } const fn op0_is_rrr_and_Z_operand(mut self, category: ZOperandCategory, reg_num: u8) -> Self { self = self.set_embedded_instructions(); // if op0 is rrr, 0x2000 unset indicates the operand category written in bits 11:10 // further, reg number is bits 0:2 // // when 0x2000 is unset: // 0x1cf8 are all unused bits, so far // // if you're counting, that's 8 bits remaining. // it also means one of those (0x0400?) can be used to pick some other interpretation // scheme. self.bits |= (category as u8 as u16) << 4; self.bits |= reg_num as u16 & 0b111; self } const fn read_E(mut self) -> Self { self.bits |= 0x1000; self } const fn has_read_E(&self) -> bool { self.bits & 0x1000 != 0 } const fn byte_operands(mut self) -> Self { self.bits |= 0x0800; self } const fn mem_reg(mut self) -> Self { self.bits |= 0x0400; self } const fn reg_mem(self) -> Self { // 0x0400 unset self } const fn has_byte_operands(&self) -> bool { (self.bits & 0x0800) != 0 } const fn has_reg_mem(&self) -> bool { (self.bits & 0x0400) == 0 } const fn only_modrm_operands(mut self) -> Self { self.bits |= 0x0200; self } const fn is_only_modrm_operands(&self) -> bool { self.bits & 0x0200 != 0 } // WHEN AN IMMEDIATE IS PRESENT, THERE ARE ONLY 0x3F ALLOWED SPECIAL CASES. // WHEN NO IMMEDIATE IS PRESENT, THERE ARE 0xFF ALLOWED SPECIAL CASES. // SIZE IS DECIDED BY THE FOLLOWING TABLE: // 0: 1 BYTE // 1: 4 BYTES const fn only_imm(mut self) -> Self { self.bits |= 0x100; self } fn has_imm(&self) -> bool { self.bits & 0x100 != 0 } } /// a wrapper to hide internal library implementation details. this is only useful for the inner /// content's `Display` impl, which itself is unstable and suitable only for human consumption. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub struct OperandCodeWrapper { code: OperandCode } #[allow(non_camel_case_types)] #[derive(Debug, PartialEq, Copy, Clone)] #[repr(u8)] enum OperandCase { Internal = 0, // handled internally and completely by embedded rules. Gv_M = 1, // "internal", but must be distinguished from Gv_Ev Ibs = 2, Jvds = 3, Nothing = 4, // no operands. this is distinct from `Internal`: `Internal` may specify one or two operands depending on embedded rules. SingleMMMOper = 5, // one operand, disregard rrr bits of modrm. BaseOpWithI8 = 6, BaseOpWithIv = 7, MovI8 = 8, MovIv = 9, BitwiseWithI8 = 10, // BitwiseWithIv = 9, ShiftBy1_b, ShiftBy1_v, BitwiseByCL, ModRM_0x8f, ModRM_0xf6, ModRM_0xf7, ModRM_0xfe, ModRM_0xff, Gv_Eb, Gv_Ew, Gdq_Ed, I_3, E_G_xmm, G_M_xmm, G_E_xmm, G_E_xmm_Ib, AL_Ibs, AX_Ivd, Ivs, ModRM_0x83, Ed_G_xmm, G_Ed_xmm, /* Nothing = Nothing, Eb_R0 = SingleMMMOper, Ev = SingleMMMOper, ModRM_0x80_Eb_Ib = BaseOpWithI8, ModRM_0x81_Ev_Ivs = BaseOpWithIv, ModRM_0xc6_Eb_Ib = MovI8, ModRM_0xc7_Ev_Iv = MovIv, ModRM_0xc0_Eb_Ib = BitwiseWithI8, ModRM_0xc1_Ev_Ib = BitwiseWithIv, ModRM_0xd0_Eb_1 = ShiftBy1_b, ModRM_0xd1_Ev_1 = ShiftBy1_v, ModRM_0x8f_Ev = ModRM_0x8f, ModRM_0xd2_Eb_CL = BitwiseByCL, ModRM_0xd3_Ev_CL = BitwiseByCL, ModRM_0xf6 = ModRM_0xf6_0xf7, ModRM_0xf7 = ModRM_0xf6_0xf7, ModRM_0xfe_Eb = ModRM_0xfe, ModRM_0xff_Ev = ModRM_0xff, Gv_Eb = Gv_Eb, Gv_Ew = Gv_Ew, Gdq_Ed = Gdq_Ed, I_3 = I_3, E_G_xmm = E_G_xmm, G_M_xmm = G_M_xmm, G_E_xmm = G_E_xmm, G_E_xmm_Ib = G_E_xmm_Ib, AL_Ibs = AL_Ibs, AX_Ivd = AX_Ivd, Ivs = Ivs, ModRM_0x83_Ev_Ibs = ModRM_0x83, Ed_G_xmm = Ed_G_xmm, G_Ed_xmm = G_Ed_xmm, */ Ib, x87_d8, x87_d9, x87_da, x87_db, x87_dc, x87_dd, x87_de, x87_df, AL_Ib, AX_Ib, Ib_AL, Ib_AX, Gv_Ew_LAR, Gv_Ew_LSL, Gdq_Ev, Gv_Ev_Ib, Gv_Ev_Iv, AX_DX, AL_DX, DX_AX, DX_AL, MOVQ_f30f, Yv_Xv, Gd_Ed, Mdq_Gdq, Md_Gd, AL_Ob, AL_Xb, AX_Ov, G_xmm_E_mm, G_xmm_U_mm, G_mm_U_xmm, Rv_Gmm_Ib, G_xmm_Edq, G_xmm_Eq, G_mm_E_xmm, Gd_U_xmm, Gdq_Eq_xmm, Gv_E_xmm, G_xmm_Ew_Ib, G_E_xmm_Ub, G_U_xmm_Ub, G_U_xmm, M_G_xmm, G_E_mm, G_U_mm, E_G_mm, Edq_G_mm, Edq_G_xmm, G_mm_Edq, G_mm_E, Ev_Gv_Ib, Ev_Gv_CL, G_mm_U_mm, G_Mq_mm, G_mm_Ew_Ib, G_E_q, E_G_q, CVT_AA, CVT_DA, Rq_Cq_0, Rq_Dq_0, Cq_Rq_0, Dq_Rq_0, FS, GS, Yb_DX, Yv_DX, DX_Xb, DX_Xv, AH, AX_Xv, Ew_Sw, Fw, I_1, Iw, Iw_Ib, Ob_AL, Ov_AX, Sw_Ew, Yb_AL, Yb_Xb, Yv_AX, INV_Gv_M, PMOVX_G_E_xmm, PMOVX_E_G_xmm, G_Ev_xmm_Ib, G_E_mm_Ib, MOVDIR64B, ModRM_0x0f00, ModRM_0x0f01, ModRM_0x0f0d, ModRM_0x0f0f, ModRM_0x0f12, ModRM_0x0f16, ModRM_0x0f18, ModRM_0x0f71, ModRM_0x0f72, ModRM_0x0f73, ModRM_0x0fae, ModRM_0x0fba, ModRM_0x0fc7, ModRM_0x660f78, ModRM_0xf20f78, ModRM_0xf30f1e, ModRM_0xf30f38d8, ModRM_0xf30f38dc, ModRM_0xf30f38dd, ModRM_0xf30f38de, ModRM_0xf30f38df, ModRM_0xf30f38fa, ModRM_0xf30f38fb, ModRM_0xf30f3af0, } #[allow(non_camel_case_types)] // might be able to pack these into a u8, but with `Operand` being u16 as well now there's little // point. table entries will have a padding byte per record already. // // many of the one-off per-opcode variants could be written as 'decide based on opcode' but trying // to pack this more tightly only makes sense if opcode were smaller, to get some space savings. // // bit 15 is "read modrm?" // 0bMxxx_xxxx_xxxx_xxxx // | // | // | // | // | // | // ---------------------------> read modr/m? #[repr(u16)] #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum OperandCode { Ivs = OperandCodeBuilder::new().operand_case(OperandCase::Ivs).bits(), I_3 = OperandCodeBuilder::new().operand_case(OperandCase::I_3).bits(), Nothing = OperandCodeBuilder::new().operand_case(OperandCase::Nothing).bits(), Ib = OperandCodeBuilder::new().operand_case(OperandCase::Ib).bits(), Ibs = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Ibs).bits(), Jvds = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Jvds).bits(), Yv_Xv = OperandCodeBuilder::new().operand_case(OperandCase::Yv_Xv).bits(), x87_d8 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d8).bits(), x87_d9 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d9).bits(), x87_da = OperandCodeBuilder::new().operand_case(OperandCase::x87_da).bits(), x87_db = OperandCodeBuilder::new().operand_case(OperandCase::x87_db).bits(), x87_dc = OperandCodeBuilder::new().operand_case(OperandCase::x87_dc).bits(), x87_dd = OperandCodeBuilder::new().operand_case(OperandCase::x87_dd).bits(), x87_de = OperandCodeBuilder::new().operand_case(OperandCase::x87_de).bits(), x87_df = OperandCodeBuilder::new().operand_case(OperandCase::x87_df).bits(), Eb_R0 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::SingleMMMOper) .bits(), AL_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ib).bits(), AX_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ib).bits(), Ib_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AL).bits(), Ib_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AX).bits(), AX_DX = OperandCodeBuilder::new().operand_case(OperandCase::AX_DX).bits(), AL_DX = OperandCodeBuilder::new().operand_case(OperandCase::AL_DX).bits(), DX_AX = OperandCodeBuilder::new().operand_case(OperandCase::DX_AX).bits(), DX_AL = OperandCodeBuilder::new().operand_case(OperandCase::DX_AL).bits(), MOVQ_f30f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::MOVQ_f30f).bits(), // Unsupported = OperandCodeBuilder::new().operand_case(49).bits(), ModRM_0x0f00 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f00).bits(), ModRM_0x0f01 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f01).bits(), ModRM_0x0f0d = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0d).bits(), ModRM_0x0f0f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0f).bits(), // 3dnow ModRM_0x0fae = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fae).bits(), ModRM_0x0fba = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fba).bits(), // ModRM_0xf30fae = OperandCodeBuilder::new().read_modrm().operand_case(46).bits(), // ModRM_0x660fae = OperandCodeBuilder::new().read_modrm().operand_case(47).bits(), // ModRM_0xf30fc7 = OperandCodeBuilder::new().read_modrm().operand_case(48).bits(), // ModRM_0x660f38 = OperandCodeBuilder::new().read_modrm().operand_case(49).bits(), // ModRM_0xf20f38 = OperandCodeBuilder::new().read_modrm().operand_case(50).bits(), // ModRM_0xf30f38 = OperandCodeBuilder::new().read_modrm().operand_case(51).bits(), ModRM_0xf30f38d8 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38d8).bits(), ModRM_0xf30f38dc = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dc).bits(), ModRM_0xf30f38dd = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dd).bits(), ModRM_0xf30f38de = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38de).bits(), ModRM_0xf30f38df = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38df).bits(), ModRM_0xf30f38fa = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fa).bits(), ModRM_0xf30f38fb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fb).bits(), ModRM_0xf30f3af0 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf30f3af0).bits(), // ModRM_0x660f3a = OperandCodeBuilder::new().read_modrm().operand_case(52).bits(), // ModRM_0x0f38 = OperandCodeBuilder::new().read_modrm().operand_case(53).bits(), // ModRM_0x0f3a = OperandCodeBuilder::new().read_modrm().operand_case(54).bits(), ModRM_0x0f71 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f71).bits(), ModRM_0x0f72 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f72).bits(), ModRM_0x0f73 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f73).bits(), ModRM_0xf20f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf20f78).bits(), ModRM_0x660f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x660f78).bits(), ModRM_0xf30f1e = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xf30f1e).bits(), // ModRM_0x660f72 = OperandCodeBuilder::new().read_modrm().operand_case(61).bits(), // ModRM_0x660f73 = OperandCodeBuilder::new().read_modrm().operand_case(62).bits(), // ModRM_0x660fc7 = OperandCodeBuilder::new().read_modrm().operand_case(63).bits(), ModRM_0x0fc7 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fc7).bits(), // xmmword? ModRM_0x0f12 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f12) .bits(), // xmmword? ModRM_0x0f16 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f16) .bits(), // encode immediates? ModRM_0xc0_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xc1_Ev_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xd0_Eb_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ShiftBy1_b) .bits(), ModRM_0xd1_Ev_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ShiftBy1_v) .bits(), ModRM_0xd2_Eb_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0xd3_Ev_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0x80_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BaseOpWithI8) .bits(), ModRM_0x83_Ev_Ibs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x83) .bits(), // this would be Eb_Ivs, 0x8e ModRM_0x81_Ev_Ivs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BaseOpWithIv) .bits(), ModRM_0xc6_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::MovI8) .bits(), ModRM_0xc7_Ev_Iv = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::MovIv) .bits(), ModRM_0xfe_Eb = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xfe) .bits(), ModRM_0x8f_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x8f) .bits(), // gap, 0x94 ModRM_0xff_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xff) .bits(), ModRM_0x0f18 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x0f18) .bits(), ModRM_0xf6 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xf6) .bits(), ModRM_0xf7 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xf7) .bits(), Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::SingleMMMOper) .bits(), Zv_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 0).bits(), Zv_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 1).bits(), Zv_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 2).bits(), Zv_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 3).bits(), Zv_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 4).bits(), Zv_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 5).bits(), Zv_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 6).bits(), Zv_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 7).bits(), Zv_AX_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 0).bits(), Zv_AX_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 1).bits(), Zv_AX_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 2).bits(), Zv_AX_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 3).bits(), Zv_AX_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 4).bits(), Zv_AX_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 5).bits(), Zv_AX_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 6).bits(), Zv_AX_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 7).bits(), Zb_Ib_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 0).bits(), Zb_Ib_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 1).bits(), Zb_Ib_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 2).bits(), Zb_Ib_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 3).bits(), Zb_Ib_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 4).bits(), Zb_Ib_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 5).bits(), Zb_Ib_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 6).bits(), Zb_Ib_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 7).bits(), Zv_Ivq_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 0).bits(), Zv_Ivq_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 1).bits(), Zv_Ivq_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 2).bits(), Zv_Ivq_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 3).bits(), Zv_Ivq_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 4).bits(), Zv_Ivq_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 5).bits(), Zv_Ivq_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 6).bits(), Zv_Ivq_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Ivq_R, 7).bits(), Gv_Eb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Eb).bits(), Gv_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew).bits(), Gv_Ew_LAR = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LAR).bits(), Gv_Ew_LSL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LSL).bits(), Gdq_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gdq_Ed).bits(), Gd_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ed).bits(), Md_Gd = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::Md_Gd).bits(), // Edq_Gdq = OperandCodeBuilder::new().read_E().operand_case(49).bits(), Gdq_Ev = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gdq_Ev).bits(), Mdq_Gdq = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Mdq_Gdq).bits(), G_E_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ib).bits(), G_E_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ub).bits(), G_U_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_U_xmm_Ub).bits(), AL_Ob = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ob).bits(), AL_Xb = OperandCodeBuilder::new().operand_case(OperandCase::AL_Xb).bits(), AX_Ov = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ov).bits(), AL_Ibs = OperandCodeBuilder::new().byte_operands().operand_case(OperandCase::AL_Ibs).bits(), AX_Ivd = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ivd).bits(), Eb_Gb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Ev_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Gb_Eb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_Ev = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_M = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().deny_regmmm().operand_case(OperandCase::Gv_M).bits(), MOVDIR64B = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::MOVDIR64B).bits(), M_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().deny_regmmm().operand_case(OperandCase::Internal).bits(), Gv_Ev_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Ib).bits(), Gv_Ev_Iv = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Iv).bits(), Rv_Gmm_Ib = OperandCodeBuilder::new().read_modrm().read_E().reg_mem().operand_case(OperandCase::Rv_Gmm_Ib).bits(), // gap, 0x9a G_xmm_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_E_mm).bits(), G_xmm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_U_mm).bits(), G_mm_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_xmm).bits(), G_xmm_Edq = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Edq).bits(), G_xmm_Eq = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Eq).bits(), G_mm_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_E_xmm).bits(), Gd_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gd_U_xmm).bits(), Gdq_Eq_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gdq_Eq_xmm).bits(), Gv_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_E_xmm).bits(), //= 0x816f, // mirror G_xmm_Edq, but also read an immediate G_xmm_Ew_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Ew_Ib).bits(), G_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_xmm).bits(), G_M_xmm = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::G_M_xmm).bits(), G_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_xmm).bits(), E_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_xmm).bits(), G_Ed_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Ed_xmm).bits(), Ed_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Ed_G_xmm).bits(), M_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::M_G_xmm).bits(), G_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_mm).bits(), G_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_mm).bits(), E_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_mm).bits(), Edq_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Edq_G_mm).bits(), Edq_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Edq_G_xmm).bits(), G_mm_Edq = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Edq).bits(), G_mm_E = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_E).bits(), Ev_Gv_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_Ib).bits(), Ev_Gv_CL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_CL).bits(), G_mm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_mm).bits(), G_Mq_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Mq_mm).bits(), G_mm_Ew_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Ew_Ib).bits(), G_E_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_q).bits(), E_G_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::E_G_q).bits(), CVT_AA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_AA).bits(), CVT_DA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_DA).bits(), Rq_Cq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Cq_0).bits(), Rq_Dq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Dq_0).bits(), Cq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Cq_Rq_0).bits(), Dq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Dq_Rq_0).bits(), FS = OperandCodeBuilder::new().operand_case(OperandCase::FS).bits(), GS = OperandCodeBuilder::new().operand_case(OperandCase::GS).bits(), Yb_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yb_DX).bits(), Yv_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_DX).bits(), DX_Xb = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xb).bits(), DX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xv).bits(), AH = OperandCodeBuilder::new().operand_case(OperandCase::AH).bits(), AX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::AX_Xv).bits(), Ew_Sw = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ew_Sw).bits(), Fw = OperandCodeBuilder::new().operand_case(OperandCase::Fw).bits(), I_1 = OperandCodeBuilder::new().operand_case(OperandCase::I_1).bits(), Iw = OperandCodeBuilder::new().operand_case(OperandCase::Iw).bits(), Iw_Ib = OperandCodeBuilder::new().operand_case(OperandCase::Iw_Ib).bits(), Ob_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ob_AL).bits(), Ov_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ov_AX).bits(), Sw_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Sw_Ew).read_E().bits(), Yb_AL = OperandCodeBuilder::new().operand_case(OperandCase::Yb_AL).bits(), Yb_Xb = OperandCodeBuilder::new().operand_case(OperandCase::Yb_Xb).bits(), Yv_AX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_AX).bits(), INV_Gv_M = OperandCodeBuilder::new().read_E().deny_regmmm().operand_case(OperandCase::INV_Gv_M).bits(), PMOVX_G_E_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_G_E_xmm).bits(), PMOVX_E_G_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_E_G_xmm).bits(), G_Ev_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_Ev_xmm_Ib).bits(), G_E_mm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_mm_Ib).bits(), } fn base_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ADD, 1 => Opcode::OR, 2 => Opcode::ADC, 3 => Opcode::SBB, 4 => Opcode::AND, 5 => Opcode::SUB, 6 => Opcode::XOR, 7 => Opcode::CMP, _ => { unsafe { unreachable_unchecked() } } } } fn bitwise_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ROL, 1 => Opcode::ROR, 2 => Opcode::RCL, 3 => Opcode::RCR, 4 => Opcode::SHL, 5 => Opcode::SHR, 6 => Opcode::SAL, 7 => Opcode::SAR, _ => { unsafe { unreachable_unchecked() } } } } #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum Interpretation { Instruction(Opcode), Prefix, } #[derive(Copy, Clone, Debug, PartialEq)] // this should be a 32-byte struct.. struct OpcodeRecord(u64); //Interpretation, u32); // OperandCode); impl OpcodeRecord { const fn new(interp: Interpretation, code: OperandCode) -> Self { let interp_bits = unsafe { core::mem::transmute::(interp) as u64 }; let code_bits = code as u16 as u64; let stored_bits = interp_bits | (code_bits << 32); OpcodeRecord(stored_bits) } const fn interp(&self) -> Interpretation { unsafe { core::mem::transmute(self.0 as u32) } } const fn operand(&self) -> OperandCode { unsafe { core::mem::transmute((self.0 >> 32) as u16) } } } const OPCODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x40: OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // 0x50: OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R7), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSXD), OperandCode::Gdq_Ed), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yb_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yv_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xv), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Ibs), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x80_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x81_Ev_Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x83_Ev_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ew_Sw), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEA), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Sw_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x8f_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_AA), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_DA), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WAIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSHF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AL_Ob), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AX_Ov), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ob_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ov_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yv_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AL_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AX_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yv_AX), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Ivq_R7), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc0_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc1_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc6_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc7_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ENTER), OperandCode::Iw_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEAVE), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_3), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::IRET), OperandCode::Fw), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd0_Eb_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd1_Ev_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd2_Eb_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd3_Ev_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // XLAT OpcodeRecord::new(Interpretation::Instruction(Opcode::XLAT), OperandCode::Nothing), // x86 d8 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d8), // x86 d9 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d9), // x86 da OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_da), // x86 db OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_db), // x86 dc OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dc), // x86 dd OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dd), // x86 de OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_de), // x86 df OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_df), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JRCXZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AX), // 0xe8 OpcodeRecord::new(Interpretation::Instruction(Opcode::CALL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AX), // 0xf0 OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // ICEBP? OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_1), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // 0xf4 OpcodeRecord::new(Interpretation::Instruction(Opcode::HLT), OperandCode::Nothing), // CMC OpcodeRecord::new(Interpretation::Instruction(Opcode::CMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf6), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf7), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xfe_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xff_Ev), ]; #[allow(non_snake_case)] #[inline(always)] pub(self) fn read_E< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_st< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { instr.regs[1] = RegSpec { bank: RegisterBank::ST, num: modrm & 7 }; Ok(OperandSpec::RegMMM) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_xmm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::X, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_ymm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::Y, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { let res = read_M(words, instr, modrm, sink)?; if (modrm & 0b01_000_000) == 0b01_000_000 { instr.prefixes.apply_compressed_disp(true); } Ok(res) } } #[allow(non_snake_case)] #[inline(always)] fn read_modrm_reg< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &mut Instruction, words: &mut T, modrm: u8, reg_bank: RegisterBank, sink: &mut S) -> Result { instr.regs[1] = RegSpec::from_parts(modrm & 7, instr.prefixes.rex_unchecked().b(), reg_bank); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 6, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(words.offset() as u32 * 8 - 8 + 2) ); Ok(OperandSpec::RegMMM) } #[inline(always)] fn read_sib_disp< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &Instruction, words: &mut T, modrm: u8, sibbyte: u8, sink: &mut S) -> Result { let sib_start = words.offset() as u32 * 8 - 8; let modbit_addr = words.offset() as u32 * 8 - 10; let disp_start = words.offset() as u32 * 8; let disp = if modrm < 0b01_000_000 { // modbits == 0b00 if (sibbyte & 7) == 0b101 { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); sink.record(sib_start, sib_start + 2, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { 0 } } else if modrm < 0b10_000_000 { // modbits == 0b01 sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("1-byte displacement").with_id(sib_start + 0)); if instr.prefixes.evex().is_some() { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("EVEX prefix implies displacement is scaled by vector size") .with_id(sib_start + 0)); } let disp = read_num(words, 1)? as i8 as i32; sink.record(disp_start, disp_start + 7, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp }; Ok(disp) } #[allow(non_snake_case)] #[inline(always)] fn read_sib< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let sib_start = words.offset() as u32 * 8; let sibbyte = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let disp = read_sib_disp(instr, words, modrm, sibbyte, sink)?; instr.disp = disp as u32 as u64; let mut r = 0; if instr.prefixes.rex_unchecked().b() { r |= 0b1000; } instr.regs[1].num = r | (sibbyte & 7); let mut r = 0; if instr.prefixes.rex_unchecked().x() { r = 0b1000; } instr.regs[2].num = r | ((sibbyte >> 3) & 7); let scale = 1u8 << (sibbyte >> 6); instr.scale = scale; let op_spec = if disp == 0 { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address, but displacement is 0") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii + rex.x selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::Deref } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num & 0b111, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register") .with_id(sib_start + 0) ); OperandSpec::RegScale } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii + rex.x selects no index register") .with_id(sib_start + 0) ); OperandSpec::Deref } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num & 0b111, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii + rex.x selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegDisp } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num & 0b111, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, [index+disp] only") .with_id(sib_start + 0) ); OperandSpec::RegScaleDisp } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } } else { sink.record( sib_start + 0, sib_start + 2, InnerDescription::RegisterNumber("bbb", instr.regs[1].num & 0b111, instr.regs[2]) .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii + rex.x selects no index register") .with_id(sib_start + 0) ); OperandSpec::RegDisp } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num & 0b111, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } }; // b = 101? // i = 100? // rex.x? // mod = 0? // disp = 0? Ok(op_spec) } #[allow(non_snake_case)] #[inline(always)] fn read_M< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let mmm = modrm & 7; let op_spec = if mmm == 4 { sink.record( modrm_start, modrm_start + 2, InnerDescription::Misc("`mmm` field selects sib access") .with_id(modrm_start + 2) ); return read_sib(words, instr, modrm, sink); } else { instr.regs[1].num = mmm; if instr.prefixes.rex_unchecked().b() { instr.regs[1].num |= 0b1000; } sink.record( modrm_start, modrm_start + 2, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(modrm_start + 2) ); if modrm < 0b01_000_000 { // modbits == 0b00 if mmm == 5 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("rip-relative reference") .with_id(modrm_start + 0) ); sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("rip-relative reference") .with_id(modrm_start + 0) ); if instr.prefixes.address_size() { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("address-size override selects `eip` instead") .with_id(modrm_start + 1) ); sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("address-size override selects `eip` instead") .with_id(modrm_start + 1) ); } let disp = read_num(words, 4)? as i32; sink.record( modrm_start + 8, modrm_start + 8 + 32, InnerDescription::Number("displacement", disp as i64) .with_id(modrm_start + 3) ); instr.regs[1] = if !instr.prefixes.address_size() { RegSpec::rip() } else { RegSpec::eip() }; if disp == 0 { OperandSpec::Deref } else { instr.disp = disp as i64 as u64; OperandSpec::RegDisp } } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)") .with_id(modrm_start + 0) ); OperandSpec::Deref } } else { let disp_start = words.offset(); let disp = if modrm < 0b10_000_000 { // modbits == 0b01 (not 0b00, as detected above) sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp8] indexed by register selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); read_num(words, 1)? as i8 as i32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp32] indexed by register selected by `mmm` (mod bits: 10)") .with_id(modrm_start + 0) ); read_num(words, 4)? as i32 }; let disp_end = words.offset(); sink.record( disp_start as u32 * 8, disp_end as u32 * 8 - 1, InnerDescription::Number("displacement", disp as i64) .with_id(words.offset() as u32 * 8 + 3) ); if disp == 0 { OperandSpec::Deref } else { instr.disp = disp as i64 as u64; OperandSpec::RegDisp } } }; Ok(op_spec) } // well, ya forgot to make the enum non-exhausitve, and now adding variants to describe vex and // evex operand codes would be a breaking change. TODO for 2.x .... /// the actual description for a selection of bits involved in decoding an [`long_mode::Instruction`]. /// /// some prefixes are only identified as an `InnerDescription::Misc` string, while some are full /// `InnerDescription::SegmentPrefix(Segment)`. generally, strings should be considered unstable /// and only useful for displaying for human consumption. #[derive(Clone, Debug, PartialEq, Eq)] pub enum InnerDescription { /// the literal byte read for a `rex` prefix, `0x4_`. RexPrefix(u8), /// the segment selected by a segment override prefix. this is not necessarily the actual /// segement used in the instruction's memory accesses, if any are made. SegmentPrefix(Segment), /// the opcode read for this instruction. this may be reported multiple times in an instruction /// if multiple spans of bits are necessary to determine the opcode. it is a bug if two /// different `Opcode` are indicated by different `InnerDescription::Opcode` reported from /// decoding the same instruction. this invariant is not well-tested, and may occur in /// practice. Opcode(Opcode), /// the operand code indicating how to read operands for this instruction. this is an internal /// detail of `yaxpeax-x86` but is typically named in a manner that can aid understanding the /// decoding process. `OperandCode` names are unstable, and this variant is only useful for /// displaying for human consumption. OperandCode(OperandCodeWrapper), /// a decoded register: a name for the bits used to decode it, the register number those bits /// specify, and the fully-constructed [`long_mode::RegSpec`] that was decoded. RegisterNumber(&'static str, u8, RegSpec), /// a miscellaneous string describing some bits of the instruction. this may describe a prefix, /// internal details of a prefix, error or constraints on an opcode, operand encoding details, /// or other items involved in an instruction. Misc(&'static str), /// a number involved in the instruction: typically either a disaplacement or immediate. the /// string describes which. the `i64` member is typically a sign-extended value from the /// appropriate original size, meaning there may be incorrect cases of a `65535u16` sign /// extending to `-1`. bug reports are highly encouraged for unexpected values. Number(&'static str, i64), /// a boundary between two logically distinct sections of an instruction. these typically /// separate the leading prefix string (if any), opcode, and operands (if any). the included /// string describes which boundary this is. boundary names should not be considered stable, /// and are useful at most for displaying for human consumption. Boundary(&'static str), } impl InnerDescription { fn with_id(self, id: u32) -> FieldDescription { FieldDescription { desc: self, id, } } } cfg_if::cfg_if! { if #[cfg(feature="fmt")] { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { InnerDescription::RexPrefix(bits) => { write!(f, "rex prefix: {}{}{}{}", if bits & 0x8 != 0 { "w" } else { "-" }, if bits & 0x4 != 0 { "r" } else { "-" }, if bits & 0x2 != 0 { "x" } else { "-" }, if bits & 0x1 != 0 { "b" } else { "-" }, ) } InnerDescription::SegmentPrefix(segment) => { write!(f, "segment override: {}", segment) } InnerDescription::Misc(text) => { f.write_str(text) } InnerDescription::Number(text, num) => { write!(f, "{}: {:#x}", text, num) } InnerDescription::Opcode(opc) => { write!(f, "opcode `{}`", opc) } InnerDescription::OperandCode(OperandCodeWrapper { code }) => { write!(f, "operand code `{:?}`", code) } InnerDescription::RegisterNumber(name, num, reg) => { write!(f, "`{}` (`{}` selects register number {})", reg, name, num) } InnerDescription::Boundary(desc) => { write!(f, "{}", desc) } } } } } else { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str("non-fmt build") } } } } #[cfg_attr(feature="fmt", derive(Debug))] #[derive(Clone, PartialEq, Eq)] pub struct FieldDescription { desc: InnerDescription, id: u32, } impl FieldDescription { /// the actual description associated with this bitfield. pub fn desc(&self) -> &InnerDescription { &self.desc } } impl yaxpeax_arch::annotation::FieldDescription for FieldDescription { fn id(&self) -> u32 { self.id } fn is_separator(&self) -> bool { if let InnerDescription::Boundary(_) = &self.desc { true } else { false } } } impl fmt::Display for FieldDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fmt::Display::fmt(&self.desc, f) } } #[inline(always)] fn record_opcode_record_found< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, sink: &mut S, opc: Opcode, code: OperandCode, opc_length: u32) { let offset = words.offset() as u32; let opcode_start_bit = (offset - opc_length) * 8; let opcode_end_bit = offset * 8 - 1; if offset > opc_length { sink.record( opcode_start_bit - 1, opcode_start_bit - 1, InnerDescription::Boundary("prefixes end") .with_id(opcode_start_bit) ); } if opc != Opcode::Invalid { sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::Opcode(opc), id: offset * 8 - opc_length * 8, }); } sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::OperandCode(OperandCodeWrapper { code }), id: offset * 8 - opc_length * 8 + 1, }); } #[derive(Copy, Clone)] struct DecodeCtx { check_lock: bool, vqp_size: RegisterBank, rb_size: RegisterBank, rrr: u8, } impl DecodeCtx { fn new() -> Self { DecodeCtx { check_lock: false, vqp_size: RegisterBank::D, rb_size: RegisterBank::B, rrr: 0 } } #[inline(always)] fn vqp_size(&self) -> RegisterBank { self.vqp_size } #[inline(always)] fn rb_size(&self) -> RegisterBank { self.rb_size } fn read_opc_hotpath< T: Reader<::Address, ::Word>, S: DescriptionSink, >(&mut self, mut b: u8, nextb: &mut u8, record: &mut OpcodeRecord, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result { if b >= 0x40 && b < 0x50 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::RexPrefix(b), id: words.offset() as u32 * 8 - 8, }); instruction.prefixes.rex_from(b); if instruction.prefixes.rex_unchecked().w() { self.vqp_size = RegisterBank::Q; } self.rb_size = RegisterBank::rB; b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; *record = OPCODES[b as usize]; } else if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 16 bits)"), id: words.offset() as u32 * 8 - 8, }); b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; *record = OPCODES[b as usize]; instruction.prefixes.set_operand_size(); self.vqp_size = RegisterBank::W; } if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); instruction.opcode = opc; return Ok(true); } else if b == 0x0f { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (r, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, &mut instruction.prefixes)?, 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, &mut instruction.prefixes)?, 3) } else { (self.read_0f_opcode(b, &mut instruction.prefixes), 2) }; *record = r; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); instruction.opcode = opc; } else { unsafe { unreachable_unchecked(); } } return Ok(true); } else { *nextb = b; return Ok(false); } } #[inline(always)] fn read_with_annotations< T: Reader<::Address, ::Word>, S: DescriptionSink, >(mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { words.mark(); let mut nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let mut next_rec = OPCODES[nextb as usize]; instruction.prefixes = Prefixes::new(0); // const RAXRAXRAXRAX: [RegSpec; 4] = [RegSpec::rax(); 4]; // default x86_64 registers to `[rax; 4]` // instruction.regs = RAXRAXRAXRAX; instruction.regs[1] = RegSpec::rax(); instruction.regs[2] = RegSpec::rax(); let record: OperandCode = if self.read_opc_hotpath(nextb, &mut nextb, &mut next_rec, words, instruction, sink)? { next_rec.operand() } else { let prefixes = &mut instruction.prefixes; let record = loop { let mut record = next_rec; if nextb >= 0x40 && nextb < 0x50 { let b = nextb; sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::RexPrefix(b), id: words.offset() as u32 * 8 - 8, }); nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; next_rec = OPCODES[nextb as usize]; record = next_rec; prefixes.rex_from(b); self.rb_size = RegisterBank::rB; if prefixes.rex_unchecked().w() { self.vqp_size = RegisterBank::Q; } } if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); break record; } else { let b = nextb; if b == 0x0f { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (rec, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, prefixes)?, 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, prefixes)?, 3) } else { (self.read_0f_opcode(b, prefixes), 2) }; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); } break rec; } if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 16 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_operand_size(); self.vqp_size = RegisterBank::W; } else if b == 0x67 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("address size override (to 32 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_address_size(); instruction.regs[1].bank = RegisterBank::D; instruction.regs[2].bank = RegisterBank::D; } else if b == 0xf2 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("repnz prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_repnz(); } else if b == 0xf3 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("rep prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_rep(); } else { match b { 0x26 | 0x2e | 0x36 | 0x3e => { /* no-op in amd64 */ sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("ignored prefix in 64-bit mode"), id: words.offset() as u32 * 8 - 8, }); }, 0x64 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::FS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_fs(); }, 0x65 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::GS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_gs(); }, 0xf0 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("lock prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_lock(); self.check_lock = true; }, _ => { return self.read_avx_prefixed(b, words, instruction, sink); } } } nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; next_rec = OPCODES[nextb as usize]; if prefixes.rex.bits != 0 { sink.record((words.offset() - 2) as u32 * 8, (words.offset() - 2) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("invalidates prior rex prefix"), id: (words.offset() as u32 * 8 - 16) + 1, }); } prefixes.rex_from(0); self.rb_size = RegisterBank::B; self.vqp_size = if prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; } if words.offset() >= 15 { return Err(DecodeError::TooLong); } }; if let Interpretation::Instruction(opcode) = record.interp() { instruction.opcode = opcode; } else { unsafe { unreachable_unchecked(); } } record.operand() }; self.read_operands(decoder, words, instruction, record, sink)?; if self.check_lock { if (instruction.opcode as u32) < 0x1000 || !instruction.operands[0].is_memory() { return Err(DecodeError::InvalidPrefixes); } } Ok(()) } #[inline(never)] fn read_avx_prefixed< T: Reader<::Address, ::Word>, S: DescriptionSink, >(self, b: u8, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { if instruction.prefixes.vex_invalid() { // rex and then vex is invalid! reject it. return Err(DecodeError::InvalidPrefixes); } instruction.mem_size = 0; instruction.operand_count = 2; // some prefix seen after we saw rex, but before the 0f escape or an actual // opcode. so we must forget the rex prefix! // this is to handle sequences like 41660f21cf // where if 660f21 were a valid opcode, 41 would apply a rex.b // prefix, but since 660f21 is not valid, the opcode is interpreted // as 0f21, where 66 is a prefix, which makes 41 not the last // prefix before the opcode, and it's discarded. // 2.3.2 // Any VEX-encoded instruction with a LOCK prefix preceding VEX will #UD. // 2.3.3 // Any VEX-encoded instruction with a 66H, F2H, or F3H prefix preceding VEX // will #UD. // 2.3.4 // Any VEX-encoded instruction with a REX prefix proceeding VEX will #UD. if b == 0xc5 { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("two-byte vex prefix (0xc5)") .with_id(words.offset() as u32 * 8 - 8) ); vex::two_byte_vex(words, instruction, sink)?; } else if b == 0xc4 { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("three-byte vex prefix (0xc4)") .with_id(words.offset() as u32 * 8 - 8) ); vex::three_byte_vex(words, instruction, sink)?; } else if b == 0x62 { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("evex prefix (0x62)") .with_id(words.offset() as u32 * 8 - 8) ); evex::read_evex(words, instruction, None, sink)?; } return Ok(()); } #[inline(always)] fn read_operands< T: Reader<::Address, ::Word>, S: DescriptionSink >(&mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, operand_code: OperandCode, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 1, words.offset() as u32 * 8 - 1, InnerDescription::Boundary("opcode ends/operands begin (typically)") .with_id(words.offset() as u32 * 8 - 1) ); let operand_code = OperandCodeBuilder::from_bits(operand_code as u16); let modrm_start = words.offset() as u32 * 8; let opcode_start = modrm_start - 8; if operand_code.is_only_modrm_operands() { let bank; let modrm = read_modrm(words)?; let rrr = (modrm >> 3) & 7; self.rrr = rrr; let num = rrr + if instruction.prefixes.rex_unchecked().r() { 0b1000 } else { 0 }; instruction.regs[0].num = num; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E bank = self.vqp_size(); instruction.mem_size = bank as u8; instruction.regs[0].bank = bank; } else { instruction.mem_size = 1; bank = self.rb_size(); if num < 4 { instruction.regs[0].bank = RegisterBank::B; } else { instruction.regs[0].bank = bank; } }; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", (modrm >> 3) & 7, instruction.regs[0]) .with_id(modrm_start + 3) ); } let mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if mem_oper == OperandSpec::RegMMM { if instruction.regs[1].bank == RegisterBank::rB && instruction.regs[1].num < 4 { instruction.regs[1].bank = RegisterBank::B; } } if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } instruction.operand_count = 2; return Ok(()); } if operand_code.has_imm() { instruction.mem_size = 0; if operand_code.operand_case_handler_index() == OperandCase::Ibs { instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmI8; } else { instruction.imm = read_imm_signed(words, 4)? as u64; sink.record( words.offset() as u32 * 8 - 32, words.offset() as u32 * 8 - 1, InnerDescription::Number("4-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); if instruction.opcode == Opcode::CALL { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::ImmI32; } instruction.operand_count = 1; return Ok(()); } let mut mem_oper = OperandSpec::Nothing; if operand_code.has_read_E() { let bank; let modrm = read_modrm(words)?; let rrr = (modrm >> 3) & 7; self.rrr = rrr; let num = rrr + if instruction.prefixes.rex_unchecked().r() { 0b1000 } else { 0 }; instruction.regs[0].num = num; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E bank = self.vqp_size(); instruction.mem_size = bank as u8; instruction.regs[0].bank = bank; } else { instruction.mem_size = 1; bank = self.rb_size(); if num < 4 { instruction.regs[0].bank = RegisterBank::B; } else { instruction.regs[0].bank = bank; } }; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start + 3) ); } mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if mem_oper == OperandSpec::RegMMM { if instruction.regs[1].bank == RegisterBank::rB && instruction.regs[1].num < 4 { instruction.regs[1].bank = RegisterBank::B; } } if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } } else { instruction.mem_size = 0; } if let Some(z_operand_code) = operand_code.get_embedded_instructions() { instruction.operands[0] = OperandSpec::RegRRR; let reg = z_operand_code.reg(); match z_operand_code.category() { 0 => { // these are Zv_R let bank = bank_from_prefixes_64(SizeCode::vq, instruction.prefixes); instruction.regs[0] = RegSpec::from_parts(reg, instruction.prefixes.rex_unchecked().b(), bank); instruction.mem_size = 8; sink.record( opcode_start + 0, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); if instruction.prefixes.rex_unchecked().b() { sink.record( opcode_start + 0, opcode_start + 2, InnerDescription::Misc("rex.b selects register `zzz` + 8") .with_id(opcode_start + 2) ); } instruction.operand_count = 1; } 1 => { // Zv_AX // in 64-bit mode, rex.b is able to make "nop" into an `xchg`, as in `4190` // aka `xchg eax, r8d. if reg == 0 && !instruction.prefixes.rex_unchecked().b() { instruction.opcode = Opcode::NOP; instruction.operand_count = 0; return Ok(()); } let bank = self.vqp_size(); // always *ax, but size is determined by prefixes (or lack thereof) instruction.regs[0] = RegSpec::from_parts(0, false, bank); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(reg, instruction.prefixes.rex_unchecked().b(), bank); sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); if instruction.prefixes.rex_unchecked().b() { sink.record( opcode_start, opcode_start + 2, InnerDescription::Misc("rex.b selects register `zzz` + 8") .with_id(opcode_start + 1) ); } sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("opcode selects `eax` operand") .with_id(opcode_start + 2) ); // TODO: hmm let opwidth = 0; if opwidth == 2 { sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("operand-size prefix override selects `ax`") .with_id(opcode_start + 2) ); } else if opwidth == 8 { sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("rex.w prefix selects `rax`") .with_id(opcode_start + 2) ); } instruction.operand_count = 2; } 2 => { // these are Zb_Ib_R let num = reg + if instruction.prefixes.rex_unchecked().b() { 0b1000 } else { 0 }; let bank = if num < 4 { RegisterBank::B } else { self.rb_size() }; instruction.regs[0] = RegSpec { num, bank }; sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); if instruction.prefixes.rex_unchecked().b() { sink.record( opcode_start, opcode_start + 2, InnerDescription::Misc("rex.b selects register `zzz` + 8") .with_id(opcode_start + 1) ); } instruction.imm = read_imm_unsigned(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8)); instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } 3 => { // category == 3, Zv_Ivq_R if instruction.prefixes.rex_unchecked().w() { instruction.regs[0] = RegSpec::from_parts(reg, instruction.prefixes.rex_unchecked().b(), RegisterBank::Q); instruction.imm = read_num(words, 8)? as u64; instruction.operands[1] = OperandSpec::ImmI64; let width = 8; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } else if instruction.prefixes.operand_size() { instruction.regs[0] = RegSpec::from_parts(reg, instruction.prefixes.rex_unchecked().b(), RegisterBank::W); instruction.imm = read_num(words, 2)? as u16 as u64; instruction.operands[1] = OperandSpec::ImmI16; let width = 2; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } else { instruction.regs[0] = RegSpec::from_parts(reg, instruction.prefixes.rex_unchecked().b(), RegisterBank::D); instruction.imm = read_num(words, 4)? as u32 as u64; instruction.operands[1] = OperandSpec::ImmI32; let width = 4; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); if instruction.prefixes.rex_unchecked().b() { sink.record( opcode_start, opcode_start + 2, InnerDescription::Misc("rex.b selects register `zzz` + 8") .with_id(opcode_start + 2) ); } instruction.operand_count = 2; } _ => { unreachable!("bad category"); } } return Ok(()); } if !operand_code.has_read_E() { instruction.operands = [OperandSpec::RegRRR, OperandSpec::Nothing, OperandSpec::Nothing, OperandSpec::Nothing]; } instruction.operand_count = 2; // match operand_code { match operand_code.operand_case_handler_index() { // these operand cases are all `only_*`, and are unreachable here.. OperandCase::Internal | OperandCase::Gv_M | OperandCase::Ibs | OperandCase::Jvds => { } OperandCase::SingleMMMOper => { instruction.operands[0] = mem_oper; instruction.operand_count = 1; }, OperandCase::BaseOpWithI8 => { instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); } OperandCase::BaseOpWithIv => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.vqp_size == RegisterBank::W { let opwidth = 2; instruction.imm = read_imm_signed(words, opwidth)? as u64; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); instruction.operands[1] = OperandSpec::ImmI16; } else { let opwidth = 4; instruction.imm = read_imm_signed(words, opwidth)? as u64; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); if self.vqp_size == RegisterBank::Q { instruction.operands[1] = OperandSpec::ImmI64; } else { instruction.operands[1] = OperandSpec::ImmI32; } } }, OperandCase::MovI8 => { if self.rrr != 0 { if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XABORT; instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); instruction.operands[0] = OperandSpec::ImmI8; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 1 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } OperandCase::MovIv => { if self.rrr != 0 { let opwidth = instruction.regs[0].bank as u8; if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XBEGIN; instruction.imm = if opwidth == 2 { let imm = read_imm_signed(words, 2)? as i16 as i64 as u64; sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 16) ); imm } else { let imm = read_imm_signed(words, 4)? as i32 as i64 as u64; sink.record( words.offset() as u32 * 8 - 32, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 32) ); imm }; instruction.operands[0] = OperandSpec::ImmI32; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; if self.vqp_size == RegisterBank::W { instruction.imm = read_imm_signed(words, 2)? as u64; sink.record( modrm_start + 8, modrm_start + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI16; } else { instruction.imm = read_imm_signed(words, 4)? as u64; sink.record( modrm_start + 8, modrm_start + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); if self.vqp_size == RegisterBank::Q { instruction.operands[1] = OperandSpec::ImmI64; } else { instruction.operands[1] = OperandSpec::ImmI32; } } }, OperandCase::BitwiseWithI8 => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = read_num(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", num as i64) .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::ShiftBy1_v | OperandCase::ShiftBy1_b => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = 1; sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Misc("opcode specifies integer immediate 1") .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::BitwiseByCL => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.regs[0] = RegSpec::cl(); sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::RegisterNumber("reg", 1, instruction.regs[0]) .with_id(modrm_start - 7) ); instruction.operands[1] = OperandSpec::RegRRR; }, OperandCase::ModRM_0xf6 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { instruction.opcode = Opcode::TEST; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 8 + 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xf7 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { if self.vqp_size == RegisterBank::W { instruction.imm = read_imm_signed(words, 2)? as u64; instruction.operands[1] = OperandSpec::ImmI16; sink.record( modrm_start + 8, modrm_start + 8 + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.imm = read_imm_signed(words, 4)? as u64; sink.record( modrm_start + 8, modrm_start + 8 + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); if self.vqp_size == RegisterBank::Q { instruction.operands[1] = OperandSpec::ImmI64; } else { instruction.operands[1] = OperandSpec::ImmI32; } }; } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xfe => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 2 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr: opcode requires rrr < 0b010") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOpcode); } instruction.opcode = [ Opcode::INC, Opcode::DEC, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operand_count = 1; } OperandCase::ModRM_0xff => { instruction.operands[0] = mem_oper; let r = self.rrr; if r == 7 { return Err(DecodeError::InvalidOpcode); } const TABLE: [Opcode; 7] = [ Opcode::INC, Opcode::DEC, Opcode::CALL, Opcode::CALLF, Opcode::JMP, Opcode::JMPF, Opcode::PUSH, ]; let opcode = TABLE[r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(opcode) .with_id(modrm_start - 8) ); if instruction.operands[0] == OperandSpec::RegMMM { if opcode == Opcode::CALL || opcode == Opcode::JMP { instruction.regs[1].bank = RegisterBank::Q; if opcode == Opcode::CALL { instruction.mem_size = 8; } } else if opcode == Opcode::PUSH || opcode == Opcode::POP { if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 8; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { return Err(DecodeError::InvalidOperand); } } else { if opcode == Opcode::CALL || opcode == Opcode::JMP { instruction.mem_size = 8; } else if opcode == Opcode::PUSH || opcode == Opcode::POP { if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 8; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { instruction.mem_size = 10; } } instruction.opcode = opcode; instruction.operand_count = 1; } OperandCase::Gv_Eb => { let w = self.rb_size(); instruction.operands[1] = mem_oper; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; if instruction.regs[1].num < 4 { instruction.regs[1].bank = RegisterBank::B; } else { instruction.regs[1].bank = w; } } else { instruction.mem_size = 1; } instruction.operand_count = 2; } OperandCase::Gv_Ew => { let w = RegisterBank::W; instruction.operands[1] = mem_oper; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = w; } else { instruction.mem_size = 2; } instruction.operand_count = 2; }, OperandCase::Gdq_Ed => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::Q; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); }, OperandCase::E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if instruction.operands[0] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, OperandCase::G_M_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 16; } OperandCase::G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; if instruction.operands[1] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { if instruction.opcode == Opcode::MOVDDUP { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } }, OperandCase::G_E_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); instruction.imm = read_num(words, 1)? as u8 as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8 + 1) ); if instruction.operands[1] != OperandSpec::RegMMM { if instruction.opcode == Opcode::CMPSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::CMPSD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; }, OperandCase::AL_Ibs => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::AX_Ivd => { let bank = self.vqp_size(); let numwidth = if bank as u8 == 8 { 4 } else { bank as u8 }; instruction.regs[0] = RegSpec::gp_from_parts_non_byte(0, false, bank); sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.imm = read_imm_signed(words, numwidth)? as u64; instruction.operands[1] = match bank as u8 { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, 8 => OperandSpec::ImmI64, _ => unsafe { unreachable_unchecked() } }; sink.record( words.offset() as u32 * 8 - numwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - numwidth as u32 * 8 + 1) ); } OperandCase::Ivs => { if instruction.prefixes.rex_unchecked().w() || !instruction.prefixes.operand_size() { instruction.imm = read_imm_unsigned(words, 4)?; instruction.operands[0] = OperandSpec::ImmI32; let opwidth = 4; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } else { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmI16; let opwidth = 2; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } instruction.operand_count = 1; }, OperandCase::ModRM_0x83 => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operands[1] = OperandSpec::ImmI8; }, OperandCase::I_3 => { sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Number("int", 3 as i64) .with_id(modrm_start - 1) ); instruction.imm = 3; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Nothing => { if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } if instruction.opcode == Opcode::RETURN { instruction.mem_size = 8; } else if instruction.opcode == Opcode::RETF { instruction.mem_size = 10; } // TODO: leave? instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); }, OperandCase::Ed_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; if instruction.operands[0] == OperandSpec::RegMMM { // fix the register to XMM sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } }, OperandCase::ModRM_0x8f => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 1 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("rrr field > 0b000 for this opcode is illegal, except with XOP extensions") .with_id(modrm_start - 8) ); // TODO: this is where XOP decoding would occur return Err(DecodeError::IncompleteDecoder); } instruction.opcode = [ Opcode::POP, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if mem_oper != OperandSpec::RegMMM { // the right size is set by default except for the default case; by default // operands are dword, but 0x8f `pop` defaults to qword (with no way to encode a // `pop dword [mem]`) if !instruction.prefixes.operand_size() { instruction.mem_size = 8; } } instruction.operand_count = 1; } OperandCase::G_Ed_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operand_count = 2; if instruction.operands[1] == OperandSpec::RegMMM { // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } }, OperandCase::G_E_mm_Ib => { instruction.operands[1] = mem_oper; instruction.imm = read_num(words, 1)? as u8 as u64; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; instruction.mem_size = 0; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_Ev_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u64; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = match instruction.opcode { Opcode::PEXTRB => 1, Opcode::PEXTRW => 2, Opcode::PEXTRD => 4, Opcode::EXTRACTPS => 4, Opcode::INSERTPS => 4, Opcode::PINSRB => 1, Opcode::PINSRW => 2, Opcode::PINSRD => 4, _ => 8, }; } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::PMOVX_E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { if [].contains(&instruction.opcode) { instruction.mem_size = 2; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD || instruction.opcode == Opcode::MOVHPS { return Err(DecodeError::InvalidOperand); } } } OperandCase::PMOVX_G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { if [Opcode::PMOVSXBQ, Opcode::PMOVZXBQ].contains(&instruction.opcode) { instruction.mem_size = 2; } else if [Opcode::PMOVZXBD, Opcode::UCOMISS, Opcode::COMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD { return Err(DecodeError::InvalidOperand); } } } OperandCase::INV_Gv_M => { instruction.regs[0].bank = RegisterBank::Q; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) { if instruction.prefixes.rex_unchecked().w() { instruction.mem_size = 10; } else { instruction.mem_size = 4; } } else if [Opcode::ENQCMD, Opcode::ENQCMDS].contains(&instruction.opcode) { instruction.mem_size = 64; } else { instruction.mem_size = 16; } } OperandCase::G_U_xmm_Ub => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u64; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::ModRM_0xf20f78 => { instruction.opcode = Opcode::INSERTQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex_unchecked().r(), RegisterBank::X); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, instruction.prefixes.rex_unchecked().r(), RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u64; instruction.disp = read_num(words, 1)? as u8 as u64; instruction.operands[2] = OperandSpec::ImmU8; instruction.operands[3] = OperandSpec::ImmInDispField; instruction.operand_count = 4; } OperandCase::ModRM_0x660f78 => { instruction.opcode = Opcode::EXTRQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } if modrm >= 0b11_001_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, instruction.prefixes.rex_unchecked().r(), RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u64; instruction.disp = read_num(words, 1)? as u8 as u64; instruction.operands[1] = OperandSpec::ImmU8; instruction.operands[2] = OperandSpec::ImmInDispField; instruction.operand_count = 3; } OperandCase::ModRM_0xf30f1e => { let modrm = read_modrm(words)?; match modrm { 0xfa => { instruction.opcode = Opcode::ENDBR64; instruction.operand_count = 0; }, 0xfb => { instruction.opcode = Opcode::ENDBR32; instruction.operand_count = 0; }, _ => { let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; instruction.mem_size = bank as u8; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.rex_unchecked().r(), bank); instruction.operand_count = 2; } }; } OperandCase::G_E_xmm_Ub => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } instruction.imm = read_num(words, 1)? as u8 as u64; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::Gd_Ed => { instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } instruction.operands[1] = mem_oper; } OperandCase::Md_Gd => { instruction.regs[0].bank = RegisterBank::D; } /* OperandCase::Edq_Gdq => { let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0].bank = bank; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = bank; } instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.operand_count = 2; } */ OperandCase::G_U_xmm => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::X; instruction.regs[1].bank = RegisterBank::X; }, OperandCase::Gv_Ev_Ib => { instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Gv_Ev_Iv => { let opwidth = self.vqp_size() as u8; let numwidth = if opwidth == 8 { 4 } else { opwidth }; instruction.imm = read_imm_signed(words, numwidth)? as u64; instruction.operands[2] = match opwidth { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, 8 => OperandSpec::ImmI64, _ => unsafe { unreachable_unchecked() } }; instruction.operand_count = 3; } OperandCase::Ev_Gv_Ib => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Ev_Gv_CL => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[3] = RegSpec::cl(); instruction.operand_count = 3; } OperandCase::G_mm_Ew_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } instruction.imm = read_num(words, 1)? as u8 as u64; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_E_mm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if [Opcode::PUNPCKLBW, Opcode::PUNPCKLWD, Opcode::PUNPCKLDQ].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } }, OperandCase::G_U_mm => { instruction.regs[0].bank = RegisterBank::D; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; }, OperandCase::Gv_Ew_LAR => { instruction.operands[1] = mem_oper; // lar is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword/qword for // larger modes even though the upper 16 bits would be ignored. // // so the registers are correct by the time we're here, we might just need to override // mem size as well. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.regs[0].bank = self.vqp_size(); }, OperandCase::Gv_Ew_LSL => { instruction.operands[1] = mem_oper; // lsl is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword for larger // modes even though the upper 16 bits would be ignored. if instruction.operands[1] == OperandSpec::RegMMM { if instruction.regs[1].bank == RegisterBank::Q { instruction.regs[1].bank = RegisterBank::D; } } else { instruction.mem_size = 2; } instruction.regs[0].bank = self.vqp_size(); }, OperandCase::Gdq_Ev => { instruction.operands[1] = mem_oper; // `opwidth` can be 2, 4, or 8 here. if opwidth is 2, the first operand is a dword. // if opwidth is 4, both registers are dwords. and if opwidth is 8, both registers are // qword. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } if instruction.regs[0].bank == RegisterBank::W { instruction.regs[0].bank = RegisterBank::D; }; instruction.operand_count = 2; }, op @ OperandCase::AL_Ob | op @ OperandCase::AX_Ov => { match op { OperandCase::AL_Ob => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::AX_Ov => { let b = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; if instruction.prefixes.address_size() { instruction.operands[1] = OperandSpec::DispU32; } else { instruction.operands[1] = OperandSpec::DispU64; }; instruction.operand_count = 2; } op @ OperandCase::Ob_AL | op @ OperandCase::Ov_AX => { match op { OperandCase::Ob_AL => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::Ov_AX => { let b = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if instruction.prefixes.address_size() { 4 } else { 8 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; instruction.operands[0] = if instruction.prefixes.address_size() { OperandSpec::DispU32 } else { OperandSpec::DispU64 }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::I_1 => { instruction.imm = 1; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } /* OperandCase::Unsupported => { return Err(DecodeError::IncompleteDecoder); } */ OperandCase::Iw_Ib => { instruction.disp = read_num(words, 2)? as u64; instruction.imm = read_num(words, 1)? as u64; instruction.operands[0] = OperandSpec::ImmInDispField; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Fw => { if instruction.prefixes.rex_unchecked().w() { instruction.opcode = Opcode::IRETQ; } else if instruction.prefixes.operand_size() { instruction.opcode = Opcode::IRET; } else { instruction.opcode = Opcode::IRETD; } instruction.operand_count = 0; } OperandCase::Mdq_Gdq => { let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = bank as u8; } instruction.regs[0].bank = bank; instruction.operand_count = 2; } OperandCase::G_mm_U_mm => { instruction.regs[0].bank = RegisterBank::MM; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::E_G_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0].bank = RegisterBank::Q; instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::Q; } } OperandCase::G_E_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::Q; instruction.operand_count = 2; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::Q; } } OperandCase::G_Mq_mm => { instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::MOVQ_f30f => { // if rex.w is set, the f3 prefix no longer applies and this becomes an 0f7e movq, // rather than f30f7e movq. // // the difference here is that 0f7e movq has reversed operand order from f30f7e movq, // in addition to the selected register banks being different. // // anyway, there are two operands, and the primary concern here is "what are they?". instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.prefixes.rex_unchecked().w() { let op = instruction.operands[0]; instruction.operands[0] = instruction.operands[1]; instruction.operands[1] = op; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; instruction.opcode = Opcode::MOVD; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } else { instruction.regs[1].bank = RegisterBank::Q; } } else { if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::X; } } } OperandCase::ModRM_0x0f0d => { let r = instruction.regs[0].num & 0b111; let bank = bank_from_prefixes_64(SizeCode::vq, instruction.prefixes); match r { 1 => { instruction.opcode = Opcode::PREFETCHW; } _ => { instruction.opcode = Opcode::NOP; } } instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 64; } else { instruction.regs[1].bank = bank; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f0f => { // 3dnow instructions are WILD, the opcode is encoded as an imm8 trailing the // instruction. instruction.operands[1] = mem_oper; instruction.regs[0].num &= 0b0111; instruction.regs[0].bank = RegisterBank::MM; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; } let opcode = read_modrm(words)?; match opcode { 0x0c => { instruction.opcode = Opcode::PI2FW; } 0x0d => { instruction.opcode = Opcode::PI2FD; } 0x1c => { instruction.opcode = Opcode::PF2IW; } 0x1d => { instruction.opcode = Opcode::PF2ID; } 0x8a => { instruction.opcode = Opcode::PFNACC; } 0x8e => { instruction.opcode = Opcode::PFPNACC; } 0x90 => { instruction.opcode = Opcode::PFCMPGE; } 0x94 => { instruction.opcode = Opcode::PFMIN; } 0x96 => { instruction.opcode = Opcode::PFRCP; } 0x97 => { instruction.opcode = Opcode::PFRSQRT; } 0x9a => { instruction.opcode = Opcode::PFSUB; } 0x9e => { instruction.opcode = Opcode::PFADD; } 0xa0 => { instruction.opcode = Opcode::PFCMPGT; } 0xa4 => { instruction.opcode = Opcode::PFMAX; } 0xa6 => { instruction.opcode = Opcode::PFRCPIT1; } 0xa7 => { instruction.opcode = Opcode::PFRSQIT1; } 0xaa => { instruction.opcode = Opcode::PFSUBR; } 0xae => { instruction.opcode = Opcode::PFACC; } 0xb0 => { instruction.opcode = Opcode::PFCMPEQ; } 0xb4 => { instruction.opcode = Opcode::PFMUL; } 0xb6 => { instruction.opcode = Opcode::PFRCPIT2; } 0xb7 => { instruction.opcode = Opcode::PMULHRW; } 0xbb => { instruction.opcode = Opcode::PSWAPD; } 0xbf => { instruction.opcode = Opcode::PAVGUSB; } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0x0fc7 => { if instruction.prefixes.repnz() { let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex_unchecked().w() { instruction.opcode = Opcode::CMPXCHG16B; instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; } instruction.operand_count = 1; let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } if instruction.prefixes.operand_size() { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex_unchecked().w() { instruction.opcode = Opcode::CMPXCHG16B; instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; } instruction.operand_count = 1; let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } return Ok(()); } 6 => { instruction.opcode = Opcode::VMCLEAR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // word-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::W, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDRAND; } else { instruction.mem_size = 8; } instruction.operand_count = 1; return Ok(()); } 7 => { instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // word-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::W, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDSEED; } else { return Err(DecodeError::InvalidOpcode); } instruction.operand_count = 1; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } if instruction.prefixes.rep() { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex_unchecked().w() { instruction.opcode = Opcode::CMPXCHG16B; instruction.mem_size = 16; } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; } instruction.operand_count = 1; let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } 6 => { instruction.opcode = Opcode::VMXON; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // invalid as `vmxon`, reg-form is `senduipi` instruction.opcode = Opcode::SENDUIPI; // and the operand is always a qword register instruction.regs[1].bank = RegisterBank::Q; } else { instruction.mem_size = 8; } instruction.operand_count = 1; } 7 => { instruction.opcode = Opcode::RDPID; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 0b111; let opcode = match r { 0b001 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex_unchecked().w() { instruction.mem_size = 16; Opcode::CMPXCHG16B } else { instruction.mem_size = 8; Opcode::CMPXCHG8B } } } 0b011 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; if instruction.prefixes.rex_unchecked().w() { Opcode::XRSTORS64 } else { Opcode::XRSTORS } } } 0b100 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; if instruction.prefixes.rex_unchecked().w() { Opcode::XSAVEC64 } else { Opcode::XSAVEC } } } 0b101 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; if instruction.prefixes.rex_unchecked().w() { Opcode::XSAVES64 } else { Opcode::XSAVES } } } 0b110 => { if is_reg { Opcode::RDRAND } else { instruction.mem_size = 8; Opcode::VMPTRLD } } 0b111 => { if is_reg { Opcode::RDSEED } else { instruction.mem_size = 8; Opcode::VMPTRST } } _ => { return Err(DecodeError::InvalidOperand); } }; instruction.opcode = opcode; instruction.operand_count = 1; let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; }, OperandCase::ModRM_0x0f71 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLW, Opcode::Invalid, Opcode::PSRAW, Opcode::Invalid, Opcode::PSLLW, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; }, OperandCase::ModRM_0x0f72 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLD, Opcode::Invalid, Opcode::PSRAD, Opcode::Invalid, Opcode::PSLLD, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0x0f73 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; match r { 2 => { instruction.opcode = Opcode::PSRLQ; } 3 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSRLDQ; } 6 => { instruction.opcode = Opcode::PSLLQ; } 7 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0xf30f38d8 => { instruction.operand_count = 1; let r = instruction.regs[0].num & 0b111; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } match r { 0b000 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESENCWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b001 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESDECWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b010 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESENCWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b011 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESDECWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0xf30f38dc => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::LOADIWKEY; } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESENC128KL; } } OperandCase::ModRM_0xf30f38dd => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESDEC128KL; } } OperandCase::ModRM_0xf30f38de => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESENC256KL; } } OperandCase::ModRM_0xf30f38df => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESDEC256KL; } } OperandCase::ModRM_0xf30f38fa => { instruction.opcode = Opcode::ENCODEKEY128; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f38fb => { instruction.opcode = Opcode::ENCODEKEY256; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f3af0 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOpcode); // invalid } instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::G_mm_Edq => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.rex_unchecked().w() { instruction.regs[1].bank = RegisterBank::Q; } else { instruction.regs[1].bank = RegisterBank::D; } } } OperandCase::G_mm_E => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } OperandCase::Edq_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.rex_unchecked().w() { instruction.regs[1].bank = RegisterBank::Q; } else { instruction.regs[1].bank = RegisterBank::D; } } else { if instruction.prefixes.rex_unchecked().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } } OperandCase::Edq_G_xmm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.rex_unchecked().w() { instruction.regs[1].bank = RegisterBank::Q; // movd/q is so weird instruction.opcode = Opcode::MOVQ; } else { instruction.regs[1].bank = RegisterBank::D; } } else { if instruction.prefixes.rex_unchecked().w() { instruction.opcode = Opcode::MOVQ; instruction.mem_size = 8; } else { instruction.mem_size = 4; } } } OperandCase::E_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } /* OperandCase::G_xmm_Ed => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } }, */ OperandCase::G_xmm_Edq => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.rex_unchecked().w() { instruction.regs[1].bank = RegisterBank::Q; } else { instruction.regs[1].bank = RegisterBank::D; } } }, OperandCase::G_xmm_Ew_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u64; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } }, OperandCase::G_xmm_Eq => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::Q; } else { instruction.mem_size = 8; } }, OperandCase::G_mm_E_xmm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, op @ OperandCase::G_xmm_U_mm | op @ OperandCase::G_xmm_E_mm => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if op == OperandCase::G_xmm_U_mm { return Err(DecodeError::InvalidOperand); } else { if instruction.prefixes.rex_unchecked().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } } }, OperandCase::Rv_Gmm_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u64; instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } OperandCase::G_mm_U_xmm => { instruction.regs[1].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } // sure hope these aren't backwards huh OperandCase::AL_Xb => { instruction.regs[0] = RegSpec::al(); if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::esi(); } else { instruction.regs[1] = RegSpec::rsi(); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_Xb => { if instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } else { instruction.operands[0] = OperandSpec::Deref_rdi; instruction.operands[1] = OperandSpec::Deref_rsi; } instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_AL => { instruction.regs[0] = RegSpec::al(); if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::edi(); } else { instruction.regs[1] = RegSpec::rdi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::AX_Xv => { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::esi(); } else { instruction.regs[1] = RegSpec::rsi(); } instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = bank as u8; } OperandCase::Yv_AX => { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::edi(); } else { instruction.regs[1] = RegSpec::rdi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = bank as u8; } OperandCase::Yv_Xv => { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.mem_size = bank as u8; if instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } else { instruction.operands[0] = OperandSpec::Deref_rdi; instruction.operands[1] = OperandSpec::Deref_rsi; } } OperandCase::ModRM_0x0f12 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::MOVHLPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVLPD; } else { instruction.opcode = Opcode::MOVLPS; } } } OperandCase::ModRM_0x0f16 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::MOVLHPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVHPD; } else { instruction.opcode = Opcode::MOVHPS; } } } OperandCase::ModRM_0x0f18 => { let rrr = instruction.regs[0].num & 0b111; instruction.operands[0] = mem_oper; instruction.operand_count = 1; // only PREFETCH* are invalid on reg operand instruction.opcode = if mem_oper == OperandSpec::RegMMM && rrr < 4 { Opcode::NOP } else { match rrr { 0 => Opcode::PREFETCHNTA, 1 => Opcode::PREFETCH0, 2 => Opcode::PREFETCH1, 3 => Opcode::PREFETCH2, _ => Opcode::NOP, } }; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 64; } } OperandCase::Gd_U_xmm => { if instruction.operands[1] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; } OperandCase::Gdq_Eq_xmm => { if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { // should not be possible to reach `instruction.regs[0].bank == W`, as that would // be `cvttpd2pi mm, xmm` instruction.mem_size = 8; } } OperandCase::Gv_E_xmm => { if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } } OperandCase::M_G_xmm => { if instruction.opcode == Opcode::MOVNTSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::MOVNTPD || instruction.opcode == Opcode::MOVNTDQ || instruction.opcode == Opcode::MOVNTPS { instruction.mem_size = 16; } else { instruction.mem_size = 8; } instruction.regs[0].bank = RegisterBank::X; } OperandCase::Ew_Sw => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::Sw_Ew => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } // quoth the manual: // ``` // The MOV instruction cannot be used to load the CS register. Attempting to do so // results in an invalid opcode excep-tion (#UD). To load the CS register, use the far // JMP, CALL, or RET instruction. // ``` if r == 1 { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::CVT_AA => { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = match bank { RegisterBank::W => { Opcode::CBW }, RegisterBank::D => { Opcode::CWDE }, RegisterBank::Q => { Opcode::CDQE }, _ => { unreachable!("invalid operation width"); }, } } OperandCase::CVT_DA => { let bank = bank_from_prefixes_64(SizeCode::vqp, instruction.prefixes); instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = match bank { RegisterBank::W => { Opcode::CWD }, RegisterBank::D => { Opcode::CDQ }, RegisterBank::Q => { Opcode::CQO }, _ => { unreachable!("invalid operation width"); }, } } OperandCase::Ib => { instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Iw => { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmU16; if instruction.opcode == Opcode::RETURN { instruction.mem_size = 8; } else { instruction.mem_size = 10; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f00 => { instruction.operand_count = 1; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { instruction.opcode = Opcode::SLDT; } else if r == 1 { instruction.opcode = Opcode::STR; } else if r == 2 { instruction.opcode = Opcode::LLDT; } else if r == 3 { instruction.opcode = Opcode::LTR; } else if r == 4 { instruction.opcode = Opcode::VERR; } else if r == 5 { instruction.opcode = Opcode::VERW; } else if r == 6 { // TODO: this would be jmpe for x86-on-itanium systems. instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else if r == 7 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else { unreachable!("r <= 8"); } instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCase::ModRM_0x0f01 => { let bank = bank_from_prefixes_64(SizeCode::vq, instruction.prefixes); let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; const TBL: [Opcode; 8] = [ Opcode::ENCLV, Opcode::VMCALL, Opcode::VMLAUNCH, Opcode::VMRESUME, Opcode::VMXOFF, Opcode::PCONFIG, Opcode::Invalid, Opcode::Invalid, ]; instruction.opcode = TBL[m as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::SGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 1 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } if instruction.prefixes.operand_size() { match m { 0b100 => { instruction.opcode = Opcode::TDCALL; } 0b101 => { instruction.opcode = Opcode::SEAMRET; } 0b110 => { instruction.opcode = Opcode::SEAMOPS; } 0b111 => { instruction.opcode = Opcode::SEAMCALL; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { match m { 0b000 => { instruction.opcode = Opcode::MONITOR; } 0b001 => { instruction.opcode = Opcode::MWAIT; }, 0b010 => { instruction.opcode = Opcode::CLAC; } 0b011 => { instruction.opcode = Opcode::STAC; } 0b111 => { instruction.opcode = Opcode::ENCLS; } _ => { return Err(DecodeError::InvalidOpcode); } } } } else { instruction.opcode = Opcode::SIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 2 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match m { 0b000 => { instruction.opcode = Opcode::XGETBV; } 0b001 => { instruction.opcode = Opcode::XSETBV; } 0b100 => { instruction.opcode = Opcode::VMFUNC; } 0b101 => { instruction.opcode = Opcode::XEND; } 0b110 => { instruction.opcode = Opcode::XTEST; } 0b111 => { instruction.opcode = Opcode::ENCLU; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { instruction.opcode = Opcode::LGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 3 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { match m { 0b000 => { instruction.opcode = Opcode::VMRUN; instruction.operand_count = 1; instruction.regs[0] = RegSpec::rax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b001 => { instruction.opcode = Opcode::VMMCALL; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b010 => { instruction.opcode = Opcode::VMLOAD; instruction.operand_count = 1; instruction.regs[0] = RegSpec::rax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b011 => { instruction.opcode = Opcode::VMSAVE; instruction.operand_count = 1; instruction.regs[0] = RegSpec::rax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b100 => { instruction.opcode = Opcode::STGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b101 => { instruction.opcode = Opcode::CLGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b110 => { instruction.opcode = Opcode::SKINIT; instruction.operand_count = 1; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::eax(); }, 0b111 => { instruction.opcode = Opcode::INVLPGA; instruction.operand_count = 2; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[0] = RegSpec::rax(); instruction.regs[1] = RegSpec::ecx(); }, _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } } } else { instruction.opcode = Opcode::LIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 4 { // TODO: this permits storing only to word-size registers // spec suggets this might do something different for f.ex rdi? instruction.opcode = Opcode::SMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 5 { let mod_bits = modrm >> 6; if mod_bits != 0b11 { if !instruction.prefixes.rep() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RSTORSSP; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::Q, sink)?; instruction.mem_size = 8; instruction.operand_count = 1; return Ok(()); } let m = modrm & 7; match m { 0b000 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XSUSLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SETSSBSY; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b001 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XRESLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b010 => { if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SAVEPREVSSP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b100 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::UIRET; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b101 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::TESTUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b110 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::CLUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RDPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b111 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::STUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::WRPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } } else if r == 6 { instruction.opcode = Opcode::LMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 7 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if m == 0 { instruction.opcode = Opcode::SWAPGS; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 1 { instruction.opcode = Opcode::RDTSCP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 2 { instruction.opcode = Opcode::MONITORX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 3 { instruction.opcode = Opcode::MWAITX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 4 { instruction.opcode = Opcode::CLZERO; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 5 { instruction.opcode = Opcode::RDPRU; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::ecx(); instruction.operand_count = 1; } else if m == 6 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPADJUST; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPUPDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::INVLPGB; instruction.operand_count = 3; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[0] = RegSpec::rax(); instruction.regs[1] = RegSpec::edx(); instruction.regs[3] = RegSpec::ecx(); } else if m == 7 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSMASH; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PVALIDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::TLBSYNC; instruction.operand_count = 0; } else { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::INVLPG; instruction.operand_count = 1; instruction.mem_size = 1; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else { unreachable!("r <= 8"); } } OperandCase::ModRM_0x0fae => { let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; let m = modrm & 7; if instruction.prefixes.operand_size() && !(instruction.prefixes.rep() || instruction.prefixes.repnz()) { instruction.prefixes.unset_operand_size(); if instruction.prefixes.rex_unchecked().w() { self.vqp_size = RegisterBank::Q; } else { self.vqp_size = RegisterBank::D; }; if modrm < 0xc0 { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::CLWB } 7 => { Opcode::CLFLUSHOPT } _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::B /* opwidth */, sink)?; instruction.mem_size = 64; instruction.operand_count = 1; } else { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::TPAUSE } _ => { return Err(DecodeError::InvalidOpcode); } }; let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; instruction.operand_count = 1; } return Ok(()); } if instruction.prefixes.repnz() { if (modrm & 0xc0) == 0xc0 { match r { 6 => { instruction.opcode = Opcode::UMWAIT; instruction.regs[0] = RegSpec { bank: if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }, num: m + if instruction.prefixes.rex_unchecked().x() { 0b1000 } else { 0 }, }; instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } } if instruction.prefixes.rep() { if r == 4 { if instruction.prefixes.operand_size() { // xed specifically rejects this. seeems out of line since rep takes // precedence elsewhere, but ok i guess return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::PTWRITE; let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 1; return Ok(()); } if (modrm & 0xc0) == 0xc0 { match r { 0 => { instruction.opcode = Opcode::RDFSBASE; let opwidth = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), opwidth); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 1 => { instruction.opcode = Opcode::RDGSBASE; let opwidth = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), opwidth); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 2 => { instruction.opcode = Opcode::WRFSBASE; let opwidth = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), opwidth); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 3 => { instruction.opcode = Opcode::WRGSBASE; let opwidth = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), opwidth); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 5 => { instruction.opcode = Opcode::INCSSP; let opwidth = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), opwidth); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 6 => { instruction.opcode = Opcode::UMONITOR; instruction.regs[1] = RegSpec::from_parts(m, instruction.prefixes.rex_unchecked().x(), RegisterBank::Q); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } else { match r { 6 => { instruction.opcode = Opcode::CLRSSBSY; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::Q, sink)?; instruction.operand_count = 1; instruction.mem_size = 8; return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } } let mod_bits = modrm >> 6; // all the 0b11 instructions are err or no-operands if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match r { // invalid rrr for 0x0fae, mod: 11 0 | 1 | 2 | 3 | 4 => { return Err(DecodeError::InvalidOpcode); }, 5 => { instruction.opcode = Opcode::LFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 6 => { instruction.opcode = Opcode::MFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 7 => { instruction.opcode = Opcode::SFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, _ => { unsafe { unreachable_unchecked() } /* r <=7 */ } } } else { // these can't be prefixed, so says `xed` i guess. if instruction.prefixes.operand_size() || instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; let (opcode, mem_size) = [ (Opcode::FXSAVE, 63), (Opcode::FXRSTOR, 63), (Opcode::LDMXCSR, 4), (Opcode::STMXCSR, 4), (Opcode::XSAVE, 63), (Opcode::XRSTOR, 63), (Opcode::XSAVEOPT, 63), (Opcode::CLFLUSH, 64), ][r as usize]; instruction.opcode = opcode; instruction.mem_size = mem_size; instruction.operands[0] = read_M(words, instruction, modrm, sink)?; } } OperandCase::ModRM_0x0fba => { let bank = bank_from_prefixes_64(SizeCode::vq, instruction.prefixes); let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::BT, Opcode::BTS, Opcode::BTR, Opcode::BTC ]; instruction.opcode = TBL[r as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.imm = read_imm_signed(words, 1)? as u64; instruction.operands[1] = OperandSpec::ImmI8; instruction.operand_count = 2; } op @ OperandCase::Rq_Cq_0 | op @ OperandCase::Rq_Dq_0 | op @ OperandCase::Cq_Rq_0 | op @ OperandCase::Dq_Rq_0 => { let modrm = read_modrm(words)?; let mut m = modrm & 7; let mut r = (modrm >> 3) & 7; if instruction.prefixes.rex_unchecked().r() { r += 0b1000; } if instruction.prefixes.rex_unchecked().b() { m += 0b1000; } let bank = match op { OperandCase::Rq_Cq_0 | OperandCase::Cq_Rq_0 => { if r != 0 && r != 2 && r != 3 && r != 4 && r != 8 { return Err(DecodeError::InvalidOperand); } RegisterBank::CR }, OperandCase::Rq_Dq_0 | OperandCase::Dq_Rq_0 => { if r > 7 { return Err(DecodeError::InvalidOperand); } RegisterBank::DR }, _ => unsafe { unreachable_unchecked() } }; let (rrr, mmm) = match op { OperandCase::Rq_Cq_0 | OperandCase::Rq_Dq_0 => (1, 0), OperandCase::Cq_Rq_0 | OperandCase::Dq_Rq_0 => (0, 1), _ => unsafe { unreachable_unchecked() } }; instruction.regs[0] = RegSpec { bank: bank, num: r }; instruction.regs[1] = RegSpec { bank: RegisterBank::Q, num: m }; instruction.operands[mmm] = OperandSpec::RegMMM; instruction.operands[rrr] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::FS => { instruction.regs[0] = RegSpec::fs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::GS => { instruction.regs[0] = RegSpec::gs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::AL_Ib => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::AX_Ib => { instruction.regs[0].num = 0; instruction.regs[0].bank = bank_from_prefixes_64(SizeCode::vd, instruction.prefixes); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Ib_AL => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Ib_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = bank_from_prefixes_64(SizeCode::vd, instruction.prefixes); instruction.imm = read_imm_signed(words, 1)? as u64; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::AX_DX => { instruction.regs[0].num = 0; instruction.regs[0].bank = bank_from_prefixes_64(SizeCode::vd, instruction.prefixes); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::AL_DX => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::DX_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = bank_from_prefixes_64(SizeCode::vd, instruction.prefixes); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::DX_AL => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Yb_DX => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::rdi(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::Yv_DX => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::rdi(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::DX_Xb => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::rsi(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::AH => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } OperandCase::DX_Xv => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::rsi(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::x87_d8 | OperandCase::x87_d9 | OperandCase::x87_da | OperandCase::x87_db | OperandCase::x87_dc | OperandCase::x87_dd | OperandCase::x87_de | OperandCase::x87_df => { return decode_x87(words, instruction, operand_code.operand_case_handler_index(), sink); } OperandCase::MOVDIR64B => { // because the first operand is actually a memory address, and this is the only x86 // instruction other than movs to have two memory operands, the first operand has to be // sized by address-size, not operand-size. instruction.mem_size = 64; if instruction.prefixes.address_size() { instruction.regs[0].bank = RegisterBank::D; } else { instruction.regs[0].bank = RegisterBank::Q; }; } }; Ok(()) } #[inline(always)] fn read_0f_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // seems like f2 takes priority, then f3, then 66, then "no prefix". for SOME instructions an // invalid prefix is in fact an invalid instruction. so just duplicate for the four kinds of // opcode lists. if prefixes.repnz() { REPNZ_0F_CODES[opcode as usize] } else if prefixes.rep() { REP_0F_CODES[opcode as usize] } else if prefixes.operand_size() { OPERAND_SIZE_0F_CODES[opcode as usize] } else { NORMAL_0F_CODES[opcode as usize] } } #[inline(always)] fn read_0f38_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> Result { if prefixes.rep() { const TBL: [OpcodeRecord; 0x28] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38d8), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dc), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38de), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38df), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf6 OpcodeRecord::new(Interpretation::Instruction(Opcode::ADOX), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf8 OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xfa OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fa), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fb), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), ]; return if opcode < 0xd8 { Err(DecodeError::InvalidOpcode) } else { Ok(TBL[(opcode - 0xd8) as usize]) }; /* 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ADOX), OperandCode::Gv_Ev), 0xf8 => { prefixes.unset_operand_size(); if prefixes.rex_unchecked().w() { self.vqp_size = RegisterBank::Q; } else { self.vqp_size = RegisterBank::D; } OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::INV_Gv_M) }, 0xfa => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fa), 0xfb => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fb), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; */ } if prefixes.repnz() { const TBL: [OpcodeRecord; 0x10] = [ // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gdq_Ev), // 0xf2 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf8 OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMD), OperandCode::INV_Gv_M), // 0xf9 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), ]; return if opcode < 0xf0 { Err(DecodeError::InvalidOpcode) } else { Ok(TBL[(opcode - 0xf0) as usize]) }; } if prefixes.operand_size() { // leave operand size present for `movbe` if opcode != 0xf0 && opcode != 0xf1 { prefixes.unset_operand_size(); if prefixes.rex_unchecked().w() { self.vqp_size = RegisterBank::Q; } else { self.vqp_size = RegisterBank::D; } } return Ok(TBL_ASDF[opcode as usize]); } else { return Ok(TBL_ASDF2[opcode as usize]); } } #[inline(always)] fn read_0f3a_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> Result { if prefixes.rep() { if prefixes != &Prefixes::new(0x10) { return Err(DecodeError::InvalidOpcode); } return match opcode { 0xf0 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0)), _ => Err(DecodeError::InvalidOpcode), }; } if prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } if prefixes.operand_size() { if opcode == 0x16 && prefixes.rex_unchecked().w() { return Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRQ), OperandCode::G_Ev_xmm_Ib)); } else if opcode == 0x22 && prefixes.rex_unchecked().w() { return Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRQ), OperandCode::G_Ev_xmm_Ib)); } return match opcode { 0x08 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPS), OperandCode::G_E_xmm_Ib)), 0x09 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPD), OperandCode::G_E_xmm_Ib)), 0x0a => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSS), OperandCode::G_E_xmm_Ib)), 0x0b => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSD), OperandCode::G_E_xmm_Ib)), 0x0c => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPS), OperandCode::G_E_xmm_Ib)), 0x0d => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPD), OperandCode::G_E_xmm_Ib)), 0x0e => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDW), OperandCode::G_E_xmm_Ib)), 0x0f => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_xmm_Ib)), 0x14 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRB), OperandCode::G_Ev_xmm_Ib)), 0x15 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_Ev_xmm_Ib)), 0x16 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRD), OperandCode::G_Ev_xmm_Ib)), 0x17 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRACTPS), OperandCode::G_Ev_xmm_Ib)), 0x20 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRB), OperandCode::G_Ev_xmm_Ib)), 0x21 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTPS), OperandCode::G_Ev_xmm_Ib)), 0x22 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRD), OperandCode::G_Ev_xmm_Ib)), 0x40 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPS), OperandCode::G_E_xmm_Ib)), 0x41 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPD), OperandCode::G_E_xmm_Ib)), 0x42 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::MPSADBW), OperandCode::G_E_xmm_Ib)), 0x44 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PCLMULQDQ), OperandCode::G_E_xmm_Ib)), 0x60 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRM), OperandCode::G_E_xmm_Ib)), 0x61 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRI), OperandCode::G_E_xmm_Ib)), 0x62 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRM), OperandCode::G_E_xmm_Ib)), 0x63 => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRI), OperandCode::G_E_xmm_Ib)), // 0xcc => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ib)), 0xce => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEQB), OperandCode::G_E_xmm_Ub)), 0xcf => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEINVQB), OperandCode::G_E_xmm_Ub)), 0xdf => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::AESKEYGENASSIST), OperandCode::G_E_xmm_Ub)), _ => Err(DecodeError::InvalidOpcode), }; } return match opcode { 0xcc => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ub)), 0x0f => Ok(OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_mm_Ib)), _ => Err(DecodeError::InvalidOpcode) }; } } fn decode_x87< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: OperandCase, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("x87 opcode") .with_id(words.offset() as u32 * 8 - 1) ); #[allow(non_camel_case_types)] enum OperandCodeX87 { Est, St_Est, St_Edst, St_Eqst, St_Ew, St_Mw, St_Md, St_Mq, St_Mm, Ew, Est_St, Edst_St, Eqst_St, Ed_St, Mw_St, Md_St, Mq_St, Mm_St, Ex87S, Nothing, } // every x87 instruction is conditional on rrr bits let modrm = read_modrm(words)?; let r = (modrm >> 3) & 0b111; let (opcode, x87_operands) = match operand_code { OperandCase::x87_d8 => { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Edst), 1 => (Opcode::FMUL, OperandCodeX87::St_Edst), 2 => (Opcode::FCOM, OperandCodeX87::St_Edst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Edst), 4 => (Opcode::FSUB, OperandCodeX87::St_Edst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Edst), 6 => (Opcode::FDIV, OperandCodeX87::St_Edst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Edst), _ => { unreachable!("impossible r"); } } } OperandCase::x87_d9 => { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Edst), 1 => { if modrm >= 0xc0 { (Opcode::FXCH, OperandCodeX87::St_Est) } else { return Err(DecodeError::InvalidOpcode); } }, 2 => { if modrm >= 0xc0 { if modrm == 0xd0 { (Opcode::FNOP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } else { (Opcode::FST, OperandCodeX87::Ed_St) } } 3 => { if modrm >= 0xc0 { (Opcode::FSTPNCE, OperandCodeX87::Est_St) } else { (Opcode::FSTP, OperandCodeX87::Edst_St) } }, 4 => { if modrm >= 0xc0 { match modrm { 0xe0 => (Opcode::FCHS, OperandCodeX87::Nothing), 0xe1 => (Opcode::FABS, OperandCodeX87::Nothing), 0xe2 => { return Err(DecodeError::InvalidOpcode); }, 0xe3 => { return Err(DecodeError::InvalidOpcode); }, 0xe4 => (Opcode::FTST, OperandCodeX87::Nothing), 0xe5 => (Opcode::FXAM, OperandCodeX87::Nothing), 0xe6 => { return Err(DecodeError::InvalidOpcode); }, 0xe7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDENV, OperandCodeX87::Ex87S) // x87 state } }, 5 => { if modrm >= 0xc0 { match modrm { 0xe8 => (Opcode::FLD1, OperandCodeX87::Nothing), 0xe9 => (Opcode::FLDL2T, OperandCodeX87::Nothing), 0xea => (Opcode::FLDL2E, OperandCodeX87::Nothing), 0xeb => (Opcode::FLDPI, OperandCodeX87::Nothing), 0xec => (Opcode::FLDLG2, OperandCodeX87::Nothing), 0xed => (Opcode::FLDLN2, OperandCodeX87::Nothing), 0xee => (Opcode::FLDZ, OperandCodeX87::Nothing), 0xef => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDCW, OperandCodeX87::Ew) } } 6 => { if modrm >= 0xc0 { match modrm { 0xf0 => (Opcode::F2XM1, OperandCodeX87::Nothing), 0xf1 => (Opcode::FYL2X, OperandCodeX87::Nothing), 0xf2 => (Opcode::FPTAN, OperandCodeX87::Nothing), 0xf3 => (Opcode::FPATAN, OperandCodeX87::Nothing), 0xf4 => (Opcode::FXTRACT, OperandCodeX87::Nothing), 0xf5 => (Opcode::FPREM1, OperandCodeX87::Nothing), 0xf6 => (Opcode::FDECSTP, OperandCodeX87::Nothing), 0xf7 => (Opcode::FINCSTP, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTENV, OperandCodeX87::Ex87S) // x87 state } } 7 => { if modrm >= 0xc0 { match modrm { 0xf8 => (Opcode::FPREM, OperandCodeX87::Nothing), 0xf9 => (Opcode::FYL2XP1, OperandCodeX87::Nothing), 0xfa => (Opcode::FSQRT, OperandCodeX87::Nothing), 0xfb => (Opcode::FSINCOS, OperandCodeX87::Nothing), 0xfc => (Opcode::FRNDINT, OperandCodeX87::Nothing), 0xfd => (Opcode::FSCALE, OperandCodeX87::Nothing), 0xfe => (Opcode::FSIN, OperandCodeX87::Nothing), 0xff => (Opcode::FCOS, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTCW, OperandCodeX87::Ew) } } _ => { unreachable!("impossible r"); } } } OperandCase::x87_da => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVU, OperandCodeX87::St_Est), _ => { if modrm == 0xe9 { (Opcode::FUCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Md), // 0xd9d0 -> fnop 1 => (Opcode::FIMUL, OperandCodeX87::St_Md), 2 => (Opcode::FICOM, OperandCodeX87::St_Md), // FCMOVE 3 => (Opcode::FICOMP, OperandCodeX87::St_Md), // FCMOVBE 4 => (Opcode::FISUB, OperandCodeX87::St_Md), 5 => (Opcode::FISUBR, OperandCodeX87::St_Md), // FUCOMPP 6 => (Opcode::FIDIV, OperandCodeX87::St_Md), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Md), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_db => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVNB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVNE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVNBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVNU, OperandCodeX87::St_Est), 4 => { match modrm { 0xe0 => (Opcode::FENI8087_NOP, OperandCodeX87::Nothing), 0xe1 => (Opcode::FDISI8087_NOP, OperandCodeX87::Nothing), 0xe2 => (Opcode::FNCLEX, OperandCodeX87::Nothing), 0xe3 => (Opcode::FNINIT, OperandCodeX87::Nothing), 0xe4 => (Opcode::FSETPM287_NOP, OperandCodeX87::Nothing), _ => { return Err(DecodeError::InvalidOpcode); } } } 5 => (Opcode::FUCOMI, OperandCodeX87::St_Est), 6 => (Opcode::FCOMI, OperandCodeX87::St_Est), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Md), 1 => (Opcode::FISTTP, OperandCodeX87::Md_St), 2 => (Opcode::FIST, OperandCodeX87::Md_St), 3 => (Opcode::FISTP, OperandCodeX87::Md_St), 5 => (Opcode::FLD, OperandCodeX87::St_Mm), // 80bit 7 => (Opcode::FSTP, OperandCodeX87::Mm_St), // 80bit _ => { return Err(DecodeError::InvalidOpcode); } } } } OperandCase::x87_dc => { // mod=11 swaps operand order for some instructions if modrm >= 0xc0 { match r { 0 => (Opcode::FADD, OperandCodeX87::Eqst_St), 1 => (Opcode::FMUL, OperandCodeX87::Eqst_St), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUBR, OperandCodeX87::Eqst_St), 5 => (Opcode::FSUB, OperandCodeX87::Eqst_St), 6 => (Opcode::FDIVR, OperandCodeX87::Eqst_St), 7 => (Opcode::FDIV, OperandCodeX87::Eqst_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Eqst), 1 => (Opcode::FMUL, OperandCodeX87::St_Eqst), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUB, OperandCodeX87::St_Eqst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Eqst), 6 => (Opcode::FDIV, OperandCodeX87::St_Eqst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Eqst), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_dd => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREE, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FST, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => (Opcode::FUCOM, OperandCodeX87::St_Est), 5 => (Opcode::FUCOMP, OperandCodeX87::St_Est), 6 => (Opcode::Invalid, OperandCodeX87::Nothing), 7 => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Eqst), 1 => (Opcode::FISTTP, OperandCodeX87::Eqst_St), 2 => (Opcode::FST, OperandCodeX87::Eqst_St), 3 => (Opcode::FSTP, OperandCodeX87::Eqst_St), 4 => (Opcode::FRSTOR, OperandCodeX87::Ex87S), 5 => (Opcode::Invalid, OperandCodeX87::Nothing), 6 => (Opcode::FNSAVE, OperandCodeX87::Ex87S), 7 => (Opcode::FNSTSW, OperandCodeX87::Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_de => { if modrm >= 0xc0 { match r { 0 => (Opcode::FADDP, OperandCodeX87::Est_St), 1 => (Opcode::FMULP, OperandCodeX87::Est_St), // undocumented in intel manual, argument order inferred from // by xed and capstone. TODO: check amd manual. 2 => (Opcode::FCOMP, OperandCodeX87::St_Est), 3 => { if modrm == 0xd9 { (Opcode::FCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOperand); } }, 4 => (Opcode::FSUBRP, OperandCodeX87::Est_St), 5 => (Opcode::FSUBP, OperandCodeX87::Est_St), 6 => (Opcode::FDIVRP, OperandCodeX87::Est_St), 7 => (Opcode::FDIVP, OperandCodeX87::Est_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Ew), 1 => (Opcode::FIMUL, OperandCodeX87::St_Ew), 2 => (Opcode::FICOM, OperandCodeX87::St_Ew), 3 => (Opcode::FICOMP, OperandCodeX87::St_Ew), 4 => (Opcode::FISUB, OperandCodeX87::St_Ew), 5 => (Opcode::FISUBR, OperandCodeX87::St_Ew), 6 => (Opcode::FIDIV, OperandCodeX87::St_Ew), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_df => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREEP, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FSTP, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => { if modrm == 0xe0 { (Opcode::FNSTSW, OperandCodeX87::Ew) } else { return Err(DecodeError::InvalidOpcode); } }, 5 => (Opcode::FUCOMIP, OperandCodeX87::St_Est), 6 => (Opcode::FCOMIP, OperandCodeX87::St_Est), 7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Mw), 1 => (Opcode::FISTTP, OperandCodeX87::Mw_St), 2 => (Opcode::FIST, OperandCodeX87::Mw_St), 3 => (Opcode::FISTP, OperandCodeX87::Mw_St), 4 => (Opcode::FBLD, OperandCodeX87::St_Mm), 5 => (Opcode::FILD, OperandCodeX87::St_Mq), 6 => (Opcode::FBSTP, OperandCodeX87::Mm_St), 7 => (Opcode::FISTP, OperandCodeX87::Mq_St), _ => { unreachable!("impossible r"); } } } } other => { panic!("invalid x87 operand dispatch, operand code is {:?}", other); } }; instruction.opcode = opcode; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } match x87_operands { OperandCodeX87::Est => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 1; } OperandCodeX87::St_Est => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 2; } OperandCodeX87::St_Edst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::St_Eqst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 2; } OperandCodeX87::St_Ew => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.operand_count = 2; } OperandCodeX87::St_Mm => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operand_count = 2; } OperandCodeX87::St_Mq => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operand_count = 2; } OperandCodeX87::St_Md => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operand_count = 2; } OperandCodeX87::St_Mw => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operand_count = 2; } OperandCodeX87::Ew => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; instruction.operand_count = 1; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCodeX87::Est_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Edst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } } OperandCodeX87::Eqst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 8; } } OperandCodeX87::Ed_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::Mm_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mq_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Md_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mw_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Ex87S => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 63; } OperandCodeX87::Nothing => { instruction.operand_count = 0; }, } Ok(()) } #[inline(always)] fn read_num::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { match width { 1 => { bytes.next().ok().ok_or(DecodeError::ExhaustedInput).map(|x| x as u64) } 2 => { let mut buf = [0u8; 2]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u16::from_le_bytes(buf) as u64) } 4 => { let mut buf = [0u8; 4]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u32::from_le_bytes(buf) as u64) } 8 => { let mut buf = [0u8; 8]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u64::from_le_bytes(buf)) } _ => { unsafe { unreachable_unchecked(); } } } } #[inline(always)] fn read_imm_signed::Address, ::Word>>(bytes: &mut T, num_width: u8) -> Result { if num_width == 1 { Ok(read_num(bytes, 1)? as i8 as i64) } else if num_width == 2 { Ok(read_num(bytes, 2)? as i16 as i64) } else { // this is for 4 and 8, the only values for num_width may be 1, 2, 4, and 8. Ok(read_num(bytes, 4)? as i32 as i64) } } #[inline] fn read_imm_unsigned::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { read_num(bytes, width) } #[inline] fn bank_from_prefixes_64(interpretation: SizeCode, prefixes: Prefixes) -> RegisterBank { match interpretation { SizeCode::b => RegisterBank::B, SizeCode::vd => { if prefixes.rex_unchecked().w() || !prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W } }, SizeCode::vq => { if prefixes.operand_size() { RegisterBank::W } else { RegisterBank::Q } }, SizeCode::vqp => { if prefixes.rex_unchecked().w() { RegisterBank::Q } else if prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D } }, } } #[inline] fn read_modrm::Address, ::Word>>(words: &mut T) -> Result { words.next().ok().ok_or(DecodeError::ExhaustedInput) } const REPNZ_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDDUP), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), // 0x20 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SD), OperandCode::G_xmm_Edq), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSD2SI), OperandCode::Gdq_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SI), OperandCode::Gdq_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFLW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf20f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), // cmpxchg permits an f2 prefix, which is the only reason this entry is not `Nothing` OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQ2Q), OperandCode::G_mm_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::LDDQU), OperandCode::G_M_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const REP_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::Ed_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSLDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSHDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::ModRM_0xf30f1e), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SS), OperandCode::G_xmm_Edq), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_Ed_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::G_E_xmm), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFHW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::MOVQ_f30f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::LZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ2DQ), OperandCode::G_xmm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const OPERAND_SIZE_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PD), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPD), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_xmm_Eq), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x660f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Edq_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_xmm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_U_xmm_Ub), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_xmm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQ), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_xmm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVDQU), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const NORMAL_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f12), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f16), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPS), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PS), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISS), OperandCode::PMOVX_G_E_xmm), // 0x30 OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::GETSEC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x40 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPS), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPS), OperandCode::G_E_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::G_mm_Edq), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_mm_E), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFW), OperandCode::G_E_mm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::EMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMREAD), OperandCode::E_G_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMWRITE), OperandCode::G_E_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Edq_G_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::E_G_mm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // JMPE, ITANIUM OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTI), OperandCode::Mdq_Gdq), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_mm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::Rv_Gmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::G_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_mm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTQ), OperandCode::G_Mq_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_mm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVQ), OperandCode::G_mm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const TBL_ASDF: [OpcodeRecord; 0x100] = [ // 0x00 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_xmm), // 0x01 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_xmm), // 0x02 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_xmm), // 0x03 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_xmm), // 0x04 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_xmm), // 0x05 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_xmm), // 0x06 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_xmm), // 0x07 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_xmm), // 0x08 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_xmm), // 0x09 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_xmm), // 0x0a OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_xmm), // 0x0b OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x10 OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDVB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x14 OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPS), OperandCode::G_E_xmm), // 0x15 OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x17 OpcodeRecord::new(Interpretation::Instruction(Opcode::PTEST), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x1c OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_xmm), // 0x1d OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_xmm), // 0x1e OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x20 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBW), OperandCode::PMOVX_G_E_xmm), // 0x21 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBD), OperandCode::PMOVX_G_E_xmm), // 0x22 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBQ), OperandCode::PMOVX_G_E_xmm), // 0x23 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWD), OperandCode::PMOVX_G_E_xmm), // 0x24 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWQ), OperandCode::PMOVX_G_E_xmm), // 0x25 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXDQ), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x28 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULDQ), OperandCode::G_E_xmm), // 0x29 OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQQ), OperandCode::G_E_xmm), // 0x2a OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQA), OperandCode::G_M_xmm), // 0x2b OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x30 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBW), OperandCode::PMOVX_G_E_xmm), // 0x31 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBD), OperandCode::PMOVX_G_E_xmm), // 0x32 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBQ), OperandCode::PMOVX_G_E_xmm), // 0x33 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWD), OperandCode::PMOVX_G_E_xmm), // 0x34 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWQ), OperandCode::PMOVX_G_E_xmm), // 0x35 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXDQ), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x37 OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTQ), OperandCode::G_E_xmm), // 0x38 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSB), OperandCode::G_E_xmm), // 0x39 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSD), OperandCode::G_E_xmm), // 0x3a OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUW), OperandCode::G_E_xmm), // 0x3b OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUD), OperandCode::G_E_xmm), // 0x3c OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSB), OperandCode::G_E_xmm), // 0x3d OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSD), OperandCode::G_E_xmm), // 0x3e OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUW), OperandCode::G_E_xmm), // 0x3f OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUD), OperandCode::G_E_xmm), // 0x40 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLD), OperandCode::G_E_xmm), // 0x41 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHMINPOSUW), OperandCode::G_E_xmm), // 0x42 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::INVEPT), OperandCode::INV_Gv_M), // 0x81 OpcodeRecord::new(Interpretation::Instruction(Opcode::INVVPID), OperandCode::INV_Gv_M), // 0x82 OpcodeRecord::new(Interpretation::Instruction(Opcode::INVPCID), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xcf OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8MULB), OperandCode::G_E_xmm), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xdb OpcodeRecord::new(Interpretation::Instruction(Opcode::AESIMC), OperandCode::G_E_xmm), // 0xdc OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENC), OperandCode::G_E_xmm), // 0xdd OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENCLAST), OperandCode::G_E_xmm), // 0xde OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDEC), OperandCode::G_E_xmm), // 0xdf OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDECLAST), OperandCode::G_E_xmm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), // 0xf1 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf5 OpcodeRecord::new(Interpretation::Instruction(Opcode::WRUSS), OperandCode::Mdq_Gdq), // 0xf6 OpcodeRecord::new(Interpretation::Instruction(Opcode::ADCX), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf8 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIR64B), OperandCode::MOVDIR64B), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), ]; const TBL_ASDF2: [OpcodeRecord; 0x100] = [ // 0x00 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_mm), // 0x01 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_mm), // 0x02 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_mm), // 0x03 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_mm), // 0x04 OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_mm), // 0x05 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_mm), // 0x06 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_mm), // 0x07 OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_mm), // 0x08 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_mm), // 0x09 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_mm), // 0x0a OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_mm), // 0x0b OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x10 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x1c OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_mm), // 0x1d OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_mm), // 0x1e OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x20 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x30 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x40 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xc8 OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1NEXTE), OperandCode::G_E_xmm), // 0xc9 OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG1), OperandCode::G_E_xmm), // 0xca OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG2), OperandCode::G_E_xmm), // 0xcb OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256RNDS2), OperandCode::G_E_xmm), // 0xcc OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG1), OperandCode::G_E_xmm), // 0xcd OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG2), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), // 0xf1 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf6 OpcodeRecord::new(Interpretation::Instruction(Opcode::WRSS), OperandCode::Mdq_Gdq), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf9 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIRI), OperandCode::Md_Gd), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), ]; yaxpeax-x86-1.2.2/src/long_mode/uarch.rs000064400000000000000000000204531046102023000161360ustar 00000000000000pub mod amd { //! most information about instruction set extensions for microarchitectures here was sourced //! from //! [https://en.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit#Feature_overview](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/protected_mode/uarch/intel/index.html) //! and //! [https://en.wikipedia.org/wiki/Template:AMD_x86_CPU_features](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/protected_mode/uarch/intel/index.html). //! these mappings are best-effort but fairly unused, so a critical eye should be kept towards //! these decoders rejecting instructions they should not, or incorrectly accepting //! instructions. //! //! microarchitectures as defined here are with respect to flags reported by CPUID. notably, //! `Zen` does not report `FMA4` support by `CPUID`, but instructions in that extension //! reportedly function correctly (agner p217). //! //! [agner](https://www.agner.org/optimize/microarchitecture.pdf) //! as retrieved 2020 may 19, //! `sha256: 87ff152ae18c017dcbfb9f7ee6e88a9f971f6250fd15a70a3dd87c3546323bd5` use crate::long_mode::InstDecoder; /// `k8` was the first AMD microarchitecture to implement x86_64, launched in 2003. while later /// `k8`-based processors supported SSE3, these predefined decoders pick the lower end of /// support - SSE2 and no later. pub fn k8() -> InstDecoder { InstDecoder::minimal() } /// `k10` was the successor to `k8`, launched in 2007. `k10` cores extended SSE support through /// to SSE4.2a, as well as consistent `cmov` support, among other features. pub fn k10() -> InstDecoder { k8() .with_cmov() .with_cmpxchg16b() .with_svm() .with_abm() .with_lahfsahf() .with_sse3() .with_ssse3() .with_sse4() .with_sse4_2() .with_sse4a() } /// `Bulldozer` was the successor to `K10`, launched in 2011. `Bulldozer` cores include AVX /// support among other extensions, and are notable for including `AESNI`. pub fn bulldozer() -> InstDecoder { k10() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_avx() .with_fma4() .with_xop() } /// `Piledriver` was the successor to `Bulldozer`, launched in 2012. pub fn piledriver() -> InstDecoder { bulldozer() .with_tbm() .with_fma3() .with_fma4() } /// `Steamroller` was the successor to `Piledriver`, launched in 2014. unlike `Piledriver` /// cores, these cores do not support `TBM` or `FMA3`. pub fn steamroller() -> InstDecoder { bulldozer() } /// `Excavator` was the successor to `Steamroller`, launched in 2015. pub fn excavator() -> InstDecoder { steamroller() .with_movbe() .with_bmi2() .with_rdrand() .with_avx() .with_xop() .with_bmi2() .with_sha() .with_rdrand() .with_avx2() } /// `Zen` was the successor to `Excavator`, launched in 2017. `Zen` cores extend SIMD /// instructions to AVX2 and discarded FMA4, TBM, and XOP extensions. they also gained ADX, /// SHA, RDSEED, and other extensions. pub fn zen() -> InstDecoder { k10() .with_avx() .with_avx2() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_movbe() .with_bmi2() .with_rdrand() .with_adx() .with_sha() .with_rdseed() .with_fma3() // TODO: XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO? } } pub mod intel { //! sourced by walking wikipedia pages. seriously! this stuff is kinda hard to figure out! use crate::long_mode::InstDecoder; /// `Netburst` was the first Intel microarchitecture to implement x86_64, beginning with the /// `Prescott` family launched in 2004. while the wider `Netburst` family launched in 2000 /// with only SSE2, the first `x86_64`-supporting incarnation was `Prescott` which indeed /// included SSE3. pub fn netburst() -> InstDecoder { InstDecoder::minimal() .with_cmov() .with_cmpxchg16b() .with_sse3() } /// `Core` was the successor to `Netburst`, launched in 2006. it included up to SSE4, with /// processors using this architecture shipped under the names "Merom", "Conroe", and /// "Woodcrest", for mobile, desktop, and server processors respectively. not to be confused /// with the later `Nehalem` microarchitecture that introduced the `Core i*` product lines, /// `Core 2 *` processors used the `Core` architecture. pub fn core() -> InstDecoder { netburst() .with_ssse3() .with_sse4() } /// `Penryn` was the successor to `Core`, launched in early 2008. it added SSE4.1, along with /// virtualization extensions. pub fn penryn() -> InstDecoder { core() .with_sse4_1() } /// `Nehalem` was the successor to `Penryn`, launched in late 2008. not to be confused with the /// earlier `Core` microarchitecture, the `Core i*` products were based on `Nehalem` cores. /// `Nehalem` added SSE4.2 extensions, along with the `POPCNT` instruction. pub fn nehalem() -> InstDecoder { penryn() .with_sse4_2() .with_popcnt() } /// `Westmere` was the successor to `Nehalem`, launched in 2010. it added AES-NI and CLMUL /// extensions. pub fn westmere() -> InstDecoder { nehalem() .with_aesni() .with_pclmulqdq() } /// `Sandy Bridge` was the successor to `Westmere`, launched in 2011. it added AVX /// instructions. pub fn sandybridge() -> InstDecoder { westmere() .with_avx() } /// `Ivy Bridge` was the successor to `Sandy Bridge`, launched in 2012. it added F16C /// extensions for 16-bit floating point conversion, and the RDRAND instruction. pub fn ivybridge() -> InstDecoder { sandybridge() .with_f16c() .with_rdrand() } /// `Haswell` was the successor to `Ivy Bridge`, launched in 2013. it added several instruction /// set extensions: AVX2, BMI1, BMI2, ABM, and FMA3. pub fn haswell() -> InstDecoder { ivybridge() .with_bmi1() .with_bmi2() .with_abm() .with_fma3() .with_avx2() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores /// were shipped as `E7-48xx/E7-88xx v3` models of processors. pub fn haswell_ex() -> InstDecoder { haswell() .with_tsx() } /// `Broadwell` was the successor to `Haswell`, launched in late 2014. it added ADX, RDSEED, /// and PREFETCHW, as well as broadly rolling out TSX. TSX is enabled on this decoder because /// some chips of this microarchitecture rolled out with TSX, and lack of TSX seems to be /// reported as an errata (for example, the `Broadwell-Y` line of parts). pub fn broadwell() -> InstDecoder { haswell_ex() .with_adx() .with_rdseed() .with_prefetchw() } /// `Skylake` was the successor to `Broadwell`, launched in mid 2015. it added MPX and SGX /// extensions, as well as a mixed rollout of AVX512 in different subsets for different product /// lines. /// /// AVX512 is not enabled on this decoder by default because there doesn't seem to be a lowest /// common denominator: if you want a `Skylake` decoder with AVX512, something like the /// following: /// ``` /// yaxpeax_x86::long_mode::uarch::intel::skylake() /// .with_avx512_f() /// .with_avx512_dq(); /// ``` /// is likely your best option. pub fn skylake() -> InstDecoder { broadwell() .with_mpx() .with_sgx() } /// `Kaby Lake` was the successor to `Sky Lake`, launched in 2016. it adds no extensions to /// x86_64 implementation beyond `skylake`. pub fn kabylake() -> InstDecoder { skylake() } // ice lake is shipping so that should probably be included... } yaxpeax-x86-1.2.2/src/long_mode/vex.rs000064400000000000000000003712271046102023000156460ustar 00000000000000use yaxpeax_arch::Reader; use yaxpeax_arch::annotation::DescriptionSink; use crate::long_mode::Arch; use crate::long_mode::OperandSpec; use crate::long_mode::DecodeError; use crate::long_mode::FieldDescription; use crate::long_mode::RegSpec; use crate::long_mode::RegisterBank; use crate::long_mode::InnerDescription; use crate::long_mode::Instruction; use crate::long_mode::Opcode; use crate::long_mode::read_modrm; use crate::long_mode::read_E; use crate::long_mode::read_E_xmm; use crate::long_mode::read_E_ymm; use crate::long_mode::read_imm_unsigned; #[derive(Debug)] enum VEXOpcodeMap { Map0F, Map0F38, Map0F3A, } #[derive(Debug)] enum VEXOpcodePrefix { None, Prefix66, PrefixF3, PrefixF2, } #[allow(non_camel_case_types)] #[derive(Debug)] enum VEXOperandCode { Nothing, VPS_71, VPS_72, VPS_73, VMOVSS_10, VMOVSD_10, VMOVSD_11, VMOVSS_11, VMOVLPS_12, VMOVHPS_16, M_G_xmm, G_M_xmm, G_U_xmm, Gd_U_xmm, E_G_xmm_imm8, Ud_G_xmm_imm8, Ud_G_xyLmm, M_G_xyLmm, M_G_ymm, G_E_ymm, G_M_ymm, Gd_U_ymm, E_xmm_G_ymm_imm8, Ev_G_xmm_imm8, G_ExyL_V_xyLmm, G_E_xmm, G_E_xmm_imm8, G_E_ymm_imm8, G_xmm_E_xmm, G_xmm_E_ymm, G_ymm_E_xmm, G_ymm_M_xmm, G_ymm_E_ymm, G_V_ymm_E_xmm, M_V_G_xmm, M_V_G_ymm, G_V_xmm_Ed, G_V_xmm_Eq, G_V_E_xyLmm, G_E_xyLmm, E_G_xyLmm, G_E_xyLmm_imm8, G_V_E_xyLmm_imm8, G_V_E_xmm, G_V_E_xmm_imm8, G_V_E_xmm_xmm4, G_V_Ed_xmm, G_V_Eq_xmm, G_V_E_ymm, G_V_E_ymm_imm8, G_V_E_ymm_ymm4, G_V_xmm_Ev_imm8, G_V_M_xmm, G_V_M_ymm, G_ymm_V_ymm_E_xmm_imm8, Eq_G_xmm, Ed_G_xmm, G_xmm_Ed, G_xmm_Eq, G_E_V, G_V_E, G_E_Ib, VCVT_Gd_Ed_xmm, VCVT_Gd_Eq_xmm, VCVT_Gq_Eq_xmm, VCVT_Gq_Ed_xmm, BMI1_F3, MXCSR, } #[inline(always)] pub(crate) fn three_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8; let vex_byte_one = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let vex_byte_two = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let p = vex_byte_two & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; sink.record( vex_start + 8, vex_start + 9, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); let m = vex_byte_one & 0b11111; sink.record( vex_start + 0, vex_start + 4, InnerDescription::Misc(match m { 0b00001 => "vex.mmmmm indicates opcode escape of 0f", 0b00010 => "vex.mmmmm indicates opcode escape of 0f38", 0b00011 => "vex.mmmmm indicates opcode escape of 0f3a", _ => "vex.mmmmm indicates illegal opcode escape and is invalid", }) .with_id(vex_start) ); let m = match m { 0b00001 => VEXOpcodeMap::Map0F, 0b00010 => VEXOpcodeMap::Map0F38, 0b00011 => VEXOpcodeMap::Map0F3A, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte_two >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 11, vex_start + 14, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte_one & 0b10000000 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 6, vex_start + 6, InnerDescription::Misc(if vex_byte_one & 0b01000000 == 0 { "vex.x extends extends index reg (if used) by 0b1000" } else { "vex.x does not alter index reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 5, vex_start + 5, InnerDescription::Misc(if vex_byte_one & 0b00100000 == 0 { "vex.b extends extends base reg (if used) by 0b1000" } else { "vex.b does not alter base reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 10, vex_start + 10, InnerDescription::Misc(if vex_byte_two & 0b100 == 0 { "vex.l selects 128-bit vector sizes" } else { "vex.l selects 256-bit vector sizes" }) .with_id(vex_start + 1) ); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Misc(if vex_byte_two & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c4(vex_byte_one, vex_byte_two); sink.record( vex_start + 23, vex_start + 23, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 23) ); read_vex_instruction(m, words, instruction, p, sink) } #[inline(always)] pub(crate) fn two_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8; let vex_byte = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let p = vex_byte & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 0, vex_start + 1, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); sink.record( vex_start + 3, vex_start + 6, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 2, vex_start + 2, InnerDescription::Misc(if vex_byte & 0b100 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c5(vex_byte); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 15) ); read_vex_instruction(VEXOpcodeMap::Map0F, words, instruction, p, sink) } #[inline(always)] fn read_vex_operands< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: VEXOperandCode, sink: &mut S) -> Result<(), DecodeError> { // println!("operand code: {:?}", operand_code); match operand_code { VEXOperandCode::VPS_71 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let rrr = (modrm >> 3) & 0b111; if rrr == 0b001 && L { return Err(DecodeError::InvalidOpcode); } instruction.opcode = match rrr { 0b001 => Opcode::VPSLLW, 0b010 => Opcode::VPSRLW, 0b100 => Opcode::VPSRAW, 0b110 => Opcode::VPSLLW, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[0] = RegSpec::from_parts(modrm & 7, instruction.prefixes.vex_unchecked().r(), bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_72 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLD; } 0b100 => { instruction.opcode = Opcode::VPSRAD; } 0b110 => { instruction.opcode = Opcode::VPSLLD; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, instruction.prefixes.vex_unchecked().r(), bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_73 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLQ; } 0b011 => { instruction.opcode = Opcode::VPSRLDQ; } 0b110 => { instruction.opcode = Opcode::VPSLLQ; } 0b111 => { instruction.opcode = Opcode::VPSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, instruction.prefixes.vex_unchecked().r(), bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVSS_10 | VEXOperandCode::VMOVSD_10 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegMMM; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[1] = other; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVSS_11 | VEXOperandCode::VMOVSD_11 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[2] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegVex; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[0] = other; instruction.operands[1] = instruction.operands[2]; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVLPS_12 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVHLPS } else { instruction.mem_size = 8; Opcode::VMOVLPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVHPS_16 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVLHPS } else { instruction.mem_size = 8; Opcode::VMOVHPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::Nothing => { if instruction.opcode == Opcode::VZEROUPPER || instruction.opcode == Opcode::VZEROALL { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } } instruction.operand_count = 0; Ok(()) }, VEXOperandCode::Ev_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPEXTRB => { instruction.mem_size = 1; } Opcode::VPEXTRW => { instruction.mem_size = 2; } Opcode::VEXTRACTPS | Opcode::VPEXTRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } else if instruction.opcode == Opcode::VPEXTRQ { instruction.regs[1].bank = RegisterBank::Q; } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(words, 1)?; Ok(()) }, VEXOperandCode::G_xmm_Eq => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::Q, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_Ed => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::Eq_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::Q, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ed_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Ed_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Eq_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gq_Ed_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Q); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gq_Eq_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Q); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_xmm_G_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::Gd_U_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Gd_U_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::D); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_xmm | op @ VEXOperandCode::G_U_xmm | op @ VEXOperandCode::G_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_U_xmm, 0xc0) => { /* this is the only accepted operand */ } (VEXOperandCode::G_U_xmm, _) | (VEXOperandCode::G_M_xmm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_xmm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VMOVDDUP, Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVQ].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_ymm_M_xmm | op @ VEXOperandCode::G_ymm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { if let VEXOperandCode::G_ymm_M_xmm = op { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VBROADCASTSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_ymm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::M_G_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::M_G_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::M_G_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_ymm | op @ VEXOperandCode::G_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_M_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_V_E_ymm | op @ VEXOperandCode::G_V_M_ymm => { let modrm = read_modrm(words)?; if let VEXOperandCode::G_V_M_ymm = op { if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_ymm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_M_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm_imm8 => { // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_E_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } if instruction.opcode == Opcode::VMOVDDUP && !L { instruction.mem_size = 8; } else if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVQ].contains(&instruction.opcode) { instruction.mem_size = 8; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm => { let modrm = read_modrm(words)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Ed_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Eq_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ed => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Eq => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::Q, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_ExyL_V_xyLmm => { #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L && instruction.opcode != Opcode::VGATHERQPS && instruction.opcode != Opcode::VPGATHERQD { RegisterBank::Y } else { RegisterBank::X }; let index_bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if instruction.opcode == Opcode::VPGATHERDQ { instruction.regs[2].bank = RegisterBank::X; } else { instruction.regs[2].bank = index_bank; } instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VPGATHERDD || instruction.opcode == Opcode::VPGATHERQD || instruction.opcode == Opcode::VGATHERDPS || instruction.opcode == Opcode::VGATHERQPS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E => { let modrm = read_modrm(words)?; let bank = if instruction.prefixes.vex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_V => { let modrm = read_modrm(words)?; let bank = if instruction.prefixes.vex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_Ib => { let modrm = read_modrm(words)?; let bank = if instruction.prefixes.vex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::BMI1_F3 => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 1 => { Opcode::BLSR } 2 => { Opcode::BLSMSK } 3 => { Opcode::BLSI } _ => { return Err(DecodeError::InvalidOpcode); } }; let bank = if instruction.prefixes.vex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.regs[3].bank = bank; Ok(()) } VEXOperandCode::MXCSR => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 2 => { Opcode::VLDMXCSR } 3 => { Opcode::VSTMXCSR } _ => { return Err(DecodeError::InvalidOpcode); } }; let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operands[0] = mem_oper; instruction.operand_count = 1; Ok(()) } VEXOperandCode::G_E_xyLmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); if L { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, instruction.prefixes.vex_unchecked().r(), RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_ymm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_E_xmm_xmm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_ymm_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ev_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,instruction.prefixes.vex_unchecked().x(), RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; // TODO: but the memory access is word-sized let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPINSRB => { instruction.mem_size = 1; } Opcode::VPINSRW => { instruction.mem_size = 2; } Opcode::VINSERTPS | Opcode::VPINSRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } else if instruction.opcode == Opcode::VPINSRQ { instruction.regs[1].bank = RegisterBank::Q; } instruction.operand_count = 4; Ok(()) } } } #[inline(never)] fn read_vex_instruction< T: Reader<::Address, ::Word>, S: DescriptionSink, >(opcode_map: VEXOpcodeMap, words: &mut T, instruction: &mut Instruction, p: VEXOpcodePrefix, sink: &mut S) -> Result<(), DecodeError> { let opcode_start = words.offset() as u32 * 8; let opc = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); // println!("reading vex instruction from opcode prefix {:?}, L: {}, opc: {:#x}, map:{:?}", p, L, opc, opcode_map); // println!("w? {}", instruction.prefixes.vex_unchecked().w()); // several combinations simply have no instructions. check for those first. let (opcode, operand_code) = match opcode_map { VEXOpcodeMap::Map0F => { match p { VEXOpcodePrefix::None => { match opc { 0x10 => (Opcode::VMOVUPS, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPS, VEXOperandCode::E_G_xyLmm), 0x12 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVLPS_12 }), 0x13 => (Opcode::VMOVLPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPS, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPS, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVHPS_16 }), 0x17 => (Opcode::VMOVHPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPS, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPS, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPS, if L { VEXOperandCode::M_G_ymm } else { VEXOperandCode::M_G_xmm }), 0x2e => (Opcode::VUCOMISS, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISS, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPS, VEXOperandCode::Ud_G_xyLmm), 0x51 => (Opcode::VSQRTPS, VEXOperandCode::G_E_xyLmm), 0x52 => (Opcode::VRSQRTPS, VEXOperandCode::G_E_xyLmm), 0x53 => (Opcode::VRCPPS, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPS, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPS, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPS, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPS, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPS, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPS, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPS2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x5B => (Opcode::VCVTDQ2PS, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPS, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPS, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPS, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPS, VEXOperandCode::G_V_E_xyLmm), 0x77 => if L { (Opcode::VZEROALL, VEXOperandCode::Nothing) } else { (Opcode::VZEROUPPER, VEXOperandCode::Nothing) }, 0xAE => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::MXCSR }), 0xC2 => (Opcode::VCMPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC6 => (Opcode::VSHUFPS, VEXOperandCode::G_V_E_xyLmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } }, VEXOpcodePrefix::Prefix66 => { match opc { // 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), // 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x12 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x13 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPD, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPD, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x17 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPD, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPD, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPD, VEXOperandCode::M_G_xyLmm), 0x2e => (Opcode::VUCOMISD, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISD, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPD, if L { VEXOperandCode::Gd_U_ymm } else { VEXOperandCode::Gd_U_xmm }), 0x51 => (Opcode::VSQRTPD, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPD, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPD, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPD, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPD, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPD, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPD, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPD2PS, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5B => (Opcode::VCVTPS2DQ, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPD, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPD, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPD, VEXOperandCode::G_V_E_xyLmm), 0x60 => (Opcode::VPUNPCKLBW, VEXOperandCode::G_V_E_xyLmm), 0x61 => (Opcode::VPUNPCKLWD, VEXOperandCode::G_V_E_xyLmm), 0x62 => (Opcode::VPUNPCKLDQ, VEXOperandCode::G_V_E_xyLmm), 0x63 => (Opcode::VPACKSSWB, VEXOperandCode::G_V_E_xyLmm), 0x64 => (Opcode::VPCMPGTB, VEXOperandCode::G_V_E_xyLmm), 0x65 => (Opcode::VPCMPGTW, VEXOperandCode::G_V_E_xyLmm), 0x66 => (Opcode::VPCMPGTD, VEXOperandCode::G_V_E_xyLmm), 0x67 => (Opcode::VPACKUSWB, VEXOperandCode::G_V_E_xyLmm), 0x68 => (Opcode::VPUNPCKHBW, VEXOperandCode::G_V_E_xyLmm), 0x69 => (Opcode::VPUNPCKHWD, VEXOperandCode::G_V_E_xyLmm), 0x6A => (Opcode::VPUNPCKHDQ, VEXOperandCode::G_V_E_xyLmm), 0x6B => (Opcode::VPACKSSDW, VEXOperandCode::G_V_E_xyLmm), 0x6C => (Opcode::VPUNPCKLQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6D => (Opcode::VPUNPCKHQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6E => if instruction.prefixes.vex_unchecked().w() { (Opcode::VMOVQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_xmm_Eq }) } else { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_xmm_Ed }) }, 0x6F => (Opcode::VMOVDQA, VEXOperandCode::G_E_xyLmm), 0x70 => (Opcode::VPSHUFD, VEXOperandCode::G_E_xyLmm_imm8), 0x71 => (Opcode::Invalid, VEXOperandCode::VPS_71), 0x72 => (Opcode::Invalid, VEXOperandCode::VPS_72), 0x73 => (Opcode::Invalid, VEXOperandCode::VPS_73), 0x74 => (Opcode::VPCMPEQB, VEXOperandCode::G_V_E_xyLmm), 0x75 => (Opcode::VPCMPEQW, VEXOperandCode::G_V_E_xyLmm), 0x76 => (Opcode::VPCMPEQD, VEXOperandCode::G_V_E_xyLmm), 0x7C => (Opcode::VHADDPD, VEXOperandCode::G_V_E_xyLmm), 0x7D => (Opcode::VHSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x7E => if instruction.prefixes.vex_unchecked().w() { (Opcode::VMOVQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Eq_G_xmm }) } else { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ed_G_xmm }) } 0x7F => (Opcode::VMOVDQA, VEXOperandCode::E_G_xyLmm), 0xC2 => (Opcode::VCMPPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC4 => (Opcode::VPINSRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0xC5 => (Opcode::VPEXTRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ud_G_xmm_imm8 }), 0xC6 => (Opcode::VSHUFPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xD0 => (Opcode::VADDSUBPD, VEXOperandCode::G_V_E_xyLmm), 0xD1 => (Opcode::VPSRLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD2 => (Opcode::VPSRLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD3 => (Opcode::VPSRLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD4 => (Opcode::VPADDQ, VEXOperandCode::G_V_E_xyLmm), 0xD5 => (Opcode::VPMULLW, VEXOperandCode::G_V_E_xyLmm), 0xD6 => (Opcode::VMOVQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xD7 => (Opcode::VPMOVMSKB, VEXOperandCode::Ud_G_xyLmm), 0xD8 => (Opcode::VPSUBUSB, VEXOperandCode::G_V_E_xyLmm), 0xD9 => (Opcode::VPSUBUSW, VEXOperandCode::G_V_E_xyLmm), 0xDA => (Opcode::VPMINUB, VEXOperandCode::G_V_E_xyLmm), 0xDB => (Opcode::VPAND, VEXOperandCode::G_V_E_xyLmm), 0xDC => (Opcode::VPADDUSB, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VPADDUSW, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VPMAXUB, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VPANDN, VEXOperandCode::G_V_E_xyLmm), 0xE0 => (Opcode::VPAVGB, VEXOperandCode::G_V_E_xyLmm), 0xE1 => (Opcode::VPSRAW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE2 => (Opcode::VPSRAD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE3 => (Opcode::VPAVGW, VEXOperandCode::G_V_E_xyLmm), 0xE4 => (Opcode::VPMULHUW, VEXOperandCode::G_V_E_xyLmm), 0xE5 => (Opcode::VPMULHW, VEXOperandCode::G_V_E_xyLmm), 0xE6 => (Opcode::VCVTTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_E_xmm }), 0xE7 => (Opcode::VMOVNTDQ, VEXOperandCode::M_G_xyLmm), 0xE8 => (Opcode::VPSUBSB, VEXOperandCode::G_V_E_xyLmm), 0xE9 => (Opcode::VPSUBSW, VEXOperandCode::G_V_E_xyLmm), 0xEA => (Opcode::VPMINSW, VEXOperandCode::G_V_E_xyLmm), 0xEB => (Opcode::VPOR, VEXOperandCode::G_V_E_xyLmm), 0xEC => (Opcode::VPADDSB, VEXOperandCode::G_V_E_xyLmm), 0xED => (Opcode::VPADDSW, VEXOperandCode::G_V_E_xyLmm), 0xEE => (Opcode::VPMAXSW, VEXOperandCode::G_V_E_xyLmm), 0xEF => (Opcode::VPXOR, VEXOperandCode::G_V_E_xyLmm), 0xF1 => (Opcode::VPSLLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF2 => (Opcode::VPSLLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF3 => (Opcode::VPSLLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF4 => (Opcode::VPMULUDQ, VEXOperandCode::G_V_E_xyLmm), 0xF5 => (Opcode::VPMADDWD, VEXOperandCode::G_V_E_xyLmm), 0xF6 => (Opcode::VPSADBW, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::VMASKMOVDQU, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_U_xmm }), 0xF8 => (Opcode::VPSUBB, VEXOperandCode::G_V_E_xyLmm), 0xF9 => (Opcode::VPSUBW, VEXOperandCode::G_V_E_xyLmm), 0xFA => (Opcode::VPSUBD, VEXOperandCode::G_V_E_xyLmm), 0xFB => (Opcode::VPSUBQ, VEXOperandCode::G_V_E_xyLmm), 0xFC => (Opcode::VPADDB, VEXOperandCode::G_V_E_xyLmm), 0xFD => (Opcode::VPADDW, VEXOperandCode::G_V_E_xyLmm), 0xFE => (Opcode::VPADDD, VEXOperandCode::G_V_E_xyLmm), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF2 => { match opc { 0x10 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_10), 0x11 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_11), 0x12 => (Opcode::VMOVDDUP, VEXOperandCode::G_E_xyLmm), 0x2a => (Opcode::VCVTSI2SD, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::G_V_xmm_Eq // 64-bit last operand } else { VEXOperandCode::G_V_xmm_Ed // 32-bit last operand }), 0x2c => (Opcode::VCVTTSD2SI, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::VCVT_Gq_Eq_xmm // 64-bit } else { VEXOperandCode::VCVT_Gd_Eq_xmm // 32-bit }), 0x2d => (Opcode::VCVTSD2SI, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::VCVT_Gq_Eq_xmm // 64-bit } else { VEXOperandCode::VCVT_Gd_Eq_xmm // 32-bit }), 0x51 => (Opcode::VSQRTSD, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSD, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSD, VEXOperandCode::G_V_E_xmm), 0x5a => (Opcode::VCVTSD2SS, VEXOperandCode::G_V_Eq_xmm), 0x5c => (Opcode::VSUBSD, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSD, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSD, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSD, VEXOperandCode::G_V_E_xmm), 0x70 => (Opcode::VPSHUFLW, VEXOperandCode::G_E_xyLmm_imm8), 0x7c => (Opcode::VHADDPS, VEXOperandCode::G_V_E_xyLmm), 0x7d => (Opcode::VHSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xc2 => (Opcode::VCMPSD, VEXOperandCode::G_V_E_xmm_imm8), 0xd0 => (Opcode::VADDSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xe6 => (Opcode::VCVTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0xf0 => (Opcode::VLDDQU, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF3 => { match opc { 0x10 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_10), 0x11 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_11), 0x12 => (Opcode::VMOVSLDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x16 => (Opcode::VMOVSHDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x2a => (Opcode::VCVTSI2SS, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::G_V_xmm_Eq } else { VEXOperandCode::G_V_xmm_Ed }), 0x2c => (Opcode::VCVTTSS2SI, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::VCVT_Gq_Ed_xmm } else { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x2d => (Opcode::VCVTSS2SI, if instruction.prefixes.vex_unchecked().w() { VEXOperandCode::VCVT_Gq_Ed_xmm } else { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x51 => (Opcode::VSQRTSS, VEXOperandCode::G_V_E_xmm), 0x52 => (Opcode::VRSQRTSS, VEXOperandCode::G_V_E_xmm), 0x53 => (Opcode::VRCPSS, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSS, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSS, VEXOperandCode::G_V_E_xmm), 0x5a => (Opcode::VCVTSS2SD, VEXOperandCode::G_V_Ed_xmm), 0x5b => (Opcode::VCVTTPS2DQ, if L { VEXOperandCode::G_ymm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5c => (Opcode::VSUBSS, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSS, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSS, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSS, VEXOperandCode::G_V_E_xmm), 0x6f => (Opcode::VMOVDQU, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x70 => (Opcode::VPSHUFHW, VEXOperandCode::G_E_xyLmm_imm8), 0x7e => (Opcode::VMOVQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x7f => (Opcode::VMOVDQU, VEXOperandCode::E_G_xyLmm), 0xc2 => (Opcode::VCMPSS, VEXOperandCode::G_V_E_xmm_imm8), 0xe6 => (Opcode::VCVTDQ2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_xmm_E_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } } } VEXOpcodeMap::Map0F38 => { // TODO: verify rejecting invalid W bit if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPSHUFB, VEXOperandCode::G_V_E_xyLmm), 0x01 => (Opcode::VPHADDW, VEXOperandCode::G_V_E_xyLmm), 0x02 => (Opcode::VPHADDD, VEXOperandCode::G_V_E_xyLmm), 0x03 => (Opcode::VPHADDSW, VEXOperandCode::G_V_E_xyLmm), 0x04 => (Opcode::VPMADDUBSW, VEXOperandCode::G_V_E_xyLmm), 0x05 => (Opcode::VPHSUBW, VEXOperandCode::G_V_E_xyLmm), 0x06 => (Opcode::VPHSUBD, VEXOperandCode::G_V_E_xyLmm), 0x07 => (Opcode::VPHSUBSW, VEXOperandCode::G_V_E_xyLmm), 0x08 => (Opcode::VPSIGNB, VEXOperandCode::G_V_E_xyLmm), 0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm), 0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm), 0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm), 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm), 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm), 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm), 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm), 0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm), 0x16 => (Opcode::VPERMPS, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x17 => (Opcode::VPTEST, VEXOperandCode::G_E_xyLmm), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSS, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) } 0x1A => (Opcode::VBROADCASTF128, if L { VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x1C => (Opcode::VPABSB, VEXOperandCode::G_E_xyLmm), 0x1D => (Opcode::VPABSW, VEXOperandCode::G_E_xyLmm), 0x1E => (Opcode::VPABSD, VEXOperandCode::G_E_xyLmm), 0x20 => (Opcode::VPMOVSXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x21 => (Opcode::VPMOVSXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x22 => (Opcode::VPMOVSXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x23 => (Opcode::VPMOVSXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x24 => (Opcode::VPMOVSXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x25 => (Opcode::VPMOVSXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x28 => (Opcode::VPMULDQ, VEXOperandCode::G_V_E_xyLmm), 0x29 => (Opcode::VPCMPEQQ, VEXOperandCode::G_V_E_xyLmm), 0x2A => (Opcode::VMOVNTDQA, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), 0x2B => (Opcode::VPACKUSDW, VEXOperandCode::G_V_E_xyLmm), 0x2C => (Opcode::VMASKMOVPS, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2D => (Opcode::VMASKMOVPD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2E => (Opcode::VMASKMOVPS, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x2F => (Opcode::VMASKMOVPD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x30 => (Opcode::VPMOVZXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x31 => (Opcode::VPMOVZXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x32 => (Opcode::VPMOVZXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x33 => (Opcode::VPMOVZXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x34 => (Opcode::VPMOVZXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x35 => (Opcode::VPMOVZXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x36 => (Opcode::VPERMD, if L { VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x37 => (Opcode::VPCMPGTQ, VEXOperandCode::G_V_E_xyLmm), 0x38 => (Opcode::VPMINSB, VEXOperandCode::G_V_E_xyLmm), 0x39 => (Opcode::VPMINSD, VEXOperandCode::G_V_E_xyLmm), 0x3A => (Opcode::VPMINUW, VEXOperandCode::G_V_E_xyLmm), 0x3B => (Opcode::VPMINUD, VEXOperandCode::G_V_E_xyLmm), 0x3C => (Opcode::VPMAXSB, VEXOperandCode::G_V_E_xyLmm), 0x3D => (Opcode::VPMAXSD, VEXOperandCode::G_V_E_xyLmm), 0x3E => (Opcode::VPMAXUW, VEXOperandCode::G_V_E_xyLmm), 0x3F => (Opcode::VPMAXUD, VEXOperandCode::G_V_E_xyLmm), 0x40 => (Opcode::VPMULLD, VEXOperandCode::G_V_E_xyLmm), 0x41 => (Opcode::VPHMINPOSUW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x45 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSRLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSRLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x46 => (Opcode::VPSRAVD, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_xmm }), 0x47 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSLLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSLLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x58 => (Opcode::VPBROADCASTD, VEXOperandCode::G_E_xyLmm), 0x59 => (Opcode::VPBROADCASTQ, VEXOperandCode::G_E_xyLmm), 0x5A => (Opcode::VBROADCASTI128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x78 => (Opcode::VPBROADCASTB, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x79 => (Opcode::VPBROADCASTW, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x8C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } }, 0x8E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } }, 0x90 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERDQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERDD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x91 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERQQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERQD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x92 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERDPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERDPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x93 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERQPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERQPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x96 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x97 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x98 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x99 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9A => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9B => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9D => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9F => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xA6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xB6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xDB => (Opcode::VAESIMC, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xDC => (Opcode::VAESENC, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VAESENCLAST, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VAESDEC, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VAESDECLAST, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::SHLX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF5 => (Opcode::PDEP, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF6 => (Opcode::MULX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SHRX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF3 = p { match opc { 0xF5 => (Opcode::PEXT, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SARX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match opc { 0xF2 => (Opcode::ANDN, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF3 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::BMI1_F3 }), 0xF5 => (Opcode::BZHI, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), 0xF7 => (Opcode::BEXTR, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } } VEXOpcodeMap::Map0F3A => { if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPERMQ, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x01 => (Opcode::VPERMPD, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x02 => (Opcode::VPBLENDD, if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xyLmm_imm8 }), 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8), 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8), 0x06 => (Opcode::VPERM2F128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x08 => (Opcode::VROUNDPS, VEXOperandCode::G_E_xyLmm_imm8), 0x09 => (Opcode::VROUNDPD, VEXOperandCode::G_E_xyLmm_imm8), 0x0A => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), 0x0B => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x0C => (Opcode::VBLENDPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0D => (Opcode::VBLENDPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0E => (Opcode::VPBLENDW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0F => (Opcode::VPALIGNR, VEXOperandCode::G_V_E_xyLmm_imm8), 0x14 => (Opcode::VPEXTRB, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x15 => (Opcode::VPEXTRW, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x16 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPEXTRQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }) } else { (Opcode::VPEXTRD, if L { return Err(DecodeError::InvalidOpcode); } else { // varies on W VEXOperandCode::Ev_G_xmm_imm8 }) }, 0x17 => (Opcode::VEXTRACTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VINSERTF128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VEXTRACTF128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x1D => (Opcode::VCVTPS2PH, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { VEXOperandCode::E_G_xmm_imm8 }), 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0x21 => (Opcode::VINSERTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x22 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPINSRQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }) } else { (Opcode::VPINSRD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }) }, 0x38 => (Opcode::VINSERTI128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x39 => (Opcode::VEXTRACTI128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x40 => (Opcode::VDPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x41 => (Opcode::VDPPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x42 => (Opcode::VMPSADBW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x44 => (Opcode::VPCLMULQDQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x46 => (Opcode::VPERM2I128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x4A => (Opcode::VBLENDVPS, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4B => (Opcode::VBLENDVPD, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4C => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VPBLENDVB, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }) }, 0x60 => (Opcode::VPCMPESTRM, VEXOperandCode::G_E_xmm_imm8), 0x61 => (Opcode::VPCMPESTRI, VEXOperandCode::G_E_xmm_imm8), 0x62 => (Opcode::VPCMPISTRM, VEXOperandCode::G_E_xmm_imm8), 0x63 => (Opcode::VPCMPISTRI, VEXOperandCode::G_E_xmm_imm8), 0xDF => (Opcode::VAESKEYGENASSIST, VEXOperandCode::G_E_xmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF0 => (Opcode::RORX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_Ib }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { // the only VEX* 0f3a instructions have an implied 66 prefix. return Err(DecodeError::InvalidOpcode); } } }; instruction.opcode = opcode; sink.record( opcode_start, opcode_start + 7, InnerDescription::Opcode(instruction.opcode) .with_id(opcode_start) ); sink.record( opcode_start + 7, opcode_start + 7, InnerDescription::Boundary("vex opcode ends/operands begin") .with_id(opcode_start + 7) ); read_vex_operands(words, instruction, operand_code, sink) } yaxpeax-x86-1.2.2/src/protected_mode/display.rs000064400000000000000000003212051046102023000175320ustar 00000000000000use core::fmt; use crate::safer_unchecked::GetSaferUnchecked as _; use yaxpeax_arch::{Colorize, ShowContextual, NoColors, YaxColors}; use yaxpeax_arch::display::*; use crate::MEM_SIZE_STRINGS; use crate::protected_mode::{RegSpec, Opcode, Operand, MergeMode, InstDecoder, Instruction, Segment, PrefixVex, OperandSpec}; impl fmt::Display for InstDecoder { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self == &InstDecoder::default() { return write!(f, ""); } else if self == &InstDecoder::minimal() { return write!(f, ""); } if self.sse3() { write!(f, "sse3 ")? } if self.ssse3() { write!(f, "ssse3 ")? } if self.monitor() { write!(f, "monitor ")? } if self.vmx() { write!(f, "vmx ")? } if self.fma3() { write!(f, "fma3 ")? } if self.cmpxchg16b() { write!(f, "cmpxchg16b ")? } if self.sse4_1() { write!(f, "sse4_1 ")? } if self.sse4_2() { write!(f, "sse4_2 ")? } if self.movbe() { write!(f, "movbe ")? } if self.popcnt() { write!(f, "popcnt ")? } if self.aesni() { write!(f, "aesni ")? } if self.xsave() { write!(f, "xsave ")? } if self.rdrand() { write!(f, "rdrand ")? } if self.sgx() { write!(f, "sgx ")? } if self.bmi1() { write!(f, "bmi1 ")? } if self.avx2() { write!(f, "avx2 ")? } if self.bmi2() { write!(f, "bmi2 ")? } if self.invpcid() { write!(f, "invpcid ")? } if self.mpx() { write!(f, "mpx ")? } if self.avx512_f() { write!(f, "avx512_f ")? } if self.avx512_dq() { write!(f, "avx512_dq ")? } if self.rdseed() { write!(f, "rdseed ")? } if self.adx() { write!(f, "adx ")? } if self.avx512_fma() { write!(f, "avx512_fma ")? } if self.pcommit() { write!(f, "pcommit ")? } if self.clflushopt() { write!(f, "clflushopt ")? } if self.clwb() { write!(f, "clwb ")? } if self.avx512_pf() { write!(f, "avx512_pf ")? } if self.avx512_er() { write!(f, "avx512_er ")? } if self.avx512_cd() { write!(f, "avx512_cd ")? } if self.sha() { write!(f, "sha ")? } if self.avx512_bw() { write!(f, "avx512_bw ")? } if self.avx512_vl() { write!(f, "avx512_vl ")? } if self.prefetchwt1() { write!(f, "prefetchwt1 ")? } if self.avx512_vbmi() { write!(f, "avx512_vbmi ")? } if self.avx512_vbmi2() { write!(f, "avx512_vbmi2 ")? } if self.gfni() { write!(f, "gfni ")? } if self.vaes() { write!(f, "vaes ")? } if self.pclmulqdq() { write!(f, "pclmulqdq ")? } if self.avx_vnni() { write!(f, "avx_vnni ")? } if self.avx512_bitalg() { write!(f, "avx512_bitalg ")? } if self.avx512_vpopcntdq() { write!(f, "avx512_vpopcntdq ")? } if self.avx512_4vnniw() { write!(f, "avx512_4vnniw ")? } if self.avx512_4fmaps() { write!(f, "avx512_4fmaps ")? } if self.cx8() { write!(f, "cx8 ")? } if self.syscall() { write!(f, "syscall ")? } if self.rdtscp() { write!(f, "rdtscp ")? } if self.abm() { write!(f, "abm ")? } if self.sse4a() { write!(f, "sse4a ")? } if self._3dnowprefetch() { write!(f, "_3dnowprefetch ")? } if self.xop() { write!(f, "xop ")? } if self.skinit() { write!(f, "skinit ")? } if self.tbm() { write!(f, "tbm ")? } if self.intel_quirks() { write!(f, "intel_quirks ")? } if self.amd_quirks() { write!(f, "amd_quirks ")? } if self.avx() { write!(f, "avx ")? } Ok(()) } } impl fmt::Display for PrefixVex { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self.present() { write!(f, "vex:{}{}{}{}", if self.w() { "w" } else { "-" }, if self.r() { "r" } else { "-" }, if self.x() { "x" } else { "-" }, if self.b() { "b" } else { "-" }, ) } else { write!(f, "vex:none") } } } impl fmt::Display for Segment { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { Segment::CS => write!(f, "cs"), Segment::DS => write!(f, "ds"), Segment::ES => write!(f, "es"), Segment::FS => write!(f, "fs"), Segment::GS => write!(f, "gs"), Segment::SS => write!(f, "ss"), } } } // register names are grouped by indices scaled by 16. // xmm, ymm, zmm all get two indices. const REG_NAMES: &[&'static str] = &[ "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", "es", "cs", "ss", "ds", "fs", "gs", "", "", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "st(0)", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", "eip", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "eflags", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", ]; pub(crate) fn regspec_label(spec: &RegSpec) -> &'static str { unsafe { REG_NAMES.get_kinda_unchecked((spec.num as u16 + ((spec.bank as u16) << 3)) as usize) } } impl fmt::Display for RegSpec { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(regspec_label(self)) } } impl fmt::Display for Operand { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } impl Colorize for Operand { fn colorize(&self, colors: &Y, f: &mut T) -> fmt::Result { match self { &Operand::ImmediateU8(imm) => { write!(f, "{}", colors.number(u8_hex(imm))) } &Operand::ImmediateI8(imm) => { write!(f, "{}", colors.number(signed_i8_hex(imm))) }, &Operand::ImmediateU16(imm) => { write!(f, "{}", colors.number(u16_hex(imm))) } &Operand::ImmediateI16(imm) => { write!(f, "{}", colors.number(signed_i16_hex(imm))) }, &Operand::ImmediateU32(imm) => { write!(f, "{}", colors.number(u32_hex(imm))) } &Operand::ImmediateI32(imm) => { write!(f, "{}", colors.number(signed_i32_hex(imm))) }, &Operand::AbsoluteFarAddress { segment, address } => { write!(f, "{}:{}", colors.number(u16_hex(segment as u16)), colors.number(u32_hex(address as u32)), ) }, &Operand::Register(ref spec) => { f.write_str(regspec_label(spec)) } &Operand::RegisterMaskMerge(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } Ok(()) } &Operand::RegisterMaskMergeSae(ref spec, ref mask, merge_mode, sae_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str(sae_mode.label())?; Ok(()) } &Operand::RegisterMaskMergeSaeNoround(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str("{sae}")?; Ok(()) } &Operand::DisplacementU16(imm) => { write!(f, "[{}]", colors.address(u16_hex(imm))) } &Operand::DisplacementU32(imm) => { write!(f, "[{}]", colors.address(u32_hex(imm))) } &Operand::RegDisp(ref spec, disp) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDeref(ref spec) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]") }, &Operand::RegScale(ref spec, scale) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) ) }, &Operand::RegScaleDisp(ref spec, scale, disp) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBase(ref base, ref index) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]") } &Operand::RegIndexBaseDisp(ref base, ref index, disp) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBaseScale(ref base, ref index, scale) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) ) } &Operand::RegIndexBaseScaleDisp(ref base, ref index, scale, disp) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDispMasked(ref spec, disp, ref mask_reg) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegDerefMasked(ref spec, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleMasked(ref spec, scale, ref mask_reg) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleDispMasked(ref spec, scale, disp, ref mask_reg) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseMasked(ref base, ref index, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseDispMasked(ref base, ref index, disp, ref mask_reg) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseScaleMasked(ref base, ref index, scale, ref mask_reg) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseScaleDispMasked(ref base, ref index, scale, disp, ref mask_reg) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::Nothing => { Ok(()) }, } } } impl fmt::Display for Opcode { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.name()) } } const MNEMONICS: &[&'static str] = &[ "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp", "rol", "ror", "rcl", "rcr", "shl", "shr", "sal", "sar", "btc", "btr", "bts", "cmpxchg", "cmpxchg8b", "cmpxchg16b", "dec", "inc", "neg", "not", "xadd", "xchg", "invalid", "bt", "bsf", "bsr", "tzcnt", "movss", "addss", "subss", "mulss", "divss", "minss", "maxss", "sqrtss", "movsd", "sqrtsd", "addsd", "subsd", "mulsd", "divsd", "minsd", "maxsd", "movsldup", "movshdup", "movddup", "haddps", "hsubps", "addsubpd", "addsubps", "cvtsi2ss", "cvtsi2sd", "cvttsd2si", "cvttps2dq", "cvtpd2dq", "cvtpd2ps", "cvtps2dq", "cvtsd2si", "cvtsd2ss", "cvttss2si", "cvtss2si", "cvtss2sd", "cvtdq2pd", "lddqu", "movzx", "movsx", "movsxd", "shrd", // " inc", // " dec", "hlt", "call", "callf", "jmp", "jmpf", "push", "pop", "lea", "nop", "prefetchnta", "prefetch0", "prefetch1", "prefetch2", // " xchg", "popf", "int", "into", "iret", "iretd", "iretq", "retf", "enter", "leave", "mov", "ret", "pushf", "wait", "cbw", "cwde", "cdqe", "cwd", "cdq", "cqo", "lods", "stos", "lahf", "sahf", "cmps", "scas", "movs", "test", "ins", "in", "outs", "out", "imul", "jo", "jno", "jb", "jnb", "jz", "jnz", "ja", "jna", "js", "jns", "jp", "jnp", "jl", "jge", "jle", "jg", "cmova", "cmovb", "cmovg", "cmovge", "cmovl", "cmovle", "cmovna", "cmovnb", "cmovno", "cmovnp", "cmovns", "cmovnz", "cmovo", "cmovp", "cmovs", "cmovz", "div", "idiv", "mul", // " neg", // " not", // " cmpxchg", "seto", "setno", "setb", "setae", "setz", "setnz", "setbe", "seta", "sets", "setns", "setp", "setnp", "setl", "setge", "setle", "setg", "cpuid", "ud0", "ud1", "ud2", "wbinvd", "invd", "sysret", "clts", "syscall", "lsl", "lar", "les", "lds", "sgdt", "sidt", "lgdt", "lidt", "smsw", "lmsw", "swapgs", "rdtscp", "invlpg", "fxsave", "fxrstor", "ldmxcsr", "stmxcsr", "xsave", "xrstor", "xsaveopt", "lfence", "mfence", "sfence", "clflush", "clflushopt", "clwb", "wrmsr", "rdtsc", "rdmsr", "rdpmc", "sldt", "str", "lldt", "ltr", "verr", "verw", "cmc", "clc", "stc", "cli", "sti", "cld", "std", "jmpe", "popcnt", "movdqu", "movdqa", "movq", "cmpss", "cmpsd", "unpcklps", "unpcklpd", "unpckhps", "unpckhpd", "pshufhw", "pshuflw", "movups", "movq2dq", "movdq2q", "rsqrtss", "rcpss", "andn", "bextr", "blsi", "blsmsk", "blsr", "vmclear", "vmxon", "vmcall", "vmlaunch", "vmresume", "vmxoff", "pconfig", "monitor", "mwait", "monitorx", "mwaitx", "clac", "stac", "encls", "enclv", "xgetbv", "xsetbv", "vmfunc", "xabort", "xbegin", "xend", "xtest", "enclu", "rdpkru", "wrpkru", "rdpru", "clzero", "rdseed", "rdrand", "addps", "addpd", "andnps", "andnpd", "andps", "andpd", "bswap", "cmppd", "cmpps", "comisd", "comiss", "cvtdq2ps", "cvtpi2ps", "cvtpi2pd", "cvtps2pd", "cvtps2pi", "cvtpd2pi", "cvttps2pi", "cvttpd2pi", "cvttpd2dq", "divps", "divpd", "emms", "getsec", "lfs", "lgs", "lss", "maskmovq", "maskmovdqu", "maxps", "maxpd", "minps", "minpd", "movaps", "movapd", "movd", "movlps", "movlpd", "movhps", "movhpd", "movlhps", "movhlps", "movupd", "movmskps", "movmskpd", "movnti", "movntps", "movntpd", "extrq", "insertq", "movntss", "movntsd", "movntq", "movntdq", "mulps", "mulpd", "orps", "orpd", "packssdw", "packsswb", "packuswb", "paddb", "paddd", "paddq", "paddsb", "paddsw", "paddusb", "paddusw", "paddw", "pand", "pandn", "pavgb", "pavgw", "pcmpeqb", "pcmpeqd", "pcmpeqw", "pcmpgtb", "pcmpgtd", "pcmpgtw", "pinsrw", "pmaddwd", "pmaxsw", "pmaxub", "pminsw", "pminub", "pmovmskb", "pmulhuw", "pmulhw", "pmullw", "pmuludq", "por", "psadbw", "pshufw", "pshufd", "pslld", "pslldq", "psllq", "psllw", "psrad", "psraw", "psrld", "psrldq", "psrlq", "psrlw", "psubb", "psubd", "psubq", "psubsb", "psubsw", "psubusb", "psubusw", "psubw", "punpckhbw", "punpckhdq", "punpckhwd", "punpcklbw", "punpckldq", "punpcklwd", "punpcklqdq", "punpckhqdq", "pxor", "rcpps", "rsm", "rsqrtps", "shld", "shufpd", "shufps", "slhd", "sqrtps", "sqrtpd", "subps", "subpd", "sysenter", "sysexit", "ucomisd", "ucomiss", "vmread", "vmwrite", "xorps", "xorpd", "vmovddup", "vpshuflw", "vpshufhw", "vhaddps", "vhsubps", "vaddsubps", "vcvtpd2dq", "vlddqu", "vcomisd", "vcomiss", "vucomisd", "vucomiss", "vaddpd", "vaddps", "vaddsd", "vaddss", "vaddsubpd", "vaesdec", "vaesdeclast", "vaesenc", "vaesenclast", "vaesimc", "vaeskeygenassist", "vblendpd", "vblendps", "vblendvpd", "vblendvps", "vbroadcastf128", "vbroadcasti128", "vbroadcastsd", "vbroadcastss", "vcmpsd", "vcmpss", "vcmppd", "vcmpps", "vcvtdq2pd", "vcvtdq2ps", "vcvtpd2ps", "vcvtph2ps", "vcvtps2dq", "vcvtps2pd", "vcvtss2sd", "vcvtsi2ss", "vcvtsi2sd", "vcvtsd2si", "vcvtsd2ss", "vcvtps2ph", "vcvtss2si", "vcvttpd2dq", "vcvttps2dq", "vcvttss2si", "vcvttsd2si", "vdivpd", "vdivps", "vdivsd", "vdivss", "vdppd", "vdpps", "vextractf128", "vextracti128", "vextractps", "vfmadd132pd", "vfmadd132ps", "vfmadd132sd", "vfmadd132ss", "vfmadd213pd", "vfmadd213ps", "vfmadd213sd", "vfmadd213ss", "vfmadd231pd", "vfmadd231ps", "vfmadd231sd", "vfmadd231ss", "vfmaddsub132pd", "vfmaddsub132ps", "vfmaddsub213pd", "vfmaddsub213ps", "vfmaddsub231pd", "vfmaddsub231ps", "vfmsub132pd", "vfmsub132ps", "vfmsub132sd", "vfmsub132ss", "vfmsub213pd", "vfmsub213ps", "vfmsub213sd", "vfmsub213ss", "vfmsub231pd", "vfmsub231ps", "vfmsub231sd", "vfmsub231ss", "vfmsubadd132pd", "vfmsubadd132ps", "vfmsubadd213pd", "vfmsubadd213ps", "vfmsubadd231pd", "vfmsubadd231ps", "vfnmadd132pd", "vfnmadd132ps", "vfnmadd132sd", "vfnmadd132ss", "vfnmadd213pd", "vfnmadd213ps", "vfnmadd213sd", "vfnmadd213ss", "vfnmadd231pd", "vfnmadd231ps", "vfnmadd231sd", "vfnmadd231ss", "vfnmsub132pd", "vfnmsub132ps", "vfnmsub132sd", "vfnmsub132ss", "vfnmsub213pd", "vfnmsub213ps", "vfnmsub213sd", "vfnmsub213ss", "vfnmsub231pd", "vfnmsub231ps", "vfnmsub231sd", "vfnmsub231ss", "vgatherdpd", "vgatherdps", "vgatherqpd", "vgatherqps", "vhaddpd", "vhsubpd", "vinsertf128", "vinserti128", "vinsertps", "vmaskmovdqu", "vmaskmovpd", "vmaskmovps", "vmaxpd", "vmaxps", "vmaxsd", "vmaxss", "vminpd", "vminps", "vminsd", "vminss", "vmovapd", "vmovaps", "vmovd", "vmovdqa", "vmovdqu", "vmovhlps", "vmovhpd", "vmovhps", "vmovlhps", "vmovlpd", "vmovlps", "vmovmskpd", "vmovmskps", "vmovntdq", "vmovntdqa", "vmovntpd", "vmovntps", "vmovq", "vmovss", "vmovsd", "vmovshdup", "vmovsldup", "vmovupd", "vmovups", "vmpsadbw", "vmulpd", "vmulps", "vmulsd", "vmulss", "vpabsb", "vpabsd", "vpabsw", "vpackssdw", "vpackusdw", "vpacksswb", "vpackuswb", "vpaddb", "vpaddd", "vpaddq", "vpaddsb", "vpaddsw", "vpaddusb", "vpaddusw", "vpaddw", "vpalignr", "vandpd", "vandps", "vorpd", "vorps", "vandnpd", "vandnps", "vpand", "vpandn", "vpavgb", "vpavgw", "vpblendd", "vpblendvb", "vpblendw", "vpbroadcastb", "vpbroadcastd", "vpbroadcastq", "vpbroadcastw", "vpclmulqdq", "vpcmpeqb", "vpcmpeqd", "vpcmpeqq", "vpcmpeqw", "vpcmpgtb", "vpcmpgtd", "vpcmpgtq", "vpcmpgtw", "vpcmpestri", "vpcmpestrm", "vpcmpistri", "vpcmpistrm", "vperm2f128", "vperm2i128", "vpermd", "vpermilpd", "vpermilps", "vpermpd", "vpermps", "vpermq", "vpextrb", "vpextrd", "vpextrq", "vpextrw", "vpgatherdd", "vpgatherdq", "vpgatherqd", "vpgatherqq", "vphaddd", "vphaddsw", "vphaddw", "vpmaddubsw", "vphminposuw", "vphsubd", "vphsubsw", "vphsubw", "vpinsrb", "vpinsrd", "vpinsrq", "vpinsrw", "vpmaddwd", "vpmaskmovd", "vpmaskmovq", "vpmaxsb", "vpmaxsd", "vpmaxsw", "vpmaxub", "vpmaxuw", "vpmaxud", "vpminsb", "vpminsw", "vpminsd", "vpminub", "vpminuw", "vpminud", "vpmovmskb", "vpmovsxbd", "vpmovsxbq", "vpmovsxbw", "vpmovsxdq", "vpmovsxwd", "vpmovsxwq", "vpmovzxbd", "vpmovzxbq", "vpmovzxbw", "vpmovzxdq", "vpmovzxwd", "vpmovzxwq", "vpmuldq", "vpmulhrsw", "vpmulhuw", "vpmulhw", "vpmullq", "vpmulld", "vpmullw", "vpmuludq", "vpor", "vpsadbw", "vpshufb", "vpshufd", "vpsignb", "vpsignd", "vpsignw", "vpslld", "vpslldq", "vpsllq", "vpsllvd", "vpsllvq", "vpsllw", "vpsrad", "vpsravd", "vpsraw", "vpsrld", "vpsrldq", "vpsrlq", "vpsrlvd", "vpsrlvq", "vpsrlw", "vpsubb", "vpsubd", "vpsubq", "vpsubsb", "vpsubsw", "vpsubusb", "vpsubusw", "vpsubw", "vptest", "vpunpckhbw", "vpunpckhdq", "vpunpckhqdq", "vpunpckhwd", "vpunpcklbw", "vpunpckldq", "vpunpcklqdq", "vpunpcklwd", "vpxor", "vrcpps", "vroundpd", "vroundps", "vroundsd", "vroundss", "vrsqrtps", "vrsqrtss", "vrcpss", "vshufpd", "vshufps", "vsqrtpd", "vsqrtps", "vsqrtss", "vsqrtsd", "vsubpd", "vsubps", "vsubsd", "vsubss", "vtestpd", "vtestps", "vunpckhpd", "vunpckhps", "vunpcklpd", "vunpcklps", "vxorpd", "vxorps", "vzeroupper", "vzeroall", "vldmxcsr", "vstmxcsr", "pclmulqdq", "aeskeygenassist", "aesimc", "aesenc", "aesenclast", "aesdec", "aesdeclast", "pcmpgtq", "pcmpistrm", "pcmpistri", "pcmpestri", "packusdw", "pcmpestrm", "pcmpeqq", "ptest", "phminposuw", "dpps", "dppd", "mpsadbw", "pmovzxdq", "pmovsxdq", "pmovzxbd", "pmovsxbd", "pmovzxwq", "pmovsxwq", "pmovzxbq", "pmovsxbq", "pmovsxwd", "pmovzxwd", "pextrq", "pextrd", "pextrw", "pextrb", "pmovsxbw", "pmovzxbw", "pinsrq", "pinsrd", "pinsrb", "extractps", "insertps", "roundss", "roundsd", "roundps", "roundpd", "pmaxsb", "pmaxsd", "pmaxuw", "pmaxud", "pminsd", "pminsb", "pminud", "pminuw", "blendw", "pblendvb", "pblendw", "blendvps", "blendvpd", "blendps", "blendpd", "pmuldq", "movntdqa", "pmulld", "palignr", "psignw", "psignd", "psignb", "pshufb", "pmulhrsw", "pmaddubsw", "pabsd", "pabsw", "pabsb", "phsubsw", "phsubw", "phsubd", "phaddd", "phaddsw", "phaddw", "hsubpd", "haddpd", "sha1rnds4", "sha1nexte", "sha1msg1", "sha1msg2", "sha256rnds2", "sha256msg1", "sha256msg2", "lzcnt", "clgi", "stgi", "skinit", "vmload", "vmmcall", "vmsave", "vmrun", "invlpga", "invlpgb", "tlbsync", "movbe", "adcx", "adox", "prefetchw", "rdpid", // " cmpxchg8b", // " cmpxchg16b", "vmptrld", "vmptrst", "bzhi", "mulx", "shlx", "shrx", "sarx", "pdep", "pext", "rorx", "xrstors", "xrstors64", "xsavec", "xsavec64", "xsaves", "xsaves64", "rdfsbase", "rdgsbase", "wrfsbase", "wrgsbase", "crc32", "salc", "xlat", "f2xm1", "fabs", "fadd", "faddp", "fbld", "fbstp", "fchs", "fcmovb", "fcmovbe", "fcmove", "fcmovnb", "fcmovnbe", "fcmovne", "fcmovnu", "fcmovu", "fcom", "fcomi", "fcomip", "fcomp", "fcompp", "fcos", "fdecstp", "fdisi8087_nop", "fdiv", "fdivp", "fdivr", "fdivrp", "feni8087_nop", "ffree", "ffreep", "fiadd", "ficom", "ficomp", "fidiv", "fidivr", "fild", "fimul", "fincstp", "fist", "fistp", "fisttp", "fisub", "fisubr", "fld", "fld1", "fldcw", "fldenv", "fldl2e", "fldl2t", "fldlg2", "fldln2", "fldpi", "fldz", "fmul", "fmulp", "fnclex", "fninit", "fnop", "fnsave", "fnstcw", "fnstenv", "fnstor", "fnstsw", "fpatan", "fprem", "fprem1", "fptan", "frndint", "frstor", "fscale", "fsetpm287_nop", "fsin", "fsincos", "fsqrt", "fst", "fstp", "fstpnce", "fsub", "fsubp", "fsubr", "fsubrp", "ftst", "fucom", "fucomi", "fucomip", "fucomp", "fucompp", "fxam", "fxch", "fxtract", "fyl2x", "fyl2xp1", "loopnz", "loopz", "loop", "jecxz", "pusha", "popa", "bound", "arpl", "aas", "aaa", "das", "daa", "aam", "aad", // started shipping in tremont, 2020 sept 23 "movdir64b", "movdiri", // started shipping in tiger lake, 2020 sept 2 "aesdec128kl", "aesdec256kl", "aesdecwide128kl", "aesdecwide256kl", "aesenc128kl", "aesenc256kl", "aesencwide128kl", "aesencwide256kl", "encodekey128", "encodekey256", "loadiwkey", // unsure "hreset", // 3dnow "femms", "pi2fw", "pi2fd", "pf2iw", "pf2id", "pmulhrw", "pfcmpge", "pfmin", "pfrcp", "pfrsqrt", "pfsub", "pfadd", "pfcmpgt", "pfmax", "pfrcpit1", "pfrsqit1", "pfsubr", "pfacc", "pfcmpeq", "pfmul", "pfmulhrw", "pfrcpit2", "pfnacc", "pfpnacc", "pswapd", "pavgusb", // enqcmd "enqcmd", "enqcmds", // invpcid "invept", "invvpid", "invpcid", // ptwrite "ptwrite", // gfni "gf2p8affineqb", "gf2p8affineinvqb", "gf2p8mulb", // cet "wruss", "wrss", "incssp", "saveprevssp", "setssbsy", "clrssbsy", "rstorssp", "endbr64", "endbr32", // tdx "tdcall", "seamret", "seamops", "seamcall", // waitpkg "tpause", "umonitor", "umwait", // uintr "uiret", "testui", "clui", "stui", "senduipi", // tsxldtrk "xsusldtrk", "xresldtrk", // avx512f "valignd", "valignq", "vblendmpd", "vblendmps", "vcompresspd", "vcompressps", "vcvtpd2udq", "vcvttpd2udq", "vcvtps2udq", "vcvttps2udq", "vcvtqq2pd", "vcvtqq2ps", "vcvtsd2usi", "vcvttsd2usi", "vcvtss2usi", "vcvttss2usi", "vcvtudq2pd", "vcvtudq2ps", "vcvtusi2usd", "vcvtusi2uss", "vexpandpd", "vexpandps", "vextractf32x4", "vextractf64x4", "vextracti32x4", "vextracti64x4", "vfixupimmpd", "vfixupimmps", "vfixupimmsd", "vfixupimmss", "vgetexppd", "vgetexpps", "vgetexpsd", "vgetexpss", "vgetmantpd", "vgetmantps", "vgetmantsd", "vgetmantss", "vinsertf32x4", "vinsertf64x4", "vinserti64x4", "vmovdqa32", "vmovdqa64", "vmovdqu32", "vmovdqu64", "vpblendmd", "vpblendmq", "vpcmpd", "vpcmpud", "vpcmpq", "vpcmpuq", "vpcompressq", "vpcompressd", "vpermi2d", "vpermi2q", "vpermi2pd", "vpermi2ps", "vpermt2d", "vpermt2q", "vpermt2pd", "vpermt2ps", "vpmaxsq", "vpmaxuq", "vpminsq", "vpminuq", "vpmovsqb", "vpmovusqb", "vpmovsqw", "vpmovusqw", "vpmovsqd", "vpmovusqd", "vpmovsdb", "vpmovusdb", "vpmovsdw", "vpmovusdw", "vprold", "vprolq", "vprolvd", "vprolvq", "vprord", "vprorq", "vprorrd", "vprorrq", "vpscatterdd", "vpscatterdq", "vpscatterqd", "vpscatterqq", "vpsraq", "vpsravq", "vptestnmd", "vptestnmq", "vpternlogd", "vpternlogq", "vptestmd", "vptestmq", "vrcp14pd", "vrcp14ps", "vrcp14sd", "vrcp14ss", "vrndscalepd", "vrndscaleps", "vrndscalesd", "vrndscaless", "vrsqrt14pd", "vrsqrt14ps", "vrsqrt14sd", "vrsqrt14ss", "vscaledpd", "vscaledps", "vscaledsd", "vscaledss", "vscatterdd", "vscatterdq", "vscatterqd", "vscatterqq", "vshuff32x4", "vshuff64x2", "vshufi32x4", "vshufi64x2", // avx512dq "vcvttpd2qq", "vcvtpd2qq", "vcvttpd2uqq", "vcvtpd2uqq", "vcvttps2qq", "vcvtps2qq", "vcvttps2uqq", "vcvtps2uqq", "vcvtuqq2pd", "vcvtuqq2ps", "vextractf64x2", "vextracti64x2", "vfpclasspd", "vfpclassps", "vfpclasssd", "vfpclassss", "vinsertf64x2", "vinserti64x2", "vpmovm2d", "vpmovm2q", "vpmovb2d", "vpmovq2m", "vrangepd", "vrangeps", "vrangesd", "vrangess", "vreducepd", "vreduceps", "vreducesd", "vreducess", // avx512bw "vdbpsadbw", "vmovdqu8", "vmovdqu16", "vpblendmb", "vpblendmw", "vpcmpb", "vpcmpub", "vpcmpw", "vpcmpuw", "vpermw", "vpermi2b", "vpermi2w", "vpmovm2b", "vpmovm2w", "vpmovb2m", "vpmovw2m", "vpmovswb", "vpmovuswb", "vpsllvw", "vpsravw", "vpsrlvw", "vptestnmb", "vptestnmw", "vptestmb", "vptestmw", // avx512cd "vpbroadcastm", "vpconflictd", "vpconflictq", "vplzcntd", "vplzcntq", "kunpckbw", "kunpckwd", "kunpckdq", "kaddb", "kandb", "kandnb", "kmovb", "knotb", "korb", "kortestb", "kshiftlb", "kshiftrb", "ktestb", "kxnorb", "kxorb", "kaddw", "kandw", "kandnw", "kmovw", "knotw", "korw", "kortestw", "kshiftlw", "kshiftrw", "ktestw", "kxnorw", "kxorw", "kaddd", "kandd", "kandnd", "kmovd", "knotd", "kord", "kortestd", "kshiftld", "kshiftrd", "ktestd", "kxnord", "kxord", "kaddq", "kandq", "kandnq", "kmovq", "knotq", "korq", "kortestq", "kshiftlq", "kshiftrq", "ktestq", "kxnorq", "kxorq", // avx512er "vexp2pd", "vexp2ps", "vexp2sd", "vexp2ss", "vrcp28pd", "vrcp28ps", "vrcp28sd", "vrcp28ss", "vrsqrt28pd", "vrsqrt28ps", "vrsqrt28sd", "vrsqrt28ss", // avx512pf "vgatherpf0dpd", "vgatherpf0dps", "vgatherpf0qpd", "vgatherpf0qps", "vgatherpf1dpd", "vgatherpf1dps", "vgatherpf1qpd", "vgatherpf1qps", "vscatterpf0dpd", "vscatterpf0dps", "vscatterpf0qpd", "vscatterpf0qps", "vscatterpf1dpd", "vscatterpf1dps", "vscatterpf1qpd", "vscatterpf1qps", // mpx "bndmk", "bndcl", "bndcu", "bndcn", "bndmov", "bndldx", "bndstx", "vgf2p8affineqb", "vgf2p8affineinvqb", "vpshrdq", "vpshrdd", "vpshrdw", "vpshldq", "vpshldd", "vpshldw", "vbroadcastf32x8", "vbroadcastf64x4", "vbroadcastf32x4", "vbroadcastf64x2", "vbroadcastf32x2", "vbroadcasti32x8", "vbroadcasti64x4", "vbroadcasti32x4", "vbroadcasti64x2", "vbroadcasti32x2", "vextracti32x8", "vextractf32x8", "vinserti32x8", "vinsertf32x8", "vinserti32x4", "v4fnmaddss", "v4fnmaddps", "vcvtneps2bf16", "v4fmaddss", "v4fmaddps", "vcvtne2ps2bf16", "vp2intersectd", "vp2intersectq", "vp4dpwssds", "vp4dpwssd", "vpdpwssds", "vpdpwssd", "vpdpbusds", "vdpbf16ps", "vpbroadcastmw2d", "vpbroadcastmb2q", "vpmovd2m", "vpmovqd", "vpmovwb", "vpmovdb", "vpmovdw", "vpmovqb", "vpmovqw", "vgf2p8mulb", "vpmadd52huq", "vpmadd52luq", "vpshufbitqmb", "vpermb", "vpexpandd", "vpexpandq", "vpabsq", "vprorvd", "vprorvq", "vpmultishiftqb", "vpermt2b", "vpermt2w", "vpshrdvq", "vpshrdvd", "vpshrdvw", "vpshldvq", "vpshldvd", "vpshldvw", "vpcompressb", "vpcompressw", "vpexpandb", "vpexpandw", "vpopcntd", "vpopcntq", "vpopcntb", "vpopcntw", "vscalefss", "vscalefsd", "vscalefps", "vscalefpd", "vpdpbusd", "vcvtusi2sd", "vcvtusi2ss", "vpxord", "vpxorq", "vpord", "vporq", "vpandnd", "vpandnq", "vpandd", "vpandq", "psmash", "pvalidate", "rmpadjust", "rmpupdate", ]; impl Opcode { fn name(&self) -> &'static str { unsafe { MNEMONICS.get_kinda_unchecked(*self as usize & 0xfff) } } } impl Colorize for Opcode { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { match self { Opcode::VGF2P8AFFINEQB | Opcode::VGF2P8AFFINEINVQB | Opcode::VPSHRDQ | Opcode::VPSHRDD | Opcode::VPSHRDW | Opcode::VPSHLDQ | Opcode::VPSHLDD | Opcode::VPSHLDW | Opcode::VBROADCASTF32X8 | Opcode::VBROADCASTF64X4 | Opcode::VBROADCASTF32X4 | Opcode::VBROADCASTF64X2 | Opcode::VBROADCASTF32X2 | Opcode::VBROADCASTI32X8 | Opcode::VBROADCASTI64X4 | Opcode::VBROADCASTI32X4 | Opcode::VBROADCASTI64X2 | Opcode::VBROADCASTI32X2 | Opcode::VEXTRACTI32X8 | Opcode::VEXTRACTF32X8 | Opcode::VINSERTI32X8 | Opcode::VINSERTF32X8 | Opcode::VINSERTI32X4 | Opcode::V4FNMADDSS | Opcode::V4FNMADDPS | Opcode::VCVTNEPS2BF16 | Opcode::V4FMADDSS | Opcode::V4FMADDPS | Opcode::VCVTNE2PS2BF16 | Opcode::VP2INTERSECTD | Opcode::VP2INTERSECTQ | Opcode::VP4DPWSSDS | Opcode::VP4DPWSSD | Opcode::VPDPWSSDS | Opcode::VPDPWSSD | Opcode::VPDPBUSDS | Opcode::VDPBF16PS | Opcode::VPBROADCASTMW2D | Opcode::VPBROADCASTMB2Q | Opcode::VPMOVD2M | Opcode::VPMOVQD | Opcode::VPMOVWB | Opcode::VPMOVDB | Opcode::VPMOVDW | Opcode::VPMOVQB | Opcode::VPMOVQW | Opcode::VGF2P8MULB | Opcode::VPMADD52HUQ | Opcode::VPMADD52LUQ | Opcode::VPSHUFBITQMB | Opcode::VPERMB | Opcode::VPEXPANDD | Opcode::VPEXPANDQ | Opcode::VPABSQ | Opcode::VPRORVD | Opcode::VPRORVQ | Opcode::VPMULTISHIFTQB | Opcode::VPERMT2B | Opcode::VPERMT2W | Opcode::VPSHRDVQ | Opcode::VPSHRDVD | Opcode::VPSHRDVW | Opcode::VPSHLDVQ | Opcode::VPSHLDVD | Opcode::VPSHLDVW | Opcode::VPCOMPRESSB | Opcode::VPCOMPRESSW | Opcode::VPEXPANDB | Opcode::VPEXPANDW | Opcode::VPOPCNTD | Opcode::VPOPCNTQ | Opcode::VPOPCNTB | Opcode::VPOPCNTW | Opcode::VSCALEFSS | Opcode::VSCALEFSD | Opcode::VSCALEFPS | Opcode::VSCALEFPD | Opcode::VPDPBUSD | Opcode::VCVTUSI2SD | Opcode::VCVTUSI2SS | Opcode::VPXORD | Opcode::VPXORQ | Opcode::VPORD | Opcode::VPORQ | Opcode::VPANDND | Opcode::VPANDNQ | Opcode::VPANDD | Opcode::VPANDQ | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::HADDPD | Opcode::HSUBPD | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::PABSB | Opcode::PABSD | Opcode::PABSW | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::PSIGNB | Opcode::PSIGND | Opcode::PSIGNW | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::PCLMULQDQ | Opcode::PMULDQ | Opcode::PMULHRSW | Opcode::PMULLD | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VEXP2PD | Opcode::VEXP2PS | Opcode::VEXP2SD | Opcode::VEXP2SS | Opcode::VRCP28PD | Opcode::VRCP28PS | Opcode::VRCP28SD | Opcode::VRCP28SS | Opcode::VRCP14PD | Opcode::VRCP14PS | Opcode::VRCP14SD | Opcode::VRCP14SS | Opcode::VRNDSCALEPD | Opcode::VRNDSCALEPS | Opcode::VRNDSCALESD | Opcode::VRNDSCALESS | Opcode::VRSQRT14PD | Opcode::VRSQRT14PS | Opcode::VRSQRT14SD | Opcode::VRSQRT14SS | Opcode::VSCALEDPD | Opcode::VSCALEDPS | Opcode::VSCALEDSD | Opcode::VSCALEDSS | Opcode::VRSQRT28PD | Opcode::VRSQRT28PS | Opcode::VRSQRT28SD | Opcode::VRSQRT28SS | Opcode::VRSQRTPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VRCPSS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::ROUNDPD | Opcode::ROUNDPS | Opcode::ROUNDSD | Opcode::ROUNDSS | Opcode::VRSQRTSS | Opcode::VSQRTSD | Opcode::VSQRTSS | Opcode::VPSADBW | Opcode::VMPSADBW | Opcode::VDBPSADBW | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPMADDUBSW | Opcode::VPMADDWD | Opcode::VDPPD | Opcode::VDPPS | Opcode::VRCPPS | Opcode::VORPD | Opcode::VORPS | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VPAND | Opcode::VPANDN | Opcode::VPOR | Opcode::VPXOR | Opcode::VXORPD | Opcode::VXORPS | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPROLD | Opcode::VPROLQ | Opcode::VPROLVD | Opcode::VPROLVQ | Opcode::VPRORD | Opcode::VPRORQ | Opcode::VPRORRD | Opcode::VPRORRQ | Opcode::VPSLLVW | Opcode::VPSRAQ | Opcode::VPSRAVQ | Opcode::VPSRAVW | Opcode::VPSRLVW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::PHADDD | Opcode::PHADDSW | Opcode::PHADDW | Opcode::PHSUBD | Opcode::PHSUBSW | Opcode::PHSUBW | Opcode::PMADDUBSW | Opcode::ADDSUBPD | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::RCPSS | Opcode::RSQRTSS | Opcode::SQRTSD | Opcode::ADDSD | Opcode::SUBSD | Opcode::MULSD | Opcode::DIVSD | Opcode::SQRTSS | Opcode::ADDSS | Opcode::SUBSS | Opcode::MULSS | Opcode::DIVSS | Opcode::HADDPS | Opcode::HSUBPS | Opcode::ADDSUBPS | Opcode::PMULHRW | Opcode::PFRCP | Opcode::PFRSQRT | Opcode::PFSUB | Opcode::PFADD | Opcode::PFRCPIT1 | Opcode::PFRSQIT1 | Opcode::PFSUBR | Opcode::PFACC | Opcode::PFMUL | Opcode::PFMULHRW | Opcode::PFRCPIT2 | Opcode::PFNACC | Opcode::PFPNACC | Opcode::PSWAPD | Opcode::PAVGUSB | Opcode::XADD| Opcode::DIV | Opcode::IDIV | Opcode::MUL | Opcode::MULX | Opcode::NEG | Opcode::NOT | Opcode::SAR | Opcode::SAL | Opcode::SHR | Opcode::SARX | Opcode::SHLX | Opcode::SHRX | Opcode::SHRD | Opcode::SHL | Opcode::RCR | Opcode::RCL | Opcode::ROR | Opcode::RORX | Opcode::ROL | Opcode::INC | Opcode::DEC | Opcode::SBB | Opcode::AND | Opcode::XOR | Opcode::OR | Opcode::LEA | Opcode::ADD | Opcode::ADC | Opcode::ADCX | Opcode::ADOX | Opcode::SUB | Opcode::POPCNT | Opcode::LZCNT | Opcode::VPLZCNTD | Opcode::VPLZCNTQ | Opcode::BT | Opcode::BTS | Opcode::BTR | Opcode::BTC | Opcode::BSF | Opcode::BSR | Opcode::BZHI | Opcode::PDEP | Opcode::PEXT | Opcode::TZCNT | Opcode::ANDN | Opcode::BEXTR | Opcode::BLSI | Opcode::BLSMSK | Opcode::BLSR | Opcode::ADDPS | Opcode::ADDPD | Opcode::ANDNPS | Opcode::ANDNPD | Opcode::ANDPS | Opcode::ANDPD | Opcode::COMISD | Opcode::COMISS | Opcode::DIVPS | Opcode::DIVPD | Opcode::MULPS | Opcode::MULPD | Opcode::ORPS | Opcode::ORPD | Opcode::PADDB | Opcode::PADDD | Opcode::PADDQ | Opcode::PADDSB | Opcode::PADDSW | Opcode::PADDUSB | Opcode::PADDUSW | Opcode::PADDW | Opcode::PAND | Opcode::PANDN | Opcode::PAVGB | Opcode::PAVGW | Opcode::PMADDWD | Opcode::PMULHUW | Opcode::PMULHW | Opcode::PMULLW | Opcode::PMULUDQ | Opcode::POR | Opcode::PSADBW | Opcode::PSHUFD | Opcode::PSHUFW | Opcode::PSHUFB | Opcode::PSLLD | Opcode::PSLLDQ | Opcode::PSLLQ | Opcode::PSLLW | Opcode::PSRAD | Opcode::PSRAW | Opcode::PSRLD | Opcode::PSRLDQ | Opcode::PSRLQ | Opcode::PSRLW | Opcode::PSUBB | Opcode::PSUBD | Opcode::PSUBQ | Opcode::PSUBSB | Opcode::PSUBSW | Opcode::PSUBUSB | Opcode::PSUBUSW | Opcode::PSUBW | Opcode::PXOR | Opcode::RSQRTPS | Opcode::SQRTPS | Opcode::SQRTPD | Opcode::SUBPS | Opcode::SUBPD | Opcode::XORPS | Opcode::XORPD | Opcode::RCPPS | Opcode::SHLD | Opcode::SLHD | Opcode::UCOMISD | Opcode::UCOMISS | Opcode::F2XM1 | Opcode::FABS | Opcode::FADD | Opcode::FADDP | Opcode::FCHS | Opcode::FCOS | Opcode::FDIV | Opcode::FDIVP | Opcode::FDIVR | Opcode::FDIVRP | Opcode::FIADD | Opcode::FIDIV | Opcode::FIDIVR | Opcode::FIMUL | Opcode::FISUB | Opcode::FISUBR | Opcode::FMUL | Opcode::FMULP | Opcode::FNCLEX | Opcode::FNINIT | Opcode::FPATAN | Opcode::FPREM | Opcode::FPREM1 | Opcode::FPTAN | Opcode::FRNDINT | Opcode::FSCALE | Opcode::FSIN | Opcode::FSINCOS | Opcode::FSQRT | Opcode::FSUB | Opcode::FSUBP | Opcode::FSUBR | Opcode::FSUBRP | Opcode::FXTRACT | Opcode::FYL2X | Opcode::FYL2XP1 | Opcode::AAA | Opcode::AAS | Opcode::DAS | Opcode::DAA | Opcode::AAD | Opcode::AAM | Opcode::KADDB | Opcode::KANDB | Opcode::KANDNB | Opcode::KNOTB | Opcode::KORB | Opcode::KSHIFTLB | Opcode::KSHIFTRB | Opcode::KXNORB | Opcode::KXORB | Opcode::KADDW | Opcode::KANDW | Opcode::KANDNW | Opcode::KNOTW | Opcode::KORW | Opcode::KSHIFTLW | Opcode::KSHIFTRW | Opcode::KXNORW | Opcode::KXORW | Opcode::KADDD | Opcode::KANDD | Opcode::KANDND | Opcode::KNOTD | Opcode::KORD | Opcode::KSHIFTLD | Opcode::KSHIFTRD | Opcode::KXNORD | Opcode::KXORD | Opcode::KADDQ | Opcode::KANDQ | Opcode::KANDNQ | Opcode::KNOTQ | Opcode::KORQ | Opcode::KSHIFTLQ | Opcode::KSHIFTRQ | Opcode::KXNORQ | Opcode::KXORQ | Opcode::IMUL => { write!(out, "{}", colors.arithmetic_op(self)) } Opcode::POPF | Opcode::PUSHF | Opcode::ENTER | Opcode::LEAVE | Opcode::PUSHA | Opcode::POPA | Opcode::PUSH | Opcode::POP => { write!(out, "{}", colors.stack_op(self)) } Opcode::WAIT | Opcode::FNOP | Opcode::FDISI8087_NOP | Opcode::FENI8087_NOP | Opcode::FSETPM287_NOP | Opcode::PREFETCHNTA | Opcode::PREFETCH0 | Opcode::PREFETCH1 | Opcode::PREFETCH2 | Opcode::PREFETCHW | Opcode::NOP => { write!(out, "{}", colors.nop_op(self)) } /* Control flow */ Opcode::HLT | Opcode::INT | Opcode::INTO | Opcode::IRET | Opcode::IRETD | Opcode::IRETQ | Opcode::RETF | Opcode::RETURN => { write!(out, "{}", colors.stop_op(self)) } Opcode::LOOPNZ | Opcode::LOOPZ | Opcode::LOOP | Opcode::JECXZ | Opcode::CALL | Opcode::CALLF | Opcode::JMP | Opcode::JMPF | Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JLE | Opcode::JG => { write!(out, "{}", colors.control_flow_op(self)) } /* Data transfer */ Opcode::PI2FW | Opcode::PI2FD | Opcode::PF2ID | Opcode::PF2IW | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2DQ | Opcode::VCVTPD2PS | Opcode::VCVTPH2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTPS2PH | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSI2SD | Opcode::VCVTSI2SS | Opcode::VCVTSS2SD | Opcode::VCVTSS2SI | Opcode::VCVTTSD2SI | Opcode::VCVTTSS2SI | Opcode::VCVTPD2UDQ | Opcode::VCVTTPD2UDQ | Opcode::VCVTPS2UDQ | Opcode::VCVTTPS2UDQ | Opcode::VCVTQQ2PD | Opcode::VCVTQQ2PS | Opcode::VCVTSD2USI | Opcode::VCVTTSD2USI | Opcode::VCVTSS2USI | Opcode::VCVTTSS2USI | Opcode::VCVTUDQ2PD | Opcode::VCVTUDQ2PS | Opcode::VCVTUSI2USD | Opcode::VCVTUSI2USS | Opcode::VCVTTPD2QQ | Opcode::VCVTPD2QQ | Opcode::VCVTTPD2UQQ | Opcode::VCVTPD2UQQ | Opcode::VCVTTPS2QQ | Opcode::VCVTPS2QQ | Opcode::VCVTTPS2UQQ | Opcode::VCVTPS2UQQ | Opcode::VCVTUQQ2PD | Opcode::VCVTUQQ2PS | Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VBLENDMPD | Opcode::VBLENDMPS | Opcode::VPBLENDMD | Opcode::VPBLENDMQ | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VPBLENDMB | Opcode::VPBLENDMW | Opcode::PBLENDVB | Opcode::PBLENDW | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::BLENDW | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VPBROADCASTM | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::EXTRACTPS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VGATHERPF0DPD | Opcode::VGATHERPF0DPS | Opcode::VGATHERPF0QPD | Opcode::VGATHERPF0QPS | Opcode::VGATHERPF1DPD | Opcode::VGATHERPF1DPS | Opcode::VGATHERPF1QPD | Opcode::VGATHERPF1QPS | Opcode::VSCATTERDD | Opcode::VSCATTERDQ | Opcode::VSCATTERQD | Opcode::VSCATTERQQ | Opcode::VPSCATTERDD | Opcode::VPSCATTERDQ | Opcode::VPSCATTERQD | Opcode::VPSCATTERQQ | Opcode::VSCATTERPF0DPD | Opcode::VSCATTERPF0DPS | Opcode::VSCATTERPF0QPD | Opcode::VSCATTERPF0QPS | Opcode::VSCATTERPF1DPD | Opcode::VSCATTERPF1DPS | Opcode::VSCATTERPF1QPD | Opcode::VSCATTERPF1QPS | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::INSERTPS | Opcode::VEXTRACTF32X4 | Opcode::VEXTRACTF64X2 | Opcode::VEXTRACTF64X4 | Opcode::VEXTRACTI32X4 | Opcode::VEXTRACTI64X2 | Opcode::VEXTRACTI64X4 | Opcode::VINSERTF32X4 | Opcode::VINSERTF64X2 | Opcode::VINSERTF64X4 | Opcode::VINSERTI64X2 | Opcode::VINSERTI64X4 | Opcode::VSHUFF32X4 | Opcode::VSHUFF64X2 | Opcode::VSHUFI32X4 | Opcode::VSHUFI64X2 | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::MOVDIR64B | Opcode::MOVDIRI | Opcode::MOVNTDQA | Opcode::VMOVQ | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMOVSD | Opcode::VMOVSS | Opcode::VMOVDQA32 | Opcode::VMOVDQA64 | Opcode::VMOVDQU32 | Opcode::VMOVDQU64 | Opcode::VPMOVM2B | Opcode::VPMOVM2W | Opcode::VPMOVB2M | Opcode::VPMOVW2M | Opcode::VPMOVSWB | Opcode::VPMOVUSWB | Opcode::VPMOVSQB | Opcode::VPMOVUSQB | Opcode::VPMOVSQW | Opcode::VPMOVUSQW | Opcode::VPMOVSQD | Opcode::VPMOVUSQD | Opcode::VPMOVSDB | Opcode::VPMOVUSDB | Opcode::VPMOVSDW | Opcode::VPMOVUSDW | Opcode::VPMOVM2D | Opcode::VPMOVM2Q | Opcode::VPMOVB2D | Opcode::VPMOVQ2M | Opcode::VMOVDQU8 | Opcode::VMOVDQU16 | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPCLMULQDQ | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::PMOVSXBD | Opcode::PMOVSXBQ | Opcode::PMOVSXBW | Opcode::PMOVSXDQ | Opcode::PMOVSXWD | Opcode::PMOVSXWQ | Opcode::PMOVZXBD | Opcode::PMOVZXBQ | Opcode::PMOVZXBW | Opcode::PMOVZXDQ | Opcode::PMOVZXWD | Opcode::PMOVZXWQ | Opcode::KUNPCKBW | Opcode::KUNPCKWD | Opcode::KUNPCKDQ | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::PACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VALIGND | Opcode::VALIGNQ | Opcode::VPALIGNR | Opcode::PALIGNR | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPERMI2D | Opcode::VPERMI2Q | Opcode::VPERMI2PD | Opcode::VPERMI2PS | Opcode::VPERMT2D | Opcode::VPERMT2Q | Opcode::VPERMT2PD | Opcode::VPERMT2PS | Opcode::VPERMI2B | Opcode::VPERMI2W | Opcode::VPERMW | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::PEXTRB | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::EXTRQ | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::INSERTQ | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VCOMPRESSPD | Opcode::VCOMPRESSPS | Opcode::VPCOMPRESSQ | Opcode::VPCOMPRESSD | Opcode::VEXPANDPD | Opcode::VEXPANDPS | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPHMINPOSUW | Opcode::PHMINPOSUW | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VFIXUPIMMPD | Opcode::VFIXUPIMMPS | Opcode::VFIXUPIMMSD | Opcode::VFIXUPIMMSS | Opcode::VREDUCEPD | Opcode::VREDUCEPS | Opcode::VREDUCESD | Opcode::VREDUCESS | Opcode::VGETEXPPD | Opcode::VGETEXPPS | Opcode::VGETEXPSD | Opcode::VGETEXPSS | Opcode::VGETMANTPD | Opcode::VGETMANTPS | Opcode::VGETMANTSD | Opcode::VGETMANTSS | Opcode::VLDDQU | Opcode::BSWAP | Opcode::CVTDQ2PD | Opcode::CVTDQ2PS | Opcode::CVTPS2DQ | Opcode::CVTPD2DQ | Opcode::CVTPI2PS | Opcode::CVTPI2PD | Opcode::CVTPS2PD | Opcode::CVTPD2PS | Opcode::CVTPS2PI | Opcode::CVTPD2PI | Opcode::CVTSD2SI | Opcode::CVTSD2SS | Opcode::CVTSI2SD | Opcode::CVTSI2SS | Opcode::CVTSS2SD | Opcode::CVTSS2SI | Opcode::CVTTPD2DQ | Opcode::CVTTPS2DQ | Opcode::CVTTPS2PI | Opcode::CVTTPD2PI | Opcode::CVTTSD2SI | Opcode::CVTTSS2SI | Opcode::MASKMOVQ | Opcode::MASKMOVDQU | Opcode::MOVAPS | Opcode::MOVAPD | Opcode::MOVD | Opcode::MOVHPS | Opcode::MOVHPD | Opcode::MOVHLPS | Opcode::MOVLPS | Opcode::MOVLPD | Opcode::MOVLHPS | Opcode::MOVMSKPS | Opcode::MOVMSKPD | Opcode::MOVNTI | Opcode::MOVNTPS | Opcode::MOVNTPD | Opcode::MOVNTSS | Opcode::MOVNTSD | Opcode::MOVNTQ | Opcode::MOVNTDQ | Opcode::MOVSD | Opcode::MOVSS | Opcode::MOVUPD | Opcode::PSHUFHW | Opcode::PSHUFLW | Opcode::PUNPCKHBW | Opcode::PUNPCKHDQ | Opcode::PUNPCKHWD | Opcode::PUNPCKLBW | Opcode::PUNPCKLDQ | Opcode::PUNPCKLWD | Opcode::PUNPCKLQDQ | Opcode::PUNPCKHQDQ | Opcode::PACKSSDW | Opcode::PACKSSWB | Opcode::PACKUSWB | Opcode::UNPCKHPS | Opcode::UNPCKHPD | Opcode::UNPCKLPS | Opcode::UNPCKLPD | Opcode::SHUFPD | Opcode::SHUFPS | Opcode::PMOVMSKB | Opcode::KMOVB | Opcode::KMOVW | Opcode::KMOVD | Opcode::KMOVQ | Opcode::BNDMOV | Opcode::LDDQU | Opcode::CMC | Opcode::CLC | Opcode::CLI | Opcode::CLD | Opcode::STC | Opcode::STI | Opcode::STD | Opcode::CBW | Opcode::CWDE | Opcode::CDQE | Opcode::CWD | Opcode::CDQ | Opcode::CQO | Opcode::MOVDDUP | Opcode::MOVSLDUP | Opcode::MOVDQ2Q | Opcode::MOVDQU | Opcode::MOVDQA | Opcode::MOVQ | Opcode::MOVQ2DQ | Opcode::MOVSHDUP | Opcode::MOVUPS | Opcode::PEXTRW | Opcode::PINSRW | Opcode::MOV | Opcode::MOVBE | Opcode::LODS | Opcode::STOS | Opcode::LAHF | Opcode::SAHF | Opcode::MOVS | Opcode::INS | Opcode::IN | Opcode::OUTS | Opcode::OUT | Opcode::MOVZX | Opcode::MOVSX | Opcode::MOVSXD | Opcode::FILD | Opcode::FBLD | Opcode::FBSTP | Opcode::FIST | Opcode::FISTP | Opcode::FISTTP | Opcode::FLD | Opcode::FLD1 | Opcode::FLDCW | Opcode::FLDENV | Opcode::FLDL2E | Opcode::FLDL2T | Opcode::FLDLG2 | Opcode::FLDLN2 | Opcode::FLDPI | Opcode::FLDZ | Opcode::FST | Opcode::FSTP | Opcode::FSTPNCE | Opcode::FNSAVE | Opcode::FNSTCW | Opcode::FNSTENV | Opcode::FNSTOR | Opcode::FNSTSW | Opcode::FRSTOR | Opcode::FXCH | Opcode::XCHG | Opcode::XLAT | Opcode::CMOVA | Opcode::CMOVB | Opcode::CMOVG | Opcode::CMOVGE | Opcode::CMOVL | Opcode::CMOVLE | Opcode::CMOVNA | Opcode::CMOVNB | Opcode::CMOVNO | Opcode::CMOVNP | Opcode::CMOVNS | Opcode::CMOVNZ | Opcode::CMOVO | Opcode::CMOVP | Opcode::CMOVS | Opcode::CMOVZ | Opcode::FCMOVB | Opcode::FCMOVBE | Opcode::FCMOVE | Opcode::FCMOVNB | Opcode::FCMOVNBE | Opcode::FCMOVNE | Opcode::FCMOVNU | Opcode::FCMOVU | Opcode::SALC | Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETBE | Opcode::SETA | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETLE | Opcode::SETG => { write!(out, "{}", colors.data_op(self)) } Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::KORTESTB | Opcode::KTESTB | Opcode::KORTESTW | Opcode::KTESTW | Opcode::KORTESTD | Opcode::KTESTD | Opcode::KORTESTQ | Opcode::KTESTQ | Opcode::VPTESTNMD | Opcode::VPTESTNMQ | Opcode::VPTERNLOGD | Opcode::VPTERNLOGQ | Opcode::VPTESTMD | Opcode::VPTESTMQ | Opcode::VPTESTNMB | Opcode::VPTESTNMW | Opcode::VPTESTMB | Opcode::VPTESTMW | Opcode::VPCMPD | Opcode::VPCMPUD | Opcode::VPCMPQ | Opcode::VPCMPUQ | Opcode::VPCMPB | Opcode::VPCMPUB | Opcode::VPCMPW | Opcode::VPCMPUW | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VPMAXSQ | Opcode::VPMAXUQ | Opcode::VPMINSQ | Opcode::VPMINUQ | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VFPCLASSPD | Opcode::VFPCLASSPS | Opcode::VFPCLASSSD | Opcode::VFPCLASSSS | Opcode::VRANGEPD | Opcode::VRANGEPS | Opcode::VRANGESD | Opcode::VRANGESS | Opcode::VPCONFLICTD | Opcode::VPCONFLICTQ | Opcode::VPTEST | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::PCMPEQB | Opcode::PCMPEQD | Opcode::PCMPEQQ | Opcode::PCMPEQW | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPGTB | Opcode::PCMPGTD | Opcode::PCMPGTQ | Opcode::PCMPGTW | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PTEST | Opcode::MAXPD | Opcode::MAXPS | Opcode::MAXSD | Opcode::MAXSS | Opcode::MINPD | Opcode::MINPS | Opcode::MINSD | Opcode::MINSS | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::PMAXSW | Opcode::PMAXUB | Opcode::PMAXUD | Opcode::PMAXUW | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMINSW | Opcode::PMINUB | Opcode::PMINUD | Opcode::PMINUW | Opcode::PFCMPGE | Opcode::PFMIN | Opcode::PFCMPGT | Opcode::PFMAX | Opcode::PFCMPEQ | Opcode::CMPS | Opcode::SCAS | Opcode::TEST | Opcode::FTST | Opcode::FXAM | Opcode::FUCOM | Opcode::FUCOMI | Opcode::FUCOMIP | Opcode::FUCOMP | Opcode::FUCOMPP | Opcode::FCOM | Opcode::FCOMI | Opcode::FCOMIP | Opcode::FCOMP | Opcode::FCOMPP | Opcode::FICOM | Opcode::FICOMP | Opcode::CMPSD | Opcode::CMPSS | Opcode::CMP | Opcode::CMPPS | Opcode::CMPPD | Opcode::CMPXCHG8B | Opcode::CMPXCHG16B | Opcode::CMPXCHG => { write!(out, "{}", colors.comparison_op(self)) } Opcode::WRMSR | Opcode::RDMSR | Opcode::RDTSC | Opcode::RDPMC | Opcode::RDPID | Opcode::RDFSBASE | Opcode::RDGSBASE | Opcode::WRFSBASE | Opcode::WRGSBASE | Opcode::FXSAVE | Opcode::FXRSTOR | Opcode::LDMXCSR | Opcode::STMXCSR | Opcode::VLDMXCSR | Opcode::VSTMXCSR | Opcode::XSAVE | Opcode::XSAVEC | Opcode::XSAVES | Opcode::XSAVEC64 | Opcode::XSAVES64 | Opcode::XRSTOR | Opcode::XRSTORS | Opcode::XRSTORS64 | Opcode::XSAVEOPT | Opcode::LFENCE | Opcode::MFENCE | Opcode::SFENCE | Opcode::CLFLUSH | Opcode::CLFLUSHOPT | Opcode::CLWB | Opcode::LDS | Opcode::LES | Opcode::SGDT | Opcode::SIDT | Opcode::LGDT | Opcode::LIDT | Opcode::SMSW | Opcode::LMSW | Opcode::SWAPGS | Opcode::RDTSCP | Opcode::INVEPT | Opcode::INVVPID | Opcode::INVPCID | Opcode::INVLPG | Opcode::INVLPGA | Opcode::INVLPGB | Opcode::TLBSYNC | Opcode::PSMASH | Opcode::PVALIDATE | Opcode::RMPADJUST | Opcode::RMPUPDATE | Opcode::CPUID | Opcode::WBINVD | Opcode::INVD | Opcode::SYSRET | Opcode::CLTS | Opcode::SYSCALL | Opcode::TDCALL | Opcode::SEAMRET | Opcode::SEAMOPS | Opcode::SEAMCALL | Opcode::TPAUSE | Opcode::UMONITOR | Opcode::UMWAIT | Opcode::LSL | Opcode::SLDT | Opcode::STR | Opcode::LLDT | Opcode::LTR | Opcode::VERR | Opcode::VERW | Opcode::JMPE | Opcode::EMMS | Opcode::FEMMS | Opcode::GETSEC | Opcode::LFS | Opcode::LGS | Opcode::LSS | Opcode::RSM | Opcode::SYSENTER | Opcode::SYSEXIT | Opcode::VMREAD | Opcode::VMWRITE | Opcode::VMCLEAR | Opcode::VMPTRLD | Opcode::VMPTRST | Opcode::VMXON | Opcode::VMCALL | Opcode::VMLAUNCH | Opcode::VMRESUME | Opcode::VMLOAD | Opcode::VMMCALL | Opcode::VMSAVE | Opcode::VMRUN | Opcode::VMXOFF | Opcode::PCONFIG | Opcode::MONITOR | Opcode::MWAIT | Opcode::MONITORX | Opcode::MWAITX | Opcode::SKINIT | Opcode::CLGI | Opcode::STGI | Opcode::CLAC | Opcode::STAC | Opcode::ENCLS | Opcode::ENCLV | Opcode::XGETBV | Opcode::XSETBV | Opcode::VMFUNC | Opcode::XEND | Opcode::XTEST | Opcode::XABORT | Opcode::XBEGIN | Opcode::ENCLU | Opcode::RDPKRU | Opcode::WRPKRU | Opcode::RDPRU | Opcode::CLZERO | Opcode::ENQCMD | Opcode::ENQCMDS | Opcode::PTWRITE | Opcode::UIRET | Opcode::TESTUI | Opcode::CLUI | Opcode::STUI | Opcode::SENDUIPI | Opcode::XSUSLDTRK | Opcode::XRESLDTRK | Opcode::BOUND | Opcode::ARPL | Opcode::BNDMK | Opcode::BNDCL | Opcode::BNDCU | Opcode::BNDCN | Opcode::BNDLDX | Opcode::BNDSTX | Opcode::LAR => { write!(out, "{}", colors.platform_op(self)) } Opcode::CRC32 | Opcode::RDSEED | Opcode::RDRAND | Opcode::SHA1RNDS4 | Opcode::SHA1NEXTE | Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA256RNDS2 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::FFREE | Opcode::FFREEP | Opcode::FDECSTP | Opcode::FINCSTP | Opcode::GF2P8MULB | Opcode::GF2P8AFFINEQB | Opcode::GF2P8AFFINEINVQB | Opcode::AESDEC128KL | Opcode::AESDEC256KL | Opcode::AESDECWIDE128KL | Opcode::AESDECWIDE256KL | Opcode::AESENC128KL | Opcode::AESENC256KL | Opcode::AESENCWIDE128KL | Opcode::AESENCWIDE256KL | Opcode::ENCODEKEY128 | Opcode::ENCODEKEY256 | Opcode::LOADIWKEY | Opcode::HRESET | Opcode::WRUSS | Opcode::WRSS | Opcode::INCSSP | Opcode::SAVEPREVSSP | Opcode::SETSSBSY | Opcode::CLRSSBSY | Opcode::RSTORSSP | Opcode::ENDBR64 | Opcode::ENDBR32 | Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST | Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { write!(out, "{}", colors.misc_op(self)) } Opcode::UD0 | Opcode::UD1 | Opcode::UD2 | Opcode::Invalid => { write!(out, "{}", colors.invalid_op(self)) } } } } impl fmt::Display for Instruction { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.display_with(DisplayStyle::Intel).colorize(&NoColors, fmt) } } impl<'instr> fmt::Display for InstructionDisplayer<'instr> { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } /// enum controlling how `Instruction::display_with` renders instructions. `Intel` is more or less /// intel syntax, though memory operand sizes are elided if they can be inferred from other /// operands. #[derive(Copy, Clone)] pub enum DisplayStyle { /// intel-style syntax for instructions, like /// `add eax, [edx + ecx * 2 + 0x1234]` Intel, /// C-style syntax for instructions, like /// `eax += [edx + ecx * 2 + 0x1234]` C, // one might imagine an ATT style here, which is mostly interesting for reversing operand // order. // well. // it also complicates memory operands in an offset-only operand, and is just kind of awful, so // it's just not implemented yet. // ATT, } /// implementation of [`Display`](fmt::Display) that renders instructions using a specified display /// style. pub struct InstructionDisplayer<'instr> { pub(crate) instr: &'instr Instruction, pub(crate) style: DisplayStyle, } /* * Can't implement this as accepting a formatter because rust * doesn't let me build one outside println! or write! or whatever. * * can't write this as an intermediate struct because i refuse to copy * all data into the struct, and having a function producing a struct with * some lifetimes gets really hairy if it's from a trait - same GAT kind * of nonsense as i saw with ContextRead, because someone could hold onto * the dang intermediate struct forever. * * so write to some Write thing i guess. bite me. i really just want to * stop thinking about how to support printing instructions... */ impl <'instr, T: fmt::Write, Y: YaxColors> Colorize for InstructionDisplayer<'instr> { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { // TODO: I DONT LIKE THIS, there is no address i can give contextualize here, // the address operand maybe should be optional.. self.contextualize(colors, 0, Some(&NoContext), out) } } /// No per-operand context when contextualizing an instruction! struct NoContext; impl Instruction { pub fn write_to(&self, out: &mut T) -> fmt::Result { self.display_with(DisplayStyle::Intel).contextualize(&NoColors, 0, Some(&NoContext), out) } } fn contextualize_intel(instr: &Instruction, colors: &Y, _address: u32, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { if instr.xacquire() { out.write_str("xacquire ")?; } if instr.xrelease() { out.write_str("xrelease ")?; } if instr.prefixes.lock() { out.write_str("lock ")?; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { if instr.prefixes.rep() { write!(out, "rep ")?; } else if instr.prefixes.repnz() { write!(out, "repnz ")?; } } } out.write_str(instr.opcode.name())?; if instr.opcode == Opcode::XBEGIN { if (instr.imm as i32) >= 0 { return write!(out, " $+{}", colors.number(signed_i32_hex(instr.imm as i32))); } else { return write!(out, " ${}", colors.number(signed_i32_hex(instr.imm as i32))); } } if instr.operand_count > 0 { out.write_str(" ")?; let x = Operand::from_spec(instr, instr.operands[0]); const RELATIVE_BRANCHES: [Opcode; 21] = [ Opcode::JMP, Opcode::JECXZ, Opcode::LOOP, Opcode::LOOPZ, Opcode::LOOPNZ, Opcode::JO, Opcode::JNO, Opcode::JB, Opcode::JNB, Opcode::JZ, Opcode::JNZ, Opcode::JNA, Opcode::JA, Opcode::JS, Opcode::JNS, Opcode::JP, Opcode::JNP, Opcode::JL, Opcode::JGE, Opcode::JLE, Opcode::JG, ]; if instr.operands[0] == OperandSpec::ImmI8 || instr.operands[0] == OperandSpec::ImmI32 { if RELATIVE_BRANCHES.contains(&instr.opcode) { return match x { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } _ => { unreachable!() } }; } } if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; for i in 1..instr.operand_count { match instr.opcode { _ => { match &instr.operands[i as usize] { &OperandSpec::Nothing => { return Ok(()); }, _ => { out.write_str(", ")?; let x = Operand::from_spec(instr, instr.operands[i as usize]); if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(i) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; if let Some(evex) = instr.prefixes.evex() { if evex.broadcast() && x.is_memory() { let scale = if instr.opcode == Opcode::VCVTPD2PS || instr.opcode == Opcode::VCVTTPD2UDQ || instr.opcode == Opcode::VCVTPD2UDQ || instr.opcode == Opcode::VCVTUDQ2PD || instr.opcode == Opcode::VCVTPS2PD || instr.opcode == Opcode::VCVTQQ2PS || instr.opcode == Opcode::VCVTDQ2PD || instr.opcode == Opcode::VCVTTPD2DQ || instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VFPCLASSPD || instr.opcode == Opcode::VCVTNEPS2BF16 || instr.opcode == Opcode::VCVTUQQ2PS || instr.opcode == Opcode::VCVTPD2DQ || instr.opcode == Opcode::VCVTTPS2UQQ || instr.opcode == Opcode::VCVTPS2UQQ || instr.opcode == Opcode::VCVTTPS2QQ || instr.opcode == Opcode::VCVTPS2QQ { if instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VCVTNEPS2BF16 { if evex.vex().l() { 8 } else if evex.lp() { 16 } else { 4 } } else if instr.opcode == Opcode::VFPCLASSPD { if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } else { // vcvtpd2ps is "cool": in broadcast mode, it can read a // double-precision float (qword), resize to single-precision, // then broadcast that to the whole destination register. this // means we need to show `xmm, qword [addr]{1to4}` if vector // size is 256. likewise, scale of 8 for the same truncation // reason if vector size is 512. // vcvtudq2pd is the same story. // vfpclassp{s,d} is a mystery to me. if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } } else { // this should never be `None` - that would imply two // memory operands for a broadcasted operation. if let Some(width) = Operand::from_spec(instr, instr.operands[i as usize - 1]).width() { width / instr.mem_size } else { 0 } }; write!(out, "{{1to{}}}", scale)?; } } } } } } } } Ok(()) } fn contextualize_c(instr: &Instruction, colors: &Y, _address: u32, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { let mut brace_count = 0; let mut prefixed = false; if instr.xacquire() { out.write_str("xacquire ")?; prefixed = true; } if instr.xrelease() { out.write_str("xrelease ")?; prefixed = true; } if instr.prefixes.lock() { out.write_str("lock ")?; prefixed = true; } if prefixed { out.write_str("{ ")?; brace_count += 1; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { let word_str = match instr.mem_size { 1 => "byte", 2 => "word", 4 => "dword", 8 => "qword", _ => { unreachable!("invalid word size") } }; // only a few of you actually use the prefix... if instr.prefixes.rep() { out.write_str("rep ")?; } else if instr.prefixes.repnz() { out.write_str("repnz ")?; } // TODO: other rep kinds? out.write_str(word_str)?; out.write_str(" { ")?; brace_count += 1; } } fn write_jmp_operand(op: Operand, colors: &Y, out: &mut T) -> fmt::Result { match op { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } other => { write!(out, "{}", other) } } } match instr.opcode { Opcode::Invalid => { out.write_str("invalid")?; }, Opcode::MOVS => { out.write_str("es:[edi++] = ds:[esi++]")?; }, Opcode::CMPS => { out.write_str("eflags = flags(ds:[esi++] - es:[edi++])")?; }, Opcode::LODS => { // TODO: size out.write_str("rax = ds:[esi++]")?; }, Opcode::STOS => { // TODO: size out.write_str("es:[edi++] = rax")?; }, Opcode::INS => { // TODO: size out.write_str("es:[edi++] = port(dx)")?; }, Opcode::OUTS => { // TODO: size out.write_str("port(dx) = ds:[esi++]")?; } Opcode::ADD => { write!(out, "{} += {}", instr.operand(0), instr.operand(1))?; } Opcode::OR => { write!(out, "{} |= {}", instr.operand(0), instr.operand(1))?; } Opcode::ADC => { write!(out, "{} += {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADCX => { write!(out, "{} += {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADOX => { write!(out, "{} += {} + eflags.of", instr.operand(0), instr.operand(1))?; } Opcode::SBB => { write!(out, "{} -= {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::AND => { write!(out, "{} &= {}", instr.operand(0), instr.operand(1))?; } Opcode::XOR => { write!(out, "{} ^= {}", instr.operand(0), instr.operand(1))?; } Opcode::SUB => { write!(out, "{} -= {}", instr.operand(0), instr.operand(1))?; } Opcode::CMP => { write!(out, "eflags = flags({} - {})", instr.operand(0), instr.operand(1))?; } Opcode::TEST => { write!(out, "eflags = flags({} & {})", instr.operand(0), instr.operand(1))?; } Opcode::XADD => { write!(out, "({}, {}) = ({} + {}, {})", instr.operand(0), instr.operand(1), instr.operand(0), instr.operand(1), instr.operand(0))?; } Opcode::BT => { write!(out, "bt")?; } Opcode::BTS => { write!(out, "bts")?; } Opcode::BTC => { write!(out, "btc")?; } Opcode::BSR => { write!(out, "{} = msb({})", instr.operand(0), instr.operand(1))?; } Opcode::BSF => { write!(out, "{} = lsb({}) (x86 bsf)", instr.operand(0), instr.operand(1))?; } Opcode::TZCNT => { write!(out, "{} = lsb({})", instr.operand(0), instr.operand(1))?; } Opcode::MOV => { write!(out, "{} = {}", instr.operand(0), instr.operand(1))?; } Opcode::SAR => { write!(out, "{} = {} >>> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SAL => { write!(out, "{} = {} <<< {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHR => { write!(out, "{} = {} >> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHRX => { write!(out, "{} = {} >> {} (x86 shrx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::SHL => { write!(out, "{} = {} << {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHLX => { write!(out, "{} = {} << {} (x86 shlx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROR => { write!(out, "{} = {} ror {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RORX => { write!(out, "{} = {} ror {} (x86 rorx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROL => { write!(out, "{} = {} rol {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCR => { write!(out, "{} = {} rcr {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCL => { write!(out, "{} = {} rcl {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::PUSH => { write!(out, "push({})", instr.operand(0))?; } Opcode::POP => { write!(out, "{} = pop()", instr.operand(0))?; } Opcode::MOVD => { write!(out, "{} = movd({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVQ => { write!(out, "{} = movq({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVNTQ => { write!(out, "{} = movntq({})", instr.operand(0), instr.operand(1))?; } Opcode::INC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}++", instr.operand(0))?; }, 2 => { write!(out, "word {}++", instr.operand(0))?; }, 4 => { write!(out, "dword {}++", instr.operand(0))?; }, _ => { write!(out, "qword {}++", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}++", instr.operand(0))?; } } Opcode::DEC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}--", instr.operand(0))?; }, 2 => { write!(out, "word {}--", instr.operand(0))?; }, 4 => { write!(out, "dword {}--", instr.operand(0))?; }, _ => { write!(out, "qword {}--", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}--", instr.operand(0))?; } } Opcode::JMP => { out.write_str("jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JECXZ => { out.write_str("if ecx == 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOP => { out.write_str("ecx--; if ecx != 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPZ => { out.write_str("ecx--; if ecx != 0 and zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPNZ => { out.write_str("ecx--; if ecx != 0 and !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JB => { out.write_str("if /* unsigned */ below(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNB => { out.write_str("if /* unsigned */ above_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JZ => { out.write_str("if zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNZ => { out.write_str("if !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNA => { out.write_str("if /* unsigned */ below_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JA => { out.write_str("if /* unsigned */ above(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JS => { out.write_str("if signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNS => { out.write_str("if !signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JP => { out.write_str("if parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNP => { out.write_str("if !parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JL => { out.write_str("if /* signed */ less(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JGE => { out.write_str("if /* signed */ greater_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JLE => { out.write_str("if /* signed */ less_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JG => { out.write_str("if /* signed */ greater(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::NOP => { write!(out, "nop")?; } _ => { if instr.operand_count() == 0 { write!(out, "{}()", instr.opcode())?; } else { write!(out, "{} = {}({}", instr.operand(0), instr.opcode(), instr.operand(0))?; let mut comma = true; for i in 1..instr.operand_count() { if comma { write!(out, ", ")?; } write!(out, "{}", instr.operand(i))?; comma = true; } write!(out, ")")?; } } } while brace_count > 0 { out.write_str(" }")?; brace_count -= 1; } Ok(()) } impl <'instr, T: fmt::Write, Y: YaxColors> ShowContextual for InstructionDisplayer<'instr> { fn contextualize(&self, colors: &Y, address: u32, context: Option<&NoContext>, out: &mut T) -> fmt::Result { let InstructionDisplayer { instr, style, } = self; match style { DisplayStyle::Intel => { contextualize_intel(instr, colors, address, context, out) } DisplayStyle::C => { contextualize_c(instr, colors, address, context, out) } } } } #[cfg(feature="std")] impl ShowContextual], T, Y> for Instruction { fn contextualize(&self, colors: &Y, _address: u64, context: Option<&[Option]>, out: &mut T) -> fmt::Result { if self.prefixes.lock() { write!(out, "lock ")?; } if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&self.opcode) { // only a few of you actually use the prefix... if self.prefixes.rep() { write!(out, "rep ")?; } else if self.prefixes.repnz() { write!(out, "repnz ")?; } } self.opcode.colorize(colors, out)?; match context.and_then(|xs| xs[0].as_ref()) { Some(s) => { write!(out, " {}", s)?; }, None => { match self.operands[0] { OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, " ")?; if let Some(prefix) = self.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } } } let x = Operand::from_spec(self, self.operands[0]); x.colorize(colors, out)?; } }; for i in 1..self.operand_count { let i = i as usize; match context.and_then(|xs| xs[i].as_ref()) { Some(s) => { write!(out, ", {}", s)? } None => { match &self.operands[i] { &OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, ", ")?; if let Some(prefix) = self.segment_override_for_op(1) { write!(out, "{}:", prefix)?; } let x = Operand::from_spec(self, self.operands[i]); x.colorize(colors, out)? } } } } } Ok(()) } } yaxpeax-x86-1.2.2/src/protected_mode/evex.rs000064400000000000000000000010011046102023000170210ustar 00000000000000// use crate::long_mode::{OperandSpec, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::protected_mode::{Arch, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::protected_mode::{read_modrm, read_E_vex, read_imm_unsigned}; use yaxpeax_arch::Reader; const DEFAULT_EVEX_REGISTER_SIZE: RegisterBank = RegisterBank::D; const DEFAULT_EVEX_REGISTER_WIDTH: u8 = 4; fn isa_has_qwords() -> bool { false } include!("../shared/generated_evex.in"); include!("../shared/evex.in"); yaxpeax-x86-1.2.2/src/protected_mode/mod.rs000064400000000000000000016614161046102023000166600ustar 00000000000000mod vex; mod evex; #[cfg(feature = "fmt")] mod display; pub mod uarch; pub use crate::MemoryAccessSize; #[cfg(feature = "fmt")] pub use self::display::{DisplayStyle, InstructionDisplayer}; use core::cmp::PartialEq; use crate::safer_unchecked::unreachable_kinda_unchecked as unreachable_unchecked; use yaxpeax_arch::{AddressDiff, Decoder, Reader, LengthedInstruction}; use yaxpeax_arch::annotation::{AnnotatingDecoder, DescriptionSink, NullSink}; use yaxpeax_arch::{DecodeError as ArchDecodeError}; use core::fmt; impl fmt::Display for DecodeError { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.description()) } } /// an `x86` register, including its number and type. if `fmt` is enabled, name too. /// /// ``` /// use yaxpeax_x86::long_mode::{RegSpec, register_class}; /// /// assert_eq!(RegSpec::ecx().num(), 1); /// assert_eq!(RegSpec::ecx().class(), register_class::D); /// ``` /// /// some registers have classes of their own, and only one member: `eip` and `eflags`. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, PartialOrd, Ord, Eq, PartialEq)] pub struct RegSpec { num: u8, bank: RegisterBank } use core::hash::Hash; use core::hash::Hasher; impl Hash for RegSpec { fn hash(&self, state: &mut H) { let code = ((self.bank as u16) << 8) | (self.num as u16); code.hash(state); } } /// the condition for a conditional instruction. /// /// these are only obtained through [`Opcode::condition()`]: /// ``` /// use yaxpeax_x86::long_mode::{Opcode, ConditionCode}; /// /// assert_eq!(Opcode::JB.condition(), Some(ConditionCode::B)); /// ``` #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] pub enum ConditionCode { O, NO, B, AE, Z, NZ, A, BE, S, NS, P, NP, L, GE, G, LE, } macro_rules! register { ($bank:ident, $name:ident => $num:expr, $($tail:tt)+) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } register!($bank, $($tail)*); }; ($bank:ident, $name:ident => $num:expr) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } }; } #[allow(non_snake_case)] impl RegSpec { /// the register `eip`. this register is in the class `eip`, which contains only it. pub const EIP: RegSpec = RegSpec::eip(); /// the number of this register in its `RegisterClass`. /// /// for many registers this is a number in the name, but for registers harkening back to /// `x86_32`, the first eight registers are `rax`, `rcx`, `rdx`, `rbx`, `rsp`, `rbp`, `rsi`, /// and `rdi` (or `eXX` for the 32-bit forms, `XX` for 16-bit forms). pub fn num(&self) -> u8 { self.num } /// the class of register this register is in. /// /// this corresponds to the register's size, but is by the register's usage in the instruction /// set; `rax` and `mm0` are the same size, but different classes (`Q`(word) and `MM` (mmx) /// respectively). pub fn class(&self) -> RegisterClass { RegisterClass { kind: self.bank } } #[cfg(feature = "fmt")] /// return a human-friendly name for this register. the returned name is the same as would be /// used to render this register in an instruction. pub fn name(&self) -> &'static str { display::regspec_label(self) } /// construct a `RegSpec` for x87 register `st(num)` #[inline] pub fn st(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x87 reg st({})", num); } RegSpec { num, bank: RegisterBank::ST } } /// construct a `RegSpec` for xmm reg `num` #[inline] pub fn xmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 xmm reg {}", num); } RegSpec { num, bank: RegisterBank::X } } /// construct a `RegSpec` for ymm reg `num` #[inline] pub fn ymm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 ymm reg {}", num); } RegSpec { num, bank: RegisterBank::Y } } /// construct a `RegSpec` for zmm reg `num` #[inline] pub fn zmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 zmm reg {}", num); } RegSpec { num, bank: RegisterBank::Z } } /// construct a `RegSpec` for mask reg `num` #[inline] pub fn mask(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 mask reg {}", num); } RegSpec { num, bank: RegisterBank::K } } /// construct a `RegSpec` for dword reg `num` #[inline] pub fn d(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 dword reg {}", num); } RegSpec { num, bank: RegisterBank::D } } /// construct a `RegSpec` for word reg `num` #[inline] pub fn w(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 word reg {}", num); } RegSpec { num, bank: RegisterBank::W } } /// construct a `RegSpec` for byte reg `num` #[inline] pub fn b(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 byte reg {}", num); } RegSpec { num, bank: RegisterBank::B } } #[inline] fn from_parts(num: u8, bank: RegisterBank) -> RegSpec { RegSpec { num: num, bank: bank } } register!(EIP, eip => 0); register!(EFlags, eflags => 0); register!(S, es => 0, cs => 1, ss => 2, ds => 3, fs => 4, gs => 5); register!(D, eax => 0, ecx => 1, edx => 2, ebx => 3, esp => 4, ebp => 5, esi => 6, edi => 7 ); register!(W, ax => 0, cx => 1, dx => 2, bx => 3, sp => 4, bp => 5, si => 6, di => 7 ); register!(B, al => 0, cl => 1, dl => 2, bl => 3, ah => 4, ch => 5, dh => 6, bh => 7 ); #[inline] pub const fn zmm0() -> RegSpec { RegSpec { bank: RegisterBank::Z, num: 0 } } #[inline] pub const fn ymm0() -> RegSpec { RegSpec { bank: RegisterBank::Y, num: 0 } } #[inline] pub const fn xmm0() -> RegSpec { RegSpec { bank: RegisterBank::X, num: 0 } } #[inline] pub const fn st0() -> RegSpec { RegSpec { bank: RegisterBank::ST, num: 0 } } #[inline] pub const fn mm0() -> RegSpec { RegSpec { bank: RegisterBank::MM, num: 0 } } /// return the size of this register, in bytes #[inline] pub fn width(&self) -> u8 { self.class().width() } } #[allow(non_camel_case_types)] #[allow(dead_code)] enum SizeCode { b, vd, } /// an operand for an `x86` instruction. /// /// `Operand::Nothing` should be unreachable in practice; any such instructions should have an /// operand count of 0 (or at least one fewer than the `Nothing` operand's position). #[derive(Clone, Debug, PartialEq)] #[non_exhaustive] pub enum Operand { /// a sign-extended byte ImmediateI8(i8), /// a zero-extended byte ImmediateU8(u8), /// a sign-extended word ImmediateI16(i16), /// a zero-extended word ImmediateU16(u16), /// a sign-extended dword ImmediateI32(i32), /// a zero-extended dword ImmediateU32(u32), /// a bare register operand, such as `rcx`. Register(RegSpec), /// an `avx512` register operand with optional mask register and merge mode, such as /// `zmm3{k4}{z}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMerge(RegSpec, RegSpec, MergeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, such as `zmm3{k4}{z}{rd-sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSae(RegSpec, RegSpec, MergeMode, SaeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, with no overridden rounding mode, such as `zmm3{k4}{z}{sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSaeNoround(RegSpec, RegSpec, MergeMode), /// a memory access to a literal word address. it's extremely rare that a well-formed x86 /// instruction uses this mode. as an example, `[0x1133]` DisplacementU16(u16), /// a memory access to a literal qword address. it's relatively rare that a well-formed x86 /// instruction uses this mode, but plausible. for example, `fs:[0x14]`. segment overrides, /// however, are maintained on the instruction itself. DisplacementU32(u32), /// a simple dereference of the address held in some register. for example: `[esi]`. RegDeref(RegSpec), /// a dereference of the address held in some register with offset. for example: `[esi + 0x14]`. RegDisp(RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8. this is almost always used with the `lea` instruction. for example: `[edx * 4]`. RegScale(RegSpec, u8), /// a dereference of the address from summing two registers. for example: `[ebp + rax]` RegIndexBase(RegSpec, RegSpec), /// a dereference of the address from summing two registers with offset. for example: `[edi + ecx + 0x40]` RegIndexBaseDisp(RegSpec, RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8 with offset. this is almost always used with the `lea` instruction. for example: `[eax * 4 + 0x30]`. RegScaleDisp(RegSpec, u8, i32), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8. for /// example: `[esi + ecx * 4]` RegIndexBaseScale(RegSpec, RegSpec, u8), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8, with offset. for /// example: `[esi + ecx * 4 + 0x1234]` RegIndexBaseScaleDisp(RegSpec, RegSpec, u8, i32), /// an `avx512` dereference of register with optional masking. for example: `[edx]{k3}` RegDerefMasked(RegSpec, RegSpec), /// an `avx512` dereference of register plus offset, with optional masking. for example: `[esp + 0x40]{k3}` RegDispMasked(RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8, with optional masking. this /// seems extraordinarily unlikely to occur in practice. for example: `[esi * 4]{k2}` RegScaleMasked(RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional masking. /// for example: `[esi + eax * 4]{k6}` RegIndexBaseMasked(RegSpec, RegSpec, RegSpec), /// an `avx512` dereference of a register plus offset, with optional masking. for example: /// `[esi + eax + 0x1313]{k6}` RegIndexBaseDispMasked(RegSpec, RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8 plus offset, with optional /// masking. this seems extraordinarily unlikely to occur in practice. for example: `[esi * /// 4 + 0x1357]{k2}` RegScaleDispMasked(RegSpec, u8, i32, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional /// masking. for example: `[esi + eax * 4]{k6}` RegIndexBaseScaleMasked(RegSpec, RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8 and offset, with /// optional masking. for example: `[esi + eax * 4 + 0x1313]{k6}` RegIndexBaseScaleDispMasked(RegSpec, RegSpec, u8, i32, RegSpec), /// no operand. it is a bug for `yaxpeax-x86` to construct an `Operand` of this kind for public /// use; the instruction's `operand_count` should be reduced so as to make this invisible to /// library clients. Nothing, /// absolute far call. this is only used for `9a` far calls with absolute `u16:u{16,32}` /// operand, and so only exists in 32- and 16-bit modes. AbsoluteFarAddress { segment: u16, address: u32 }, } impl OperandSpec { fn masked(self) -> Self { match self { OperandSpec::RegRRR => OperandSpec::RegRRR_maskmerge, OperandSpec::RegMMM => OperandSpec::RegMMM_maskmerge, OperandSpec::RegVex => OperandSpec::RegVex_maskmerge, OperandSpec::Deref => OperandSpec::Deref_mask, OperandSpec::RegDisp => OperandSpec::RegDisp_mask, OperandSpec::RegScale => OperandSpec::RegScale_mask, OperandSpec::RegScaleDisp => OperandSpec::RegScaleDisp_mask, OperandSpec::RegIndexBaseScale => OperandSpec::RegIndexBaseScale_mask, OperandSpec::RegIndexBaseScaleDisp => OperandSpec::RegIndexBaseScaleDisp_mask, o => o, } } fn is_memory(&self) -> bool { (*self as u8) & 0x80 != 0 } } /// an `avx512` merging mode. /// /// the behavior for non-`avx512` instructions is equivalent to `merge`. `zero` is only useful in /// conjunction with a mask register, where bits specified in the mask register correspond to /// unmodified items in the instruction's destination. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum MergeMode { Merge, Zero, } impl From for MergeMode { fn from(b: bool) -> Self { if b { MergeMode::Zero } else { MergeMode::Merge } } } /// an `avx512` custom rounding mode. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum SaeMode { RoundNearest, RoundDown, RoundUp, RoundZero, } const SAE_MODES: [SaeMode; 4] = [ SaeMode::RoundNearest, SaeMode::RoundDown, SaeMode::RoundUp, SaeMode::RoundZero, ]; impl SaeMode { /// a human-friendly label for this `SaeMode`: /// /// ``` /// use yaxpeax_x86::long_mode::SaeMode; /// /// assert_eq!(SaeMode::RoundNearest.label(), "{rne-sae}"); /// assert_eq!(SaeMode::RoundDown.label(), "{rd-sae}"); /// assert_eq!(SaeMode::RoundUp.label(), "{ru-sae}"); /// assert_eq!(SaeMode::RoundZero.label(), "{rz-sae}"); /// ``` pub fn label(&self) -> &'static str { match self { SaeMode::RoundNearest => "{rne-sae}", SaeMode::RoundDown => "{rd-sae}", SaeMode::RoundUp => "{ru-sae}", SaeMode::RoundZero => "{rz-sae}", } } fn from(l: bool, lp: bool) -> Self { let mut idx = 0; if l { idx |= 1; } if lp { idx |= 2; } SAE_MODES[idx] } } impl Operand { fn from_spec(inst: &Instruction, spec: OperandSpec) -> Operand { match spec { OperandSpec::Nothing => { Operand::Nothing } // the register in regs[0] OperandSpec::RegRRR => { Operand::Register(inst.regs[0]) } OperandSpec::RegRRR_maskmerge => { Operand::RegisterMaskMerge( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegRRR_maskmerge_sae => { Operand::RegisterMaskMergeSae( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), SaeMode::from(inst.prefixes.evex_unchecked().vex().l(), inst.prefixes.evex_unchecked().lp()), ) } OperandSpec::RegRRR_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } // the register in regs[1] (eg modrm mod bits were 11) OperandSpec::RegMMM => { Operand::Register(inst.regs[1]) } OperandSpec::RegMMM_maskmerge => { Operand::RegisterMaskMerge( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegMMM_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegVex => { Operand::Register(inst.regs[3]) } OperandSpec::RegVex_maskmerge => { Operand::RegisterMaskMerge( inst.regs[3], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::Reg4 => { Operand::Register(RegSpec { num: inst.imm as u8, bank: inst.regs[3].bank }) } OperandSpec::ImmI8 => Operand::ImmediateI8(inst.imm as i8), OperandSpec::ImmU8 => Operand::ImmediateU8(inst.imm as u8), OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16), OperandSpec::ImmU16 => Operand::ImmediateU16(inst.imm as u16), OperandSpec::ImmI32 => Operand::ImmediateI32(inst.imm as i32), OperandSpec::ImmInDispField => Operand::ImmediateU16(inst.disp as u16), OperandSpec::DispU16 => Operand::DisplacementU16(inst.disp as u16), OperandSpec::DispU32 => Operand::DisplacementU32(inst.disp), OperandSpec::Deref => { Operand::RegDeref(inst.regs[1]) } OperandSpec::Deref_si => { Operand::RegDeref(RegSpec::si()) } OperandSpec::Deref_di => { Operand::RegDeref(RegSpec::di()) } OperandSpec::Deref_esi => { Operand::RegDeref(RegSpec::esi()) } OperandSpec::Deref_edi => { Operand::RegDeref(RegSpec::edi()) } OperandSpec::RegDisp => { Operand::RegDisp(inst.regs[1], inst.disp as i32) } OperandSpec::RegScale => { Operand::RegScale(inst.regs[2], inst.scale) } OperandSpec::RegScaleDisp => { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::RegIndexBaseScale => { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } OperandSpec::RegIndexBaseScaleDisp => { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::Deref_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDerefMasked(inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDeref(inst.regs[1]) } } OperandSpec::RegDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDispMasked(inst.regs[1], inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDisp(inst.regs[1], inst.disp as i32) } } OperandSpec::RegScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleMasked(inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScale(inst.regs[2], inst.scale) } } OperandSpec::RegScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleDispMasked(inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } } OperandSpec::RegIndexBaseScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleMasked(inst.regs[1], inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } } OperandSpec::RegIndexBaseScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleDispMasked(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } } OperandSpec::AbsoluteFarAddress => { Operand::AbsoluteFarAddress { segment: inst.disp as u16, address: inst.imm as u32, } } } } /// returns `true` if this operand implies a memory access, `false` otherwise. /// /// notably, the `lea` instruction uses a memory operand without actually ever accessing /// memory. pub fn is_memory(&self) -> bool { match self { Operand::DisplacementU16(_) | Operand::DisplacementU32(_) | Operand::RegDeref(_) | Operand::RegDisp(_, _) | Operand::RegScale(_, _) | Operand::RegIndexBase(_, _) | Operand::RegIndexBaseDisp(_, _, _) | Operand::RegScaleDisp(_, _, _) | Operand::RegIndexBaseScale(_, _, _) | Operand::RegIndexBaseScaleDisp(_, _, _, _) | Operand::RegDerefMasked(_, _) | Operand::RegDispMasked(_, _, _) | Operand::RegScaleMasked(_, _, _) | Operand::RegIndexBaseMasked(_, _, _) | Operand::RegIndexBaseDispMasked(_, _, _, _) | Operand::RegScaleDispMasked(_, _, _, _) | Operand::RegIndexBaseScaleMasked(_, _, _, _) | Operand::RegIndexBaseScaleDispMasked(_, _, _, _, _) => { true }, Operand::ImmediateI8(_) | Operand::ImmediateU8(_) | Operand::ImmediateI16(_) | Operand::ImmediateU16(_) | Operand::ImmediateU32(_) | Operand::ImmediateI32(_) | Operand::Register(_) | Operand::RegisterMaskMerge(_, _, _) | Operand::RegisterMaskMergeSae(_, _, _, _) | Operand::RegisterMaskMergeSaeNoround(_, _, _) | Operand::AbsoluteFarAddress { .. } | Operand::Nothing => { false } } } /// return the width of this operand, in bytes. register widths are determined by the /// register's class. the widths of memory operands are recorded on the instruction this /// `Operand` came from; `None` here means the authoritative width is `instr.mem_size()`. pub fn width(&self) -> Option { match self { Operand::Register(reg) => { Some(reg.width()) } Operand::RegisterMaskMerge(reg, _, _) => { Some(reg.width()) } Operand::ImmediateI8(_) | Operand::ImmediateU8(_) => { Some(1) } Operand::ImmediateI16(_) | Operand::ImmediateU16(_) => { Some(2) } Operand::ImmediateI32(_) | Operand::ImmediateU32(_) => { Some(4) } // memory operands or `Nothing` _ => { None } } } } #[test] fn operand_size() { assert_eq!(core::mem::size_of::(), 1); assert_eq!(core::mem::size_of::(), 2); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 8); // assert_eq!(core::mem::size_of::(), 4); // assert_eq!(core::mem::size_of::(), 40); } /// an `x86` register class - `qword`, `dword`, `xmmword`, `segment`, and so on. /// /// this is mostly useful for comparing a `RegSpec`'s [`RegSpec::class()`] with a constant out of /// [`register_class`]. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] pub struct RegisterClass { kind: RegisterBank, } const REGISTER_CLASS_NAMES: &[&'static str] = &[ "BUG. PLEASE REPORT", "byte", "word", "BUG. PLEASE REPORT", "dword", "cr", "dr", "segment", "xmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "ymm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "zmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "x87-stack", "mmx", "k", "eip", "eflags", ]; /// high-level register classes in an x86 machine, such as "4-byte general purpose", "xmm", "x87", /// and so on. constants in this module are useful for inspecting the register class of a decoded /// instruction. as an example: /// ``` /// use yaxpeax_x86::protected_mode::{self as amd64}; /// use yaxpeax_x86::protected_mode::{Opcode, Operand, RegisterClass}; /// use yaxpeax_arch::{Decoder, U8Reader}; /// /// let movsx_eax_cl = &[0x0f, 0xbe, 0xc1]; /// let decoder = amd64::InstDecoder::default(); /// let instruction = decoder /// .decode(&mut U8Reader::new(movsx_eax_cl)) /// .expect("can decode"); /// /// assert_eq!(instruction.opcode(), Opcode::MOVSX); /// /// fn show_register_class_info(regclass: RegisterClass) { /// match regclass { /// amd64::register_class::D => { /// println!(" and is a dword register"); /// } /// amd64::register_class::B => { /// println!(" and is a byte register"); /// } /// other => { /// panic!("unexpected and invalid register class {:?}", other); /// } /// } /// } /// /// if let Operand::Register(regspec) = instruction.operand(0) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// /// if let Operand::Register(regspec) = instruction.operand(1) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// ``` /// /// this is preferable to alternatives like checking register names against a known list: a /// register class is one byte and "is qword general-purpose" can then be a simple one-byte /// compare, instead of 16 string compares. /// /// `yaxpeax-x86` does not attempt to further distinguish between, for example, register /// suitability as operands. as an example, `cl` is only a byte register, with no additional /// register class to describe its use as an implicit shift operand. pub mod register_class { use super::{RegisterBank, RegisterClass}; /// doubleword registers: eax through edi. pub const D: RegisterClass = RegisterClass { kind: RegisterBank::D }; /// word registers: ax through di. pub const W: RegisterClass = RegisterClass { kind: RegisterBank::W }; /// byte registers: al, cl, dl, bl, ah, ch, dh, bh. pub const B: RegisterClass = RegisterClass { kind: RegisterBank::B }; /// control registers cr0 through cr7. pub const CR: RegisterClass = RegisterClass { kind: RegisterBank::CR}; /// debug registers dr0 through dr7. pub const DR: RegisterClass = RegisterClass { kind: RegisterBank::DR }; /// segment registers es, cs, ss, ds, fs, gs. pub const S: RegisterClass = RegisterClass { kind: RegisterBank::S }; /// xmm registers xmm0 through xmm31. pub const X: RegisterClass = RegisterClass { kind: RegisterBank::X }; /// ymm registers ymm0 through ymm31. pub const Y: RegisterClass = RegisterClass { kind: RegisterBank::Y }; /// zmm registers zmm0 through zmm31. pub const Z: RegisterClass = RegisterClass { kind: RegisterBank::Z }; /// x87 floating point stack entries st(0) through st(7). pub const ST: RegisterClass = RegisterClass { kind: RegisterBank::ST }; /// mmx registers mm0 through mm7. pub const MM: RegisterClass = RegisterClass { kind: RegisterBank::MM }; /// `AVX512` mask registers k0 through k7. pub const K: RegisterClass = RegisterClass { kind: RegisterBank::K }; /// the full instruction pointer register. pub const EIP: RegisterClass = RegisterClass { kind: RegisterBank::EIP }; /// the full cpu flags register. pub const EFLAGS: RegisterClass = RegisterClass { kind: RegisterBank::EFlags }; } impl RegisterClass { /// return a human-friendly name for this register class pub fn name(&self) -> &'static str { REGISTER_CLASS_NAMES[self.kind as usize] } /// return the size of this register class, in bytes pub fn width(&self) -> u8 { match self.kind { RegisterBank::D => 4, RegisterBank::W => 2, RegisterBank::B => 1, RegisterBank::CR | RegisterBank::DR => { 4 }, RegisterBank::S => { 2 }, RegisterBank::EIP => { 4 } RegisterBank::EFlags => { 4 } RegisterBank::X => { 16 } RegisterBank::Y => { 32 } RegisterBank::Z => { 64 } RegisterBank::ST => { 10 } RegisterBank::MM => { 8 } RegisterBank::K => { 8 } } } } #[allow(non_camel_case_types)] #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] enum RegisterBank { D = 4, W = 2, B = 1, // Dword, Word, Byte CR = 5, DR = 6, S = 7, EIP = 23, EFlags = 24, // Control reg, Debug reg, Selector, ... X = 8, Y = 12, Z = 16, // XMM, YMM, ZMM ST = 20, MM = 21, // ST, MM regs (x87, mmx) K = 22, // AVX512 mask registers } /// the segment register used by the corresponding instruction. /// /// typically this will be `ds` but can be overridden. some instructions have specific segment /// registers used regardless of segment prefixes, and in these cases `yaxpeax-x86` will report the /// actual segment register a physical processor would use. #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)] pub enum Segment { DS = 0, CS, ES, FS, GS, SS } const BMI1: [Opcode; 6] = [ Opcode::ANDN, Opcode::BEXTR, Opcode::BLSI, Opcode::BLSMSK, Opcode::BLSR, Opcode::TZCNT, ]; const BMI2: [Opcode; 8] = [ Opcode::BZHI, Opcode::MULX, Opcode::PDEP, Opcode::PEXT, Opcode::RORX, Opcode::SARX, Opcode::SHRX, Opcode::SHLX, ]; #[allow(dead_code)] const XSAVE: [Opcode; 10] = [ Opcode::XGETBV, Opcode::XRSTOR, Opcode::XRSTORS, Opcode::XSAVE, Opcode::XSAVEC, Opcode::XSAVEC64, Opcode::XSAVEOPT, Opcode::XSAVES, Opcode::XSAVES64, Opcode::XSETBV, ]; #[allow(non_camel_case_types)] #[derive(Copy, Clone, Debug, Eq, PartialEq)] #[non_exhaustive] #[repr(u32)] pub enum Opcode { ADD = 0x1000, OR = 0x1001, ADC = 0x1002, SBB = 0x1003, AND = 0x1004, SUB = 0x1005, XOR = 0x1006, CMP = 7, ROL = 8, ROR, RCL, RCR, SHL, SHR, SAL, SAR = 0x0f, BTC = 0x1010, BTR = 0x1011, BTS = 0x1012, CMPXCHG = 0x1013, CMPXCHG8B = 0x1014, CMPXCHG16B = 0x1015, DEC = 0x1016, INC = 0x1017, NEG = 0x1018, NOT = 0x1019, XADD = 0x101a, XCHG = 0x101b, Invalid = 0x1c, // XADD, BT, // BTS, // BTC, // BTR, BSF, BSR, TZCNT, MOVSS, ADDSS, SUBSS, MULSS, DIVSS, MINSS, MAXSS, SQRTSS, MOVSD, SQRTSD, ADDSD, SUBSD, MULSD, DIVSD, MINSD, MAXSD, MOVSLDUP, MOVSHDUP, MOVDDUP, HADDPS, HSUBPS, ADDSUBPD, ADDSUBPS, CVTSI2SS, CVTSI2SD, CVTTSD2SI, CVTTPS2DQ, CVTPD2DQ, CVTPD2PS, CVTPS2DQ, CVTSD2SI, CVTSD2SS, CVTTSS2SI, CVTSS2SI, CVTSS2SD, CVTDQ2PD, LDDQU, MOVZX, MOVSX, MOVSXD, SHRD, // INC, // DEC, HLT, CALL, CALLF, JMP, JMPF, PUSH, POP, LEA, NOP, PREFETCHNTA, PREFETCH0, PREFETCH1, PREFETCH2, // XCHG, POPF, INT, INTO, IRET, IRETD, IRETQ, RETF, ENTER, LEAVE, MOV, RETURN, PUSHF, WAIT, CBW, CWDE, CDQE, CWD, CDQ, CQO, LODS, STOS, LAHF, SAHF, CMPS, SCAS, MOVS, TEST, INS, IN, OUTS, OUT, IMUL, JO, JNO, JB, JNB, JZ, JNZ, JA, JNA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, CMOVA, CMOVB, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNB, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVS, CMOVZ, DIV, IDIV, MUL, // NEG, // NOT, // CMPXCHG, SETO, SETNO, SETB, SETAE, SETZ, SETNZ, SETBE, SETA, SETS, SETNS, SETP, SETNP, SETL, SETGE, SETLE, SETG, CPUID, UD0, UD1, UD2, WBINVD, INVD, SYSRET, CLTS, SYSCALL, LSL, LAR, LES, LDS, SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, SWAPGS, RDTSCP, INVLPG, FXSAVE, FXRSTOR, LDMXCSR, STMXCSR, XSAVE, XRSTOR, XSAVEOPT, LFENCE, MFENCE, SFENCE, CLFLUSH, CLFLUSHOPT, CLWB, WRMSR, RDTSC, RDMSR, RDPMC, SLDT, STR, LLDT, LTR, VERR, VERW, CMC, CLC, STC, CLI, STI, CLD, STD, JMPE, POPCNT, MOVDQU, MOVDQA, MOVQ, CMPSS, CMPSD, UNPCKLPS, UNPCKLPD, UNPCKHPS, UNPCKHPD, PSHUFHW, PSHUFLW, MOVUPS, MOVQ2DQ, MOVDQ2Q, RSQRTSS, RCPSS, ANDN, BEXTR, BLSI, BLSMSK, BLSR, VMCLEAR, VMXON, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, PCONFIG, MONITOR, MWAIT, MONITORX, MWAITX, CLAC, STAC, ENCLS, ENCLV, XGETBV, XSETBV, VMFUNC, XABORT, XBEGIN, XEND, XTEST, ENCLU, RDPKRU, WRPKRU, RDPRU, CLZERO, RDSEED, RDRAND, ADDPS, ADDPD, ANDNPS, ANDNPD, ANDPS, ANDPD, BSWAP, CMPPD, CMPPS, COMISD, COMISS, CVTDQ2PS, CVTPI2PS, CVTPI2PD, CVTPS2PD, CVTPS2PI, CVTPD2PI, CVTTPS2PI, CVTTPD2PI, CVTTPD2DQ, DIVPS, DIVPD, EMMS, GETSEC, LFS, LGS, LSS, MASKMOVQ, MASKMOVDQU, MAXPS, MAXPD, MINPS, MINPD, MOVAPS, MOVAPD, MOVD, MOVLPS, MOVLPD, MOVHPS, MOVHPD, MOVLHPS, MOVHLPS, MOVUPD, MOVMSKPS, MOVMSKPD, MOVNTI, MOVNTPS, MOVNTPD, EXTRQ, INSERTQ, MOVNTSS, MOVNTSD, MOVNTQ, MOVNTDQ, MULPS, MULPD, ORPS, ORPD, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PAVGB, PAVGW, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PINSRW, PMADDWD, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PMULHW, PMULLW, PMULUDQ, POR, PSADBW, PSHUFW, PSHUFD, PSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PUNPCKLQDQ, PUNPCKHQDQ, PXOR, RCPPS, RSM, RSQRTPS, SHLD, SHUFPD, SHUFPS, SLHD, SQRTPS, SQRTPD, SUBPS, SUBPD, SYSENTER, SYSEXIT, UCOMISD, UCOMISS, VMREAD, VMWRITE, XORPS, XORPD, VMOVDDUP, VPSHUFLW, VPSHUFHW, VHADDPS, VHSUBPS, VADDSUBPS, VCVTPD2DQ, VLDDQU, VCOMISD, VCOMISS, VUCOMISD, VUCOMISS, VADDPD, VADDPS, VADDSD, VADDSS, VADDSUBPD, VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST, VBLENDPD, VBLENDPS, VBLENDVPD, VBLENDVPS, VBROADCASTF128, VBROADCASTI128, VBROADCASTSD, VBROADCASTSS, VCMPSD, VCMPSS, VCMPPD, VCMPPS, VCVTDQ2PD, VCVTDQ2PS, VCVTPD2PS, VCVTPH2PS, VCVTPS2DQ, VCVTPS2PD, VCVTSS2SD, VCVTSI2SS, VCVTSI2SD, VCVTSD2SI, VCVTSD2SS, VCVTPS2PH, VCVTSS2SI, VCVTTPD2DQ, VCVTTPS2DQ, VCVTTSS2SI, VCVTTSD2SI, VDIVPD, VDIVPS, VDIVSD, VDIVSS, VDPPD, VDPPS, VEXTRACTF128, VEXTRACTI128, VEXTRACTPS, VFMADD132PD, VFMADD132PS, VFMADD132SD, VFMADD132SS, VFMADD213PD, VFMADD213PS, VFMADD213SD, VFMADD213SS, VFMADD231PD, VFMADD231PS, VFMADD231SD, VFMADD231SS, VFMADDSUB132PD, VFMADDSUB132PS, VFMADDSUB213PD, VFMADDSUB213PS, VFMADDSUB231PD, VFMADDSUB231PS, VFMSUB132PD, VFMSUB132PS, VFMSUB132SD, VFMSUB132SS, VFMSUB213PD, VFMSUB213PS, VFMSUB213SD, VFMSUB213SS, VFMSUB231PD, VFMSUB231PS, VFMSUB231SD, VFMSUB231SS, VFMSUBADD132PD, VFMSUBADD132PS, VFMSUBADD213PD, VFMSUBADD213PS, VFMSUBADD231PD, VFMSUBADD231PS, VFNMADD132PD, VFNMADD132PS, VFNMADD132SD, VFNMADD132SS, VFNMADD213PD, VFNMADD213PS, VFNMADD213SD, VFNMADD213SS, VFNMADD231PD, VFNMADD231PS, VFNMADD231SD, VFNMADD231SS, VFNMSUB132PD, VFNMSUB132PS, VFNMSUB132SD, VFNMSUB132SS, VFNMSUB213PD, VFNMSUB213PS, VFNMSUB213SD, VFNMSUB213SS, VFNMSUB231PD, VFNMSUB231PS, VFNMSUB231SD, VFNMSUB231SS, VGATHERDPD, VGATHERDPS, VGATHERQPD, VGATHERQPS, VHADDPD, VHSUBPD, VINSERTF128, VINSERTI128, VINSERTPS, VMASKMOVDQU, VMASKMOVPD, VMASKMOVPS, VMAXPD, VMAXPS, VMAXSD, VMAXSS, VMINPD, VMINPS, VMINSD, VMINSS, VMOVAPD, VMOVAPS, VMOVD, VMOVDQA, VMOVDQU, VMOVHLPS, VMOVHPD, VMOVHPS, VMOVLHPS, VMOVLPD, VMOVLPS, VMOVMSKPD, VMOVMSKPS, VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS, VMOVQ, VMOVSS, VMOVSD, VMOVSHDUP, VMOVSLDUP, VMOVUPD, VMOVUPS, VMPSADBW, VMULPD, VMULPS, VMULSD, VMULSS, VPABSB, VPABSD, VPABSW, VPACKSSDW, VPACKUSDW, VPACKSSWB, VPACKUSWB, VPADDB, VPADDD, VPADDQ, VPADDSB, VPADDSW, VPADDUSB, VPADDUSW, VPADDW, VPALIGNR, VANDPD, VANDPS, VORPD, VORPS, VANDNPD, VANDNPS, VPAND, VPANDN, VPAVGB, VPAVGW, VPBLENDD, VPBLENDVB, VPBLENDW, VPBROADCASTB, VPBROADCASTD, VPBROADCASTQ, VPBROADCASTW, VPCLMULQDQ, VPCMPEQB, VPCMPEQD, VPCMPEQQ, VPCMPEQW, VPCMPGTB, VPCMPGTD, VPCMPGTQ, VPCMPGTW, VPCMPESTRI, VPCMPESTRM, VPCMPISTRI, VPCMPISTRM, VPERM2F128, VPERM2I128, VPERMD, VPERMILPD, VPERMILPS, VPERMPD, VPERMPS, VPERMQ, VPEXTRB, VPEXTRD, VPEXTRQ, VPEXTRW, VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ, VPHADDD, VPHADDSW, VPHADDW, VPMADDUBSW, VPHMINPOSUW, VPHSUBD, VPHSUBSW, VPHSUBW, VPINSRB, VPINSRD, VPINSRQ, VPINSRW, VPMADDWD, VPMASKMOVD, VPMASKMOVQ, VPMAXSB, VPMAXSD, VPMAXSW, VPMAXUB, VPMAXUW, VPMAXUD, VPMINSB, VPMINSW, VPMINSD, VPMINUB, VPMINUW, VPMINUD, VPMOVMSKB, VPMOVSXBD, VPMOVSXBQ, VPMOVSXBW, VPMOVSXDQ, VPMOVSXWD, VPMOVSXWQ, VPMOVZXBD, VPMOVZXBQ, VPMOVZXBW, VPMOVZXDQ, VPMOVZXWD, VPMOVZXWQ, VPMULDQ, VPMULHRSW, VPMULHUW, VPMULHW, VPMULLQ, VPMULLD, VPMULLW, VPMULUDQ, VPOR, VPSADBW, VPSHUFB, VPSHUFD, VPSIGNB, VPSIGND, VPSIGNW, VPSLLD, VPSLLDQ, VPSLLQ, VPSLLVD, VPSLLVQ, VPSLLW, VPSRAD, VPSRAVD, VPSRAW, VPSRLD, VPSRLDQ, VPSRLQ, VPSRLVD, VPSRLVQ, VPSRLW, VPSUBB, VPSUBD, VPSUBQ, VPSUBSB, VPSUBSW, VPSUBUSB, VPSUBUSW, VPSUBW, VPTEST, VPUNPCKHBW, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLDQ, VPUNPCKLQDQ, VPUNPCKLWD, VPXOR, VRCPPS, VROUNDPD, VROUNDPS, VROUNDSD, VROUNDSS, VRSQRTPS, VRSQRTSS, VRCPSS, VSHUFPD, VSHUFPS, VSQRTPD, VSQRTPS, VSQRTSS, VSQRTSD, VSUBPD, VSUBPS, VSUBSD, VSUBSS, VTESTPD, VTESTPS, VUNPCKHPD, VUNPCKHPS, VUNPCKLPD, VUNPCKLPS, VXORPD, VXORPS, VZEROUPPER, VZEROALL, VLDMXCSR, VSTMXCSR, PCLMULQDQ, AESKEYGENASSIST, AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST, PCMPGTQ, PCMPISTRM, PCMPISTRI, PCMPESTRI, PACKUSDW, PCMPESTRM, PCMPEQQ, PTEST, PHMINPOSUW, DPPS, DPPD, MPSADBW, PMOVZXDQ, PMOVSXDQ, PMOVZXBD, PMOVSXBD, PMOVZXWQ, PMOVSXWQ, PMOVZXBQ, PMOVSXBQ, PMOVSXWD, PMOVZXWD, PEXTRQ, PEXTRD, PEXTRW, PEXTRB, PMOVSXBW, PMOVZXBW, PINSRQ, PINSRD, PINSRB, EXTRACTPS, INSERTPS, ROUNDSS, ROUNDSD, ROUNDPS, ROUNDPD, PMAXSB, PMAXSD, PMAXUW, PMAXUD, PMINSD, PMINSB, PMINUD, PMINUW, BLENDW, PBLENDVB, PBLENDW, BLENDVPS, BLENDVPD, BLENDPS, BLENDPD, PMULDQ, MOVNTDQA, PMULLD, PALIGNR, PSIGNW, PSIGND, PSIGNB, PSHUFB, PMULHRSW, PMADDUBSW, PABSD, PABSW, PABSB, PHSUBSW, PHSUBW, PHSUBD, PHADDD, PHADDSW, PHADDW, HSUBPD, HADDPD, SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2, SHA256RNDS2, SHA256MSG1, SHA256MSG2, LZCNT, CLGI, STGI, SKINIT, VMLOAD, VMMCALL, VMSAVE, VMRUN, INVLPGA, INVLPGB, TLBSYNC, MOVBE, ADCX, ADOX, PREFETCHW, RDPID, // CMPXCHG8B, // CMPXCHG16B, VMPTRLD, VMPTRST, BZHI, MULX, SHLX, SHRX, SARX, PDEP, PEXT, RORX, XRSTORS, XRSTORS64, XSAVEC, XSAVEC64, XSAVES, XSAVES64, RDFSBASE, RDGSBASE, WRFSBASE, WRGSBASE, CRC32, SALC, XLAT, F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU, FCOM, FCOMI, FCOMIP, FCOMP, FCOMPP, FCOS, FDECSTP, FDISI8087_NOP, FDIV, FDIVP, FDIVR, FDIVRP, FENI8087_NOP, FFREE, FFREEP, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNINIT, FNOP, FNSAVE, FNSTCW, FNSTENV, FNSTOR, FNSTSW, FPATAN, FPREM, FPREM1, FPTAN, FRNDINT, FRSTOR, FSCALE, FSETPM287_NOP, FSIN, FSINCOS, FSQRT, FST, FSTP, FSTPNCE, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FUCOM, FUCOMI, FUCOMIP, FUCOMP, FUCOMPP, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1, LOOPNZ, LOOPZ, LOOP, JECXZ, PUSHA, POPA, BOUND, ARPL, AAS, AAA, DAS, DAA, AAM, AAD, // started shipping in Tremont, 2020 sept 23 MOVDIR64B, MOVDIRI, // started shipping in Tiger Lake, 2020 sept 2 AESDEC128KL, AESDEC256KL, AESDECWIDE128KL, AESDECWIDE256KL, AESENC128KL, AESENC256KL, AESENCWIDE128KL, AESENCWIDE256KL, ENCODEKEY128, ENCODEKEY256, LOADIWKEY, // unsure HRESET, // 3dnow FEMMS, PI2FW, PI2FD, PF2IW, PF2ID, PMULHRW, PFCMPGE, PFMIN, PFRCP, PFRSQRT, PFSUB, PFADD, PFCMPGT, PFMAX, PFRCPIT1, PFRSQIT1, PFSUBR, PFACC, PFCMPEQ, PFMUL, PFMULHRW, PFRCPIT2, PFNACC, PFPNACC, PSWAPD, PAVGUSB, // ENQCMD ENQCMD, ENQCMDS, // INVPCID INVEPT, INVVPID, INVPCID, // PTWRITE PTWRITE, // GFNI GF2P8AFFINEQB, GF2P8AFFINEINVQB, GF2P8MULB, // CET WRUSS, WRSS, INCSSP, SAVEPREVSSP, SETSSBSY, CLRSSBSY, RSTORSSP, ENDBR64, ENDBR32, // TDX TDCALL, SEAMRET, SEAMOPS, SEAMCALL, // WAITPKG TPAUSE, UMONITOR, UMWAIT, // UINTR UIRET, TESTUI, CLUI, STUI, SENDUIPI, // TSXLDTRK XSUSLDTRK, XRESLDTRK, // AVX512F VALIGND, VALIGNQ, VBLENDMPD, VBLENDMPS, VCOMPRESSPD, VCOMPRESSPS, VCVTPD2UDQ, VCVTTPD2UDQ, VCVTPS2UDQ, VCVTTPS2UDQ, VCVTQQ2PD, VCVTQQ2PS, VCVTSD2USI, VCVTTSD2USI, VCVTSS2USI, VCVTTSS2USI, VCVTUDQ2PD, VCVTUDQ2PS, VCVTUSI2USD, VCVTUSI2USS, VEXPANDPD, VEXPANDPS, VEXTRACTF32X4, VEXTRACTF64X4, VEXTRACTI32X4, VEXTRACTI64X4, VFIXUPIMMPD, VFIXUPIMMPS, VFIXUPIMMSD, VFIXUPIMMSS, VGETEXPPD, VGETEXPPS, VGETEXPSD, VGETEXPSS, VGETMANTPD, VGETMANTPS, VGETMANTSD, VGETMANTSS, VINSERTF32X4, VINSERTF64X4, VINSERTI64X4, VMOVDQA32, VMOVDQA64, VMOVDQU32, VMOVDQU64, VPBLENDMD, VPBLENDMQ, VPCMPD, VPCMPUD, VPCMPQ, VPCMPUQ, VPCOMPRESSQ, VPCOMPRESSD, VPERMI2D, VPERMI2Q, VPERMI2PD, VPERMI2PS, VPERMT2D, VPERMT2Q, VPERMT2PD, VPERMT2PS, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ, VPMOVSQB, VPMOVUSQB, VPMOVSQW, VPMOVUSQW, VPMOVSQD, VPMOVUSQD, VPMOVSDB, VPMOVUSDB, VPMOVSDW, VPMOVUSDW, VPROLD, VPROLQ, VPROLVD, VPROLVQ, VPRORD, VPRORQ, VPRORRD, VPRORRQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, VPSRAQ, VPSRAVQ, VPTESTNMD, VPTESTNMQ, VPTERNLOGD, VPTERNLOGQ, VPTESTMD, VPTESTMQ, VRCP14PD, VRCP14PS, VRCP14SD, VRCP14SS, VRNDSCALEPD, VRNDSCALEPS, VRNDSCALESD, VRNDSCALESS, VRSQRT14PD, VRSQRT14PS, VRSQRT14SD, VRSQRT14SS, VSCALEDPD, VSCALEDPS, VSCALEDSD, VSCALEDSS, VSCATTERDD, VSCATTERDQ, VSCATTERQD, VSCATTERQQ, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2, // AVX512DQ VCVTTPD2QQ, VCVTPD2QQ, VCVTTPD2UQQ, VCVTPD2UQQ, VCVTTPS2QQ, VCVTPS2QQ, VCVTTPS2UQQ, VCVTPS2UQQ, VCVTUQQ2PD, VCVTUQQ2PS, VEXTRACTF64X2, VEXTRACTI64X2, VFPCLASSPD, VFPCLASSPS, VFPCLASSSD, VFPCLASSSS, VINSERTF64X2, VINSERTI64X2, VPMOVM2D, VPMOVM2Q, VPMOVB2D, VPMOVQ2M, VRANGEPD, VRANGEPS, VRANGESD, VRANGESS, VREDUCEPD, VREDUCEPS, VREDUCESD, VREDUCESS, // AVX512BW VDBPSADBW, VMOVDQU8, VMOVDQU16, VPBLENDMB, VPBLENDMW, VPCMPB, VPCMPUB, VPCMPW, VPCMPUW, VPERMW, VPERMI2B, VPERMI2W, VPMOVM2B, VPMOVM2W, VPMOVB2M, VPMOVW2M, VPMOVSWB, VPMOVUSWB, VPSLLVW, VPSRAVW, VPSRLVW, VPTESTNMB, VPTESTNMW, VPTESTMB, VPTESTMW, // AVX512CD VPBROADCASTM, VPCONFLICTD, VPCONFLICTQ, VPLZCNTD, VPLZCNTQ, KUNPCKBW, KUNPCKWD, KUNPCKDQ, KADDB, KANDB, KANDNB, KMOVB, KNOTB, KORB, KORTESTB, KSHIFTLB, KSHIFTRB, KTESTB, KXNORB, KXORB, KADDW, KANDW, KANDNW, KMOVW, KNOTW, KORW, KORTESTW, KSHIFTLW, KSHIFTRW, KTESTW, KXNORW, KXORW, KADDD, KANDD, KANDND, KMOVD, KNOTD, KORD, KORTESTD, KSHIFTLD, KSHIFTRD, KTESTD, KXNORD, KXORD, KADDQ, KANDQ, KANDNQ, KMOVQ, KNOTQ, KORQ, KORTESTQ, KSHIFTLQ, KSHIFTRQ, KTESTQ, KXNORQ, KXORQ, // AVX512ER VEXP2PD, VEXP2PS, VEXP2SD, VEXP2SS, VRCP28PD, VRCP28PS, VRCP28SD, VRCP28SS, VRSQRT28PD, VRSQRT28PS, VRSQRT28SD, VRSQRT28SS, // AVX512PF VGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS, VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD, VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTERPF1DPS, VSCATTERPF1QPD, VSCATTERPF1QPS, // MPX BNDMK, BNDCL, BNDCU, BNDCN, BNDMOV, BNDLDX, BNDSTX, VGF2P8AFFINEQB, VGF2P8AFFINEINVQB, VPSHRDQ, VPSHRDD, VPSHRDW, VPSHLDQ, VPSHLDD, VPSHLDW, VBROADCASTF32X8, VBROADCASTF64X4, VBROADCASTF32X4, VBROADCASTF64X2, VBROADCASTF32X2, VBROADCASTI32X8, VBROADCASTI64X4, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X2, VEXTRACTI32X8, VEXTRACTF32X8, VINSERTI32X8, VINSERTF32X8, VINSERTI32X4, V4FNMADDSS, V4FNMADDPS, VCVTNEPS2BF16, V4FMADDSS, V4FMADDPS, VCVTNE2PS2BF16, VP2INTERSECTD, VP2INTERSECTQ, VP4DPWSSDS, VP4DPWSSD, VPDPWSSDS, VPDPWSSD, VPDPBUSDS, VDPBF16PS, VPBROADCASTMW2D, VPBROADCASTMB2Q, VPMOVD2M, VPMOVQD, VPMOVWB, VPMOVDB, VPMOVDW, VPMOVQB, VPMOVQW, VGF2P8MULB, VPMADD52HUQ, VPMADD52LUQ, VPSHUFBITQMB, VPERMB, VPEXPANDD, VPEXPANDQ, VPABSQ, VPRORVD, VPRORVQ, VPMULTISHIFTQB, VPERMT2B, VPERMT2W, VPSHRDVQ, VPSHRDVD, VPSHRDVW, VPSHLDVQ, VPSHLDVD, VPSHLDVW, VPCOMPRESSB, VPCOMPRESSW, VPEXPANDB, VPEXPANDW, VPOPCNTD, VPOPCNTQ, VPOPCNTB, VPOPCNTW, VSCALEFSS, VSCALEFSD, VSCALEFPS, VSCALEFPD, VPDPBUSD, VCVTUSI2SD, VCVTUSI2SS, VPXORD, VPXORQ, VPORD, VPORQ, VPANDND, VPANDNQ, VPANDD, VPANDQ, PSMASH, PVALIDATE, RMPADJUST, RMPUPDATE, } impl PartialEq for Instruction { fn eq(&self, other: &Self) -> bool { if self.prefixes != other.prefixes { return false; } if self.opcode != other.opcode { return false; } if self.operand_count != other.operand_count { return false; } if self.mem_size != other.mem_size { return false; } for i in 0..self.operand_count { if self.operands[i as usize] != other.operands[i as usize] { return false; } if self.operand(i) != other.operand(i) { return false; } } true } } /// an `x86` instruction. /// /// typically an opcode will be inspected by [`Instruction::opcode()`], and an instruction has /// [`Instruction::operand_count()`] many operands. operands are provided by /// [`Instruction::operand()`]. #[derive(Debug, Clone, Copy, Eq)] pub struct Instruction { pub prefixes: Prefixes, regs: [RegSpec; 4], scale: u8, length: u8, operand_count: u8, operands: [OperandSpec; 4], imm: u32, disp: u32, opcode: Opcode, mem_size: u8, } impl yaxpeax_arch::Instruction for Instruction { fn well_defined(&self) -> bool { // TODO: this is incorrect! true } } #[derive(Debug, PartialEq, Eq, Copy, Clone)] #[non_exhaustive] pub enum DecodeError { ExhaustedInput, InvalidOpcode, InvalidOperand, InvalidPrefixes, TooLong, IncompleteDecoder, } impl yaxpeax_arch::DecodeError for DecodeError { fn data_exhausted(&self) -> bool { self == &DecodeError::ExhaustedInput } fn bad_opcode(&self) -> bool { self == &DecodeError::InvalidOpcode } fn bad_operand(&self) -> bool { self == &DecodeError::InvalidOperand } fn description(&self) -> &'static str { match self { DecodeError::ExhaustedInput => { "exhausted input" }, DecodeError::InvalidOpcode => { "invalid opcode" }, DecodeError::InvalidOperand => { "invalid operand" }, DecodeError::InvalidPrefixes => { "invalid prefixes" }, DecodeError::TooLong => { "too long" }, DecodeError::IncompleteDecoder => { "the decoder is incomplete" }, } } } #[cfg(feature = "std")] extern crate std; #[cfg(feature = "std")] impl std::error::Error for DecodeError { fn description(&self) -> &str { ::description(self) } } #[allow(non_camel_case_types)] #[derive(Debug, Copy, Clone, Eq, PartialEq)] enum OperandSpec { Nothing = 0, // the register in regs[0] RegRRR = 0x01, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed) RegRRR_maskmerge = 0x41, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed with a potentially // custom rounding mode. RegRRR_maskmerge_sae = 0x58, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed. RegRRR_maskmerge_sae_noround = 0x59, // the register in modrm_mmm (eg modrm mod bits were 11) RegMMM = 0x02, // same as `RegRRR`: the register is modrm's `mmm` bits, and may be masked. RegMMM_maskmerge = 0x42, RegMMM_maskmerge_sae_noround = 0x5a, // the register selected by vex-vvvv bits RegVex = 0x03, RegVex_maskmerge = 0x43, // the register selected by a handful of avx2 vex-coded instructions, // stuffed in imm4. Reg4 = 0x04, ImmI8 = 0x05, ImmI16 = 0x06, ImmI32 = 0x07, // ImmI64 = 0x08, not in 64b ImmU8 = 0x09, ImmU16 = 0x0a, // ENTER is a two-immediate instruction, where the first immediate is stored in the disp field. // for this case, a second immediate-style operand is needed. // turns out `insertq` and `extrq` are also two-immediate instructions, so this is generalized // to cover them too. ImmInDispField = 0x0b, DispU16 = 0x8c, DispU32 = 0x8d, Deref = 0x8e, Deref_si = 0x8f, Deref_di = 0x90, Deref_esi = 0x91, Deref_edi = 0x92, RegDisp = 0x93, RegScale = 0x94, RegScaleDisp = 0x95, RegIndexBaseScale = 0x96, RegIndexBaseScaleDisp = 0x97, Deref_mask = 0xce, RegDisp_mask = 0xd3, RegScale_mask = 0xd4, RegScaleDisp_mask = 0xd5, RegIndexBaseScale_mask = 0xd6, RegIndexBaseScaleDisp_mask = 0xd7, // u16:u{16,32} immediate address for a far call AbsoluteFarAddress = 0x98, } // the Hash, Eq, and PartialEq impls here are possibly misleading. // They exist because downstream some structs are spelled like // Foo for T == x86. This is only to access associated types // which themselves are bounded, but their #[derive] require T to // implement these traits. /// a trivial struct for `yaxpeax_arch::Arch` to be implemented on. it's only interesting for the /// associated type parameters. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Hash, Eq, PartialEq, Debug, Copy, Clone)] #[allow(non_camel_case_types)] pub struct Arch; impl yaxpeax_arch::Arch for Arch { type Address = u32; type Word = u8; type Instruction = Instruction; type DecodeError = DecodeError; type Decoder = InstDecoder; type Operand = Operand; } impl LengthedInstruction for Instruction { type Unit = AddressDiff; #[inline] fn len(&self) -> Self::Unit { AddressDiff::from_const(self.length.into()) } #[inline] fn min_size() -> Self::Unit { AddressDiff::from_const(1) } } /// an `x86` instruction decoder. /// /// fundamentally this is one or two primitives with no additional state kept during decoding. it /// can be copied cheaply, hashed cheaply, compared cheaply. if you really want to share an /// `InstDecoder` between threads, you could - but you might want to clone it instead. /// /// unless you're using an `Arc>`, which is _fine_ but i'd be very curious about /// the design requiring that. #[derive(PartialEq, Copy, Clone, Eq, Hash, PartialOrd, Ord)] pub struct InstDecoder { // extensions tracked here: // 0. SSE3 // 1. SSSE3 // 2. monitor (intel-only?) // 3. vmx (some atom chips still lack it) // 4. fma3 (intel haswell/broadwell+, amd piledriver+) // 5. cmpxchg16b (some amd are missing this one) // 6. sse4.1 // 7. sse4.2 // 8. movbe // 9. popcnt (independent of BMI) // 10. aesni // 11. xsave (xsave, xrestor, xsetbv, xgetbv) // 12. rdrand (intel ivybridge+, amd ..??) // 13. sgx (eadd, eblock, ecreate, edbgrd, edbgwr, einit, eldb, eldu, epa, eremove, etrace, // ewb, eenter, eexit, egetkey, ereport, eresume) // 14. bmi1 (intel haswell+, amd jaguar+) // 15. avx2 (intel haswell+, amd excavator+) // 16. bmi2 (intel ?, amd ?) // 17. invpcid // 18. mpx // 19. avx512_f // 20. avx512_dq // 21. rdseed // 22. adx // 23. avx512_fma // 24. pcommit // 25. clflushopt // 26. clwb // 27. avx512_pf // 28. avx512_er // 29. avx512_cd // 30. sha // 31. avx512_bw // 32. avx512_vl // 33. prefetchwt1 // 34. avx512_vbmi // 35. avx512_vbmi2 // 36. gfni (galois field instructions) // 37. vaes // 38. pclmulqdq // 39. avx_vnni // 40. avx512_bitalg // 41. avx512_vpopcntdq // 42. avx512_4vnniw // 43. avx512_4fmaps // 44. cx8 // cmpxchg8 - is this actually optional in x86? // 45. syscall // syscall/sysret - actually optional in x86? // 46. rdtscp // actually optional in x86? // 47. abm (lzcnt, popcnt) // 48. sse4a // 49. 3dnowprefetch // actually optional? // 50. xop // 51. skinit // 52. tbm // 53. intel quirks // 54. amd quirks // 55. avx (intel ?, amd ?) // 56. amd-v/svm // 57. lahfsahf // 58. cmov // 59. f16c // 60. fma4 // 61. prefetchw // 62. tsx // 63. lzcnt flags: u64, } impl InstDecoder { /// instantiates an x86 decoder that decodes the bare minimum of protected-mode x86. /// /// pedantic and only decodes what the spec says is well-defined, rejecting undefined sequences /// and any instructions defined by extensions. pub fn minimal() -> Self { InstDecoder { flags: 0, } } /// helper to decode an instruction directly from a byte slice. /// /// this lets callers avoid the work of setting up a [`yaxpeax_arch::U8Reader`] for the slice /// to decode. pub fn decode_slice(&self, data: &[u8]) -> Result { let mut reader = yaxpeax_arch::U8Reader::new(data); self.decode(&mut reader) } pub fn sse3(&self) -> bool { self.flags & (1 << 0) != 0 } pub fn with_sse3(mut self) -> Self { self.flags |= 1 << 0; self } pub fn ssse3(&self) -> bool { self.flags & (1 << 1) != 0 } pub fn with_ssse3(mut self) -> Self { self.flags |= 1 << 1; self } pub fn monitor(&self) -> bool { self.flags & (1 << 2) != 0 } pub fn with_monitor(mut self) -> Self { self.flags |= 1 << 2; self } pub fn vmx(&self) -> bool { self.flags & (1 << 3) != 0 } pub fn with_vmx(mut self) -> Self { self.flags |= 1 << 3; self } pub fn fma3(&self) -> bool { self.flags & (1 << 4) != 0 } pub fn with_fma3(mut self) -> Self { self.flags |= 1 << 4; self } pub fn cmpxchg16b(&self) -> bool { self.flags & (1 << 5) != 0 } pub fn with_cmpxchg16b(mut self) -> Self { self.flags |= 1 << 5; self } pub fn sse4_1(&self) -> bool { self.flags & (1 << 6) != 0 } pub fn with_sse4_1(mut self) -> Self { self.flags |= 1 << 6; self } pub fn sse4_2(&self) -> bool { self.flags & (1 << 7) != 0 } pub fn with_sse4_2(mut self) -> Self { self.flags |= 1 << 7; self } pub fn with_sse4(self) -> Self { self .with_sse4_1() .with_sse4_2() } pub fn movbe(&self) -> bool { self.flags & (1 << 8) != 0 } pub fn with_movbe(mut self) -> Self { self.flags |= 1 << 8; self } pub fn popcnt(&self) -> bool { self.flags & (1 << 9) != 0 } pub fn with_popcnt(mut self) -> Self { self.flags |= 1 << 9; self } pub fn aesni(&self) -> bool { self.flags & (1 << 10) != 0 } pub fn with_aesni(mut self) -> Self { self.flags |= 1 << 10; self } pub fn xsave(&self) -> bool { self.flags & (1 << 11) != 0 } pub fn with_xsave(mut self) -> Self { self.flags |= 1 << 11; self } pub fn rdrand(&self) -> bool { self.flags & (1 << 12) != 0 } pub fn with_rdrand(mut self) -> Self { self.flags |= 1 << 12; self } pub fn sgx(&self) -> bool { self.flags & (1 << 13) != 0 } pub fn with_sgx(mut self) -> Self { self.flags |= 1 << 13; self } pub fn bmi1(&self) -> bool { self.flags & (1 << 14) != 0 } pub fn with_bmi1(mut self) -> Self { self.flags |= 1 << 14; self } pub fn avx2(&self) -> bool { self.flags & (1 << 15) != 0 } pub fn with_avx2(mut self) -> Self { self.flags |= 1 << 15; self } /// `bmi2` indicates support for the `BZHI`, `MULX`, `PDEP`, `PEXT`, `RORX`, `SARX`, `SHRX`, /// and `SHLX` instructions. `bmi2` is implemented in all x86 chips that implement `bmi`, /// except the amd `piledriver` and `steamroller` microarchitectures. pub fn bmi2(&self) -> bool { self.flags & (1 << 16) != 0 } pub fn with_bmi2(mut self) -> Self { self.flags |= 1 << 16; self } pub fn invpcid(&self) -> bool { self.flags & (1 << 17) != 0 } pub fn with_invpcid(mut self) -> Self { self.flags |= 1 << 17; self } pub fn mpx(&self) -> bool { self.flags & (1 << 18) != 0 } pub fn with_mpx(mut self) -> Self { self.flags |= 1 << 18; self } pub fn avx512_f(&self) -> bool { self.flags & (1 << 19) != 0 } pub fn with_avx512_f(mut self) -> Self { self.flags |= 1 << 19; self } pub fn avx512_dq(&self) -> bool { self.flags & (1 << 20) != 0 } pub fn with_avx512_dq(mut self) -> Self { self.flags |= 1 << 20; self } pub fn rdseed(&self) -> bool { self.flags & (1 << 21) != 0 } pub fn with_rdseed(mut self) -> Self { self.flags |= 1 << 21; self } pub fn adx(&self) -> bool { self.flags & (1 << 22) != 0 } pub fn with_adx(mut self) -> Self { self.flags |= 1 << 22; self } pub fn avx512_fma(&self) -> bool { self.flags & (1 << 23) != 0 } pub fn with_avx512_fma(mut self) -> Self { self.flags |= 1 << 23; self } pub fn pcommit(&self) -> bool { self.flags & (1 << 24) != 0 } pub fn with_pcommit(mut self) -> Self { self.flags |= 1 << 24; self } pub fn clflushopt(&self) -> bool { self.flags & (1 << 25) != 0 } pub fn with_clflushopt(mut self) -> Self { self.flags |= 1 << 25; self } pub fn clwb(&self) -> bool { self.flags & (1 << 26) != 0 } pub fn with_clwb(mut self) -> Self { self.flags |= 1 << 26; self } pub fn avx512_pf(&self) -> bool { self.flags & (1 << 27) != 0 } pub fn with_avx512_pf(mut self) -> Self { self.flags |= 1 << 27; self } pub fn avx512_er(&self) -> bool { self.flags & (1 << 28) != 0 } pub fn with_avx512_er(mut self) -> Self { self.flags |= 1 << 28; self } pub fn avx512_cd(&self) -> bool { self.flags & (1 << 29) != 0 } pub fn with_avx512_cd(mut self) -> Self { self.flags |= 1 << 29; self } pub fn sha(&self) -> bool { self.flags & (1 << 30) != 0 } pub fn with_sha(mut self) -> Self { self.flags |= 1 << 30; self } pub fn avx512_bw(&self) -> bool { self.flags & (1 << 31) != 0 } pub fn with_avx512_bw(mut self) -> Self { self.flags |= 1 << 31; self } pub fn avx512_vl(&self) -> bool { self.flags & (1 << 32) != 0 } pub fn with_avx512_vl(mut self) -> Self { self.flags |= 1 << 32; self } pub fn prefetchwt1(&self) -> bool { self.flags & (1 << 33) != 0 } pub fn with_prefetchwt1(mut self) -> Self { self.flags |= 1 << 33; self } pub fn avx512_vbmi(&self) -> bool { self.flags & (1 << 34) != 0 } pub fn with_avx512_vbmi(mut self) -> Self { self.flags |= 1 << 34; self } pub fn avx512_vbmi2(&self) -> bool { self.flags & (1 << 35) != 0 } pub fn with_avx512_vbmi2(mut self) -> Self { self.flags |= 1 << 35; self } pub fn gfni(&self) -> bool { self.flags & (1 << 36) != 0 } pub fn with_gfni(mut self) -> Self { self.flags |= 1 << 36; self } pub fn vaes(&self) -> bool { self.flags & (1 << 37) != 0 } pub fn with_vaes(mut self) -> Self { self.flags |= 1 << 37; self } pub fn pclmulqdq(&self) -> bool { self.flags & (1 << 38) != 0 } pub fn with_pclmulqdq(mut self) -> Self { self.flags |= 1 << 38; self } pub fn avx_vnni(&self) -> bool { self.flags & (1 << 39) != 0 } pub fn with_avx_vnni(mut self) -> Self { self.flags |= 1 << 39; self } pub fn avx512_bitalg(&self) -> bool { self.flags & (1 << 40) != 0 } pub fn with_avx512_bitalg(mut self) -> Self { self.flags |= 1 << 40; self } pub fn avx512_vpopcntdq(&self) -> bool { self.flags & (1 << 41) != 0 } pub fn with_avx512_vpopcntdq(mut self) -> Self { self.flags |= 1 << 41; self } pub fn avx512_4vnniw(&self) -> bool { self.flags & (1 << 42) != 0 } pub fn with_avx512_4vnniw(mut self) -> Self { self.flags |= 1 << 42; self } pub fn avx512_4fmaps(&self) -> bool { self.flags & (1 << 43) != 0 } pub fn with_avx512_4fmaps(mut self) -> Self { self.flags |= 1 << 43; self } /// returns `true` if this `InstDecoder` has **all** `avx512` features enabled. pub fn avx512(&self) -> bool { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); (self.flags & avx512_mask) == avx512_mask } /// enable all `avx512` features on this `InstDecoder`. no real CPU, at time of writing, /// actually has such a feature combination, but this is a useful overestimate for `avx512` /// generally. pub fn with_avx512(mut self) -> Self { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); self.flags |= avx512_mask; self } pub fn cx8(&self) -> bool { self.flags & (1 << 44) != 0 } pub fn with_cx8(mut self) -> Self { self.flags |= 1 << 44; self } pub fn syscall(&self) -> bool { self.flags & (1 << 45) != 0 } pub fn with_syscall(mut self) -> Self { self.flags |= 1 << 45; self } pub fn rdtscp(&self) -> bool { self.flags & (1 << 46) != 0 } pub fn with_rdtscp(mut self) -> Self { self.flags |= 1 << 46; self } pub fn abm(&self) -> bool { self.flags & (1 << 47) != 0 } pub fn with_abm(mut self) -> Self { self.flags |= 1 << 47; self } pub fn sse4a(&self) -> bool { self.flags & (1 << 48) != 0 } pub fn with_sse4a(mut self) -> Self { self.flags |= 1 << 48; self } pub fn _3dnowprefetch(&self) -> bool { self.flags & (1 << 49) != 0 } pub fn with_3dnowprefetch(mut self) -> Self { self.flags |= 1 << 49; self } pub fn xop(&self) -> bool { self.flags & (1 << 50) != 0 } pub fn with_xop(mut self) -> Self { self.flags |= 1 << 50; self } pub fn skinit(&self) -> bool { self.flags & (1 << 51) != 0 } pub fn with_skinit(mut self) -> Self { self.flags |= 1 << 51; self } pub fn tbm(&self) -> bool { self.flags & (1 << 52) != 0 } pub fn with_tbm(mut self) -> Self { self.flags |= 1 << 52; self } pub fn intel_quirks(&self) -> bool { self.flags & (1 << 53) != 0 } pub fn with_intel_quirks(mut self) -> Self { self.flags |= 1 << 53; self } pub fn amd_quirks(&self) -> bool { self.flags & (1 << 54) != 0 } pub fn with_amd_quirks(mut self) -> Self { self.flags |= 1 << 54; self } pub fn avx(&self) -> bool { self.flags & (1 << 55) != 0 } pub fn with_avx(mut self) -> Self { self.flags |= 1 << 55; self } pub fn svm(&self) -> bool { self.flags & (1 << 56) != 0 } pub fn with_svm(mut self) -> Self { self.flags |= 1 << 56; self } /// `lahfsahf` is only unset for early revisions of 64-bit amd and intel chips. unfortunately /// the clearest documentation on when these instructions were reintroduced into 64-bit /// architectures seems to be /// [wikipedia](https://en.wikipedia.org/wiki/X86-64#Older_implementations): /// ```text /// Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD /// introduced these instructions (also in 64-bit mode) with their Athlon 64, Opteron and /// Turion 64 revision D processors in March 2005[48][49][50] while Intel introduced the /// instructions with the Pentium 4 G1 stepping in December 2005. The 64-bit version of Windows /// 8.1 requires this feature.[47] /// ``` /// /// this puts reintroduction of these instructions somewhere in the middle of prescott and k8 /// lifecycles, for intel and amd respectively. because there is no specific uarch where these /// features become enabled, prescott and k8 default to not supporting these instructions, /// where later uarches support these instructions. pub fn lahfsahf(&self) -> bool { self.flags & (1 << 57) != 0 } pub fn with_lahfsahf(mut self) -> Self { self.flags |= 1 << 57; self } pub fn cmov(&self) -> bool { self.flags & (1 << 58) != 0 } pub fn with_cmov(mut self) -> Self { self.flags |= 1 << 58; self } pub fn f16c(&self) -> bool { self.flags & (1 << 59) != 0 } pub fn with_f16c(mut self) -> Self { self.flags |= 1 << 59; self } pub fn fma4(&self) -> bool { self.flags & (1 << 60) != 0 } pub fn with_fma4(mut self) -> Self { self.flags |= 1 << 60; self } pub fn prefetchw(&self) -> bool { self.flags & (1 << 61) != 0 } pub fn with_prefetchw(mut self) -> Self { self.flags |= 1 << 61; self } pub fn tsx(&self) -> bool { self.flags & (1 << 62) != 0 } pub fn with_tsx(mut self) -> Self { self.flags |= 1 << 62; self } pub fn lzcnt(&self) -> bool { self.flags & (1 << 63) != 0 } pub fn with_lzcnt(mut self) -> Self { self.flags |= 1 << 63; self } /// Optionally reject or reinterpret instruction according to the decoder's /// declared extensions. fn revise_instruction(&self, inst: &mut Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex().is_some() { if !self.avx512() { return Err(DecodeError::InvalidOpcode); } else { return Ok(()); } } match inst.opcode { Opcode::TZCNT => { if !self.bmi1() { // tzcnt is only supported if bmi1 is enabled. without bmi1, this decodes as // bsf. inst.opcode = Opcode::BSF; } } Opcode::LDDQU | Opcode::ADDSUBPS | Opcode::ADDSUBPD | Opcode::HADDPS | Opcode::HSUBPS | Opcode::HADDPD | Opcode::HSUBPD | Opcode::MOVSHDUP | Opcode::MOVSLDUP | Opcode::MOVDDUP | Opcode::MONITOR | Opcode::MWAIT => { // via Intel section 5.7, SSE3 Instructions if !self.sse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PHADDW | Opcode::PHADDSW | Opcode::PHADDD | Opcode::PHSUBW | Opcode::PHSUBSW | Opcode::PHSUBD | Opcode::PABSB | Opcode::PABSW | Opcode::PABSD | Opcode::PMADDUBSW | Opcode::PMULHRSW | Opcode::PSHUFB | Opcode::PSIGNB | Opcode::PSIGNW | Opcode::PSIGND | Opcode::PALIGNR => { // via Intel section 5.8, SSSE3 Instructions if !self.ssse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PMULLD | Opcode::PMULDQ | Opcode::MOVNTDQA | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::PBLENDVB | Opcode::BLENDW | Opcode::PMINUW | Opcode::PMINUD | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMAXUW | Opcode::PMAXUD | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::ROUNDPS | Opcode::ROUNDPD | Opcode::ROUNDSS | Opcode::ROUNDSD | Opcode::PBLENDW | Opcode::EXTRACTPS | Opcode::INSERTPS | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::PMOVSXBW | Opcode::PMOVZXBW | Opcode::PMOVSXBD | Opcode::PMOVZXBD | Opcode::PMOVSXWD | Opcode::PMOVZXWD | Opcode::PMOVSXBQ | Opcode::PMOVZXBQ | Opcode::PMOVSXWQ | Opcode::PMOVZXWQ | Opcode::PMOVSXDQ | Opcode::PMOVZXDQ | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::PHMINPOSUW | Opcode::PTEST | Opcode::PCMPEQQ | Opcode::PEXTRB | Opcode::PEXTRW | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::PACKUSDW => { // via Intel section 5.10, SSE4.1 Instructions if !self.sse4_1() { return Err(DecodeError::InvalidOpcode); } } Opcode::EXTRQ | Opcode::INSERTQ | Opcode::MOVNTSS | Opcode::MOVNTSD => { if !self.sse4a() { return Err(DecodeError::InvalidOpcode); } } Opcode::CRC32 | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PCMPGTQ => { // via Intel section 5.11, SSE4.2 Instructions if !self.sse4_2() { return Err(DecodeError::InvalidOpcode); } } Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::PCLMULQDQ => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.pclmulqdq() { return Err(DecodeError::InvalidOpcode); } } Opcode::XABORT | Opcode::XBEGIN | Opcode::XEND | Opcode::XTEST => { if !self.tsx() { return Err(DecodeError::InvalidOpcode); } } Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA1NEXTE | Opcode::SHA1RNDS4 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::SHA256RNDS2 => { if !self.sha() { return Err(DecodeError::InvalidOpcode); } } Opcode::ENCLV | Opcode::ENCLS | Opcode::ENCLU => { if !self.sgx() { return Err(DecodeError::InvalidOpcode); } } // AVX... Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VCVTPD2DQ | Opcode::VLDDQU | Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTSS2SD | Opcode::VCVTSI2SS | Opcode::VCVTSI2SD | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSS2SI | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTTSS2SI | Opcode::VCVTTSD2SI | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VDPPD | Opcode::VDPPS | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::VMOVQ | Opcode::VMOVSS | Opcode::VMOVSD | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMPSADBW | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPALIGNR | Opcode::VPAND | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VORPD | Opcode::VORPS | Opcode::VPANDN | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPCLMULQDQ | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPMADDUBSW | Opcode::VPHMINPOSUW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMADDWD | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::VPOR | Opcode::VPSADBW | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VPTEST | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VPXOR | Opcode::VRCPPS | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::VRSQRTPS | Opcode::VRSQRTSS | Opcode::VRCPSS | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSQRTSS | Opcode::VSQRTSD | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VXORPD | Opcode::VXORPS | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VLDMXCSR | Opcode::VSTMXCSR => { // TODO: check a table for these if !self.avx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { // TODO: check a table for these if !self.avx() || !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::MOVBE => { if !self.movbe() { return Err(DecodeError::InvalidOpcode); } } Opcode::POPCNT => { /* * from the intel SDM: * ``` * Before an application attempts to use the POPCNT instruction, it must check that * the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1) and POPCNT * (if CPUID.01H:ECX.POPCNT[bit 23] = 1). * ``` */ if self.intel_quirks() && (self.sse4_2() || self.popcnt()) { return Ok(()); } else if !self.popcnt() { /* * elsewhere from the amd APM: * `Instruction Subsets and CPUID Feature Flags` on page 507 indicates that * popcnt is present when the popcnt bit is reported by cpuid. this seems to be * the less quirky default, so `intel_quirks` is considered the outlier, and * before this default. * */ return Err(DecodeError::InvalidOpcode); } } Opcode::LZCNT => { /* * amd APM, `LZCNT` page 212: * LZCNT is an Advanced Bit Manipulation (ABM) instruction. Support for the LZCNT * instruction is indicated by CPUID Fn8000_0001_ECX[ABM] = 1. * * meanwhile the intel SDM simply states: * ``` * CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the * LZCNT instruction. * ``` * * so that's considered the less-quirky (default) case here. * */ if self.amd_quirks() && !self.abm() { return Err(DecodeError::InvalidOpcode); } else if !self.lzcnt() { return Err(DecodeError::InvalidOpcode); } } Opcode::ADCX | Opcode::ADOX => { if !self.adx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VMRUN | Opcode::VMLOAD | Opcode::VMSAVE | Opcode::CLGI | Opcode::VMMCALL | Opcode::INVLPGA => { if !self.svm() { return Err(DecodeError::InvalidOpcode); } } Opcode::STGI | Opcode::SKINIT => { if !self.svm() || !self.skinit() { return Err(DecodeError::InvalidOpcode); } } Opcode::LAHF | Opcode::SAHF => { if !self.lahfsahf() { return Err(DecodeError::InvalidOpcode); } } Opcode::VCVTPS2PH | Opcode::VCVTPH2PS => { /* * from intel SDM: * ``` * 14.4.1 Detection of F16C Instructions Application using float 16 instruction * must follow a detection sequence similar to AVX to ensure: • The OS has * enabled YMM state management support, • The processor support AVX as * indicated by the CPUID feature flag, i.e. CPUID.01H:ECX.AVX[bit 28] = 1. • * The processor support 16-bit floating-point conversion instructions via a * CPUID feature flag (CPUID.01H:ECX.F16C[bit 29] = 1). * ``` * * TODO: only the VEX-coded variant of this instruction should be gated on `f16c`. * the EVEX-coded variant should be gated on `avx512f` or `avx512vl` if not * EVEX.512-coded. */ if !self.avx() || !self.f16c() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDRAND => { if !self.rdrand() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDSEED => { if !self.rdseed() { return Err(DecodeError::InvalidOpcode); } } Opcode::MONITORX | Opcode::MWAITX | // these are gated on the `monitorx` and `mwaitx` cpuid bits, but are AMD-only. Opcode::CLZERO | Opcode::RDPRU => { // again, gated on specific cpuid bits, but AMD-only. if !self.amd_quirks() { return Err(DecodeError::InvalidOpcode); } } other => { if !self.bmi1() { if BMI1.contains(&other) { return Err(DecodeError::InvalidOpcode); } } if !self.bmi2() { if BMI2.contains(&other) { return Err(DecodeError::InvalidOpcode); } } } } Ok(()) } } impl Default for InstDecoder { /// Instantiates an x86 decoder that probably decodes what you want. /// /// Attempts to match real processors in interpretation of undefined sequences, and decodes any /// instruction defined in any extension. fn default() -> Self { Self { flags: 0xffffffff_ffffffff, } } } impl Decoder for InstDecoder { fn decode::Address, ::Word>>(&self, words: &mut T) -> Result::DecodeError> { let mut instr = Instruction::invalid(); DecodeCtx::new().read_with_annotations(self, words, &mut instr, &mut NullSink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(&mut instr)?; } Ok(instr) } fn decode_into::Address, ::Word>>(&self, instr: &mut Instruction, words: &mut T) -> Result<(), ::DecodeError> { self.decode_with_annotation(instr, words, &mut NullSink) } } impl AnnotatingDecoder for InstDecoder { type FieldDescription = FieldDescription; fn decode_with_annotation< T: Reader<::Address, ::Word>, S: DescriptionSink >(&self, instr: &mut Instruction, words: &mut T, sink: &mut S) -> Result<(), ::DecodeError> { DecodeCtx::new().read_with_annotations(self, words, instr, sink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(instr)?; } Ok(()) } } impl Opcode { /// check if the instruction is one of x86's sixteen conditional jump instructions. use this /// rather than `opcode.to_string().starts_with("j") && opcode != Opcode::JMP`, thank you. pub fn is_jcc(&self) -> bool { match self { Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JG | Opcode::JLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional move instructions. pub fn is_cmovcc(&self) -> bool { match self { Opcode::CMOVO | Opcode::CMOVNO | Opcode::CMOVB | Opcode::CMOVNB | Opcode::CMOVZ | Opcode::CMOVNZ | Opcode::CMOVA | Opcode::CMOVNA | Opcode::CMOVS | Opcode::CMOVNS | Opcode::CMOVP | Opcode::CMOVNP | Opcode::CMOVL | Opcode::CMOVGE | Opcode::CMOVG | Opcode::CMOVLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional set instructions. pub fn is_setcc(&self) -> bool { match self { Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETA | Opcode::SETBE | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETG | Opcode::SETLE => true, _ => false } } /// get the [`ConditionCode`] for this instruction, if it is in fact conditional. x86's /// conditional instructions are `Jcc`, `CMOVcc`, andd `SETcc`. pub fn condition(&self) -> Option { match self { Opcode::JO | Opcode::CMOVO | Opcode::SETO => { Some(ConditionCode::O) }, Opcode::JNO | Opcode::CMOVNO | Opcode::SETNO => { Some(ConditionCode::NO) }, Opcode::JB | Opcode::CMOVB | Opcode::SETB => { Some(ConditionCode::B) }, Opcode::JNB | Opcode::CMOVNB | Opcode::SETAE => { Some(ConditionCode::AE) }, Opcode::JZ | Opcode::CMOVZ | Opcode::SETZ => { Some(ConditionCode::Z) }, Opcode::JNZ | Opcode::CMOVNZ | Opcode::SETNZ => { Some(ConditionCode::NZ) }, Opcode::JA | Opcode::CMOVA | Opcode::SETA => { Some(ConditionCode::A) }, Opcode::JNA | Opcode::CMOVNA | Opcode::SETBE => { Some(ConditionCode::BE) }, Opcode::JS | Opcode::CMOVS | Opcode::SETS => { Some(ConditionCode::S) }, Opcode::JNS | Opcode::CMOVNS | Opcode::SETNS => { Some(ConditionCode::NS) }, Opcode::JP | Opcode::CMOVP | Opcode::SETP => { Some(ConditionCode::P) }, Opcode::JNP | Opcode::CMOVNP | Opcode::SETNP => { Some(ConditionCode::NP) }, Opcode::JL | Opcode::CMOVL | Opcode::SETL => { Some(ConditionCode::L) }, Opcode::JGE | Opcode::CMOVGE | Opcode::SETGE => { Some(ConditionCode::GE) }, Opcode::JG | Opcode::CMOVG | Opcode::SETG => { Some(ConditionCode::G) }, Opcode::JLE | Opcode::CMOVLE | Opcode::SETLE => { Some(ConditionCode::LE) }, _ => None, } } } impl Default for Instruction { fn default() -> Self { Instruction::invalid() } } impl Instruction { /// get the `Opcode` of this instruction. pub fn opcode(&self) -> Opcode { self.opcode } /// get the `Operand` at the provided index. /// /// panics if the index is `>= 4`. pub fn operand(&self, i: u8) -> Operand { assert!(i < 4); Operand::from_spec(self, self.operands[i as usize]) } /// get the number of operands in this instruction. useful in iterating an instruction's /// operands generically. pub fn operand_count(&self) -> u8 { self.operand_count } /// check if operand `i` is an actual operand or not. will be `false` for `i >= /// inst.operand_count()`. pub fn operand_present(&self, i: u8) -> bool { assert!(i < 4); if i >= self.operand_count { return false; } if let OperandSpec::Nothing = self.operands[i as usize] { false } else { true } } /// get the memory access information for this instruction, if it accesses memory. /// /// the corresponding `MemoryAccessSize` may report that the size of accessed memory is /// indeterminate; this is the case for `xsave/xrestor`-style instructions whose operation size /// varies based on physical processor. /// /// ## NOTE /// /// the reported size is correct for displayed operand sizes (`word [ptr]` will have a /// `MemoryAccessSize` indicating two bytes) but is _not_ sufficient to describe all accesses /// of all instructions. the most notable exception is for operand-size-prefixed `call`, where /// `66ff10` is the instruction `call word [eax]`, but will push a four-byte `eip`. tools must /// account for these inconsistent sizes internally. pub fn mem_size(&self) -> Option { if self.mem_size != 0 { Some(MemoryAccessSize { size: self.mem_size }) } else { None } } /// build a new instruction representing nothing in particular. this is primarily useful as a /// default to pass to `decode_into`. pub fn invalid() -> Instruction { Instruction { prefixes: Prefixes::new(0), opcode: Opcode::NOP, mem_size: 0, regs: [RegSpec::eax(); 4], scale: 0, length: 0, disp: 0, imm: 0, operand_count: 0, operands: [OperandSpec::Nothing; 4], } } /// get the `Segment` that will *actually* be used for accessing the operand at index `i`. /// /// `stos`, `lods`, `movs`, and `cmps` specifically name some segments for use regardless of /// prefixes. pub fn segment_override_for_op(&self, op: u8) -> Option { match self.opcode { Opcode::STOS | Opcode::SCAS => { if op == 0 { Some(Segment::ES) } else { None } } Opcode::LODS => { if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::MOVS => { if op == 0 { Some(Segment::ES) } else if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::CMPS => { if op == 0 { Some(self.prefixes.segment) } else if op == 1 { Some(Segment::ES) } else { None } }, _ => { // most operands are pretty simple: if self.operands[op as usize].is_memory() && self.prefixes.segment != Segment::DS { Some(self.prefixes.segment) } else { None } } } } #[cfg(feature = "fmt")] /// wrap a reference to this instruction with a `DisplayStyle` to format the instruction with /// later. see the documentation on [`display::DisplayStyle`] for more. /// /// ``` /// use yaxpeax_x86::long_mode::{InstDecoder, DisplayStyle}; /// /// let decoder = InstDecoder::default(); /// let inst = decoder.decode_slice(&[0x33, 0xc1]).unwrap(); /// /// assert_eq!("eax ^= ecx", inst.display_with(DisplayStyle::C).to_string()); /// assert_eq!("xor eax, ecx", inst.display_with(DisplayStyle::Intel).to_string()); /// ``` pub fn display_with<'a>(&'a self, style: display::DisplayStyle) -> display::InstructionDisplayer<'a> { display::InstructionDisplayer { style, instr: self, } } /// does this instruction include the `xacquire` hint for hardware lock elision? pub fn xacquire(&self) -> bool { if self.prefixes.repnz() { // xacquire is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else { false } } else { false } } /// does this instruction include the `xrelease` hint for hardware lock elision? pub fn xrelease(&self) -> bool { if self.prefixes.rep() { // xrelease is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. additionally, xrelease is permitted on some forms of mov. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else if self.opcode == Opcode::MOV { self.operands[0] != OperandSpec::RegMMM && ( self.operands[1] == OperandSpec::RegRRR || self.operands[1] == OperandSpec::ImmI8 || self.operands[1] == OperandSpec::ImmI16 || self.operands[1] == OperandSpec::ImmI32 ) } else { false } } else { false } } } #[derive(Debug, Copy, Clone, Eq, PartialEq)] struct EvexData { // data: present, z, b, Lp, Rp. aaa bits: u8, } /// the prefixes on an instruction. /// /// `rep`, `repnz`, `lock`, and segment override prefixes are directly accessible here. `vex` and /// `evex` prefixes are available through their associated helpers. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct Prefixes { bits: u8, vex: PrefixVex, segment: Segment, evex_data: EvexData, } #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixEvex { vex: PrefixVex, evex_data: EvexData, } impl PrefixEvex { fn present(&self) -> bool { self.evex_data.present() } /// the `evex` prefix's parts that overlap with `vex` definitions - `L`, `W`, `R`, `X`, and `B` /// bits. pub fn vex(&self) -> &PrefixVex { &self.vex } /// the `avx512` mask register in use. `0` indicates "no mask register". pub fn mask_reg(&self) -> u8 { self.evex_data.aaa() } pub fn broadcast(&self) -> bool { self.evex_data.b() } pub fn merge(&self) -> bool { self.evex_data.z() } /// the `evex` `L'` bit. pub fn lp(&self) -> bool { self.evex_data.lp() } /// the `evex` `R'` bit. pub fn rp(&self) -> bool { self.evex_data.rp() } } /// bits specified in an avx/avx2 [`vex`](https://en.wikipedia.org/wiki/VEX_prefix) prefix, `L`, `W`, `R`, `X`, and `B`. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixVex { bits: u8, } #[allow(dead_code)] impl PrefixVex { #[inline] pub fn b(&self) -> bool { (self.bits & 0x01) == 0x01 } #[inline] pub fn x(&self) -> bool { (self.bits & 0x02) == 0x02 } #[inline] pub fn r(&self) -> bool { (self.bits & 0x04) == 0x04 } #[inline] pub fn w(&self) -> bool { (self.bits & 0x08) == 0x08 } #[inline] pub fn l(&self) -> bool { (self.bits & 0x10) == 0x10 } #[inline] fn present(&self) -> bool { (self.bits & 0x80) == 0x80 } #[inline] fn compressed_disp(&self) -> bool { (self.bits & 0x20) == 0x20 } } #[allow(dead_code)] impl Prefixes { fn new(bits: u8) -> Prefixes { Prefixes { bits: bits, vex: PrefixVex { bits: 0 }, segment: Segment::DS, evex_data: EvexData { bits: 0 }, } } fn vex_from(&mut self, bits: u8) { self.vex = PrefixVex { bits }; } #[inline] pub fn rep(&self) -> bool { self.bits & 0x30 == 0x10 } #[inline] fn set_rep(&mut self) { self.bits = (self.bits & 0xcf) | 0x10 } #[inline] pub fn repnz(&self) -> bool { self.bits & 0x30 == 0x30 } #[inline] fn set_repnz(&mut self) { self.bits = (self.bits & 0xcf) | 0x30 } #[inline] pub fn rep_any(&self) -> bool { self.bits & 0x30 != 0x00 } #[inline] fn operand_size(&self) -> bool { self.bits & 0x1 == 1 } #[inline] fn set_operand_size(&mut self) { self.bits = self.bits | 0x1 } #[inline] fn unset_operand_size(&mut self) { self.bits = self.bits & !0x1 } #[inline] fn address_size(&self) -> bool { self.bits & 0x2 == 2 } #[inline] fn set_address_size(&mut self) { self.bits = self.bits | 0x2 } #[inline] fn set_lock(&mut self) { self.bits |= 0x4 } #[inline] pub fn lock(&self) -> bool { self.bits & 0x4 == 4 } #[deprecated(since = "0.0.1", note = "pub fn cs has never returned `bool` indicating the current selector is `cs`. use `selects_cs` for this purpose, until 2.x that will correct `pub fn cs`.")] #[inline] pub fn cs(&mut self) {} #[inline] pub fn selects_cs(&self) -> bool { self.segment == Segment::CS } #[inline] fn set_cs(&mut self) { self.segment = Segment::CS } #[inline] pub fn ds(&self) -> bool { self.segment == Segment::DS } #[inline] fn set_ds(&mut self) { self.segment = Segment::DS } #[inline] pub fn es(&self) -> bool { self.segment == Segment::ES } #[inline] fn set_es(&mut self) { self.segment = Segment::ES } #[inline] pub fn fs(&self) -> bool { self.segment == Segment::FS } #[inline] fn set_fs(&mut self) { self.segment = Segment::FS } #[inline] pub fn gs(&self) -> bool { self.segment == Segment::GS } #[inline] fn set_gs(&mut self) { self.segment = Segment::GS } #[inline] pub fn ss(&self) -> bool { self.segment == Segment::SS } #[inline] fn set_ss(&mut self) { self.segment = Segment::SS } #[inline] fn vex_unchecked(&self) -> PrefixVex { PrefixVex { bits: self.vex.bits } } #[inline] fn vex_invalid(&self) -> bool { /* * if instruction.prefixes.rex_unchecked().present() // but no rex outside 64-bit mode * || instruction.prefixes.lock() * || instruction.prefixes.operand_size() * || instruction.prefixes.rep() * || instruction.prefixes.repnz() { */ (self.bits & 0b1100_0101) > 0 } #[inline] pub fn vex(&self) -> Option { let vex = self.vex_unchecked(); if vex.present() { Some(vex) } else { None } } #[inline] fn evex_unchecked(&self) -> PrefixEvex { PrefixEvex { vex: PrefixVex { bits: self.vex.bits }, evex_data: self.evex_data } } #[inline] pub fn evex(&self) -> Option { let evex = self.evex_unchecked(); if evex.present() { Some(evex) } else { None } } #[inline] fn apply_compressed_disp(&mut self, state: bool) { if state { self.vex.bits |= 0x20; } else { self.vex.bits &= 0xdf; } } #[inline] fn vex_from_c5(&mut self, bits: u8) { // collect rex bits let r = bits & 0x80; let wrxb = (r >> 5) ^ 0x04; let l = (bits & 0x04) << 2; let synthetic_rex = wrxb | l | 0x80; self.vex = PrefixVex { bits: synthetic_rex }; } #[inline] fn vex_from_c4(&mut self, high: u8, low: u8) { let w = low & 0x80; let rxb = (high >> 5) ^ 0x07; let wrxb = rxb | w >> 4; let l = (low & 0x04) << 2; let synthetic_vex = wrxb | l | 0x80; self.vex = PrefixVex { bits: synthetic_vex }; } #[inline] fn evex_from(&mut self, b1: u8, b2: u8, b3: u8) { let w = b2 & 0x80; let rxb = ((b1 >> 5) & 0b111) ^ 0b111; // `rxb` is provided in inverted form let wrxb = rxb | (w >> 4); let l = (b3 & 0x20) >> 1; let synthetic_vex = wrxb | l | 0x80; self.vex_from(synthetic_vex); // R' is provided in inverted form let rp = ((b1 & 0x10) >> 4) ^ 1; let lp = (b3 & 0x40) >> 6; let aaa = b3 & 0b111; let z = (b3 & 0x80) >> 7; let b = (b3 & 0x10) >> 4; self.evex_data.from(rp, lp, z, b, aaa); } } impl EvexData { fn from(&mut self, rp: u8, lp: u8, z: u8, b: u8, aaa: u8) { let mut bits = 0; bits |= aaa; bits |= b << 3; bits |= z << 4; bits |= lp << 5; bits |= rp << 6; bits |= 0x80; self.bits = bits; } } impl EvexData { pub(crate) fn present(&self) -> bool { self.bits & 0b1000_0000 != 0 } pub(crate) fn aaa(&self) -> u8 { self.bits & 0b111 } pub(crate) fn b(&self) -> bool { (self.bits & 0b0000_1000) != 0 } pub(crate) fn z(&self) -> bool { (self.bits & 0b0001_0000) != 0 } pub(crate) fn lp(&self) -> bool { (self.bits & 0b0010_0000) != 0 } pub(crate) fn rp(&self) -> bool { (self.bits & 0b0100_0000) != 0 } } #[derive(Debug)] struct OperandCodeBuilder { bits: u16 } #[allow(non_camel_case_types)] enum ZOperandCategory { Zv_R = 0, Zv_AX = 1, Zb_Ib_R = 2, Zv_Iv_R = 3, } struct ZOperandInstructions { bits: u16 } impl ZOperandInstructions { fn category(&self) -> u8 { (self.bits >> 4) as u8 & 0b11 } fn reg(&self) -> u8 { (self.bits & 0b111) as u8 } } struct EmbeddedOperandInstructions { bits: u16 } impl EmbeddedOperandInstructions { #[allow(unused)] fn bits(&self) -> u16 { self.bits } } #[allow(non_snake_case)] impl OperandCodeBuilder { const fn new() -> Self { OperandCodeBuilder { bits: 0 } } const fn bits(&self) -> u16 { self.bits } const fn from_bits(bits: u16) -> Self { Self { bits } } const fn read_modrm(mut self) -> Self { self.bits |= 0x8000; self } // deny ModRM `mod=11` const fn deny_regmmm(mut self) -> Self { self.bits |= 0x2000; self } const fn denies_regmmm(&self) -> bool { self.bits & 0x2000 != 0 } const fn set_embedded_instructions(mut self) -> Self { self.bits |= 0x4000; self } fn has_embedded_instructions(&self) -> bool { self.bits & 0x4000 != 0 } fn get_embedded_instructions(&self) -> Option { // 0x4000 indicates embedded instructions // 0x3fff > 0x0080 indicates the embedded instructions are a Z-style operand if self.has_embedded_instructions() { Some(ZOperandInstructions { bits: self.bits }) } else { None } } fn operand_case_handler_index(&self) -> OperandCase { unsafe { core::mem::transmute(self.bits as u8) } } const fn operand_case(mut self, case: OperandCase) -> Self { // leave 0x4000 unset self.bits |= case as u8 as u16; self } const fn op0_is_rrr_and_Z_operand(mut self, category: ZOperandCategory, reg_num: u8) -> Self { self = self.set_embedded_instructions(); // if op0 is rrr, 0x2000 unset indicates the operand category written in bits 11:10 // further, reg number is bits 0:2 // // when 0x2000 is unset: // 0x1cf8 are all unused bits, so far // // if you're counting, that's 8 bits remaining. // it also means one of those (0x0400?) can be used to pick some other interpretation // scheme. self.bits |= (category as u8 as u16) << 4; self.bits |= reg_num as u16 & 0b111; self } const fn read_E(mut self) -> Self { self.bits |= 0x1000; self } const fn has_read_E(&self) -> bool { self.bits & 0x1000 != 0 } const fn byte_operands(mut self) -> Self { self.bits |= 0x0800; self } const fn mem_reg(mut self) -> Self { self.bits |= 0x0400; self } const fn reg_mem(self) -> Self { // 0x0400 unset self } const fn has_byte_operands(&self) -> bool { (self.bits & 0x0800) != 0 } const fn has_reg_mem(&self) -> bool { (self.bits & 0x0400) == 0 } const fn only_modrm_operands(mut self) -> Self { self.bits |= 0x0200; self } const fn is_only_modrm_operands(&self) -> bool { self.bits & 0x0200 != 0 } // WHEN AN IMMEDIATE IS PRESENT, THERE ARE ONLY 0x3F ALLOWED SPECIAL CASES. // WHEN NO IMMEDIATE IS PRESENT, THERE ARE 0xFF ALLOWED SPECIAL CASES. // SIZE IS DECIDED BY THE FOLLOWING TABLE: // 0: 1 BYTE // 1: 4 BYTES const fn only_imm(mut self) -> Self { self.bits |= 0x100; self } fn has_imm(&self) -> bool { self.bits & 0x100 != 0 } } /// a wrapper to hide internal library implementation details. this is only useful for the inner /// content's `Display` impl, which itself is unstable and suitable only for human consumption. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub struct OperandCodeWrapper { code: OperandCode } #[allow(non_camel_case_types)] #[derive(Debug, PartialEq, Copy, Clone)] #[repr(u8)] enum OperandCase { Internal = 0, // handled internally and completely by embedded rules. Gv_M = 1, // "internal", but must be distinguished from Gv_Ev Ibs = 2, Jvds = 3, Nothing = 4, // no operands. this is distinct from `Internal`: `Internal` may specify one or two operands depending on embedded rules. SingleMMMOper = 5, // one operand, disregard rrr bits of modrm. BaseOpWithI8 = 6, BaseOpWithIv = 7, MovI8 = 8, MovIv = 9, BitwiseWithI8 = 10, // BitwiseWithIv = 9, ShiftBy1_b, ShiftBy1_v, BitwiseByCL, ModRM_0x8f, ModRM_0xf6, ModRM_0xf7, ModRM_0xfe, ModRM_0xff, Gv_Eb, Gv_Ew, // Gdq_Ed, I_3, E_G_xmm, G_M_xmm, G_E_xmm, G_E_xmm_Ib, AL_Ibs, AX_Ivd, Ivs, ModRM_0x83, Ed_G_xmm, G_Ed_xmm, /* Nothing = Nothing, Eb_R0 = SingleMMMOper, Ev = SingleMMMOper, ModRM_0x80_Eb_Ib = BaseOpWithI8, ModRM_0x81_Ev_Ivs = BaseOpWithIv, ModRM_0xc6_Eb_Ib = MovI8, ModRM_0xc7_Ev_Iv = MovIv, ModRM_0xc0_Eb_Ib = BitwiseWithI8, ModRM_0xc1_Ev_Ib = BitwiseWithIv, ModRM_0xd0_Eb_1 = ShiftBy1_b, ModRM_0xd1_Ev_1 = ShiftBy1_v, ModRM_0x8f_Ev = ModRM_0x8f, ModRM_0xd2_Eb_CL = BitwiseByCL, ModRM_0xd3_Ev_CL = BitwiseByCL, ModRM_0xf6 = ModRM_0xf6_0xf7, ModRM_0xf7 = ModRM_0xf6_0xf7, ModRM_0xfe_Eb = ModRM_0xfe, ModRM_0xff_Ev = ModRM_0xff, Gv_Eb = Gv_Eb, Gv_Ew = Gv_Ew, Gdq_Ed = Gdq_Ed, I_3 = I_3, E_G_xmm = E_G_xmm, G_M_xmm = G_M_xmm, G_E_xmm = G_E_xmm, G_E_xmm_Ib = G_E_xmm_Ib, AL_Ibs = AL_Ibs, AX_Ivd = AX_Ivd, Ivs = Ivs, ModRM_0x83_Ev_Ibs = ModRM_0x83, Ed_G_xmm = Ed_G_xmm, G_Ed_xmm = G_Ed_xmm, */ Ib, x87_d8, x87_d9, x87_da, x87_db, x87_dc, x87_dd, x87_de, x87_df, AL_Ib, AX_Ib, Ib_AL, Ib_AX, Gv_Ew_LAR, Gv_Ew_LSL, // Gdq_Ev, Gd_Ev, Gv_Ev_Ib, Gv_Ev_Iv, AX_DX, AL_DX, DX_AX, DX_AL, MOVQ_f30f, Yv_Xv, Gd_Ed, // Mdq_Gdq, Md_Gd, AL_Ob, AL_Xb, AX_Ov, G_xmm_E_mm, G_xmm_U_mm, G_mm_U_xmm, Rv_Gmm_Ib, G_xmm_Ed, G_mm_E_xmm, Gd_U_xmm, Gd_Eq_xmm, Gv_E_xmm, G_xmm_Ew_Ib, G_E_xmm_Ub, G_U_xmm_Ub, G_U_xmm, M_G_xmm, G_E_mm, G_U_mm, E_G_mm, Ed_G_mm, G_mm_Ed, G_mm_E, Ev_Gv_Ib, Ev_Gv_CL, G_mm_U_mm, G_Mq_mm, G_mm_Ew_Ib, G_E_q, E_G_q, CVT_AA, CVT_DA, Rq_Cq_0, Rq_Dq_0, Cq_Rq_0, Dq_Rq_0, FS, GS, Yb_DX, Yv_DX, DX_Xb, DX_Xv, AH, AX_Xv, Ew_Sw, Fw, I_1, Iw, Iw_Ib, Ob_AL, Ov_AX, Sw_Ew, Yb_AL, Yb_Xb, Yv_AX, Ew_Gw, ES, CS, SS, DS, ModRM_0x62, ModRM_0xc4, ModRM_0xc5, INV_Gv_M, PMOVX_G_E_xmm, PMOVX_E_G_xmm, G_Ev_xmm_Ib, G_E_mm_Ib, AbsFar, MOVDIR64B, ModRM_0x0f00, ModRM_0x0f01, ModRM_0x0f0d, ModRM_0x0f0f, ModRM_0x0f12, ModRM_0x0f16, ModRM_0x0f18, ModRM_0x0f71, ModRM_0x0f72, ModRM_0x0f73, ModRM_0x0fae, ModRM_0x0fba, ModRM_0x0fc7, ModRM_0x660f78, ModRM_0xf20f78, ModRM_0xf30f1e, ModRM_0xf30f38d8, ModRM_0xf30f38dc, ModRM_0xf30f38dd, ModRM_0xf30f38de, ModRM_0xf30f38df, ModRM_0xf30f38fa, ModRM_0xf30f38fb, ModRM_0xf30f3af0, } #[allow(non_camel_case_types)] #[repr(u16)] #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum OperandCode { Ivs = OperandCodeBuilder::new().operand_case(OperandCase::Ivs).bits(), I_3 = OperandCodeBuilder::new().operand_case(OperandCase::I_3).bits(), Nothing = OperandCodeBuilder::new().operand_case(OperandCase::Nothing).bits(), Ib = OperandCodeBuilder::new().operand_case(OperandCase::Ib).bits(), Ibs = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Ibs).bits(), Jvds = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Jvds).bits(), Yv_Xv = OperandCodeBuilder::new().operand_case(OperandCase::Yv_Xv).bits(), x87_d8 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d8).bits(), x87_d9 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d9).bits(), x87_da = OperandCodeBuilder::new().operand_case(OperandCase::x87_da).bits(), x87_db = OperandCodeBuilder::new().operand_case(OperandCase::x87_db).bits(), x87_dc = OperandCodeBuilder::new().operand_case(OperandCase::x87_dc).bits(), x87_dd = OperandCodeBuilder::new().operand_case(OperandCase::x87_dd).bits(), x87_de = OperandCodeBuilder::new().operand_case(OperandCase::x87_de).bits(), x87_df = OperandCodeBuilder::new().operand_case(OperandCase::x87_df).bits(), Eb_R0 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::SingleMMMOper) .bits(), AL_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ib).bits(), AX_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ib).bits(), Ib_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AL).bits(), Ib_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AX).bits(), AX_DX = OperandCodeBuilder::new().operand_case(OperandCase::AX_DX).bits(), AL_DX = OperandCodeBuilder::new().operand_case(OperandCase::AL_DX).bits(), DX_AX = OperandCodeBuilder::new().operand_case(OperandCase::DX_AX).bits(), DX_AL = OperandCodeBuilder::new().operand_case(OperandCase::DX_AL).bits(), MOVQ_f30f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::MOVQ_f30f).bits(), // Unsupported = OperandCodeBuilder::new().operand_case(49).bits(), ModRM_0x0f00 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f00).bits(), ModRM_0x0f01 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f01).bits(), ModRM_0x0f0d = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0d).bits(), ModRM_0x0f0f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0f).bits(), // 3dnow ModRM_0x0fae = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fae).bits(), ModRM_0x0fba = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fba).bits(), // ModRM_0xf30fae = OperandCodeBuilder::new().read_modrm().operand_case(46).bits(), // ModRM_0x660fae = OperandCodeBuilder::new().read_modrm().operand_case(47).bits(), // ModRM_0xf30fc7 = OperandCodeBuilder::new().read_modrm().operand_case(48).bits(), // ModRM_0x660f38 = OperandCodeBuilder::new().read_modrm().operand_case(49).bits(), // ModRM_0xf20f38 = OperandCodeBuilder::new().read_modrm().operand_case(50).bits(), // ModRM_0xf30f38 = OperandCodeBuilder::new().read_modrm().operand_case(51).bits(), ModRM_0xf30f38d8 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38d8).bits(), ModRM_0xf30f38dc = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dc).bits(), ModRM_0xf30f38dd = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dd).bits(), ModRM_0xf30f38de = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38de).bits(), ModRM_0xf30f38df = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38df).bits(), ModRM_0xf30f38fa = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fa).bits(), ModRM_0xf30f38fb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fb).bits(), ModRM_0xf30f3af0 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf30f3af0).bits(), // ModRM_0x660f3a = OperandCodeBuilder::new().read_modrm().operand_case(52).bits(), // ModRM_0x0f38 = OperandCodeBuilder::new().read_modrm().operand_case(53).bits(), // ModRM_0x0f3a = OperandCodeBuilder::new().read_modrm().operand_case(54).bits(), ModRM_0x0f71 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f71).bits(), ModRM_0x0f72 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f72).bits(), ModRM_0x0f73 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f73).bits(), ModRM_0xf20f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf20f78).bits(), ModRM_0x660f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x660f78).bits(), ModRM_0xf30f1e = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xf30f1e).bits(), // ModRM_0x660f72 = OperandCodeBuilder::new().read_modrm().operand_case(61).bits(), // ModRM_0x660f73 = OperandCodeBuilder::new().read_modrm().operand_case(62).bits(), // ModRM_0x660fc7 = OperandCodeBuilder::new().read_modrm().operand_case(63).bits(), ModRM_0x0fc7 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fc7).bits(), // xmmword? ModRM_0x0f12 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f12) .bits(), // xmmword? ModRM_0x0f16 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f16) .bits(), // encode immediates? ModRM_0xc0_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xc1_Ev_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xd0_Eb_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ShiftBy1_b) .bits(), ModRM_0xd1_Ev_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ShiftBy1_v) .bits(), ModRM_0xd2_Eb_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0xd3_Ev_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0x80_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BaseOpWithI8) .bits(), ModRM_0x83_Ev_Ibs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x83) .bits(), // this would be Eb_Ivs, 0x8e ModRM_0x81_Ev_Ivs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BaseOpWithIv) .bits(), ModRM_0xc6_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::MovI8) .bits(), ModRM_0xc7_Ev_Iv = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::MovIv) .bits(), ModRM_0xfe_Eb = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xfe) .bits(), ModRM_0x8f_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x8f) .bits(), // gap, 0x94 ModRM_0xff_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xff) .bits(), ModRM_0x0f18 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x0f18) .bits(), ModRM_0xf6 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xf6) .bits(), ModRM_0xf7 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xf7) .bits(), Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::SingleMMMOper) .bits(), Zv_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 0).bits(), Zv_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 1).bits(), Zv_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 2).bits(), Zv_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 3).bits(), Zv_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 4).bits(), Zv_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 5).bits(), Zv_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 6).bits(), Zv_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 7).bits(), // Zv_AX_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 0).bits(), Zv_AX_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 1).bits(), Zv_AX_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 2).bits(), Zv_AX_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 3).bits(), Zv_AX_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 4).bits(), Zv_AX_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 5).bits(), Zv_AX_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 6).bits(), Zv_AX_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 7).bits(), Zb_Ib_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 0).bits(), Zb_Ib_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 1).bits(), Zb_Ib_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 2).bits(), Zb_Ib_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 3).bits(), Zb_Ib_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 4).bits(), Zb_Ib_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 5).bits(), Zb_Ib_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 6).bits(), Zb_Ib_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 7).bits(), Zv_Iv_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 0).bits(), Zv_Iv_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 1).bits(), Zv_Iv_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 2).bits(), Zv_Iv_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 3).bits(), Zv_Iv_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 4).bits(), Zv_Iv_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 5).bits(), Zv_Iv_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 6).bits(), Zv_Iv_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 7).bits(), Gv_Eb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Eb).bits(), Gv_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew).bits(), Gv_Ew_LAR = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LAR).bits(), Gv_Ew_LSL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LSL).bits(), // Gdq_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gdq_Ed).bits(), Gd_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ed).bits(), Md_Gd = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::Md_Gd).bits(), // Edq_Gdq = OperandCodeBuilder::new().read_E().operand_case(49).bits(), Gd_Ev = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ev).bits(), // Md_Gd = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Md_Gd).bits(), G_E_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ib).bits(), G_E_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ub).bits(), G_U_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_U_xmm_Ub).bits(), AL_Ob = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ob).bits(), AL_Xb = OperandCodeBuilder::new().operand_case(OperandCase::AL_Xb).bits(), AX_Ov = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ov).bits(), AL_Ibs = OperandCodeBuilder::new().byte_operands().operand_case(OperandCase::AL_Ibs).bits(), AX_Ivd = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ivd).bits(), Eb_Gb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Ev_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Gb_Eb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_Ev = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_M = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().deny_regmmm().operand_case(OperandCase::Gv_M).bits(), MOVDIR64B = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::MOVDIR64B).bits(), M_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().deny_regmmm().operand_case(OperandCase::Internal).bits(), Gv_Ev_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Ib).bits(), Gv_Ev_Iv = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Iv).bits(), Rv_Gmm_Ib = OperandCodeBuilder::new().read_modrm().read_E().reg_mem().operand_case(OperandCase::Rv_Gmm_Ib).bits(), // gap, 0x9a G_xmm_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_E_mm).bits(), G_xmm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_U_mm).bits(), G_mm_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_xmm).bits(), G_xmm_Ed = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Ed).bits(), G_mm_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_E_xmm).bits(), Gd_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gd_U_xmm).bits(), Gd_Eq_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gd_Eq_xmm).bits(), Gv_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_E_xmm).bits(), //= 0x816f, // mirror G_xmm_Ed, but also read an immediate G_xmm_Ew_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Ew_Ib).bits(), G_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_xmm).bits(), G_M_xmm = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::G_M_xmm).bits(), G_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_xmm).bits(), E_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_xmm).bits(), G_Ed_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Ed_xmm).bits(), Ed_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Ed_G_xmm).bits(), M_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::M_G_xmm).bits(), G_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_mm).bits(), G_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_mm).bits(), E_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_mm).bits(), Ed_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Ed_G_mm).bits(), // Edq_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Edq_G_xmm).bits(), G_mm_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Ed).bits(), G_mm_E = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_E).bits(), Ev_Gv_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_Ib).bits(), Ev_Gv_CL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_CL).bits(), G_mm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_mm).bits(), G_Mq_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Mq_mm).bits(), G_mm_Ew_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Ew_Ib).bits(), G_E_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_q).bits(), E_G_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::E_G_q).bits(), CVT_AA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_AA).bits(), CVT_DA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_DA).bits(), Rq_Cq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Cq_0).bits(), Rq_Dq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Dq_0).bits(), Cq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Cq_Rq_0).bits(), Dq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Dq_Rq_0).bits(), FS = OperandCodeBuilder::new().operand_case(OperandCase::FS).bits(), GS = OperandCodeBuilder::new().operand_case(OperandCase::GS).bits(), Yb_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yb_DX).bits(), Yv_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_DX).bits(), DX_Xb = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xb).bits(), DX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xv).bits(), AH = OperandCodeBuilder::new().operand_case(OperandCase::AH).bits(), AX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::AX_Xv).bits(), Ew_Sw = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ew_Sw).bits(), Fw = OperandCodeBuilder::new().operand_case(OperandCase::Fw).bits(), I_1 = OperandCodeBuilder::new().operand_case(OperandCase::I_1).bits(), Iw = OperandCodeBuilder::new().operand_case(OperandCase::Iw).bits(), Iw_Ib = OperandCodeBuilder::new().operand_case(OperandCase::Iw_Ib).bits(), Ob_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ob_AL).bits(), Ov_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ov_AX).bits(), Sw_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Sw_Ew).read_E().bits(), Yb_AL = OperandCodeBuilder::new().operand_case(OperandCase::Yb_AL).bits(), Yb_Xb = OperandCodeBuilder::new().operand_case(OperandCase::Yb_Xb).bits(), Yv_AX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_AX).bits(), Ew_Gw = OperandCodeBuilder::new().operand_case(OperandCase::Ew_Gw).bits(), ES = OperandCodeBuilder::new().operand_case(OperandCase::ES).bits(), CS = OperandCodeBuilder::new().operand_case(OperandCase::CS).bits(), SS = OperandCodeBuilder::new().operand_case(OperandCase::SS).bits(), DS = OperandCodeBuilder::new().operand_case(OperandCase::DS).bits(), ModRM_0x62 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0x62).bits(), INV_Gv_M = OperandCodeBuilder::new().read_E().deny_regmmm().operand_case(OperandCase::INV_Gv_M).bits(), PMOVX_G_E_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_G_E_xmm).bits(), PMOVX_E_G_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_E_G_xmm).bits(), G_Ev_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_Ev_xmm_Ib).bits(), G_E_mm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_mm_Ib).bits(), AbsFar = OperandCodeBuilder::new().operand_case(OperandCase::AbsFar).bits(), ModRM_0xc4 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xc4).bits(), ModRM_0xc5 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xc5).bits(), } fn base_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ADD, 1 => Opcode::OR, 2 => Opcode::ADC, 3 => Opcode::SBB, 4 => Opcode::AND, 5 => Opcode::SUB, 6 => Opcode::XOR, 7 => Opcode::CMP, _ => { unsafe { unreachable_unchecked() } } } } fn bitwise_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ROL, 1 => Opcode::ROR, 2 => Opcode::RCL, 3 => Opcode::RCR, 4 => Opcode::SHL, 5 => Opcode::SHR, 6 => Opcode::SAL, 7 => Opcode::SAR, _ => { unsafe { unreachable_unchecked() } } } } #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum Interpretation { Instruction(Opcode), Prefix, } #[derive(Copy, Clone, Debug, PartialEq)] // this should be a 32-byte struct.. struct OpcodeRecord(u64); //Interpretation, u32); // OperandCode); impl OpcodeRecord { const fn new(interp: Interpretation, code: OperandCode) -> Self { let interp_bits = unsafe { core::mem::transmute::(interp) as u64 }; let code_bits = code as u16 as u64; let stored_bits = interp_bits | (code_bits << 32); OpcodeRecord(stored_bits) } const fn interp(&self) -> Interpretation { unsafe { core::mem::transmute(self.0 as u32) } } const fn operand(&self) -> OperandCode { unsafe { core::mem::transmute((self.0 >> 32) as u16) } } } const OPCODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::ES), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::ES), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::CS), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::SS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::SS), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::DS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::DS), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::DAA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::DAS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAS), OperandCode::Nothing), // 0x40: OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R7), // 0x50: OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R7), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSHA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BOUND), OperandCode::ModRM_0x62), OpcodeRecord::new(Interpretation::Instruction(Opcode::ARPL), OperandCode::Ew_Gw), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yb_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yv_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xv), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Ibs), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x80_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x81_Ev_Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x83_Ev_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ew_Sw), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEA), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Sw_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x8f_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_AA), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_DA), OpcodeRecord::new(Interpretation::Instruction(Opcode::CALLF), OperandCode::AbsFar), OpcodeRecord::new(Interpretation::Instruction(Opcode::WAIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSHF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AL_Ob), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AX_Ov), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ob_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ov_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yv_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AL_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AX_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yv_AX), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R7), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc0_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc1_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::LES), OperandCode::ModRM_0xc4), OpcodeRecord::new(Interpretation::Instruction(Opcode::LDS), OperandCode::ModRM_0xc5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc6_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc7_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ENTER), OperandCode::Iw_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEAVE), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_3), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::INTO), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::IRET), OperandCode::Fw), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd0_Eb_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd1_Ev_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd2_Eb_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd3_Ev_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAM), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAD), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SALC), OperandCode::Nothing), // XLAT OpcodeRecord::new(Interpretation::Instruction(Opcode::XLAT), OperandCode::Nothing), // x86 d8 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d8), // x86 d9 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d9), // x86 da OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_da), // x86 db OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_db), // x86 dc OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dc), // x86 dd OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dd), // x86 de OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_de), // x86 df OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_df), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JECXZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AX), // 0xe8 OpcodeRecord::new(Interpretation::Instruction(Opcode::CALL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AX), // 0xf0 OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // ICEBP? OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_1), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // 0xf4 OpcodeRecord::new(Interpretation::Instruction(Opcode::HLT), OperandCode::Nothing), // CMC OpcodeRecord::new(Interpretation::Instruction(Opcode::CMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf6), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf7), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xfe_Eb), // TODO: test 0xff /3 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xff_Ev), ]; #[allow(non_snake_case)] #[inline(always)] pub(self) fn read_E< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_st< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { instr.regs[1] = RegSpec { bank: RegisterBank::ST, num: modrm & 7 }; Ok(OperandSpec::RegMMM) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_xmm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::X, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_ymm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::Y, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { let res = read_M(words, instr, modrm, sink)?; if (modrm & 0b01_000_000) == 0b01_000_000 { instr.prefixes.apply_compressed_disp(true); } Ok(res) } } #[allow(non_snake_case)] #[inline(always)] fn read_modrm_reg< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &mut Instruction, words: &mut T, modrm: u8, reg_bank: RegisterBank, sink: &mut S) -> Result { instr.regs[1] = RegSpec::from_parts(modrm & 7, reg_bank); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 6, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(words.offset() as u32 * 8 - 8 + 2) ); Ok(OperandSpec::RegMMM) } #[inline(always)] fn read_sib_disp< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &Instruction, words: &mut T, modrm: u8, sibbyte: u8, sink: &mut S) -> Result { let sib_start = words.offset() as u32 * 8 - 8; let modbit_addr = words.offset() as u32 * 8 - 10; let disp_start = words.offset() as u32 * 8; let disp = if modrm < 0b01_000_000 { // modbits == 0b00 if (sibbyte & 7) == 0b101 { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); sink.record(sib_start, sib_start + 2, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { 0 } } else if modrm < 0b10_000_000 { // modbits == 0b01 sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("1-byte displacement").with_id(sib_start + 0)); if instr.prefixes.evex().is_some() { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("EVEX prefix implies displacement is scaled by vector size") .with_id(sib_start + 0)); } let disp = read_num(words, 1)? as i8 as i32; sink.record(disp_start, disp_start + 7, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp }; Ok(disp) } #[allow(non_snake_case)] #[inline(always)] fn read_sib< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let sib_start = words.offset() as u32 * 8; let sibbyte = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let disp = read_sib_disp(instr, words, modrm, sibbyte, sink)?; instr.disp = disp as u32; instr.regs[1].num |= sibbyte & 7; instr.regs[2].num |= (sibbyte >> 3) & 7; let scale = 1u8 << (sibbyte >> 6); instr.scale = scale; let op_spec = if disp == 0 { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address, but displacement is 0") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::Deref } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register") .with_id(sib_start + 0) ); OperandSpec::RegScale } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); OperandSpec::Deref } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegDisp } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, [index+disp] only") .with_id(sib_start + 0) ); OperandSpec::RegScaleDisp } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } } else { sink.record( sib_start + 0, sib_start + 2, InnerDescription::RegisterNumber("bbb", instr.regs[1].num, instr.regs[2]) .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); OperandSpec::RegDisp } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } }; Ok(op_spec) } #[allow(non_snake_case)] fn read_M_16bit< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let modbits = modrm >> 6; let mmm = modrm & 7; if modbits == 0b00 && mmm == 0b110 { instr.disp = read_num(words, 2)? as u16 as u32; return Ok(OperandSpec::DispU16); } match mmm { 0b000 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx + si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); instr.regs[2] = RegSpec::si(); }, 0b001 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx + di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); instr.regs[2] = RegSpec::di(); }, 0b010 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp + si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); instr.regs[2] = RegSpec::si(); }, 0b011 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp + di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); instr.regs[2] = RegSpec::di(); }, 0b100 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::si(); }, 0b101 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::di(); }, 0b110 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); }, 0b111 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); }, _ => { unreachable!("impossible bit pattern"); } } match modbits { 0b00 => { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)] with no displacement, register(s) selected by `mmm` (mod bits: 00)") .with_id(modrm_start + 0) ); if mmm > 3 { Ok(OperandSpec::Deref) } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScale) } }, 0b01 => { let disp_start = words.offset() as u32 * 8; instr.disp = read_num(words, 1)? as i8 as i32 as u32; let disp_end = words.offset() as u32 * 8; sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)+disp8] indexed by register(s) selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); sink.record( disp_start, disp_end - 1, InnerDescription::Number("displacement", instr.disp as i64) .with_id(disp_start + 3) ); if mmm > 3 { if instr.disp != 0 { Ok(OperandSpec::RegDisp) } else { Ok(OperandSpec::Deref) } } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScaleDisp) } }, 0b10 => { let disp_start = words.offset() as u32 * 8; instr.disp = read_num(words, 2)? as i16 as i32 as u32; let disp_end = words.offset() as u32 * 8; sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)+disp16] indexed by register(s) selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); sink.record( disp_start, disp_end - 1, InnerDescription::Number("displacement", instr.disp as i64) .with_id(disp_start + 3) ); if mmm > 3 { if instr.disp != 0 { Ok(OperandSpec::RegDisp) } else { Ok(OperandSpec::Deref) } } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScaleDisp) } }, _ => { unreachable!("read_M_16but but mod bits were not a memory operand"); } } } #[allow(non_snake_case)] fn read_M< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; if instr.prefixes.address_size() { return read_M_16bit(words, instr, modrm, sink); } instr.regs[1].bank = RegisterBank::D; let modbits = modrm >> 6; let mmm = modrm & 7; let op_spec = if mmm == 4 { sink.record( modrm_start, modrm_start + 2, InnerDescription::Misc("`mmm` field selects sib access") .with_id(modrm_start + 2) ); return read_sib(words, instr, modrm, sink); } else if mmm == 5 && modbits == 0b00 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("absolute disp32") .with_id(modrm_start + 0) ); sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("absolute disp32") .with_id(modrm_start + 0) ); instr.disp = read_num(words, 4)?; OperandSpec::DispU32 } else { instr.regs[1].num |= mmm; sink.record( modrm_start, modrm_start + 2, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(modrm_start + 2) ); if modbits == 0b00 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)") .with_id(modrm_start + 0) ); OperandSpec::Deref } else { let disp_start = words.offset(); let disp = if modbits == 0b01 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp8] indexed by register selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); read_num(words, 1)? as i8 as i32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp32] indexed by register selected by `mmm` (mod bits: 10)") .with_id(modrm_start + 0) ); read_num(words, 4)? as i32 }; let disp_end = words.offset(); sink.record( disp_start as u32 * 8, disp_end as u32 * 8 - 1, InnerDescription::Number("displacement", disp as i64) .with_id(words.offset() as u32 * 8 + 3) ); if disp == 0 { OperandSpec::Deref } else { instr.disp = disp as i32 as u32; OperandSpec::RegDisp } } }; Ok(op_spec) } /// the actual description for a selection of bits involved in decoding a /// [`protected_mode::Instruction`]. /// /// some prefixes are only identified as an `InnerDescription::Misc` string, while some are full /// `InnerDescription::SegmentPrefix(Segment)`. generally, strings should be considered unstable /// and only useful for displaying for human consumption. #[derive(Clone, Debug, PartialEq, Eq)] pub enum InnerDescription { /// the literal byte read for a `rex` prefix, `0x4_`. while 32-bit code does not have `rex` /// prefixes, this description is also used for the implied `rex`-type bits in `vex` and `evex` /// prefixes. RexPrefix(u8), /// the segment selected by a segment override prefix. this is not necessarily the actual /// segement used in the instruction's memory accesses, if any are made. SegmentPrefix(Segment), /// the opcode read for this instruction. this may be reported multiple times in an instruction /// if multiple spans of bits are necessary to determine the opcode. it is a bug if two /// different `Opcode` are indicated by different `InnerDescription::Opcode` reported from /// decoding the same instruction. this invariant is not well-tested, and may occur in /// practice. Opcode(Opcode), /// the operand code indicating how to read operands for this instruction. this is an internal /// detail of `yaxpeax-x86` but is typically named in a manner that can aid understanding the /// decoding process. `OperandCode` names are unstable, and this variant is only useful for /// displaying for human consumption. OperandCode(OperandCodeWrapper), /// a decoded register: a name for the bits used to decode it, the register number those bits /// specify, and the fully-constructed [`long_mode::RegSpec`] that was decoded. RegisterNumber(&'static str, u8, RegSpec), /// a miscellaneous string describing some bits of the instruction. this may describe a prefix, /// internal details of a prefix, error or constraints on an opcode, operand encoding details, /// or other items involved in an instruction. Misc(&'static str), /// a number involved in the instruction: typically either a disaplacement or immediate. the /// string describes which. the `i64` member is typically a sign-extended value from the /// appropriate original size, meaning there may be incorrect cases of a `65535u16` sign /// extending to `-1`. bug reports are highly encouraged for unexpected values. Number(&'static str, i64), /// a boundary between two logically distinct sections of an instruction. these typically /// separate the leading prefix string (if any), opcode, and operands (if any). the included /// string describes which boundary this is. boundary names should not be considered stable, /// and are useful at most for displaying for human consumption. Boundary(&'static str), } impl InnerDescription { fn with_id(self, id: u32) -> FieldDescription { FieldDescription { desc: self, id, } } } cfg_if::cfg_if! { if #[cfg(feature="fmt")] { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { InnerDescription::RexPrefix(bits) => { write!(f, "rex prefix: {}{}{}{}", if bits & 0x8 != 0 { "w" } else { "-" }, if bits & 0x4 != 0 { "r" } else { "-" }, if bits & 0x2 != 0 { "x" } else { "-" }, if bits & 0x1 != 0 { "b" } else { "-" }, ) } InnerDescription::SegmentPrefix(segment) => { write!(f, "segment override: {}", segment) } InnerDescription::Misc(text) => { f.write_str(text) } InnerDescription::Number(text, num) => { write!(f, "{}: {:#x}", text, num) } InnerDescription::Opcode(opc) => { write!(f, "opcode `{}`", opc) } InnerDescription::OperandCode(OperandCodeWrapper { code }) => { write!(f, "operand code `{:?}`", code) } InnerDescription::RegisterNumber(name, num, reg) => { write!(f, "`{}` (`{}` selects register number {})", reg, name, num) } InnerDescription::Boundary(desc) => { write!(f, "{}", desc) } } } } } else { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str("non-fmt build") } } } } // TODO: this derive ought to be `feature=fmt`.. #[derive(Clone, PartialEq, Eq, Debug)] pub struct FieldDescription { desc: InnerDescription, id: u32, } impl FieldDescription { /// the actual description associated with this bitfield. pub fn desc(&self) -> &InnerDescription { &self.desc } } impl yaxpeax_arch::annotation::FieldDescription for FieldDescription { fn id(&self) -> u32 { self.id } fn is_separator(&self) -> bool { if let InnerDescription::Boundary(_) = &self.desc { true } else { false } } } impl fmt::Display for FieldDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fmt::Display::fmt(&self.desc, f) } } #[inline(always)] fn record_opcode_record_found< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, sink: &mut S, opc: Opcode, code: OperandCode, opc_length: u32) { let offset = words.offset() as u32; let opcode_start_bit = (offset - opc_length) * 8; let opcode_end_bit = offset * 8 - 1; if offset > opc_length { sink.record( opcode_start_bit - 1, opcode_start_bit - 1, InnerDescription::Boundary("prefixes end") .with_id(opcode_start_bit) ); } if opc != Opcode::Invalid { sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::Opcode(opc), id: offset * 8 - opc_length * 8, }); } sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::OperandCode(OperandCodeWrapper { code }), id: offset * 8 - opc_length * 8 + 1, }); } #[derive(Copy, Clone)] struct DecodeCtx { check_lock: bool, rrr: u8, } impl DecodeCtx { fn new() -> Self { DecodeCtx { check_lock: false, rrr: 0 } } fn read_opc_hotpath< T: Reader<::Address, ::Word>, S: DescriptionSink, >(&mut self, mut b: u8, nextb: &mut u8, record: &mut OpcodeRecord, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result { if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 16 bits)"), id: words.offset() as u32 * 8 - 8, }); b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; *record = OPCODES[b as usize]; instruction.prefixes.set_operand_size(); } if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); instruction.opcode = opc; return Ok(true); } else if b == 0x0f { if words.offset() > 1 { sink.record( words.offset() as u32 * 8 - 8 - 1, words.offset() as u32 * 8 - 8 - 1, InnerDescription::Boundary("prefixes end") .with_id(words.offset() as u32 * 8 - 9) ); } let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (r, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, &mut instruction.prefixes), 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, &mut instruction.prefixes), 3) } else { (self.read_0f_opcode(b, &mut instruction.prefixes), 2) }; *record = r; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); instruction.opcode = opc; } else { unsafe { unreachable_unchecked(); } } return Ok(true); } else { *nextb = b; return Ok(false); } } fn read_with_annotations< T: Reader<::Address, ::Word>, S: DescriptionSink, >(&mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { words.mark(); let mut nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let mut next_rec = OPCODES[nextb as usize]; instruction.prefixes = Prefixes::new(0); // default registers to `[eax; 4]` // instruction.regs = unsafe { core::mem::transmute(0u64) }; // default operands to [RegRRR, Nothing, Nothing, Nothing] // instruction.operands = unsafe { core::mem::transmute(0x00_00_00_01) }; instruction.regs[1] = RegSpec::eax(); instruction.regs[2] = RegSpec::eax(); let record: OperandCode = if self.read_opc_hotpath(nextb, &mut nextb, &mut next_rec, words, instruction, sink)? { next_rec.operand() } else { let prefixes = &mut instruction.prefixes; let record = loop { let record = next_rec; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); break record; } else { let b = nextb; if b == 0x0f { if words.offset() > 1 { sink.record( words.offset() as u32 * 8 - 8 - 1, words.offset() as u32 * 8 - 8 - 1, InnerDescription::Boundary("prefixes end") .with_id(words.offset() as u32 * 8 - 9) ); } let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (rec, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, prefixes), 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, prefixes), 3) } else { (self.read_0f_opcode(b, prefixes), 2) }; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); } break rec; } if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 16 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_operand_size(); } else if b == 0x67 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("address size override (to 16 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_address_size(); } else if b == 0xf2 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("repnz prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_repnz(); } else if b == 0xf3 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("rep prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_rep(); } else { match b { 0x26 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::ES), id: words.offset() as u32 * 8 - 8, }); prefixes.set_es(); }, 0x2e => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::CS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_cs(); }, 0x36 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::SS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_ss(); }, 0x3e => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::DS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_ds(); }, 0x64 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::FS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_fs(); }, 0x65 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::GS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_gs(); }, 0xf0 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("lock prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_lock(); self.check_lock = true; }, // unlike 64-bit mode, the vex/evex prefixes are not recorded as prefixes - // they are LES/LDS/BOUND with special-case operand decoding. so we've // actually handled all possible prefixes at this point. _ => { unsafe { unreachable_unchecked(); } } } } nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; next_rec = OPCODES[nextb as usize]; } if words.offset() >= 15 { return Err(DecodeError::TooLong); } }; if let Interpretation::Instruction(opcode) = record.interp() { instruction.opcode = opcode; } else { unsafe { unreachable_unchecked(); } } record.operand() }; self.read_operands(decoder, words, instruction, record, sink)?; if self.check_lock { if (instruction.opcode as u32) < 0x1000 || !instruction.operands[0].is_memory() { return Err(DecodeError::InvalidPrefixes); } } Ok(()) } fn read_operands< T: Reader<::Address, ::Word>, S: DescriptionSink >(&mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, operand_code: OperandCode, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 1, words.offset() as u32 * 8 - 1, InnerDescription::Boundary("opcode ends/operands begin (typically)") .with_id(words.offset() as u32 * 8 - 1) ); let operand_code = OperandCodeBuilder::from_bits(operand_code as u16); let modrm_start = words.offset() as u32 * 8; let opcode_start = modrm_start - 8; if operand_code.is_only_modrm_operands() { let bank; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = bank as u8; } else { bank = RegisterBank::B; instruction.mem_size = 1; }; let modrm = read_modrm(words)?; instruction.regs[0].bank = bank; instruction.regs[0].num = (modrm >> 3) & 7; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", (modrm >> 3) & 7, instruction.regs[0]) .with_id(modrm_start + 3) ); } let mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } instruction.operand_count = 2; return Ok(()); } if operand_code.has_imm() { instruction.mem_size = 0; if operand_code.operand_case_handler_index() == OperandCase::Ibs { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmI8; } else { instruction.imm = read_imm_signed(words, 4)? as u32; sink.record( words.offset() as u32 * 8 - 32, words.offset() as u32 * 8 - 1, InnerDescription::Number("4-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); if instruction.opcode == Opcode::CALL { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::ImmI32; } instruction.operand_count = 1; return Ok(()); } let mut mem_oper = OperandSpec::Nothing; if operand_code.has_read_E() { let bank; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = bank as u8; } else { bank = RegisterBank::B; instruction.mem_size = 1; }; let modrm = read_modrm(words)?; instruction.regs[0].bank = bank; let rrr = (modrm >> 3) & 7; self.rrr = rrr; instruction.regs[0].num = rrr; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start + 3) ); } mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } } else { instruction.mem_size = 0; } if let Some(z_operand_code) = operand_code.get_embedded_instructions() { instruction.operands[0] = OperandSpec::RegRRR; let reg = z_operand_code.reg(); match z_operand_code.category() { 0 => { // these are Zv_R let bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[0] = RegSpec::from_parts(reg, bank); instruction.mem_size = 4; sink.record( opcode_start + 0, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); instruction.operand_count = 1; } 1 => { // Zv_AX let bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[0] = RegSpec::from_parts(0, bank); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(reg, bank); sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("opcode selects `eax` operand") .with_id(opcode_start + 2) ); if instruction.prefixes.operand_size() { sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("operand-size prefix override selects `ax`") .with_id(opcode_start + 2) ); } instruction.operand_count = 2; } 2 => { // these are Zb_Ib_R instruction.regs[0] = RegSpec { num: reg, bank: RegisterBank::B, }; sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); instruction.imm = read_imm_unsigned(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8)); instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } 3 => { // category == 3, Zv_Iv_R if instruction.prefixes.operand_size() { instruction.regs[0] = RegSpec::from_parts(reg, RegisterBank::W); instruction.imm = read_num(words, 2)? as u16 as u32; instruction.operands[1] = OperandSpec::ImmI16; let width = 2; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } else { instruction.regs[0] = RegSpec::from_parts(reg, RegisterBank::D); instruction.imm = read_num(words, 4)? as u32; instruction.operands[1] = OperandSpec::ImmI32; let width = 4; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); instruction.operand_count = 2; } _ => { unreachable!("bad category"); } } return Ok(()); } if !operand_code.has_read_E() { instruction.operands = [OperandSpec::RegRRR, OperandSpec::Nothing, OperandSpec::Nothing, OperandSpec::Nothing]; } instruction.operand_count = 2; // match operand_code { match operand_code.operand_case_handler_index() { // these operand cases are all `only_*`, and are unreachable here.. OperandCase::Internal | OperandCase::Gv_M | OperandCase::Ibs | OperandCase::Jvds => { } OperandCase::SingleMMMOper => { instruction.operands[0] = mem_oper; instruction.operand_count = 1; }, OperandCase::BaseOpWithI8 => { instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); } OperandCase::BaseOpWithIv => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if instruction.prefixes.operand_size() { let opwidth = 2; instruction.imm = read_imm_signed(words, opwidth)? as u32; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); instruction.operands[1] = OperandSpec::ImmI16; } else { let opwidth = 4; instruction.imm = read_imm_signed(words, opwidth)? as u32; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); instruction.operands[1] = OperandSpec::ImmI32; } }, OperandCase::MovI8 => { if self.rrr != 0 { if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XABORT; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); instruction.operands[0] = OperandSpec::ImmI8; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 1 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } OperandCase::MovIv => { if self.rrr != 0 { let opwidth = instruction.regs[0].bank as u8; if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XBEGIN; instruction.imm = if opwidth == 2 { let imm = read_imm_signed(words, 2)? as i16 as i32 as u32; sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 16) ); imm } else { let imm = read_imm_signed(words, 4)? as i32 as u32; sink.record( words.offset() as u32 * 8 - 32, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 32) ); imm }; instruction.operands[0] = OperandSpec::ImmI32; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; if instruction.prefixes.operand_size() { instruction.imm = read_imm_signed(words, 2)? as u32; sink.record( modrm_start + 8, modrm_start + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI16; } else { instruction.imm = read_imm_signed(words, 4)? as u32; sink.record( modrm_start + 8, modrm_start + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI32; } }, OperandCase::BitwiseWithI8 => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = read_num(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", num as i64) .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::ShiftBy1_v | OperandCase::ShiftBy1_b => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = 1; sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Misc("opcode specifies integer immediate 1") .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::BitwiseByCL => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.regs[0] = RegSpec::cl(); sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::RegisterNumber("reg", 1, instruction.regs[0]) .with_id(modrm_start - 7) ); instruction.operands[1] = OperandSpec::RegRRR; }, OperandCase::ModRM_0xf6 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { instruction.opcode = Opcode::TEST; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 8 + 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xf7 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { if instruction.prefixes.operand_size() { instruction.imm = read_imm_signed(words, 2)? as u32; instruction.operands[1] = OperandSpec::ImmI16; sink.record( modrm_start + 8, modrm_start + 8 + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.imm = read_imm_signed(words, 4)? as u32; sink.record( modrm_start + 8, modrm_start + 8 + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI32; }; } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xfe => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 2 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr: opcode requires rrr < 0b010") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOpcode); } instruction.opcode = [ Opcode::INC, Opcode::DEC, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operand_count = 1; } OperandCase::ModRM_0xff => { instruction.operands[0] = mem_oper; let r = self.rrr; if r == 7 { return Err(DecodeError::InvalidOpcode); } const TABLE: [Opcode; 7] = [ Opcode::INC, Opcode::DEC, Opcode::CALL, Opcode::CALLF, Opcode::JMP, Opcode::JMPF, Opcode::PUSH, ]; let opcode = TABLE[r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(opcode) .with_id(modrm_start - 8) ); if instruction.operands[0] == OperandSpec::RegMMM { if opcode == Opcode::CALL || opcode == Opcode::JMP { instruction.regs[1].bank = RegisterBank::D; if opcode == Opcode::CALL { instruction.mem_size = 4; } } else if opcode == Opcode::PUSH || opcode == Opcode::POP { if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { return Err(DecodeError::InvalidOperand); } } else { if opcode == Opcode::CALL || opcode == Opcode::JMP || opcode == Opcode::PUSH || opcode == Opcode::POP { if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { instruction.mem_size = 6; } } instruction.opcode = opcode; instruction.operand_count = 1; } OperandCase::Gv_Eb => { let w = RegisterBank::B; instruction.operands[1] = mem_oper; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = w; } else { instruction.mem_size = 1; } instruction.operand_count = 2; } OperandCase::Gv_Ew => { let w = RegisterBank::W; instruction.operands[1] = mem_oper; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = w; } else { instruction.mem_size = 2; } instruction.operand_count = 2; }, OperandCase::E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if instruction.operands[0] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, OperandCase::G_M_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 16; } OperandCase::G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; if instruction.operands[1] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { if instruction.opcode == Opcode::MOVDDUP { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } }, OperandCase::G_E_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); instruction.imm = read_num(words, 1)? as u8 as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8 + 1) ); if instruction.operands[1] != OperandSpec::RegMMM { if instruction.opcode == Opcode::CMPSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::CMPSD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; }, OperandCase::AL_Ibs => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::AX_Ivd => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.imm = read_imm_signed(words, bank as u8)? as u32; instruction.operands[1] = match bank as u8 { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, _ => unsafe { unreachable_unchecked() } }; sink.record( words.offset() as u32 * 8 - bank as u8 as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - bank as u8 as u32 * 8 + 1) ); } OperandCase::Ivs => { if !instruction.prefixes.operand_size() { instruction.imm = read_imm_unsigned(words, 4)?; instruction.operands[0] = OperandSpec::ImmI32; let opwidth = 4; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } else { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmI16; let opwidth = 2; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } instruction.operand_count = 1; }, OperandCase::ModRM_0x83 => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operands[1] = OperandSpec::ImmI8; }, OperandCase::I_3 => { sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Number("int", 3 as i64) .with_id(modrm_start - 1) ); instruction.imm = 3; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Nothing => { if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } if instruction.opcode == Opcode::RETURN { instruction.mem_size = 4; } else if instruction.opcode == Opcode::RETF { instruction.mem_size = 6; } // TODO: leave? instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); }, OperandCase::Ed_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; if instruction.operands[0] == OperandSpec::RegMMM { // fix the register to XMM sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to dword") .with_id(modrm_start as u32 + 1) ); instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } }, OperandCase::ModRM_0x8f => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 1 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("rrr field > 0b000 for this opcode is illegal, except with XOP extensions") .with_id(modrm_start - 8) ); // TODO: this is where XOP decoding would occur return Err(DecodeError::IncompleteDecoder); } instruction.opcode = [ Opcode::POP, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operand_count = 1; } OperandCase::G_Ed_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operand_count = 2; if instruction.operands[1] == OperandSpec::RegMMM { // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } }, OperandCase::G_E_mm_Ib => { instruction.operands[1] = mem_oper; instruction.imm = read_num(words, 1)? as u8 as u32; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; instruction.mem_size = 0; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_Ev_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u32; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = match instruction.opcode { Opcode::PEXTRB => 1, Opcode::PEXTRW => 2, Opcode::PEXTRD => 4, Opcode::EXTRACTPS => 4, Opcode::INSERTPS => 4, Opcode::PINSRB => 1, Opcode::PINSRW => 2, Opcode::PINSRD => 4, _ => 8, }; } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::PMOVX_E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { if [].contains(&instruction.opcode) { instruction.mem_size = 2; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD || instruction.opcode == Opcode::MOVHPS { return Err(DecodeError::InvalidOperand); } } } OperandCase::PMOVX_G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { if [Opcode::PMOVSXBQ, Opcode::PMOVZXBQ].contains(&instruction.opcode) { instruction.mem_size = 2; } else if [Opcode::PMOVZXBD, Opcode::UCOMISS, Opcode::COMISS, Opcode::CVTSS2SD].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD { return Err(DecodeError::InvalidOperand); } } } OperandCase::INV_Gv_M => { instruction.regs[0].bank = RegisterBank::D; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) { if instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } else if [Opcode::ENQCMD, Opcode::ENQCMDS].contains(&instruction.opcode) { instruction.mem_size = 64; } else { instruction.mem_size = 16; } } OperandCase::ModRM_0xc4 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if modrm & 0b11000000 == 0b11000000 { // interpret the c4 as a vex prefix if instruction.prefixes.vex_invalid() { // prefixes and then vex is invalid! reject it. return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("three-byte vex prefix (0xc4)") .with_id(words.offset() as u32 * 8 - 16) ); vex::three_byte_vex(words, modrm, instruction, sink)?; if decoder != &InstDecoder::default() { decoder.revise_instruction(instruction)?; } return Ok(()); } } else { // LES instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; if instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } }, OperandCase::ModRM_0xc5 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if (modrm & 0b1100_0000) == 0b1100_0000 { // interpret the c5 as a vex prefix if instruction.prefixes.vex_invalid() { // prefixes and then vex is invalid! reject it. return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("two-byte vex prefix (0xc5)") .with_id(words.offset() as u32 * 8 - 16) ); vex::two_byte_vex(words, modrm, instruction, sink)?; if decoder != &InstDecoder::default() { decoder.revise_instruction(instruction)?; } return Ok(()); } } else { // LDS instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; if instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } }, OperandCase::G_U_xmm_Ub => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::ModRM_0xf20f78 => { instruction.opcode = Opcode::INSERTQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u32; instruction.disp = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operands[3] = OperandSpec::ImmInDispField; instruction.operand_count = 4; } OperandCase::ModRM_0x660f78 => { instruction.opcode = Opcode::EXTRQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } if modrm >= 0b11_001_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u32; instruction.disp = read_num(words, 1)? as u8 as u32; instruction.operands[1] = OperandSpec::ImmU8; instruction.operands[2] = OperandSpec::ImmInDispField; instruction.operand_count = 3; } OperandCase::ModRM_0xf30f1e => { let modrm = read_modrm(words)?; match modrm { 0xfa => { instruction.opcode = Opcode::ENDBR64; instruction.operand_count = 0; }, 0xfb => { instruction.opcode = Opcode::ENDBR32; instruction.operand_count = 0; }, _ => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; instruction.mem_size = bank as u8; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); instruction.operand_count = 2; } }; } OperandCase::G_E_xmm_Ub => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::Gd_Ed => { instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } instruction.operands[1] = mem_oper; } OperandCase::Md_Gd => { instruction.regs[0].bank = RegisterBank::D; } /* OperandCase::Edq_Gdq => { let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0].bank = bank; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = bank; } instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.operand_count = 2; } */ OperandCase::G_U_xmm => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::X; instruction.regs[1].bank = RegisterBank::X; }, OperandCase::Gv_Ev_Ib => { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Gv_Ev_Iv => { let opwidth = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.imm = read_imm_signed(words, opwidth as u8)? as u32; instruction.operands[2] = match opwidth as u8 { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, _ => unsafe { unreachable_unchecked() } }; instruction.operand_count = 3; } OperandCase::Ev_Gv_Ib => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Ev_Gv_CL => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[3] = RegSpec::cl(); instruction.operand_count = 3; } OperandCase::G_mm_Ew_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_E_mm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if [Opcode::PUNPCKLBW, Opcode::PUNPCKLWD, Opcode::PUNPCKLDQ].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } }, OperandCase::G_U_mm => { instruction.regs[0].bank = RegisterBank::D; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; }, OperandCase::Gv_Ew_LAR => { instruction.operands[1] = mem_oper; // lar is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword/qword for // larger modes even though the upper 16 bits would be ignored. // // so the registers are correct by the time we're here, we might just need to override // mem size as well. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; }, OperandCase::Gv_Ew_LSL => { instruction.operands[1] = mem_oper; // lsl is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword for larger // modes even though the upper 16 bits would be ignored. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; }, OperandCase::Gd_Ev => { instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } if instruction.regs[0].bank == RegisterBank::W { instruction.regs[0].bank = RegisterBank::D; }; instruction.operand_count = 2; }, op @ OperandCase::AL_Ob | op @ OperandCase::AX_Ov => { match op { OperandCase::AL_Ob => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::AX_Ov => { let b = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; if instruction.prefixes.address_size() { instruction.operands[1] = OperandSpec::DispU16; } else { instruction.operands[1] = OperandSpec::DispU32; }; instruction.operand_count = 2; } op @ OperandCase::Ob_AL | op @ OperandCase::Ov_AX => { match op { OperandCase::Ob_AL => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::Ov_AX => { let b = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if instruction.prefixes.address_size() { 2 } else { 4 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; instruction.operands[0] = if instruction.prefixes.address_size() { OperandSpec::DispU16 } else { OperandSpec::DispU32 }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::I_1 => { instruction.imm = 1; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } /* OperandCase::Unsupported => { return Err(DecodeError::IncompleteDecoder); } */ OperandCase::Iw_Ib => { instruction.disp = read_num(words, 2)? as u32; instruction.imm = read_num(words, 1)? as u32; instruction.operands[0] = OperandSpec::ImmInDispField; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Fw => { if instruction.prefixes.operand_size() { instruction.opcode = Opcode::IRET; } else { instruction.opcode = Opcode::IRETD; } instruction.operand_count = 0; } OperandCase::G_mm_U_mm => { instruction.regs[0].bank = RegisterBank::MM; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::E_G_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0].bank = RegisterBank::D; instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::D; } } OperandCase::G_E_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::D; instruction.operand_count = 2; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::D; } } OperandCase::G_Mq_mm => { instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::MOVQ_f30f => { // if rex.w is set, the f3 prefix no longer applies and this becomes an 0f7e movq, // rather than f30f7e movq. // // the difference here is that 0f7e movq has reversed operand order from f30f7e movq, // in addition to the selected register banks being different. // // anyway, there are two operands, and the primary concern here is "what are they?". instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::X; } } OperandCase::ModRM_0x0f0d => { let r = instruction.regs[0].num & 0b111; let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; match r { 1 => { instruction.opcode = Opcode::PREFETCHW; } _ => { instruction.opcode = Opcode::NOP; } } instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 64; } else { instruction.regs[1].bank = bank; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f0f => { // 3dnow instructions are WILD, the opcode is encoded as an imm8 trailing the // instruction. instruction.operands[1] = mem_oper; instruction.regs[0].num &= 0b0111; instruction.regs[0].bank = RegisterBank::MM; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; } let opcode = read_modrm(words)?; match opcode { 0x0c => { instruction.opcode = Opcode::PI2FW; } 0x0d => { instruction.opcode = Opcode::PI2FD; } 0x1c => { instruction.opcode = Opcode::PF2IW; } 0x1d => { instruction.opcode = Opcode::PF2ID; } 0x8a => { instruction.opcode = Opcode::PFNACC; } 0x8e => { instruction.opcode = Opcode::PFPNACC; } 0x90 => { instruction.opcode = Opcode::PFCMPGE; } 0x94 => { instruction.opcode = Opcode::PFMIN; } 0x96 => { instruction.opcode = Opcode::PFRCP; } 0x97 => { instruction.opcode = Opcode::PFRSQRT; } 0x9a => { instruction.opcode = Opcode::PFSUB; } 0x9e => { instruction.opcode = Opcode::PFADD; } 0xa0 => { instruction.opcode = Opcode::PFCMPGT; } 0xa4 => { instruction.opcode = Opcode::PFMAX; } 0xa6 => { instruction.opcode = Opcode::PFRCPIT1; } 0xa7 => { instruction.opcode = Opcode::PFRSQIT1; } 0xaa => { instruction.opcode = Opcode::PFSUBR; } 0xae => { instruction.opcode = Opcode::PFACC; } 0xb0 => { instruction.opcode = Opcode::PFCMPEQ; } 0xb4 => { instruction.opcode = Opcode::PFMUL; } 0xb6 => { instruction.opcode = Opcode::PFRCPIT2; } 0xb7 => { instruction.opcode = Opcode::PMULHRW; } 0xbb => { instruction.opcode = Opcode::PSWAPD; } 0xbf => { instruction.opcode = Opcode::PAVGUSB; } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0x0fc7 => { if instruction.prefixes.repnz() { let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } if instruction.prefixes.operand_size() { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } return Ok(()); } 6 => { instruction.opcode = Opcode::VMCLEAR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // word-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::W, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDRAND; } else { instruction.mem_size = 8; } instruction.operand_count = 1; return Ok(()); } 7 => { instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // word-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::W, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDSEED; } else { return Err(DecodeError::InvalidOpcode); } instruction.operand_count = 1; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } if instruction.prefixes.rep() { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } } 6 => { instruction.opcode = Opcode::VMXON; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // invalid as `vmxon`, reg-form is `senduipi` instruction.opcode = Opcode::SENDUIPI; // and the operand is always a dword register instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 8; } instruction.operand_count = 1; } 7 => { instruction.opcode = Opcode::RDPID; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 0b111; let opcode = match r { 0b001 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; Opcode::CMPXCHG8B } } 0b011 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XRSTORS } } 0b100 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XSAVEC } } 0b101 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XSAVES } } 0b110 => { if is_reg { Opcode::RDRAND } else { instruction.mem_size = 8; Opcode::VMPTRLD } } 0b111 => { if is_reg { Opcode::RDSEED } else { instruction.mem_size = 8; Opcode::VMPTRST } } _ => { return Err(DecodeError::InvalidOperand); } }; instruction.opcode = opcode; instruction.operand_count = 1; let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; }, OperandCase::ModRM_0x0f71 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLW, Opcode::Invalid, Opcode::PSRAW, Opcode::Invalid, Opcode::PSLLW, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; }, OperandCase::ModRM_0x0f72 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLD, Opcode::Invalid, Opcode::PSRAD, Opcode::Invalid, Opcode::PSLLD, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0x0f73 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; match r { 2 => { instruction.opcode = Opcode::PSRLQ; } 3 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSRLDQ; } 6 => { instruction.opcode = Opcode::PSLLQ; } 7 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0xf30f38d8 => { instruction.operand_count = 1; let r = instruction.regs[0].num & 0b111; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } match r { 0b000 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESENCWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b001 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESDECWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b010 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESENCWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b011 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESDECWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0xf30f38dc => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::LOADIWKEY; } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESENC128KL; } } OperandCase::ModRM_0xf30f38dd => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESDEC128KL; } } OperandCase::ModRM_0xf30f38de => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESENC256KL; } } OperandCase::ModRM_0xf30f38df => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESDEC256KL; } } OperandCase::ModRM_0xf30f38fa => { instruction.opcode = Opcode::ENCODEKEY128; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f38fb => { instruction.opcode = Opcode::ENCODEKEY256; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f3af0 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOpcode); // invalid } instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::G_mm_Ed => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } OperandCase::G_mm_E => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } OperandCase::Ed_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } OperandCase::E_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } OperandCase::G_xmm_Ew_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u32; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } }, OperandCase::G_xmm_Ed => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } }, OperandCase::G_mm_E_xmm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, op @ OperandCase::G_xmm_U_mm | op @ OperandCase::G_xmm_E_mm => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if op == OperandCase::G_xmm_U_mm { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } } }, OperandCase::Rv_Gmm_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u32; instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } OperandCase::G_mm_U_xmm => { instruction.regs[1].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } // sure hope these aren't backwards huh OperandCase::AL_Xb => { instruction.regs[0] = RegSpec::al(); if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::si(); } else { instruction.regs[1] = RegSpec::esi(); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_Xb => { if instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_di; instruction.operands[1] = OperandSpec::Deref_si; } else { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_AL => { instruction.regs[0] = RegSpec::al(); if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::di(); } else { instruction.regs[1] = RegSpec::edi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::AX_Xv => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::si(); } else { instruction.regs[1] = RegSpec::esi(); } instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = bank as u8; } OperandCase::Yv_AX => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::di(); } else { instruction.regs[1] = RegSpec::edi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = bank as u8; } OperandCase::Yv_Xv => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = bank as u8; if instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_di; instruction.operands[1] = OperandSpec::Deref_si; } else { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } } OperandCase::ModRM_0x0f12 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::MOVHLPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVLPD; } else { instruction.opcode = Opcode::MOVLPS; } } } OperandCase::ModRM_0x0f16 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::MOVLHPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVHPD; } else { instruction.opcode = Opcode::MOVHPS; } } } OperandCase::ModRM_0x0f18 => { let rrr = instruction.regs[0].num & 0b111; instruction.operands[0] = mem_oper; instruction.operand_count = 1; // only PREFETCH* are invalid on reg operand instruction.opcode = if mem_oper == OperandSpec::RegMMM && rrr < 4 { Opcode::NOP } else { match rrr { 0 => Opcode::PREFETCHNTA, 1 => Opcode::PREFETCH0, 2 => Opcode::PREFETCH1, 3 => Opcode::PREFETCH2, _ => Opcode::NOP, } }; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 64; } } OperandCase::Gd_U_xmm => { if instruction.operands[1] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; } OperandCase::Gd_Eq_xmm => { if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } } OperandCase::Gv_E_xmm => { if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } } OperandCase::M_G_xmm => { if instruction.opcode == Opcode::MOVNTSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::MOVNTPD || instruction.opcode == Opcode::MOVNTDQ || instruction.opcode == Opcode::MOVNTPS { instruction.mem_size = 16; } else { instruction.mem_size = 8; } instruction.regs[0].bank = RegisterBank::X; } OperandCase::Ew_Sw => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::Sw_Ew => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } // quoth the manual: // ``` // The MOV instruction cannot be used to load the CS register. Attempting to do so // results in an invalid opcode excep-tion (#UD). To load the CS register, use the far // JMP, CALL, or RET instruction. // ``` if r == 1 { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::CVT_AA => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = if !instruction.prefixes.operand_size() { Opcode::CWDE } else { Opcode::CBW }; } OperandCase::CVT_DA => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = if !instruction.prefixes.operand_size() { Opcode::CDQ } else { Opcode::CWD }; } OperandCase::Ib => { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Iw => { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmU16; if instruction.opcode == Opcode::RETURN { instruction.mem_size = 4; } else { instruction.mem_size = 6; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f00 => { instruction.operand_count = 1; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { instruction.opcode = Opcode::SLDT; } else if r == 1 { instruction.opcode = Opcode::STR; } else if r == 2 { instruction.opcode = Opcode::LLDT; } else if r == 3 { instruction.opcode = Opcode::LTR; } else if r == 4 { instruction.opcode = Opcode::VERR; } else if r == 5 { instruction.opcode = Opcode::VERW; } else if r == 6 { // TODO: this would be jmpe for x86-on-itanium systems. instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else if r == 7 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else { unreachable!("r <= 8"); } instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCase::ModRM_0x0f01 => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; const TBL: [Opcode; 8] = [ Opcode::ENCLV, Opcode::VMCALL, Opcode::VMLAUNCH, Opcode::VMRESUME, Opcode::VMXOFF, Opcode::PCONFIG, Opcode::Invalid, Opcode::Invalid, ]; instruction.opcode = TBL[m as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::SGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 1 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } if instruction.prefixes.operand_size() { match m { 0b100 => { instruction.opcode = Opcode::TDCALL; } 0b101 => { instruction.opcode = Opcode::SEAMRET; } 0b110 => { instruction.opcode = Opcode::SEAMOPS; } 0b111 => { instruction.opcode = Opcode::SEAMCALL; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { match m { 0b000 => { instruction.opcode = Opcode::MONITOR; } 0b001 => { instruction.opcode = Opcode::MWAIT; }, 0b010 => { instruction.opcode = Opcode::CLAC; } 0b011 => { instruction.opcode = Opcode::STAC; } 0b111 => { instruction.opcode = Opcode::ENCLS; } _ => { return Err(DecodeError::InvalidOpcode); } } } } else { instruction.opcode = Opcode::SIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 2 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match m { 0b000 => { instruction.opcode = Opcode::XGETBV; } 0b001 => { instruction.opcode = Opcode::XSETBV; } 0b100 => { instruction.opcode = Opcode::VMFUNC; } 0b101 => { instruction.opcode = Opcode::XEND; } 0b110 => { instruction.opcode = Opcode::XTEST; } 0b111 => { instruction.opcode = Opcode::ENCLU; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { instruction.opcode = Opcode::LGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 3 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { match m { 0b000 => { instruction.opcode = Opcode::VMRUN; instruction.operand_count = 1; instruction.regs[0] = RegSpec::eax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b001 => { instruction.opcode = Opcode::VMMCALL; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b010 => { instruction.opcode = Opcode::VMLOAD; instruction.operand_count = 1; instruction.regs[0] = RegSpec::eax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b011 => { instruction.opcode = Opcode::VMSAVE; instruction.operand_count = 1; instruction.regs[0] = RegSpec::eax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b100 => { instruction.opcode = Opcode::STGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b101 => { instruction.opcode = Opcode::CLGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b110 => { instruction.opcode = Opcode::SKINIT; instruction.operand_count = 1; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::eax(); }, 0b111 => { instruction.opcode = Opcode::INVLPGA; instruction.operand_count = 2; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[0] = RegSpec::eax(); instruction.regs[1] = RegSpec::ecx(); }, _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } } } else { instruction.opcode = Opcode::LIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 4 { // TODO: this permits storing only to word-size registers // spec suggets this might do something different for f.ex rdi? instruction.opcode = Opcode::SMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 5 { let mod_bits = modrm >> 6; if mod_bits != 0b11 { if !instruction.prefixes.rep() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RSTORSSP; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.mem_size = 8; instruction.operand_count = 1; return Ok(()); } let m = modrm & 7; match m { 0b000 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XSUSLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SETSSBSY; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b001 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XRESLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b010 => { if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SAVEPREVSSP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b100 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::UIRET; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b101 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::TESTUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b110 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::CLUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RDPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b111 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::STUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::WRPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } } else if r == 6 { instruction.opcode = Opcode::LMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 7 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if m == 0 { // swapgs is not valid in modes other than 64-bit return Err(DecodeError::InvalidOpcode); } else if m == 1 { instruction.opcode = Opcode::RDTSCP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 2 { instruction.opcode = Opcode::MONITORX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 3 { instruction.opcode = Opcode::MWAITX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 4 { instruction.opcode = Opcode::CLZERO; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 5 { instruction.opcode = Opcode::RDPRU; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::ecx(); instruction.operand_count = 1; } else if m == 6 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPADJUST; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPUPDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::INVLPGB; instruction.operand_count = 3; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[0] = RegSpec::eax(); instruction.regs[1] = RegSpec::edx(); instruction.regs[3] = RegSpec::ecx(); } else if m == 7 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSMASH; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PVALIDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::TLBSYNC; instruction.operand_count = 0; } else { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::INVLPG; instruction.operand_count = 1; instruction.mem_size = 1; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else { unreachable!("r <= 8"); } } OperandCase::ModRM_0x0fae => { let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; let m = modrm & 7; if instruction.prefixes.operand_size() && !(instruction.prefixes.rep() || instruction.prefixes.repnz()) { instruction.prefixes.unset_operand_size(); if modrm < 0xc0 { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::CLWB } 7 => { Opcode::CLFLUSHOPT } _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::B /* opwidth */, sink)?; instruction.mem_size = 64; instruction.operand_count = 1; } else { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::TPAUSE } _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; } return Ok(()); } if instruction.prefixes.repnz() { if (modrm & 0xc0) == 0xc0 { match r { 6 => { instruction.opcode = Opcode::UMWAIT; instruction.regs[0] = RegSpec { bank: RegisterBank::D, num: m, }; instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } } if instruction.prefixes.rep() { if r == 4 { if instruction.prefixes.operand_size() { // xed specifically rejects this. seeems out of line since rep takes // precedence elsewhere, but ok i guess return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::PTWRITE; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 1; return Ok(()); } if (modrm & 0xc0) == 0xc0 { match r { 0 => { instruction.opcode = Opcode::RDFSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 1 => { instruction.opcode = Opcode::RDGSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 2 => { instruction.opcode = Opcode::WRFSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 3 => { instruction.opcode = Opcode::WRGSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 5 => { instruction.opcode = Opcode::INCSSP; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 6 => { instruction.opcode = Opcode::UMONITOR; if instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::W); } else { instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); } instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } else { match r { 6 => { instruction.opcode = Opcode::CLRSSBSY; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; instruction.mem_size = 8; return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } } let mod_bits = modrm >> 6; // all the 0b11 instructions are err or no-operands if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match r { // invalid rrr for 0x0fae, mod: 11 0 | 1 | 2 | 3 | 4 => { return Err(DecodeError::InvalidOpcode); }, 5 => { instruction.opcode = Opcode::LFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 6 => { instruction.opcode = Opcode::MFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 7 => { instruction.opcode = Opcode::SFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, _ => { unsafe { unreachable_unchecked() } /* r <=7 */ } } } else { // these can't be prefixed, so says `xed` i guess. if instruction.prefixes.operand_size() || instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; let (opcode, mem_size) = [ (Opcode::FXSAVE, 63), (Opcode::FXRSTOR, 63), (Opcode::LDMXCSR, 4), (Opcode::STMXCSR, 4), (Opcode::XSAVE, 63), (Opcode::XRSTOR, 63), (Opcode::XSAVEOPT, 63), (Opcode::CLFLUSH, 64), ][r as usize]; instruction.opcode = opcode; instruction.mem_size = mem_size; instruction.operands[0] = read_M(words, instruction, modrm, sink)?; } } OperandCase::ModRM_0x0fba => { let bank = if instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::BT, Opcode::BTS, Opcode::BTR, Opcode::BTC ]; instruction.opcode = TBL[r as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; instruction.operand_count = 2; } op @ OperandCase::Rq_Cq_0 | op @ OperandCase::Rq_Dq_0 | op @ OperandCase::Cq_Rq_0 | op @ OperandCase::Dq_Rq_0 => { let modrm = read_modrm(words)?; let m = modrm & 7; let r = (modrm >> 3) & 7; let bank = match op { OperandCase::Rq_Cq_0 | OperandCase::Cq_Rq_0 => { if r != 0 && r != 2 && r != 3 && r != 4 { return Err(DecodeError::InvalidOperand); } RegisterBank::CR }, OperandCase::Rq_Dq_0 | OperandCase::Dq_Rq_0 => { if r > 7 { // unreachable but mirrors x86_64 code return Err(DecodeError::InvalidOperand); } RegisterBank::DR }, _ => unsafe { unreachable_unchecked() } }; let (rrr, mmm) = match op { OperandCase::Rq_Cq_0 | OperandCase::Rq_Dq_0 => (1, 0), OperandCase::Cq_Rq_0 | OperandCase::Dq_Rq_0 => (0, 1), _ => unsafe { unreachable_unchecked() } }; instruction.regs[0] = RegSpec { bank: bank, num: r }; instruction.regs[1] = RegSpec { bank: RegisterBank::D, num: m }; instruction.operands[mmm] = OperandSpec::RegMMM; instruction.operands[rrr] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::CS => { instruction.regs[0] = RegSpec::cs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::DS => { instruction.regs[0] = RegSpec::ds(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::ES => { instruction.regs[0] = RegSpec::es(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::SS => { instruction.regs[0] = RegSpec::ss(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::FS => { instruction.regs[0] = RegSpec::fs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::GS => { instruction.regs[0] = RegSpec::gs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::AL_Ib => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::AX_Ib => { instruction.regs[0].num = 0; instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Ib_AL => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Ib_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::AX_DX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::AL_DX => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::DX_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::DX_AL => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Yb_DX => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::edi(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::Yv_DX => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::edi(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::DX_Xb => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::esi(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::AH => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } OperandCase::DX_Xv => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::esi(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; if instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::x87_d8 | OperandCase::x87_d9 | OperandCase::x87_da | OperandCase::x87_db | OperandCase::x87_dc | OperandCase::x87_dd | OperandCase::x87_de | OperandCase::x87_df => { return decode_x87(words, instruction, operand_code.operand_case_handler_index(), sink); } OperandCase::MOVDIR64B => { instruction.mem_size = 64; if instruction.prefixes.address_size() { instruction.regs[0].bank = RegisterBank::W; } else { instruction.regs[0].bank = RegisterBank::D; } } OperandCase::ModRM_0x62 => { let modrm = read_modrm(words)?; if modrm < 0xc0 { instruction.regs[0] = RegSpec { bank: RegisterBank::D, num: (modrm >> 3) & 7 }; if instruction.prefixes.operand_size() { instruction.regs[0].bank = RegisterBank::W; instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; instruction.operand_count = 2; } else { let prefixes = &instruction.prefixes; if prefixes.lock() || prefixes.operand_size() || prefixes.rep_any() { return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("evex prefix (0x62)") .with_id(words.offset() as u32 * 8 - 16) ); evex::read_evex(words, instruction, Some(modrm), sink)?; } } } OperandCase::AbsFar => { instruction.operands[0] = OperandSpec::AbsoluteFarAddress; instruction.operand_count = 1; instruction.mem_size = 0; // read segment let addr_size = if instruction.prefixes.operand_size() { 2 } else { 4 }; instruction.imm = read_num(words, addr_size)?; instruction.disp = read_num(words, 2)? as u16 as u32; } OperandCase::Ew_Gw => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec { bank: RegisterBank::W, num: (modrm >> 3) & 7 }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = 2; instruction.operand_count = 2; }, }; Ok(()) } #[inline(always)] fn read_0f_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // seems like f2 takes priority, then f3, then 66, then "no prefix". for SOME instructions an // invalid prefix is in fact an invalid instruction. so just duplicate for the four kinds of // opcode lists. if prefixes.repnz() { REPNZ_0F_CODES[opcode as usize] } else if prefixes.rep() { REP_0F_CODES[opcode as usize] } else if prefixes.operand_size() { OPERAND_SIZE_0F_CODES[opcode as usize] } else { NORMAL_0F_CODES[opcode as usize] } } fn read_0f38_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { return match opcode { 0xd8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38d8), 0xdc => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dc), 0xdd => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dd), 0xde => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38de), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38df), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ADOX), OperandCode::Gv_Ev), 0xf8 => { prefixes.unset_operand_size(); OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::INV_Gv_M) }, 0xfa => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fa), 0xfb => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fb), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.repnz() { return match opcode { 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gv_Eb), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gd_Ev), 0xf8 => { prefixes.unset_operand_size(); OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMD), OperandCode::INV_Gv_M) }, _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.operand_size() { // leave operand size present for `movbe` if opcode != 0xf0 && opcode != 0xf1 { prefixes.unset_operand_size(); } return match opcode { 0x00 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_xmm), 0x01 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_xmm), 0x02 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_xmm), 0x03 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_xmm), 0x04 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_xmm), 0x05 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_xmm), 0x06 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_xmm), 0x07 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_xmm), 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_xmm), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_xmm), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_xmm), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_xmm), 0x10 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDVB), OperandCode::G_E_xmm), 0x14 => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPS), OperandCode::G_E_xmm), 0x15 => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPD), OperandCode::G_E_xmm), 0x17 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PTEST), OperandCode::G_E_xmm), 0x1c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_xmm), 0x1d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_xmm), 0x1e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_xmm), 0x20 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBW), OperandCode::PMOVX_G_E_xmm), 0x21 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBD), OperandCode::PMOVX_G_E_xmm), 0x22 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBQ), OperandCode::PMOVX_G_E_xmm), 0x23 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWD), OperandCode::PMOVX_G_E_xmm), 0x24 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWQ), OperandCode::PMOVX_G_E_xmm), 0x25 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXDQ), OperandCode::PMOVX_G_E_xmm), 0x28 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULDQ), OperandCode::G_E_xmm), 0x29 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQQ), OperandCode::G_E_xmm), 0x2a => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQA), OperandCode::G_M_xmm), 0x2b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSDW), OperandCode::G_E_xmm), 0x30 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBW), OperandCode::PMOVX_G_E_xmm), 0x31 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBD), OperandCode::PMOVX_G_E_xmm), 0x32 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBQ), OperandCode::PMOVX_G_E_xmm), 0x33 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWD), OperandCode::PMOVX_G_E_xmm), 0x34 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWQ), OperandCode::PMOVX_G_E_xmm), 0x35 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXDQ), OperandCode::PMOVX_G_E_xmm), 0x37 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTQ), OperandCode::G_E_xmm), 0x38 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSB), OperandCode::G_E_xmm), 0x39 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSD), OperandCode::G_E_xmm), 0x3a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUW), OperandCode::G_E_xmm), 0x3b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUD), OperandCode::G_E_xmm), 0x3c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSB), OperandCode::G_E_xmm), 0x3d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSD), OperandCode::G_E_xmm), 0x3e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUW), OperandCode::G_E_xmm), 0x3f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUD), OperandCode::G_E_xmm), 0x40 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLD), OperandCode::G_E_xmm), 0x41 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHMINPOSUW), OperandCode::G_E_xmm), 0x80 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVEPT), OperandCode::INV_Gv_M), 0x81 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVVPID), OperandCode::INV_Gv_M), 0x82 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVPCID), OperandCode::INV_Gv_M), 0xcf => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8MULB), OperandCode::G_E_xmm), 0xdb => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESIMC), OperandCode::G_E_xmm), 0xdc => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENC), OperandCode::G_E_xmm), 0xdd => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENCLAST), OperandCode::G_E_xmm), 0xde => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDEC), OperandCode::G_E_xmm), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDECLAST), OperandCode::G_E_xmm), 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), 0xf5 => OpcodeRecord::new(Interpretation::Instruction(Opcode::WRUSS), OperandCode::Md_Gd), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ADCX), OperandCode::Gv_Ev), 0xf8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIR64B), OperandCode::MOVDIR64B), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } else { return match opcode { 0x00 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_mm), 0x01 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_mm), 0x02 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_mm), 0x03 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_mm), 0x04 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_mm), 0x05 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_mm), 0x06 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_mm), 0x07 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_mm), 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_mm), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_mm), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_mm), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_mm), 0x1c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_mm), 0x1d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_mm), 0x1e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_mm), 0xc8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1NEXTE), OperandCode::G_E_xmm), 0xc9 => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG1), OperandCode::G_E_xmm), 0xca => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG2), OperandCode::G_E_xmm), 0xcb => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256RNDS2), OperandCode::G_E_xmm), 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG1), OperandCode::G_E_xmm), 0xcd => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG2), OperandCode::G_E_xmm), 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::WRSS), OperandCode::Md_Gd), 0xf9 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIRI), OperandCode::Md_Gd), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } } fn read_0f3a_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { if prefixes != &Prefixes::new(0x10) { return OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); } return match opcode { 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.repnz() { return OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); } if prefixes.operand_size() { return match opcode { 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPS), OperandCode::G_E_xmm_Ib), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPD), OperandCode::G_E_xmm_Ib), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSS), OperandCode::G_E_xmm_Ib), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSD), OperandCode::G_E_xmm_Ib), 0x0c => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPS), OperandCode::G_E_xmm_Ib), 0x0d => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPD), OperandCode::G_E_xmm_Ib), 0x0e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDW), OperandCode::G_E_xmm_Ib), 0x0f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_xmm_Ib), 0x14 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRB), OperandCode::G_Ev_xmm_Ib), 0x15 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_Ev_xmm_Ib), 0x16 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRD), OperandCode::G_Ev_xmm_Ib), 0x17 => OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRACTPS), OperandCode::G_Ev_xmm_Ib), 0x20 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRB), OperandCode::G_Ev_xmm_Ib), 0x21 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTPS), OperandCode::G_Ev_xmm_Ib), 0x22 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRD), OperandCode::G_Ev_xmm_Ib), 0x40 => OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPS), OperandCode::G_E_xmm_Ib), 0x41 => OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPD), OperandCode::G_E_xmm_Ib), 0x42 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MPSADBW), OperandCode::G_E_xmm_Ib), 0x44 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCLMULQDQ), OperandCode::G_E_xmm_Ib), 0x60 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRM), OperandCode::G_E_xmm_Ib), 0x61 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRI), OperandCode::G_E_xmm_Ib), 0x62 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRM), OperandCode::G_E_xmm_Ib), 0x63 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRI), OperandCode::G_E_xmm_Ib), 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ib), 0xce => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEQB), OperandCode::G_E_xmm_Ub), 0xcf => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEINVQB), OperandCode::G_E_xmm_Ub), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESKEYGENASSIST), OperandCode::G_E_xmm_Ub), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } return match opcode { 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ub), 0x0f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_mm_Ib), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } } fn decode_x87< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: OperandCase, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("x87 opcode") .with_id(words.offset() as u32 * 8 - 1) ); #[allow(non_camel_case_types)] enum OperandCodeX87 { Est, St_Est, St_Edst, St_Eqst, St_Ew, St_Mw, St_Md, St_Mq, St_Mm, Ew, Est_St, Edst_St, Eqst_St, Ed_St, Mw_St, Md_St, Mq_St, Mm_St, Ex87S, Nothing, } // every x87 instruction is conditional on rrr bits let modrm = read_modrm(words)?; let r = (modrm >> 3) & 0b111; let (opcode, x87_operands) = match operand_code { OperandCase::x87_d8 => { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Edst), 1 => (Opcode::FMUL, OperandCodeX87::St_Edst), 2 => (Opcode::FCOM, OperandCodeX87::St_Edst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Edst), 4 => (Opcode::FSUB, OperandCodeX87::St_Edst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Edst), 6 => (Opcode::FDIV, OperandCodeX87::St_Edst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Edst), _ => { unreachable!("impossible r"); } } } OperandCase::x87_d9 => { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Edst), 1 => { if modrm >= 0xc0 { (Opcode::FXCH, OperandCodeX87::St_Est) } else { return Err(DecodeError::InvalidOpcode); } }, 2 => { if modrm >= 0xc0 { if modrm == 0xd0 { (Opcode::FNOP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } else { (Opcode::FST, OperandCodeX87::Ed_St) } } 3 => { if modrm >= 0xc0 { (Opcode::FSTPNCE, OperandCodeX87::Est_St) } else { (Opcode::FSTP, OperandCodeX87::Edst_St) } }, 4 => { if modrm >= 0xc0 { match modrm { 0xe0 => (Opcode::FCHS, OperandCodeX87::Nothing), 0xe1 => (Opcode::FABS, OperandCodeX87::Nothing), 0xe2 => { return Err(DecodeError::InvalidOpcode); }, 0xe3 => { return Err(DecodeError::InvalidOpcode); }, 0xe4 => (Opcode::FTST, OperandCodeX87::Nothing), 0xe5 => (Opcode::FXAM, OperandCodeX87::Nothing), 0xe6 => { return Err(DecodeError::InvalidOpcode); }, 0xe7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDENV, OperandCodeX87::Ex87S) // x87 state } }, 5 => { if modrm >= 0xc0 { match modrm { 0xe8 => (Opcode::FLD1, OperandCodeX87::Nothing), 0xe9 => (Opcode::FLDL2T, OperandCodeX87::Nothing), 0xea => (Opcode::FLDL2E, OperandCodeX87::Nothing), 0xeb => (Opcode::FLDPI, OperandCodeX87::Nothing), 0xec => (Opcode::FLDLG2, OperandCodeX87::Nothing), 0xed => (Opcode::FLDLN2, OperandCodeX87::Nothing), 0xee => (Opcode::FLDZ, OperandCodeX87::Nothing), 0xef => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDCW, OperandCodeX87::Ew) } } 6 => { if modrm >= 0xc0 { match modrm { 0xf0 => (Opcode::F2XM1, OperandCodeX87::Nothing), 0xf1 => (Opcode::FYL2X, OperandCodeX87::Nothing), 0xf2 => (Opcode::FPTAN, OperandCodeX87::Nothing), 0xf3 => (Opcode::FPATAN, OperandCodeX87::Nothing), 0xf4 => (Opcode::FXTRACT, OperandCodeX87::Nothing), 0xf5 => (Opcode::FPREM1, OperandCodeX87::Nothing), 0xf6 => (Opcode::FDECSTP, OperandCodeX87::Nothing), 0xf7 => (Opcode::FINCSTP, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTENV, OperandCodeX87::Ex87S) // x87 state } } 7 => { if modrm >= 0xc0 { match modrm { 0xf8 => (Opcode::FPREM, OperandCodeX87::Nothing), 0xf9 => (Opcode::FYL2XP1, OperandCodeX87::Nothing), 0xfa => (Opcode::FSQRT, OperandCodeX87::Nothing), 0xfb => (Opcode::FSINCOS, OperandCodeX87::Nothing), 0xfc => (Opcode::FRNDINT, OperandCodeX87::Nothing), 0xfd => (Opcode::FSCALE, OperandCodeX87::Nothing), 0xfe => (Opcode::FSIN, OperandCodeX87::Nothing), 0xff => (Opcode::FCOS, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTCW, OperandCodeX87::Ew) } } _ => { unreachable!("impossible r"); } } } OperandCase::x87_da => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVU, OperandCodeX87::St_Est), _ => { if modrm == 0xe9 { (Opcode::FUCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Md), // 0xd9d0 -> fnop 1 => (Opcode::FIMUL, OperandCodeX87::St_Md), 2 => (Opcode::FICOM, OperandCodeX87::St_Md), // FCMOVE 3 => (Opcode::FICOMP, OperandCodeX87::St_Md), // FCMOVBE 4 => (Opcode::FISUB, OperandCodeX87::St_Md), 5 => (Opcode::FISUBR, OperandCodeX87::St_Md), // FUCOMPP 6 => (Opcode::FIDIV, OperandCodeX87::St_Md), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Md), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_db => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVNB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVNE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVNBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVNU, OperandCodeX87::St_Est), 4 => { match modrm { 0xe0 => (Opcode::FENI8087_NOP, OperandCodeX87::Nothing), 0xe1 => (Opcode::FDISI8087_NOP, OperandCodeX87::Nothing), 0xe2 => (Opcode::FNCLEX, OperandCodeX87::Nothing), 0xe3 => (Opcode::FNINIT, OperandCodeX87::Nothing), 0xe4 => (Opcode::FSETPM287_NOP, OperandCodeX87::Nothing), _ => { return Err(DecodeError::InvalidOpcode); } } } 5 => (Opcode::FUCOMI, OperandCodeX87::St_Est), 6 => (Opcode::FCOMI, OperandCodeX87::St_Est), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Md), 1 => (Opcode::FISTTP, OperandCodeX87::Md_St), 2 => (Opcode::FIST, OperandCodeX87::Md_St), 3 => (Opcode::FISTP, OperandCodeX87::Md_St), 5 => (Opcode::FLD, OperandCodeX87::St_Mm), // 80bit 7 => (Opcode::FSTP, OperandCodeX87::Mm_St), // 80bit _ => { return Err(DecodeError::InvalidOpcode); } } } } OperandCase::x87_dc => { // mod=11 swaps operand order for some instructions if modrm >= 0xc0 { match r { 0 => (Opcode::FADD, OperandCodeX87::Eqst_St), 1 => (Opcode::FMUL, OperandCodeX87::Eqst_St), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUBR, OperandCodeX87::Eqst_St), 5 => (Opcode::FSUB, OperandCodeX87::Eqst_St), 6 => (Opcode::FDIVR, OperandCodeX87::Eqst_St), 7 => (Opcode::FDIV, OperandCodeX87::Eqst_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Eqst), 1 => (Opcode::FMUL, OperandCodeX87::St_Eqst), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUB, OperandCodeX87::St_Eqst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Eqst), 6 => (Opcode::FDIV, OperandCodeX87::St_Eqst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Eqst), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_dd => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREE, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FST, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => (Opcode::FUCOM, OperandCodeX87::St_Est), 5 => (Opcode::FUCOMP, OperandCodeX87::St_Est), 6 => (Opcode::Invalid, OperandCodeX87::Nothing), 7 => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Eqst), 1 => (Opcode::FISTTP, OperandCodeX87::Eqst_St), 2 => (Opcode::FST, OperandCodeX87::Eqst_St), 3 => (Opcode::FSTP, OperandCodeX87::Eqst_St), 4 => (Opcode::FRSTOR, OperandCodeX87::Ex87S), 5 => (Opcode::Invalid, OperandCodeX87::Nothing), 6 => (Opcode::FNSAVE, OperandCodeX87::Ex87S), 7 => (Opcode::FNSTSW, OperandCodeX87::Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_de => { if modrm >= 0xc0 { match r { 0 => (Opcode::FADDP, OperandCodeX87::Est_St), 1 => (Opcode::FMULP, OperandCodeX87::Est_St), // undocumented in intel manual, argument order inferred from // by xed and capstone. TODO: check amd manual. 2 => (Opcode::FCOMP, OperandCodeX87::St_Est), 3 => { if modrm == 0xd9 { (Opcode::FCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOperand); } }, 4 => (Opcode::FSUBRP, OperandCodeX87::Est_St), 5 => (Opcode::FSUBP, OperandCodeX87::Est_St), 6 => (Opcode::FDIVRP, OperandCodeX87::Est_St), 7 => (Opcode::FDIVP, OperandCodeX87::Est_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Ew), 1 => (Opcode::FIMUL, OperandCodeX87::St_Ew), 2 => (Opcode::FICOM, OperandCodeX87::St_Ew), 3 => (Opcode::FICOMP, OperandCodeX87::St_Ew), 4 => (Opcode::FISUB, OperandCodeX87::St_Ew), 5 => (Opcode::FISUBR, OperandCodeX87::St_Ew), 6 => (Opcode::FIDIV, OperandCodeX87::St_Ew), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_df => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREEP, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FSTP, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => { if modrm == 0xe0 { (Opcode::FNSTSW, OperandCodeX87::Ew) } else { return Err(DecodeError::InvalidOpcode); } }, 5 => (Opcode::FUCOMIP, OperandCodeX87::St_Est), 6 => (Opcode::FCOMIP, OperandCodeX87::St_Est), 7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Mw), 1 => (Opcode::FISTTP, OperandCodeX87::Mw_St), 2 => (Opcode::FIST, OperandCodeX87::Mw_St), 3 => (Opcode::FISTP, OperandCodeX87::Mw_St), 4 => (Opcode::FBLD, OperandCodeX87::St_Mm), 5 => (Opcode::FILD, OperandCodeX87::St_Mq), 6 => (Opcode::FBSTP, OperandCodeX87::Mm_St), 7 => (Opcode::FISTP, OperandCodeX87::Mq_St), _ => { unreachable!("impossible r"); } } } } other => { panic!("invalid x87 operand dispatch, operand code is {:?}", other); } }; instruction.opcode = opcode; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } match x87_operands { OperandCodeX87::Est => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 1; } OperandCodeX87::St_Est => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 2; } OperandCodeX87::St_Edst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::St_Eqst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 2; } OperandCodeX87::St_Ew => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.operand_count = 2; } OperandCodeX87::St_Mm => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operand_count = 2; } OperandCodeX87::St_Mq => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operand_count = 2; } OperandCodeX87::St_Md => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operand_count = 2; } OperandCodeX87::St_Mw => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operand_count = 2; } OperandCodeX87::Ew => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; instruction.operand_count = 1; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCodeX87::Est_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Edst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } } OperandCodeX87::Eqst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 8; } } OperandCodeX87::Ed_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::Mm_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mq_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Md_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mw_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Ex87S => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 63; } OperandCodeX87::Nothing => { instruction.operand_count = 0; }, } Ok(()) } #[inline] fn read_num::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { match width { 1 => { bytes.next().ok().ok_or(DecodeError::ExhaustedInput).map(|x| x as u32) } 2 => { let mut buf = [0u8; 2]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u16::from_le_bytes(buf) as u32) } 4 => { let mut buf = [0u8; 4]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u32::from_le_bytes(buf) as u32) } _ => { unsafe { unreachable_unchecked(); } } } } #[inline] fn read_imm_signed::Address, ::Word>>(bytes: &mut T, num_width: u8) -> Result { if num_width == 1 { Ok(read_num(bytes, 1)? as i8 as i32) } else if num_width == 2 { Ok(read_num(bytes, 2)? as i16 as i32) } else { Ok(read_num(bytes, 4)? as i32) } } #[inline] fn read_imm_unsigned::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { read_num(bytes, width) } #[inline] fn read_modrm::Address, ::Word>>(words: &mut T) -> Result { words.next().ok().ok_or(DecodeError::ExhaustedInput) } const REPNZ_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDDUP), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), // 0x20 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SD), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSD2SI), OperandCode::Gd_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SI), OperandCode::Gd_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFLW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf20f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), // cmpxchg permits an f2 prefix, which is the only reason this entry is not `Nothing` OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQ2Q), OperandCode::G_mm_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::LDDQU), OperandCode::G_M_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const REP_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::Ed_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSLDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSHDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::ModRM_0xf30f1e), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SS), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_Ed_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::G_E_xmm), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFHW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::MOVQ_f30f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::LZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ2DQ), OperandCode::G_xmm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const OPERAND_SIZE_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PD), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPD), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x660f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Ed_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_xmm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_U_xmm_Ub), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_xmm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQ), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_xmm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVDQU), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const NORMAL_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f12), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f16), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPS), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PS), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISS), OperandCode::PMOVX_G_E_xmm), // 0x30 OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::GETSEC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x40 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPS), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPS), OperandCode::G_E_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::G_mm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_mm_E), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFW), OperandCode::G_E_mm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::EMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMREAD), OperandCode::E_G_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMWRITE), OperandCode::G_E_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Ed_G_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::E_G_mm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // JMPE, ITANIUM OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTI), OperandCode::Md_Gd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_mm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::Rv_Gmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::G_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_mm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTQ), OperandCode::G_Mq_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_mm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVQ), OperandCode::G_mm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; yaxpeax-x86-1.2.2/src/protected_mode/uarch.rs000064400000000000000000000204331046102023000171660ustar 00000000000000pub mod amd { //! most information about instruction set extensions for microarchitectures here was sourced //! from //! [https://en.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit#Feature_overview](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/protected_mode/uarch/intel/index.html) //! and //! [https://en.wikipedia.org/wiki/Template:AMD_x86_CPU_features](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/protected_mode/uarch/intel/index.html). //! these mappings are best-effort but fairly unused, so a critical eye should be kept towards //! these decoders rejecting instructions they should not, or incorrectly accepting //! instructions. //! //! microarchitectures as defined here are with respect to flags reported by CPUID. notably, //! `Zen` does not report `FMA4` support by `CPUID`, but instructions in that extension //! reportedly function correctly (agner p217). //! //! [agner](https://www.agner.org/optimize/microarchitecture.pdf) //! as retrieved 2020 may 19, //! `sha256: 87ff152ae18c017dcbfb9f7ee6e88a9f971f6250fd15a70a3dd87c3546323bd5` use crate::protected_mode::InstDecoder; /// `k8` was the first AMD microarchitecture to implement x86_64, launched in 2003. while later /// `k8`-based processors supported SSE3, these predefined decoders pick the lower end of /// support - SSE2 and no later. pub fn k8() -> InstDecoder { InstDecoder::minimal() } /// `k10` was the successor to `k8`, launched in 2007. `k10` cores extended SSE support through /// to SSE4.2a, as well as consistent `cmov` support, among other features. pub fn k10() -> InstDecoder { k8() .with_cmov() .with_cmpxchg16b() .with_svm() .with_abm() .with_lahfsahf() .with_sse3() .with_ssse3() .with_sse4() .with_sse4_2() .with_sse4a() } /// `Bulldozer` was the successor to `K10`, launched in 2011. `Bulldozer` cores include AVX /// support among other extensions, and are notable for including `AESNI`. pub fn bulldozer() -> InstDecoder { k10() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_avx() .with_fma4() .with_xop() } /// `Piledriver` was the successor to `Bulldozer`, launched in 2012. pub fn piledriver() -> InstDecoder { bulldozer() .with_tbm() .with_fma3() .with_fma4() } /// `Steamroller` was the successor to `Piledriver`, launched in 2014. unlike `Piledriver` /// cores, these cores do not support `TBM` or `FMA3`. pub fn steamroller() -> InstDecoder { bulldozer() } /// `Excavator` was the successor to `Steamroller`, launched in 2015. pub fn excavator() -> InstDecoder { steamroller() .with_movbe() .with_bmi2() .with_rdrand() .with_avx() .with_xop() .with_bmi2() .with_sha() .with_rdrand() .with_avx2() } /// `Zen` was the successor to `Excavator`, launched in 2017. `Zen` cores extend SIMD /// instructions to AVX2 and discarded FMA4, TBM, and XOP extensions. they also gained ADX, /// SHA, RDSEED, and other extensions. pub fn zen() -> InstDecoder { k10() .with_avx() .with_avx2() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_movbe() .with_bmi2() .with_rdrand() .with_adx() .with_sha() .with_rdseed() .with_fma3() // TODO: XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO? } } pub mod intel { //! sourced by walking wikipedia pages. seriously! this stuff is kinda hard to figure out! use crate::protected_mode::InstDecoder; /// `Netburst` was the first Intel microarchitecture to implement x86_64, beginning with the /// `Prescott` family launched in 2004. while the wider `Netburst` family launched in 2000 /// with only SSE2, the first `x86_64`-supporting incarnation was `Prescott` which indeed /// included SSE3. pub fn netburst() -> InstDecoder { InstDecoder::minimal() .with_cmov() .with_sse3() } /// `Core` was the successor to `Netburst`, launched in 2006. it included up to SSE4, with /// processors using this architecture shipped under the names "Merom", "Conroe", and /// "Woodcrest", for mobile, desktop, and server processors respectively. not to be confused /// with the later `Nehalem` microarchitecture that introduced the `Core i*` product lines, /// `Core 2 *` processors used the `Core` architecture. pub fn core() -> InstDecoder { netburst() .with_ssse3() .with_sse4() } /// `Penryn` was the successor to `Core`, launched in early 2008. it added SSE4.1, along with /// virtualization extensions. pub fn penryn() -> InstDecoder { core() .with_sse4_1() } /// `Nehalem` was the successor to `Penryn`, launched in late 2008. not to be confused with the /// earlier `Core` microarchitecture, the `Core i*` products were based on `Nehalem` cores. /// `Nehalem` added SSE4.2 extensions, along with the `POPCNT` instruction. pub fn nehalem() -> InstDecoder { penryn() .with_sse4_2() .with_popcnt() } /// `Westmere` was the successor to `Nehalem`, launched in 2010. it added AES-NI and CLMUL /// extensions. pub fn westmere() -> InstDecoder { nehalem() .with_aesni() .with_pclmulqdq() } /// `Sandy Bridge` was the successor to `Westmere`, launched in 2011. it added AVX /// instructions. pub fn sandybridge() -> InstDecoder { westmere() .with_avx() } /// `Ivy Bridge` was the successor to `Sandy Bridge`, launched in 2012. it added F16C /// extensions for 16-bit floating point conversion, and the RDRAND instruction. pub fn ivybridge() -> InstDecoder { sandybridge() .with_f16c() .with_rdrand() } /// `Haswell` was the successor to `Ivy Bridge`, launched in 2013. it added several instruction /// set extensions: AVX2, BMI1, BMI2, ABM, and FMA3. pub fn haswell() -> InstDecoder { ivybridge() .with_bmi1() .with_bmi2() .with_abm() .with_fma3() .with_avx2() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores /// were shipped as `E7-48xx/E7-88xx v3` models of processors. pub fn haswell_ex() -> InstDecoder { haswell() .with_tsx() } /// `Broadwell` was the successor to `Haswell`, launched in late 2014. it added ADX, RDSEED, /// and PREFETCHW, as well as broadly rolling out TSX. TSX is enabled on this decoder because /// some chips of this microarchitecture rolled out with TSX, and lack of TSX seems to be /// reported as an errata (for example, the `Broadwell-Y` line of parts). pub fn broadwell() -> InstDecoder { haswell_ex() .with_adx() .with_rdseed() .with_prefetchw() } /// `Skylake` was the successor to `Broadwell`, launched in mid 2015. it added MPX and SGX /// extensions, as well as a mixed rollout of AVX512 in different subsets for different product /// lines. /// /// AVX512 is not enabled on this decoder by default because there doesn't seem to be a lowest /// common denominator: if you want a `Skylake` decoder with AVX512, something like the /// following: /// ``` /// yaxpeax_x86::protected_mode::uarch::intel::skylake() /// .with_avx512_f() /// .with_avx512_dq(); /// ``` /// is likely your best option. pub fn skylake() -> InstDecoder { broadwell() .with_mpx() .with_sgx() } /// `Kaby Lake` was the successor to `Sky Lake`, launched in 2016. it adds no extensions to /// x86_64 implementaiton beyond `skylake`. pub fn kabylake() -> InstDecoder { skylake() } // ice lake is shipping so that should probably be included... } yaxpeax-x86-1.2.2/src/protected_mode/vex.rs000064400000000000000000003500231046102023000166670ustar 00000000000000use yaxpeax_arch::Reader; use yaxpeax_arch::annotation::DescriptionSink; use crate::protected_mode::Arch; use crate::protected_mode::OperandSpec; use crate::protected_mode::DecodeError; use crate::protected_mode::FieldDescription; use crate::protected_mode::RegSpec; use crate::protected_mode::RegisterBank; use crate::protected_mode::InnerDescription; use crate::protected_mode::Instruction; use crate::protected_mode::Opcode; use crate::protected_mode::read_modrm; use crate::protected_mode::read_E; use crate::protected_mode::read_E_xmm; use crate::protected_mode::read_E_ymm; use crate::protected_mode::read_imm_unsigned; #[derive(Debug)] enum VEXOpcodeMap { Map0F, Map0F38, Map0F3A, } #[derive(Debug)] enum VEXOpcodePrefix { None, Prefix66, PrefixF3, PrefixF2, } #[allow(non_camel_case_types)] #[derive(Debug)] enum VEXOperandCode { Nothing, VPS_71, VPS_72, VPS_73, VMOVSS_10, VMOVSD_10, VMOVSD_11, VMOVSS_11, VMOVLPS_12, VMOVHPS_16, M_G_xmm, G_M_xmm, G_U_xmm, Gd_U_xmm, E_G_xmm_imm8, Ud_G_xmm_imm8, Ud_G_xyLmm, M_G_xyLmm, M_G_ymm, G_E_ymm, G_M_ymm, Gd_U_ymm, E_xmm_G_ymm_imm8, Ev_G_xmm_imm8, G_ExyL_V_xyLmm, G_E_xmm, G_E_xmm_imm8, G_E_ymm_imm8, G_xmm_E_xmm, G_xmm_E_ymm, G_ymm_E_xmm, G_ymm_M_xmm, G_ymm_E_ymm, G_V_ymm_E_xmm, M_V_G_xmm, M_V_G_ymm, G_V_xmm_Ed, G_V_E_xyLmm, G_E_xyLmm, E_G_xyLmm, G_E_xyLmm_imm8, G_V_E_xyLmm_imm8, G_V_E_xmm, G_V_E_xmm_imm8, G_V_E_xmm_xmm4, G_V_Ed_xmm, G_V_Eq_xmm, G_V_E_ymm, G_V_E_ymm_imm8, G_V_E_ymm_ymm4, G_V_xmm_Ev_imm8, G_V_M_xmm, G_V_M_ymm, G_ymm_V_ymm_E_xmm_imm8, Ed_G_xmm, G_xmm_Ed, G_E_V, G_V_E, G_E_Ib, VCVT_Gd_Ed_xmm, VCVT_Gd_Eq_xmm, BMI1_F3, MXCSR, } #[inline(always)] pub(crate) fn three_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, vex_byte_one: u8, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8 - 8; let vex_byte_two = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let p = vex_byte_two & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; sink.record( vex_start + 8, vex_start + 9, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); let m = vex_byte_one & 0b11111; sink.record( vex_start + 0, vex_start + 4, InnerDescription::Misc(match m { 0b00001 => "vex.mmmmm indicates opcode escape of 0f", 0b00010 => "vex.mmmmm indicates opcode escape of 0f38", 0b00011 => "vex.mmmmm indicates opcode escape of 0f3a", _ => "vex.mmmmm indicates illegal opcode escape and is invalid", }) .with_id(vex_start) ); let m = match m { 0b00001 => VEXOpcodeMap::Map0F, 0b00010 => VEXOpcodeMap::Map0F38, 0b00011 => VEXOpcodeMap::Map0F3A, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte_two >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 11, vex_start + 14, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte_one & 0b10000000 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 6, vex_start + 6, InnerDescription::Misc(if vex_byte_one & 0b01000000 == 0 { "vex.x extends extends index reg (if used) by 0b1000" } else { "vex.x does not alter index reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 5, vex_start + 5, InnerDescription::Misc(if vex_byte_one & 0b00100000 == 0 { "vex.b extends extends base reg (if used) by 0b1000" } else { "vex.b does not alter base reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 10, vex_start + 10, InnerDescription::Misc(if vex_byte_two & 0b100 == 0 { "vex.l selects 128-bit vector sizes" } else { "vex.l selects 256-bit vector sizes" }) .with_id(vex_start + 1) ); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Misc(if vex_byte_two & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c4(vex_byte_one, vex_byte_two); sink.record( vex_start + 23, vex_start + 23, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 23) ); read_vex_instruction(m, words, instruction, p, sink)?; instruction.regs[3].num &= 0b0111; // ignore bit 4 in 32-bit mode Ok(()) } #[inline(always)] pub(crate) fn two_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, vex_byte: u8, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8 - 8; let p = vex_byte & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 0, vex_start + 1, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); sink.record( vex_start + 3, vex_start + 6, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 2, vex_start + 2, InnerDescription::Misc(if vex_byte & 0b100 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c5(vex_byte); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 15) ); read_vex_instruction(VEXOpcodeMap::Map0F, words, instruction, p, sink)?; instruction.regs[3].num &= 0b0111; // ignore bit 4 in 32-bit mode Ok(()) } #[inline(always)] fn read_vex_operands< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: VEXOperandCode, sink: &mut S) -> Result<(), DecodeError> { // println!("operand code: {:?}", operand_code); match operand_code { VEXOperandCode::VPS_71 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let rrr = (modrm >> 3) & 0b111; if rrr == 0b001 && L { return Err(DecodeError::InvalidOpcode); } instruction.opcode = match rrr { 0b001 => Opcode::VPSLLW, 0b010 => Opcode::VPSRLW, 0b100 => Opcode::VPSRAW, 0b110 => Opcode::VPSLLW, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_72 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLD; } 0b100 => { instruction.opcode = Opcode::VPSRAD; } 0b110 => { instruction.opcode = Opcode::VPSLLD; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_73 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLQ; } 0b011 => { instruction.opcode = Opcode::VPSRLDQ; } 0b110 => { instruction.opcode = Opcode::VPSLLQ; } 0b111 => { instruction.opcode = Opcode::VPSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVSS_10 | VEXOperandCode::VMOVSD_10 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegMMM; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[1] = other; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVSS_11 | VEXOperandCode::VMOVSD_11 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[2] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegVex; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[0] = other; instruction.operands[1] = instruction.operands[2]; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVLPS_12 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVHLPS } else { instruction.mem_size = 8; Opcode::VMOVLPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVHPS_16 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVLHPS } else { instruction.mem_size = 8; Opcode::VMOVHPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::Nothing => { if instruction.opcode == Opcode::VZEROUPPER || instruction.opcode == Opcode::VZEROALL { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } } instruction.operand_count = 0; Ok(()) }, VEXOperandCode::Ev_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPEXTRB => { instruction.mem_size = 1; } Opcode::VPEXTRW => { instruction.mem_size = 2; } Opcode::VEXTRACTPS | Opcode::VPEXTRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(words, 1)?; Ok(()) }, VEXOperandCode::G_xmm_Ed => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ed_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Ed_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Eq_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_xmm_G_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::Gd_U_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Gd_U_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_xmm | op @ VEXOperandCode::G_U_xmm | op @ VEXOperandCode::G_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_U_xmm, 0xc0) => { /* this is the only accepted operand */ } (VEXOperandCode::G_U_xmm, _) | (VEXOperandCode::G_M_xmm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_xmm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VMOVDDUP, Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_ymm_M_xmm | op @ VEXOperandCode::G_ymm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { if let VEXOperandCode::G_ymm_M_xmm = op { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VBROADCASTSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_ymm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::M_G_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::M_G_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::M_G_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_ymm | op @ VEXOperandCode::G_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_M_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_V_E_ymm | op @ VEXOperandCode::G_V_M_ymm => { let modrm = read_modrm(words)?; if let VEXOperandCode::G_V_M_ymm = op { if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_ymm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_M_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm_imm8 => { // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_E_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } if instruction.opcode == Opcode::VMOVDDUP && !L { instruction.mem_size = 8; } else if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVD].contains(&instruction.opcode) { instruction.mem_size = 8; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm => { let modrm = read_modrm(words)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Ed_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Eq_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ed => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_ExyL_V_xyLmm => { #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L && instruction.opcode != Opcode::VGATHERQPS && instruction.opcode != Opcode::VPGATHERQD { RegisterBank::Y } else { RegisterBank::X }; let index_bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if instruction.opcode == Opcode::VPGATHERDQ { instruction.regs[2].bank = RegisterBank::X; } else { instruction.regs[2].bank = index_bank; } instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VPGATHERDD || instruction.opcode == Opcode::VPGATHERQD || instruction.opcode == Opcode::VGATHERDPS || instruction.opcode == Opcode::VGATHERQPS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_V => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_Ib => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::BMI1_F3 => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 1 => { Opcode::BLSR } 2 => { Opcode::BLSMSK } 3 => { Opcode::BLSI } _ => { return Err(DecodeError::InvalidOpcode); } }; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.regs[3].bank = bank; Ok(()) } VEXOperandCode::MXCSR => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 2 => { Opcode::VLDMXCSR } 3 => { Opcode::VSTMXCSR } _ => { return Err(DecodeError::InvalidOpcode); } }; let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operands[0] = mem_oper; instruction.operand_count = 1; Ok(()) } VEXOperandCode::G_E_xyLmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); if L { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_ymm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_E_xmm_xmm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_ymm_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ev_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; // TODO: but the memory access is word-sized let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPINSRB => { instruction.mem_size = 1; } Opcode::VPINSRW => { instruction.mem_size = 2; } Opcode::VINSERTPS | Opcode::VPINSRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } instruction.operand_count = 4; Ok(()) } } } #[inline(never)] fn read_vex_instruction< T: Reader<::Address, ::Word>, S: DescriptionSink, >(opcode_map: VEXOpcodeMap, words: &mut T, instruction: &mut Instruction, p: VEXOpcodePrefix, sink: &mut S) -> Result<(), DecodeError> { let opcode_start = words.offset() as u32 * 8; let opc = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); // println!("reading vex instruction from opcode prefix {:?}, L: {}, opc: {:#x}, map:{:?}", p, L, opc, opcode_map); // println!("w? {}", instruction.prefixes.vex_unchecked().w()); // several combinations simply have no instructions. check for those first. let (opcode, operand_code) = match opcode_map { VEXOpcodeMap::Map0F => { match p { VEXOpcodePrefix::None => { match opc { 0x10 => (Opcode::VMOVUPS, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPS, VEXOperandCode::E_G_xyLmm), 0x12 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVLPS_12 }), 0x13 => (Opcode::VMOVLPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPS, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPS, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVHPS_16 }), 0x17 => (Opcode::VMOVHPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPS, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPS, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPS, if L { VEXOperandCode::M_G_ymm } else { VEXOperandCode::M_G_xmm }), 0x2e => (Opcode::VUCOMISS, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISS, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPS, VEXOperandCode::Ud_G_xyLmm), 0x51 => (Opcode::VSQRTPS, VEXOperandCode::G_E_xyLmm), 0x52 => (Opcode::VRSQRTPS, VEXOperandCode::G_E_xyLmm), 0x53 => (Opcode::VRCPPS, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPS, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPS, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPS, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPS, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPS, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPS, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPS2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x5B => (Opcode::VCVTDQ2PS, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPS, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPS, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPS, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPS, VEXOperandCode::G_V_E_xyLmm), 0x77 => if L { (Opcode::VZEROALL, VEXOperandCode::Nothing) } else { (Opcode::VZEROUPPER, VEXOperandCode::Nothing) }, 0xAE => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::MXCSR }), 0xC2 => (Opcode::VCMPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC6 => (Opcode::VSHUFPS, VEXOperandCode::G_V_E_xyLmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } }, VEXOpcodePrefix::Prefix66 => { match opc { // 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), // 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x12 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x13 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPD, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPD, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x17 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPD, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPD, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPD, VEXOperandCode::M_G_xyLmm), 0x2e => (Opcode::VUCOMISD, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISD, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPD, if L { VEXOperandCode::Gd_U_ymm } else { VEXOperandCode::Gd_U_xmm }), 0x51 => (Opcode::VSQRTPD, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPD, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPD, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPD, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPD, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPD, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPD, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPD2PS, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5B => (Opcode::VCVTPS2DQ, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPD, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPD, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPD, VEXOperandCode::G_V_E_xyLmm), 0x60 => (Opcode::VPUNPCKLBW, VEXOperandCode::G_V_E_xyLmm), 0x61 => (Opcode::VPUNPCKLWD, VEXOperandCode::G_V_E_xyLmm), 0x62 => (Opcode::VPUNPCKLDQ, VEXOperandCode::G_V_E_xyLmm), 0x63 => (Opcode::VPACKSSWB, VEXOperandCode::G_V_E_xyLmm), 0x64 => (Opcode::VPCMPGTB, VEXOperandCode::G_V_E_xyLmm), 0x65 => (Opcode::VPCMPGTW, VEXOperandCode::G_V_E_xyLmm), 0x66 => (Opcode::VPCMPGTD, VEXOperandCode::G_V_E_xyLmm), 0x67 => (Opcode::VPACKUSWB, VEXOperandCode::G_V_E_xyLmm), 0x68 => (Opcode::VPUNPCKHBW, VEXOperandCode::G_V_E_xyLmm), 0x69 => (Opcode::VPUNPCKHWD, VEXOperandCode::G_V_E_xyLmm), 0x6A => (Opcode::VPUNPCKHDQ, VEXOperandCode::G_V_E_xyLmm), 0x6B => (Opcode::VPACKSSDW, VEXOperandCode::G_V_E_xyLmm), 0x6C => (Opcode::VPUNPCKLQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6D => (Opcode::VPUNPCKHQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6E => { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_xmm_Ed }) }, 0x6F => (Opcode::VMOVDQA, VEXOperandCode::G_E_xyLmm), 0x70 => (Opcode::VPSHUFD, VEXOperandCode::G_E_xyLmm_imm8), 0x71 => (Opcode::Invalid, VEXOperandCode::VPS_71), 0x72 => (Opcode::Invalid, VEXOperandCode::VPS_72), 0x73 => (Opcode::Invalid, VEXOperandCode::VPS_73), 0x74 => (Opcode::VPCMPEQB, VEXOperandCode::G_V_E_xyLmm), 0x75 => (Opcode::VPCMPEQW, VEXOperandCode::G_V_E_xyLmm), 0x76 => (Opcode::VPCMPEQD, VEXOperandCode::G_V_E_xyLmm), 0x7C => (Opcode::VHADDPD, VEXOperandCode::G_V_E_xyLmm), 0x7D => (Opcode::VHSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x7E => { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ed_G_xmm }) } 0x7F => (Opcode::VMOVDQA, VEXOperandCode::E_G_xyLmm), 0xC2 => (Opcode::VCMPPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC4 => (Opcode::VPINSRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0xC5 => (Opcode::VPEXTRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ud_G_xmm_imm8 }), 0xC6 => (Opcode::VSHUFPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xD0 => (Opcode::VADDSUBPD, VEXOperandCode::G_V_E_xyLmm), 0xD1 => (Opcode::VPSRLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD2 => (Opcode::VPSRLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD3 => (Opcode::VPSRLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD4 => (Opcode::VPADDQ, VEXOperandCode::G_V_E_xyLmm), 0xD5 => (Opcode::VPMULLW, VEXOperandCode::G_V_E_xyLmm), 0xD6 => (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xD7 => (Opcode::VPMOVMSKB, VEXOperandCode::Ud_G_xyLmm), 0xD8 => (Opcode::VPSUBUSB, VEXOperandCode::G_V_E_xyLmm), 0xD9 => (Opcode::VPSUBUSW, VEXOperandCode::G_V_E_xyLmm), 0xDA => (Opcode::VPMINUB, VEXOperandCode::G_V_E_xyLmm), 0xDB => (Opcode::VPAND, VEXOperandCode::G_V_E_xyLmm), 0xDC => (Opcode::VPADDUSB, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VPADDUSW, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VPMAXUB, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VPANDN, VEXOperandCode::G_V_E_xyLmm), 0xE0 => (Opcode::VPAVGB, VEXOperandCode::G_V_E_xyLmm), 0xE1 => (Opcode::VPSRAW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE2 => (Opcode::VPSRAD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE3 => (Opcode::VPAVGW, VEXOperandCode::G_V_E_xyLmm), 0xE4 => (Opcode::VPMULHUW, VEXOperandCode::G_V_E_xyLmm), 0xE5 => (Opcode::VPMULHW, VEXOperandCode::G_V_E_xyLmm), 0xE6 => (Opcode::VCVTTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_E_xmm }), 0xE7 => (Opcode::VMOVNTDQ, VEXOperandCode::M_G_xyLmm), 0xE8 => (Opcode::VPSUBSB, VEXOperandCode::G_V_E_xyLmm), 0xE9 => (Opcode::VPSUBSW, VEXOperandCode::G_V_E_xyLmm), 0xEA => (Opcode::VPMINSW, VEXOperandCode::G_V_E_xyLmm), 0xEB => (Opcode::VPOR, VEXOperandCode::G_V_E_xyLmm), 0xEC => (Opcode::VPADDSB, VEXOperandCode::G_V_E_xyLmm), 0xED => (Opcode::VPADDSW, VEXOperandCode::G_V_E_xyLmm), 0xEE => (Opcode::VPMAXSW, VEXOperandCode::G_V_E_xyLmm), 0xEF => (Opcode::VPXOR, VEXOperandCode::G_V_E_xyLmm), 0xF1 => (Opcode::VPSLLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF2 => (Opcode::VPSLLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF3 => (Opcode::VPSLLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF4 => (Opcode::VPMULUDQ, VEXOperandCode::G_V_E_xyLmm), 0xF5 => (Opcode::VPMADDWD, VEXOperandCode::G_V_E_xyLmm), 0xF6 => (Opcode::VPSADBW, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::VMASKMOVDQU, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_U_xmm }), 0xF8 => (Opcode::VPSUBB, VEXOperandCode::G_V_E_xyLmm), 0xF9 => (Opcode::VPSUBW, VEXOperandCode::G_V_E_xyLmm), 0xFA => (Opcode::VPSUBD, VEXOperandCode::G_V_E_xyLmm), 0xFB => (Opcode::VPSUBQ, VEXOperandCode::G_V_E_xyLmm), 0xFC => (Opcode::VPADDB, VEXOperandCode::G_V_E_xyLmm), 0xFD => (Opcode::VPADDW, VEXOperandCode::G_V_E_xyLmm), 0xFE => (Opcode::VPADDD, VEXOperandCode::G_V_E_xyLmm), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF2 => { match opc { 0x10 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_10), 0x11 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_11), 0x12 => (Opcode::VMOVDDUP, VEXOperandCode::G_E_xyLmm), 0x2a => (Opcode::VCVTSI2SD, { VEXOperandCode::G_V_xmm_Ed // 32-bit last operand }), 0x2c => (Opcode::VCVTTSD2SI, { VEXOperandCode::VCVT_Gd_Eq_xmm }), 0x2d => (Opcode::VCVTSD2SI, { VEXOperandCode::VCVT_Gd_Eq_xmm }), 0x51 => (Opcode::VSQRTSD, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSD, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSD, VEXOperandCode::G_V_E_xmm), 0x5a => (Opcode::VCVTSD2SS, VEXOperandCode::G_V_Eq_xmm), 0x5c => (Opcode::VSUBSD, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSD, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSD, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSD, VEXOperandCode::G_V_E_xmm), 0x70 => (Opcode::VPSHUFLW, VEXOperandCode::G_E_xyLmm_imm8), 0x7c => (Opcode::VHADDPS, VEXOperandCode::G_V_E_xyLmm), 0x7d => (Opcode::VHSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xc2 => (Opcode::VCMPSD, VEXOperandCode::G_V_E_xmm_imm8), 0xd0 => (Opcode::VADDSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xe6 => (Opcode::VCVTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0xf0 => (Opcode::VLDDQU, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF3 => { match opc { 0x10 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_10), 0x11 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_11), 0x12 => (Opcode::VMOVSLDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x16 => (Opcode::VMOVSHDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x2a => (Opcode::VCVTSI2SS, { VEXOperandCode::G_V_xmm_Ed }), 0x2c => (Opcode::VCVTTSS2SI, { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x2d => (Opcode::VCVTSS2SI, { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x51 => (Opcode::VSQRTSS, VEXOperandCode::G_V_E_xmm), 0x52 => (Opcode::VRSQRTSS, VEXOperandCode::G_V_E_xmm), 0x53 => (Opcode::VRCPSS, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSS, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSS, VEXOperandCode::G_V_E_xmm), 0x5a => (Opcode::VCVTSS2SD, VEXOperandCode::G_V_Ed_xmm), 0x5b => (Opcode::VCVTTPS2DQ, if L { VEXOperandCode::G_ymm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5c => (Opcode::VSUBSS, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSS, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSS, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSS, VEXOperandCode::G_V_E_xmm), 0x6f => (Opcode::VMOVDQU, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x70 => (Opcode::VPSHUFHW, VEXOperandCode::G_E_xyLmm_imm8), 0x7e => (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x7f => (Opcode::VMOVDQU, VEXOperandCode::E_G_xyLmm), 0xc2 => (Opcode::VCMPSS, VEXOperandCode::G_V_E_xmm_imm8), 0xe6 => (Opcode::VCVTDQ2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_xmm_E_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } } } VEXOpcodeMap::Map0F38 => { // TODO: verify rejecting invalid W bit if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPSHUFB, VEXOperandCode::G_V_E_xyLmm), 0x01 => (Opcode::VPHADDW, VEXOperandCode::G_V_E_xyLmm), 0x02 => (Opcode::VPHADDD, VEXOperandCode::G_V_E_xyLmm), 0x03 => (Opcode::VPHADDSW, VEXOperandCode::G_V_E_xyLmm), 0x04 => (Opcode::VPMADDUBSW, VEXOperandCode::G_V_E_xyLmm), 0x05 => (Opcode::VPHSUBW, VEXOperandCode::G_V_E_xyLmm), 0x06 => (Opcode::VPHSUBD, VEXOperandCode::G_V_E_xyLmm), 0x07 => (Opcode::VPHSUBSW, VEXOperandCode::G_V_E_xyLmm), 0x08 => (Opcode::VPSIGNB, VEXOperandCode::G_V_E_xyLmm), 0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm), 0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm), 0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm), 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm), 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm), 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm), 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm), 0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm), 0x16 => (Opcode::VPERMPS, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x17 => (Opcode::VPTEST, VEXOperandCode::G_E_xyLmm), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSS, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) } 0x1A => (Opcode::VBROADCASTF128, if L { VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x1C => (Opcode::VPABSB, VEXOperandCode::G_E_xyLmm), 0x1D => (Opcode::VPABSW, VEXOperandCode::G_E_xyLmm), 0x1E => (Opcode::VPABSD, VEXOperandCode::G_E_xyLmm), 0x20 => (Opcode::VPMOVSXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x21 => (Opcode::VPMOVSXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x22 => (Opcode::VPMOVSXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x23 => (Opcode::VPMOVSXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x24 => (Opcode::VPMOVSXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x25 => (Opcode::VPMOVSXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x28 => (Opcode::VPMULDQ, VEXOperandCode::G_V_E_xyLmm), 0x29 => (Opcode::VPCMPEQQ, VEXOperandCode::G_V_E_xyLmm), 0x2A => (Opcode::VMOVNTDQA, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), 0x2B => (Opcode::VPACKUSDW, VEXOperandCode::G_V_E_xyLmm), 0x2C => (Opcode::VMASKMOVPS, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2D => (Opcode::VMASKMOVPD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2E => (Opcode::VMASKMOVPS, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x2F => (Opcode::VMASKMOVPD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x30 => (Opcode::VPMOVZXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x31 => (Opcode::VPMOVZXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x32 => (Opcode::VPMOVZXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x33 => (Opcode::VPMOVZXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x34 => (Opcode::VPMOVZXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x35 => (Opcode::VPMOVZXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x36 => (Opcode::VPERMD, if L { VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x37 => (Opcode::VPCMPGTQ, VEXOperandCode::G_V_E_xyLmm), 0x38 => (Opcode::VPMINSB, VEXOperandCode::G_V_E_xyLmm), 0x39 => (Opcode::VPMINSD, VEXOperandCode::G_V_E_xyLmm), 0x3A => (Opcode::VPMINUW, VEXOperandCode::G_V_E_xyLmm), 0x3B => (Opcode::VPMINUD, VEXOperandCode::G_V_E_xyLmm), 0x3C => (Opcode::VPMAXSB, VEXOperandCode::G_V_E_xyLmm), 0x3D => (Opcode::VPMAXSD, VEXOperandCode::G_V_E_xyLmm), 0x3E => (Opcode::VPMAXUW, VEXOperandCode::G_V_E_xyLmm), 0x3F => (Opcode::VPMAXUD, VEXOperandCode::G_V_E_xyLmm), 0x40 => (Opcode::VPMULLD, VEXOperandCode::G_V_E_xyLmm), 0x41 => (Opcode::VPHMINPOSUW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x45 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSRLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSRLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x46 => (Opcode::VPSRAVD, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_xmm }), 0x47 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSLLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSLLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x58 => (Opcode::VPBROADCASTD, VEXOperandCode::G_E_xyLmm), 0x59 => (Opcode::VPBROADCASTQ, VEXOperandCode::G_E_xyLmm), 0x5A => (Opcode::VBROADCASTI128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x78 => (Opcode::VPBROADCASTB, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x79 => (Opcode::VPBROADCASTW, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x8C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } }, 0x8E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } }, 0x90 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERDQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERDD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x91 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERQQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERQD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x92 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERDPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERDPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x93 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERQPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERQPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x96 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x97 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x98 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x99 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9A => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9B => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9D => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9F => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xA6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xB6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xDB => (Opcode::VAESIMC, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xDC => (Opcode::VAESENC, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VAESENCLAST, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VAESDEC, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VAESDECLAST, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::SHLX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF5 => (Opcode::PDEP, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF6 => (Opcode::MULX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SHRX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF3 = p { match opc { 0xF5 => (Opcode::PEXT, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SARX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match opc { 0xF2 => (Opcode::ANDN, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF3 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::BMI1_F3 }), 0xF5 => (Opcode::BZHI, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), 0xF7 => (Opcode::BEXTR, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } } VEXOpcodeMap::Map0F3A => { if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPERMQ, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x01 => (Opcode::VPERMPD, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x02 => (Opcode::VPBLENDD, if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xyLmm_imm8 }), 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8), 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8), 0x06 => (Opcode::VPERM2F128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x08 => (Opcode::VROUNDPS, VEXOperandCode::G_E_xyLmm_imm8), 0x09 => (Opcode::VROUNDPD, VEXOperandCode::G_E_xyLmm_imm8), 0x0A => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), 0x0B => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x0C => (Opcode::VBLENDPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0D => (Opcode::VBLENDPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0E => (Opcode::VPBLENDW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0F => (Opcode::VPALIGNR, VEXOperandCode::G_V_E_xyLmm_imm8), 0x14 => (Opcode::VPEXTRB, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x15 => (Opcode::VPEXTRW, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x16 => { (Opcode::VPEXTRD, if L { return Err(DecodeError::InvalidOpcode); } else { // varies on W VEXOperandCode::Ev_G_xmm_imm8 }) }, 0x17 => (Opcode::VEXTRACTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VINSERTF128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VEXTRACTF128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x1D => (Opcode::VCVTPS2PH, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { VEXOperandCode::E_G_xmm_imm8 }), 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0x21 => (Opcode::VINSERTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x22 => { (Opcode::VPINSRD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }) }, 0x38 => (Opcode::VINSERTI128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x39 => (Opcode::VEXTRACTI128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x40 => (Opcode::VDPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x41 => (Opcode::VDPPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x42 => (Opcode::VMPSADBW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x44 => (Opcode::VPCLMULQDQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x46 => (Opcode::VPERM2I128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x4A => (Opcode::VBLENDVPS, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4B => (Opcode::VBLENDVPD, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4C => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VPBLENDVB, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }) }, 0x60 => (Opcode::VPCMPESTRM, VEXOperandCode::G_E_xmm_imm8), 0x61 => (Opcode::VPCMPESTRI, VEXOperandCode::G_E_xmm_imm8), 0x62 => (Opcode::VPCMPISTRM, VEXOperandCode::G_E_xmm_imm8), 0x63 => (Opcode::VPCMPISTRI, VEXOperandCode::G_E_xmm_imm8), 0xDF => (Opcode::VAESKEYGENASSIST, VEXOperandCode::G_E_xmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF0 => (Opcode::RORX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_Ib }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { // the only VEX* 0f3a instructions have an implied 66 prefix. return Err(DecodeError::InvalidOpcode); } } }; instruction.opcode = opcode; sink.record( opcode_start, opcode_start + 7, InnerDescription::Opcode(instruction.opcode) .with_id(opcode_start) ); sink.record( opcode_start + 7, opcode_start + 7, InnerDescription::Boundary("vex opcode ends/operands begin") .with_id(opcode_start + 7) ); read_vex_operands(words, instruction, operand_code, sink) } yaxpeax-x86-1.2.2/src/real_mode/display.rs000064400000000000000000003211651046102023000164710ustar 00000000000000use core::fmt; use yaxpeax_arch::{Colorize, ShowContextual, NoColors, YaxColors}; use yaxpeax_arch::display::*; use crate::safer_unchecked::GetSaferUnchecked as _; use crate::MEM_SIZE_STRINGS; use crate::real_mode::{RegSpec, Opcode, Operand, MergeMode, InstDecoder, Instruction, Segment, PrefixVex, OperandSpec}; impl fmt::Display for InstDecoder { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self == &InstDecoder::default() { return write!(f, ""); } else if self == &InstDecoder::minimal() { return write!(f, ""); } if self.sse3() { write!(f, "sse3 ")? } if self.ssse3() { write!(f, "ssse3 ")? } if self.monitor() { write!(f, "monitor ")? } if self.vmx() { write!(f, "vmx ")? } if self.fma3() { write!(f, "fma3 ")? } if self.cmpxchg16b() { write!(f, "cmpxchg16b ")? } if self.sse4_1() { write!(f, "sse4_1 ")? } if self.sse4_2() { write!(f, "sse4_2 ")? } if self.movbe() { write!(f, "movbe ")? } if self.popcnt() { write!(f, "popcnt ")? } if self.aesni() { write!(f, "aesni ")? } if self.xsave() { write!(f, "xsave ")? } if self.rdrand() { write!(f, "rdrand ")? } if self.sgx() { write!(f, "sgx ")? } if self.bmi1() { write!(f, "bmi1 ")? } if self.avx2() { write!(f, "avx2 ")? } if self.bmi2() { write!(f, "bmi2 ")? } if self.invpcid() { write!(f, "invpcid ")? } if self.mpx() { write!(f, "mpx ")? } if self.avx512_f() { write!(f, "avx512_f ")? } if self.avx512_dq() { write!(f, "avx512_dq ")? } if self.rdseed() { write!(f, "rdseed ")? } if self.adx() { write!(f, "adx ")? } if self.avx512_fma() { write!(f, "avx512_fma ")? } if self.pcommit() { write!(f, "pcommit ")? } if self.clflushopt() { write!(f, "clflushopt ")? } if self.clwb() { write!(f, "clwb ")? } if self.avx512_pf() { write!(f, "avx512_pf ")? } if self.avx512_er() { write!(f, "avx512_er ")? } if self.avx512_cd() { write!(f, "avx512_cd ")? } if self.sha() { write!(f, "sha ")? } if self.avx512_bw() { write!(f, "avx512_bw ")? } if self.avx512_vl() { write!(f, "avx512_vl ")? } if self.prefetchwt1() { write!(f, "prefetchwt1 ")? } if self.avx512_vbmi() { write!(f, "avx512_vbmi ")? } if self.avx512_vbmi2() { write!(f, "avx512_vbmi2 ")? } if self.gfni() { write!(f, "gfni ")? } if self.vaes() { write!(f, "vaes ")? } if self.pclmulqdq() { write!(f, "pclmulqdq ")? } if self.avx_vnni() { write!(f, "avx_vnni ")? } if self.avx512_bitalg() { write!(f, "avx512_bitalg ")? } if self.avx512_vpopcntdq() { write!(f, "avx512_vpopcntdq ")? } if self.avx512_4vnniw() { write!(f, "avx512_4vnniw ")? } if self.avx512_4fmaps() { write!(f, "avx512_4fmaps ")? } if self.cx8() { write!(f, "cx8 ")? } if self.syscall() { write!(f, "syscall ")? } if self.rdtscp() { write!(f, "rdtscp ")? } if self.abm() { write!(f, "abm ")? } if self.sse4a() { write!(f, "sse4a ")? } if self._3dnowprefetch() { write!(f, "_3dnowprefetch ")? } if self.xop() { write!(f, "xop ")? } if self.skinit() { write!(f, "skinit ")? } if self.tbm() { write!(f, "tbm ")? } if self.intel_quirks() { write!(f, "intel_quirks ")? } if self.amd_quirks() { write!(f, "amd_quirks ")? } if self.avx() { write!(f, "avx ")? } Ok(()) } } impl fmt::Display for PrefixVex { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { if self.present() { write!(f, "vex:{}{}{}{}", if self.w() { "w" } else { "-" }, if self.r() { "r" } else { "-" }, if self.x() { "x" } else { "-" }, if self.b() { "b" } else { "-" }, ) } else { write!(f, "vex:none") } } } impl fmt::Display for Segment { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { Segment::CS => write!(f, "cs"), Segment::DS => write!(f, "ds"), Segment::ES => write!(f, "es"), Segment::FS => write!(f, "fs"), Segment::GS => write!(f, "gs"), Segment::SS => write!(f, "ss"), } } } // register names are grouped by indices scaled by 16. // xmm, ymm, zmm all get two indices. const REG_NAMES: &[&'static str] = &[ "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", "dr0", "dr1", "dr2", "dr3", "dr4", "dr5", "dr6", "dr7", "es", "cs", "ss", "ds", "fs", "gs", "", "", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", "xmm16", "xmm17", "xmm18", "xmm19", "xmm20", "xmm21", "xmm22", "xmm23", "xmm24", "xmm25", "xmm26", "xmm27", "xmm28", "xmm29", "xmm30", "xmm31", "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", "ymm16", "ymm17", "ymm18", "ymm19", "ymm20", "ymm21", "ymm22", "ymm23", "ymm24", "ymm25", "ymm26", "ymm27", "ymm28", "ymm29", "ymm30", "ymm31", "zmm0", "zmm1", "zmm2", "zmm3", "zmm4", "zmm5", "zmm6", "zmm7", "zmm8", "zmm9", "zmm10", "zmm11", "zmm12", "zmm13", "zmm14", "zmm15", "zmm16", "zmm17", "zmm18", "zmm19", "zmm20", "zmm21", "zmm22", "zmm23", "zmm24", "zmm25", "zmm26", "zmm27", "zmm28", "zmm29", "zmm30", "zmm31", "st(0)", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7", "eip", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "eflags", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", "BUG", ]; pub(crate) fn regspec_label(spec: &RegSpec) -> &'static str { unsafe { REG_NAMES.get_kinda_unchecked((spec.num as u16 + ((spec.bank as u16) << 3)) as usize) } } impl fmt::Display for RegSpec { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(regspec_label(self)) } } impl fmt::Display for Operand { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } impl Colorize for Operand { fn colorize(&self, colors: &Y, f: &mut T) -> fmt::Result { match self { &Operand::ImmediateU8(imm) => { write!(f, "{}", colors.number(u8_hex(imm))) } &Operand::ImmediateI8(imm) => { write!(f, "{}", colors.number(signed_i8_hex(imm))) }, &Operand::ImmediateU16(imm) => { write!(f, "{}", colors.number(u16_hex(imm))) } &Operand::ImmediateI16(imm) => { write!(f, "{}", colors.number(signed_i16_hex(imm))) }, &Operand::ImmediateU32(imm) => { write!(f, "{}", colors.number(u32_hex(imm))) } &Operand::ImmediateI32(imm) => { write!(f, "{}", colors.number(signed_i32_hex(imm))) }, &Operand::AbsoluteFarAddress { segment, address } => { write!(f, "{}:{}", colors.number(u16_hex(segment as u16)), colors.number(u32_hex(address as u32)), ) }, &Operand::Register(ref spec) => { f.write_str(regspec_label(spec)) } &Operand::RegisterMaskMerge(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } Ok(()) } &Operand::RegisterMaskMergeSae(ref spec, ref mask, merge_mode, sae_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str(sae_mode.label())?; Ok(()) } &Operand::RegisterMaskMergeSaeNoround(ref spec, ref mask, merge_mode) => { f.write_str(regspec_label(spec))?; if mask.num != 0 { f.write_str("{")?; f.write_str(regspec_label(mask))?; f.write_str("}")?; } if let MergeMode::Zero = merge_mode { f.write_str("{z}")?; } f.write_str("{sae}")?; Ok(()) } &Operand::DisplacementU16(imm) => { write!(f, "[{}]", colors.address(u16_hex(imm))) } &Operand::DisplacementU32(imm) => { write!(f, "[{}]", colors.address(u32_hex(imm))) } &Operand::RegDisp(ref spec, disp) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDeref(ref spec) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]") }, &Operand::RegScale(ref spec, scale) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) ) }, &Operand::RegScaleDisp(ref spec, scale, disp) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBase(ref base, ref index) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]") } &Operand::RegIndexBaseDisp(ref base, ref index, disp) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegIndexBaseScale(ref base, ref index, scale) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) ) } &Operand::RegIndexBaseScaleDisp(ref base, ref index, scale, disp) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]") }, &Operand::RegDispMasked(ref spec, disp, ref mask_reg) => { write!(f, "[{} ", regspec_label(spec))?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegDerefMasked(ref spec, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(spec))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleMasked(ref spec, scale, ref mask_reg) => { write!(f, "[{} * {}]", regspec_label(spec), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegScaleDispMasked(ref spec, scale, disp, ref mask_reg) => { write!(f, "[{} * {} ", regspec_label(spec), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseMasked(ref base, ref index, ref mask_reg) => { f.write_str("[")?; f.write_str(regspec_label(base))?; f.write_str(" + ")?; f.write_str(regspec_label(index))?; f.write_str("]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseDispMasked(ref base, ref index, disp, ref mask_reg) => { write!(f, "[{} + {} ", regspec_label(base), regspec_label(index), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::RegIndexBaseScaleMasked(ref base, ref index, scale, ref mask_reg) => { write!(f, "[{} + {} * {}]", regspec_label(base), regspec_label(index), colors.number(scale) )?; write!(f, "{{{}}}", regspec_label(mask_reg)) } &Operand::RegIndexBaseScaleDispMasked(ref base, ref index, scale, disp, ref mask_reg) => { write!(f, "[{} + {} * {} ", regspec_label(base), regspec_label(index), colors.number(scale), )?; format_number_i32(colors, f, disp, NumberStyleHint::HexSignedWithSignSplit)?; write!(f, "]")?; write!(f, "{{{}}}", regspec_label(mask_reg)) }, &Operand::Nothing => { Ok(()) }, } } } impl fmt::Display for Opcode { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.name()) } } const MNEMONICS: &[&'static str] = &[ "add", "or", "adc", "sbb", "and", "sub", "xor", "cmp", "rol", "ror", "rcl", "rcr", "shl", "shr", "sal", "sar", "btc", "btr", "bts", "cmpxchg", "cmpxchg8b", "cmpxchg16b", "dec", "inc", "neg", "not", "xadd", "xchg", "invalid", "bt", "bsf", "bsr", "tzcnt", "movss", "addss", "subss", "mulss", "divss", "minss", "maxss", "sqrtss", "movsd", "sqrtsd", "addsd", "subsd", "mulsd", "divsd", "minsd", "maxsd", "movsldup", "movshdup", "movddup", "haddps", "hsubps", "addsubpd", "addsubps", "cvtsi2ss", "cvtsi2sd", "cvttsd2si", "cvttps2dq", "cvtpd2dq", "cvtpd2ps", "cvtps2dq", "cvtsd2si", "cvtsd2ss", "cvttss2si", "cvtss2si", "cvtss2sd", "cvtdq2pd", "lddqu", "movzx", "movsx", "movsxd", "shrd", // " inc", // " dec", "hlt", "call", "callf", "jmp", "jmpf", "push", "pop", "lea", "nop", "prefetchnta", "prefetch0", "prefetch1", "prefetch2", // " xchg", "popf", "int", "into", "iret", "iretd", "iretq", "retf", "enter", "leave", "mov", "ret", "pushf", "wait", "cbw", "cwde", "cdqe", "cwd", "cdq", "cqo", "lods", "stos", "lahf", "sahf", "cmps", "scas", "movs", "test", "ins", "in", "outs", "out", "imul", "jo", "jno", "jb", "jnb", "jz", "jnz", "ja", "jna", "js", "jns", "jp", "jnp", "jl", "jge", "jle", "jg", "cmova", "cmovb", "cmovg", "cmovge", "cmovl", "cmovle", "cmovna", "cmovnb", "cmovno", "cmovnp", "cmovns", "cmovnz", "cmovo", "cmovp", "cmovs", "cmovz", "div", "idiv", "mul", // " neg", // " not", // " cmpxchg", "seto", "setno", "setb", "setae", "setz", "setnz", "setbe", "seta", "sets", "setns", "setp", "setnp", "setl", "setge", "setle", "setg", "cpuid", "ud0", "ud1", "ud2", "wbinvd", "invd", "sysret", "clts", "syscall", "lsl", "lar", "les", "lds", "sgdt", "sidt", "lgdt", "lidt", "smsw", "lmsw", "swapgs", "rdtscp", "invlpg", "fxsave", "fxrstor", "ldmxcsr", "stmxcsr", "xsave", "xrstor", "xsaveopt", "lfence", "mfence", "sfence", "clflush", "clflushopt", "clwb", "wrmsr", "rdtsc", "rdmsr", "rdpmc", "sldt", "str", "lldt", "ltr", "verr", "verw", "cmc", "clc", "stc", "cli", "sti", "cld", "std", "jmpe", "popcnt", "movdqu", "movdqa", "movq", "cmpss", "cmpsd", "unpcklps", "unpcklpd", "unpckhps", "unpckhpd", "pshufhw", "pshuflw", "movups", "movq2dq", "movdq2q", "rsqrtss", "rcpss", "andn", "bextr", "blsi", "blsmsk", "blsr", "vmclear", "vmxon", "vmcall", "vmlaunch", "vmresume", "vmxoff", "pconfig", "monitor", "mwait", "monitorx", "mwaitx", "clac", "stac", "encls", "enclv", "xgetbv", "xsetbv", "vmfunc", "xabort", "xbegin", "xend", "xtest", "enclu", "rdpkru", "wrpkru", "rdpru", "clzero", "rdseed", "rdrand", "addps", "addpd", "andnps", "andnpd", "andps", "andpd", "bswap", "cmppd", "cmpps", "comisd", "comiss", "cvtdq2ps", "cvtpi2ps", "cvtpi2pd", "cvtps2pd", "cvtps2pi", "cvtpd2pi", "cvttps2pi", "cvttpd2pi", "cvttpd2dq", "divps", "divpd", "emms", "getsec", "lfs", "lgs", "lss", "maskmovq", "maskmovdqu", "maxps", "maxpd", "minps", "minpd", "movaps", "movapd", "movd", "movlps", "movlpd", "movhps", "movhpd", "movlhps", "movhlps", "movupd", "movmskps", "movmskpd", "movnti", "movntps", "movntpd", "extrq", "insertq", "movntss", "movntsd", "movntq", "movntdq", "mulps", "mulpd", "orps", "orpd", "packssdw", "packsswb", "packuswb", "paddb", "paddd", "paddq", "paddsb", "paddsw", "paddusb", "paddusw", "paddw", "pand", "pandn", "pavgb", "pavgw", "pcmpeqb", "pcmpeqd", "pcmpeqw", "pcmpgtb", "pcmpgtd", "pcmpgtw", "pinsrw", "pmaddwd", "pmaxsw", "pmaxub", "pminsw", "pminub", "pmovmskb", "pmulhuw", "pmulhw", "pmullw", "pmuludq", "por", "psadbw", "pshufw", "pshufd", "pslld", "pslldq", "psllq", "psllw", "psrad", "psraw", "psrld", "psrldq", "psrlq", "psrlw", "psubb", "psubd", "psubq", "psubsb", "psubsw", "psubusb", "psubusw", "psubw", "punpckhbw", "punpckhdq", "punpckhwd", "punpcklbw", "punpckldq", "punpcklwd", "punpcklqdq", "punpckhqdq", "pxor", "rcpps", "rsm", "rsqrtps", "shld", "shufpd", "shufps", "slhd", "sqrtps", "sqrtpd", "subps", "subpd", "sysenter", "sysexit", "ucomisd", "ucomiss", "vmread", "vmwrite", "xorps", "xorpd", "vmovddup", "vpshuflw", "vpshufhw", "vhaddps", "vhsubps", "vaddsubps", "vcvtpd2dq", "vlddqu", "vcomisd", "vcomiss", "vucomisd", "vucomiss", "vaddpd", "vaddps", "vaddsd", "vaddss", "vaddsubpd", "vaesdec", "vaesdeclast", "vaesenc", "vaesenclast", "vaesimc", "vaeskeygenassist", "vblendpd", "vblendps", "vblendvpd", "vblendvps", "vbroadcastf128", "vbroadcasti128", "vbroadcastsd", "vbroadcastss", "vcmpsd", "vcmpss", "vcmppd", "vcmpps", "vcvtdq2pd", "vcvtdq2ps", "vcvtpd2ps", "vcvtph2ps", "vcvtps2dq", "vcvtps2pd", "vcvtss2sd", "vcvtsi2ss", "vcvtsi2sd", "vcvtsd2si", "vcvtsd2ss", "vcvtps2ph", "vcvtss2si", "vcvttpd2dq", "vcvttps2dq", "vcvttss2si", "vcvttsd2si", "vdivpd", "vdivps", "vdivsd", "vdivss", "vdppd", "vdpps", "vextractf128", "vextracti128", "vextractps", "vfmadd132pd", "vfmadd132ps", "vfmadd132sd", "vfmadd132ss", "vfmadd213pd", "vfmadd213ps", "vfmadd213sd", "vfmadd213ss", "vfmadd231pd", "vfmadd231ps", "vfmadd231sd", "vfmadd231ss", "vfmaddsub132pd", "vfmaddsub132ps", "vfmaddsub213pd", "vfmaddsub213ps", "vfmaddsub231pd", "vfmaddsub231ps", "vfmsub132pd", "vfmsub132ps", "vfmsub132sd", "vfmsub132ss", "vfmsub213pd", "vfmsub213ps", "vfmsub213sd", "vfmsub213ss", "vfmsub231pd", "vfmsub231ps", "vfmsub231sd", "vfmsub231ss", "vfmsubadd132pd", "vfmsubadd132ps", "vfmsubadd213pd", "vfmsubadd213ps", "vfmsubadd231pd", "vfmsubadd231ps", "vfnmadd132pd", "vfnmadd132ps", "vfnmadd132sd", "vfnmadd132ss", "vfnmadd213pd", "vfnmadd213ps", "vfnmadd213sd", "vfnmadd213ss", "vfnmadd231pd", "vfnmadd231ps", "vfnmadd231sd", "vfnmadd231ss", "vfnmsub132pd", "vfnmsub132ps", "vfnmsub132sd", "vfnmsub132ss", "vfnmsub213pd", "vfnmsub213ps", "vfnmsub213sd", "vfnmsub213ss", "vfnmsub231pd", "vfnmsub231ps", "vfnmsub231sd", "vfnmsub231ss", "vgatherdpd", "vgatherdps", "vgatherqpd", "vgatherqps", "vhaddpd", "vhsubpd", "vinsertf128", "vinserti128", "vinsertps", "vmaskmovdqu", "vmaskmovpd", "vmaskmovps", "vmaxpd", "vmaxps", "vmaxsd", "vmaxss", "vminpd", "vminps", "vminsd", "vminss", "vmovapd", "vmovaps", "vmovd", "vmovdqa", "vmovdqu", "vmovhlps", "vmovhpd", "vmovhps", "vmovlhps", "vmovlpd", "vmovlps", "vmovmskpd", "vmovmskps", "vmovntdq", "vmovntdqa", "vmovntpd", "vmovntps", "vmovq", "vmovss", "vmovsd", "vmovshdup", "vmovsldup", "vmovupd", "vmovups", "vmpsadbw", "vmulpd", "vmulps", "vmulsd", "vmulss", "vpabsb", "vpabsd", "vpabsw", "vpackssdw", "vpackusdw", "vpacksswb", "vpackuswb", "vpaddb", "vpaddd", "vpaddq", "vpaddsb", "vpaddsw", "vpaddusb", "vpaddusw", "vpaddw", "vpalignr", "vandpd", "vandps", "vorpd", "vorps", "vandnpd", "vandnps", "vpand", "vpandn", "vpavgb", "vpavgw", "vpblendd", "vpblendvb", "vpblendw", "vpbroadcastb", "vpbroadcastd", "vpbroadcastq", "vpbroadcastw", "vpclmulqdq", "vpcmpeqb", "vpcmpeqd", "vpcmpeqq", "vpcmpeqw", "vpcmpgtb", "vpcmpgtd", "vpcmpgtq", "vpcmpgtw", "vpcmpestri", "vpcmpestrm", "vpcmpistri", "vpcmpistrm", "vperm2f128", "vperm2i128", "vpermd", "vpermilpd", "vpermilps", "vpermpd", "vpermps", "vpermq", "vpextrb", "vpextrd", "vpextrq", "vpextrw", "vpgatherdd", "vpgatherdq", "vpgatherqd", "vpgatherqq", "vphaddd", "vphaddsw", "vphaddw", "vpmaddubsw", "vphminposuw", "vphsubd", "vphsubsw", "vphsubw", "vpinsrb", "vpinsrd", "vpinsrq", "vpinsrw", "vpmaddwd", "vpmaskmovd", "vpmaskmovq", "vpmaxsb", "vpmaxsd", "vpmaxsw", "vpmaxub", "vpmaxuw", "vpmaxud", "vpminsb", "vpminsw", "vpminsd", "vpminub", "vpminuw", "vpminud", "vpmovmskb", "vpmovsxbd", "vpmovsxbq", "vpmovsxbw", "vpmovsxdq", "vpmovsxwd", "vpmovsxwq", "vpmovzxbd", "vpmovzxbq", "vpmovzxbw", "vpmovzxdq", "vpmovzxwd", "vpmovzxwq", "vpmuldq", "vpmulhrsw", "vpmulhuw", "vpmulhw", "vpmullq", "vpmulld", "vpmullw", "vpmuludq", "vpor", "vpsadbw", "vpshufb", "vpshufd", "vpsignb", "vpsignd", "vpsignw", "vpslld", "vpslldq", "vpsllq", "vpsllvd", "vpsllvq", "vpsllw", "vpsrad", "vpsravd", "vpsraw", "vpsrld", "vpsrldq", "vpsrlq", "vpsrlvd", "vpsrlvq", "vpsrlw", "vpsubb", "vpsubd", "vpsubq", "vpsubsb", "vpsubsw", "vpsubusb", "vpsubusw", "vpsubw", "vptest", "vpunpckhbw", "vpunpckhdq", "vpunpckhqdq", "vpunpckhwd", "vpunpcklbw", "vpunpckldq", "vpunpcklqdq", "vpunpcklwd", "vpxor", "vrcpps", "vroundpd", "vroundps", "vroundsd", "vroundss", "vrsqrtps", "vrsqrtss", "vrcpss", "vshufpd", "vshufps", "vsqrtpd", "vsqrtps", "vsqrtss", "vsqrtsd", "vsubpd", "vsubps", "vsubsd", "vsubss", "vtestpd", "vtestps", "vunpckhpd", "vunpckhps", "vunpcklpd", "vunpcklps", "vxorpd", "vxorps", "vzeroupper", "vzeroall", "vldmxcsr", "vstmxcsr", "pclmulqdq", "aeskeygenassist", "aesimc", "aesenc", "aesenclast", "aesdec", "aesdeclast", "pcmpgtq", "pcmpistrm", "pcmpistri", "pcmpestri", "packusdw", "pcmpestrm", "pcmpeqq", "ptest", "phminposuw", "dpps", "dppd", "mpsadbw", "pmovzxdq", "pmovsxdq", "pmovzxbd", "pmovsxbd", "pmovzxwq", "pmovsxwq", "pmovzxbq", "pmovsxbq", "pmovsxwd", "pmovzxwd", "pextrq", "pextrd", "pextrw", "pextrb", "pmovsxbw", "pmovzxbw", "pinsrq", "pinsrd", "pinsrb", "extractps", "insertps", "roundss", "roundsd", "roundps", "roundpd", "pmaxsb", "pmaxsd", "pmaxuw", "pmaxud", "pminsd", "pminsb", "pminud", "pminuw", "blendw", "pblendvb", "pblendw", "blendvps", "blendvpd", "blendps", "blendpd", "pmuldq", "movntdqa", "pmulld", "palignr", "psignw", "psignd", "psignb", "pshufb", "pmulhrsw", "pmaddubsw", "pabsd", "pabsw", "pabsb", "phsubsw", "phsubw", "phsubd", "phaddd", "phaddsw", "phaddw", "hsubpd", "haddpd", "sha1rnds4", "sha1nexte", "sha1msg1", "sha1msg2", "sha256rnds2", "sha256msg1", "sha256msg2", "lzcnt", "clgi", "stgi", "skinit", "vmload", "vmmcall", "vmsave", "vmrun", "invlpga", "invlpgb", "tlbsync", "movbe", "adcx", "adox", "prefetchw", "rdpid", // " cmpxchg8b", // " cmpxchg16b", "vmptrld", "vmptrst", "bzhi", "mulx", "shlx", "shrx", "sarx", "pdep", "pext", "rorx", "xrstors", "xrstors64", "xsavec", "xsavec64", "xsaves", "xsaves64", "rdfsbase", "rdgsbase", "wrfsbase", "wrgsbase", "crc32", "salc", "xlat", "f2xm1", "fabs", "fadd", "faddp", "fbld", "fbstp", "fchs", "fcmovb", "fcmovbe", "fcmove", "fcmovnb", "fcmovnbe", "fcmovne", "fcmovnu", "fcmovu", "fcom", "fcomi", "fcomip", "fcomp", "fcompp", "fcos", "fdecstp", "fdisi8087_nop", "fdiv", "fdivp", "fdivr", "fdivrp", "feni8087_nop", "ffree", "ffreep", "fiadd", "ficom", "ficomp", "fidiv", "fidivr", "fild", "fimul", "fincstp", "fist", "fistp", "fisttp", "fisub", "fisubr", "fld", "fld1", "fldcw", "fldenv", "fldl2e", "fldl2t", "fldlg2", "fldln2", "fldpi", "fldz", "fmul", "fmulp", "fnclex", "fninit", "fnop", "fnsave", "fnstcw", "fnstenv", "fnstor", "fnstsw", "fpatan", "fprem", "fprem1", "fptan", "frndint", "frstor", "fscale", "fsetpm287_nop", "fsin", "fsincos", "fsqrt", "fst", "fstp", "fstpnce", "fsub", "fsubp", "fsubr", "fsubrp", "ftst", "fucom", "fucomi", "fucomip", "fucomp", "fucompp", "fxam", "fxch", "fxtract", "fyl2x", "fyl2xp1", "loopnz", "loopz", "loop", "jcxz", "pusha", "popa", "bound", "arpl", "aas", "aaa", "das", "daa", "aam", "aad", // started shipping in tremont, 2020 sept 23 "movdir64b", "movdiri", // started shipping in tiger lake, 2020 sept 2 "aesdec128kl", "aesdec256kl", "aesdecwide128kl", "aesdecwide256kl", "aesenc128kl", "aesenc256kl", "aesencwide128kl", "aesencwide256kl", "encodekey128", "encodekey256", "loadiwkey", // unsure "hreset", // 3dnow "femms", "pi2fw", "pi2fd", "pf2iw", "pf2id", "pmulhrw", "pfcmpge", "pfmin", "pfrcp", "pfrsqrt", "pfsub", "pfadd", "pfcmpgt", "pfmax", "pfrcpit1", "pfrsqit1", "pfsubr", "pfacc", "pfcmpeq", "pfmul", "pfmulhrw", "pfrcpit2", "pfnacc", "pfpnacc", "pswapd", "pavgusb", // enqcmd "enqcmd", "enqcmds", // invpcid "invept", "invvpid", "invpcid", // ptwrite "ptwrite", // gfni "gf2p8affineqb", "gf2p8affineinvqb", "gf2p8mulb", // cet "wruss", "wrss", "incssp", "saveprevssp", "setssbsy", "clrssbsy", "rstorssp", "endbr64", "endbr32", // tdx "tdcall", "seamret", "seamops", "seamcall", // waitpkg "tpause", "umonitor", "umwait", // uintr "uiret", "testui", "clui", "stui", "senduipi", // tsxldtrk "xsusldtrk", "xresldtrk", // avx512f "valignd", "valignq", "vblendmpd", "vblendmps", "vcompresspd", "vcompressps", "vcvtpd2udq", "vcvttpd2udq", "vcvtps2udq", "vcvttps2udq", "vcvtqq2pd", "vcvtqq2ps", "vcvtsd2usi", "vcvttsd2usi", "vcvtss2usi", "vcvttss2usi", "vcvtudq2pd", "vcvtudq2ps", "vcvtusi2usd", "vcvtusi2uss", "vexpandpd", "vexpandps", "vextractf32x4", "vextractf64x4", "vextracti32x4", "vextracti64x4", "vfixupimmpd", "vfixupimmps", "vfixupimmsd", "vfixupimmss", "vgetexppd", "vgetexpps", "vgetexpsd", "vgetexpss", "vgetmantpd", "vgetmantps", "vgetmantsd", "vgetmantss", "vinsertf32x4", "vinsertf64x4", "vinserti64x4", "vmovdqa32", "vmovdqa64", "vmovdqu32", "vmovdqu64", "vpblendmd", "vpblendmq", "vpcmpd", "vpcmpud", "vpcmpq", "vpcmpuq", "vpcompressq", "vpcompressd", "vpermi2d", "vpermi2q", "vpermi2pd", "vpermi2ps", "vpermt2d", "vpermt2q", "vpermt2pd", "vpermt2ps", "vpmaxsq", "vpmaxuq", "vpminsq", "vpminuq", "vpmovsqb", "vpmovusqb", "vpmovsqw", "vpmovusqw", "vpmovsqd", "vpmovusqd", "vpmovsdb", "vpmovusdb", "vpmovsdw", "vpmovusdw", "vprold", "vprolq", "vprolvd", "vprolvq", "vprord", "vprorq", "vprorrd", "vprorrq", "vpscatterdd", "vpscatterdq", "vpscatterqd", "vpscatterqq", "vpsraq", "vpsravq", "vptestnmd", "vptestnmq", "vpternlogd", "vpternlogq", "vptestmd", "vptestmq", "vrcp14pd", "vrcp14ps", "vrcp14sd", "vrcp14ss", "vrndscalepd", "vrndscaleps", "vrndscalesd", "vrndscaless", "vrsqrt14pd", "vrsqrt14ps", "vrsqrt14sd", "vrsqrt14ss", "vscaledpd", "vscaledps", "vscaledsd", "vscaledss", "vscatterdd", "vscatterdq", "vscatterqd", "vscatterqq", "vshuff32x4", "vshuff64x2", "vshufi32x4", "vshufi64x2", // avx512dq "vcvttpd2qq", "vcvtpd2qq", "vcvttpd2uqq", "vcvtpd2uqq", "vcvttps2qq", "vcvtps2qq", "vcvttps2uqq", "vcvtps2uqq", "vcvtuqq2pd", "vcvtuqq2ps", "vextractf64x2", "vextracti64x2", "vfpclasspd", "vfpclassps", "vfpclasssd", "vfpclassss", "vinsertf64x2", "vinserti64x2", "vpmovm2d", "vpmovm2q", "vpmovb2d", "vpmovq2m", "vrangepd", "vrangeps", "vrangesd", "vrangess", "vreducepd", "vreduceps", "vreducesd", "vreducess", // avx512bw "vdbpsadbw", "vmovdqu8", "vmovdqu16", "vpblendmb", "vpblendmw", "vpcmpb", "vpcmpub", "vpcmpw", "vpcmpuw", "vpermw", "vpermi2b", "vpermi2w", "vpmovm2b", "vpmovm2w", "vpmovb2m", "vpmovw2m", "vpmovswb", "vpmovuswb", "vpsllvw", "vpsravw", "vpsrlvw", "vptestnmb", "vptestnmw", "vptestmb", "vptestmw", // avx512cd "vpbroadcastm", "vpconflictd", "vpconflictq", "vplzcntd", "vplzcntq", "kunpckbw", "kunpckwd", "kunpckdq", "kaddb", "kandb", "kandnb", "kmovb", "knotb", "korb", "kortestb", "kshiftlb", "kshiftrb", "ktestb", "kxnorb", "kxorb", "kaddw", "kandw", "kandnw", "kmovw", "knotw", "korw", "kortestw", "kshiftlw", "kshiftrw", "ktestw", "kxnorw", "kxorw", "kaddd", "kandd", "kandnd", "kmovd", "knotd", "kord", "kortestd", "kshiftld", "kshiftrd", "ktestd", "kxnord", "kxord", "kaddq", "kandq", "kandnq", "kmovq", "knotq", "korq", "kortestq", "kshiftlq", "kshiftrq", "ktestq", "kxnorq", "kxorq", // avx512er "vexp2pd", "vexp2ps", "vexp2sd", "vexp2ss", "vrcp28pd", "vrcp28ps", "vrcp28sd", "vrcp28ss", "vrsqrt28pd", "vrsqrt28ps", "vrsqrt28sd", "vrsqrt28ss", // avx512pf "vgatherpf0dpd", "vgatherpf0dps", "vgatherpf0qpd", "vgatherpf0qps", "vgatherpf1dpd", "vgatherpf1dps", "vgatherpf1qpd", "vgatherpf1qps", "vscatterpf0dpd", "vscatterpf0dps", "vscatterpf0qpd", "vscatterpf0qps", "vscatterpf1dpd", "vscatterpf1dps", "vscatterpf1qpd", "vscatterpf1qps", // mpx "bndmk", "bndcl", "bndcu", "bndcn", "bndmov", "bndldx", "bndstx", "vgf2p8affineqb", "vgf2p8affineinvqb", "vpshrdq", "vpshrdd", "vpshrdw", "vpshldq", "vpshldd", "vpshldw", "vbroadcastf32x8", "vbroadcastf64x4", "vbroadcastf32x4", "vbroadcastf64x2", "vbroadcastf32x2", "vbroadcasti32x8", "vbroadcasti64x4", "vbroadcasti32x4", "vbroadcasti64x2", "vbroadcasti32x2", "vextracti32x8", "vextractf32x8", "vinserti32x8", "vinsertf32x8", "vinserti32x4", "v4fnmaddss", "v4fnmaddps", "vcvtneps2bf16", "v4fmaddss", "v4fmaddps", "vcvtne2ps2bf16", "vp2intersectd", "vp2intersectq", "vp4dpwssds", "vp4dpwssd", "vpdpwssds", "vpdpwssd", "vpdpbusds", "vdpbf16ps", "vpbroadcastmw2d", "vpbroadcastmb2q", "vpmovd2m", "vpmovqd", "vpmovwb", "vpmovdb", "vpmovdw", "vpmovqb", "vpmovqw", "vgf2p8mulb", "vpmadd52huq", "vpmadd52luq", "vpshufbitqmb", "vpermb", "vpexpandd", "vpexpandq", "vpabsq", "vprorvd", "vprorvq", "vpmultishiftqb", "vpermt2b", "vpermt2w", "vpshrdvq", "vpshrdvd", "vpshrdvw", "vpshldvq", "vpshldvd", "vpshldvw", "vpcompressb", "vpcompressw", "vpexpandb", "vpexpandw", "vpopcntd", "vpopcntq", "vpopcntb", "vpopcntw", "vscalefss", "vscalefsd", "vscalefps", "vscalefpd", "vpdpbusd", "vcvtusi2sd", "vcvtusi2ss", "vpxord", "vpxorq", "vpord", "vporq", "vpandnd", "vpandnq", "vpandd", "vpandq", "psmash", "pvalidate", "rmpadjust", "rmpupdate", ]; impl Opcode { fn name(&self) -> &'static str { unsafe { MNEMONICS.get_kinda_unchecked(*self as usize & 0xfff) } } } impl Colorize for Opcode { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { match self { Opcode::VGF2P8AFFINEQB | Opcode::VGF2P8AFFINEINVQB | Opcode::VPSHRDQ | Opcode::VPSHRDD | Opcode::VPSHRDW | Opcode::VPSHLDQ | Opcode::VPSHLDD | Opcode::VPSHLDW | Opcode::VBROADCASTF32X8 | Opcode::VBROADCASTF64X4 | Opcode::VBROADCASTF32X4 | Opcode::VBROADCASTF64X2 | Opcode::VBROADCASTF32X2 | Opcode::VBROADCASTI32X8 | Opcode::VBROADCASTI64X4 | Opcode::VBROADCASTI32X4 | Opcode::VBROADCASTI64X2 | Opcode::VBROADCASTI32X2 | Opcode::VEXTRACTI32X8 | Opcode::VEXTRACTF32X8 | Opcode::VINSERTI32X8 | Opcode::VINSERTF32X8 | Opcode::VINSERTI32X4 | Opcode::V4FNMADDSS | Opcode::V4FNMADDPS | Opcode::VCVTNEPS2BF16 | Opcode::V4FMADDSS | Opcode::V4FMADDPS | Opcode::VCVTNE2PS2BF16 | Opcode::VP2INTERSECTD | Opcode::VP2INTERSECTQ | Opcode::VP4DPWSSDS | Opcode::VP4DPWSSD | Opcode::VPDPWSSDS | Opcode::VPDPWSSD | Opcode::VPDPBUSDS | Opcode::VDPBF16PS | Opcode::VPBROADCASTMW2D | Opcode::VPBROADCASTMB2Q | Opcode::VPMOVD2M | Opcode::VPMOVQD | Opcode::VPMOVWB | Opcode::VPMOVDB | Opcode::VPMOVDW | Opcode::VPMOVQB | Opcode::VPMOVQW | Opcode::VGF2P8MULB | Opcode::VPMADD52HUQ | Opcode::VPMADD52LUQ | Opcode::VPSHUFBITQMB | Opcode::VPERMB | Opcode::VPEXPANDD | Opcode::VPEXPANDQ | Opcode::VPABSQ | Opcode::VPRORVD | Opcode::VPRORVQ | Opcode::VPMULTISHIFTQB | Opcode::VPERMT2B | Opcode::VPERMT2W | Opcode::VPSHRDVQ | Opcode::VPSHRDVD | Opcode::VPSHRDVW | Opcode::VPSHLDVQ | Opcode::VPSHLDVD | Opcode::VPSHLDVW | Opcode::VPCOMPRESSB | Opcode::VPCOMPRESSW | Opcode::VPEXPANDB | Opcode::VPEXPANDW | Opcode::VPOPCNTD | Opcode::VPOPCNTQ | Opcode::VPOPCNTB | Opcode::VPOPCNTW | Opcode::VSCALEFSS | Opcode::VSCALEFSD | Opcode::VSCALEFPS | Opcode::VSCALEFPD | Opcode::VPDPBUSD | Opcode::VCVTUSI2SD | Opcode::VCVTUSI2SS | Opcode::VPXORD | Opcode::VPXORQ | Opcode::VPORD | Opcode::VPORQ | Opcode::VPANDND | Opcode::VPANDNQ | Opcode::VPANDD | Opcode::VPANDQ | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::HADDPD | Opcode::HSUBPD | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::PABSB | Opcode::PABSD | Opcode::PABSW | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::PSIGNB | Opcode::PSIGND | Opcode::PSIGNW | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::PCLMULQDQ | Opcode::PMULDQ | Opcode::PMULHRSW | Opcode::PMULLD | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VEXP2PD | Opcode::VEXP2PS | Opcode::VEXP2SD | Opcode::VEXP2SS | Opcode::VRCP28PD | Opcode::VRCP28PS | Opcode::VRCP28SD | Opcode::VRCP28SS | Opcode::VRCP14PD | Opcode::VRCP14PS | Opcode::VRCP14SD | Opcode::VRCP14SS | Opcode::VRNDSCALEPD | Opcode::VRNDSCALEPS | Opcode::VRNDSCALESD | Opcode::VRNDSCALESS | Opcode::VRSQRT14PD | Opcode::VRSQRT14PS | Opcode::VRSQRT14SD | Opcode::VRSQRT14SS | Opcode::VSCALEDPD | Opcode::VSCALEDPS | Opcode::VSCALEDSD | Opcode::VSCALEDSS | Opcode::VRSQRT28PD | Opcode::VRSQRT28PS | Opcode::VRSQRT28SD | Opcode::VRSQRT28SS | Opcode::VRSQRTPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VRCPSS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::ROUNDPD | Opcode::ROUNDPS | Opcode::ROUNDSD | Opcode::ROUNDSS | Opcode::VRSQRTSS | Opcode::VSQRTSD | Opcode::VSQRTSS | Opcode::VPSADBW | Opcode::VMPSADBW | Opcode::VDBPSADBW | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPMADDUBSW | Opcode::VPMADDWD | Opcode::VDPPD | Opcode::VDPPS | Opcode::VRCPPS | Opcode::VORPD | Opcode::VORPS | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VPAND | Opcode::VPANDN | Opcode::VPOR | Opcode::VPXOR | Opcode::VXORPD | Opcode::VXORPS | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPROLD | Opcode::VPROLQ | Opcode::VPROLVD | Opcode::VPROLVQ | Opcode::VPRORD | Opcode::VPRORQ | Opcode::VPRORRD | Opcode::VPRORRQ | Opcode::VPSLLVW | Opcode::VPSRAQ | Opcode::VPSRAVQ | Opcode::VPSRAVW | Opcode::VPSRLVW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::PHADDD | Opcode::PHADDSW | Opcode::PHADDW | Opcode::PHSUBD | Opcode::PHSUBSW | Opcode::PHSUBW | Opcode::PMADDUBSW | Opcode::ADDSUBPD | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::RCPSS | Opcode::RSQRTSS | Opcode::SQRTSD | Opcode::ADDSD | Opcode::SUBSD | Opcode::MULSD | Opcode::DIVSD | Opcode::SQRTSS | Opcode::ADDSS | Opcode::SUBSS | Opcode::MULSS | Opcode::DIVSS | Opcode::HADDPS | Opcode::HSUBPS | Opcode::ADDSUBPS | Opcode::PMULHRW | Opcode::PFRCP | Opcode::PFRSQRT | Opcode::PFSUB | Opcode::PFADD | Opcode::PFRCPIT1 | Opcode::PFRSQIT1 | Opcode::PFSUBR | Opcode::PFACC | Opcode::PFMUL | Opcode::PFMULHRW | Opcode::PFRCPIT2 | Opcode::PFNACC | Opcode::PFPNACC | Opcode::PSWAPD | Opcode::PAVGUSB | Opcode::XADD| Opcode::DIV | Opcode::IDIV | Opcode::MUL | Opcode::MULX | Opcode::NEG | Opcode::NOT | Opcode::SAR | Opcode::SAL | Opcode::SHR | Opcode::SARX | Opcode::SHLX | Opcode::SHRX | Opcode::SHRD | Opcode::SHL | Opcode::RCR | Opcode::RCL | Opcode::ROR | Opcode::RORX | Opcode::ROL | Opcode::INC | Opcode::DEC | Opcode::SBB | Opcode::AND | Opcode::XOR | Opcode::OR | Opcode::LEA | Opcode::ADD | Opcode::ADC | Opcode::ADCX | Opcode::ADOX | Opcode::SUB | Opcode::POPCNT | Opcode::LZCNT | Opcode::VPLZCNTD | Opcode::VPLZCNTQ | Opcode::BT | Opcode::BTS | Opcode::BTR | Opcode::BTC | Opcode::BSF | Opcode::BSR | Opcode::BZHI | Opcode::PDEP | Opcode::PEXT | Opcode::TZCNT | Opcode::ANDN | Opcode::BEXTR | Opcode::BLSI | Opcode::BLSMSK | Opcode::BLSR | Opcode::ADDPS | Opcode::ADDPD | Opcode::ANDNPS | Opcode::ANDNPD | Opcode::ANDPS | Opcode::ANDPD | Opcode::COMISD | Opcode::COMISS | Opcode::DIVPS | Opcode::DIVPD | Opcode::MULPS | Opcode::MULPD | Opcode::ORPS | Opcode::ORPD | Opcode::PADDB | Opcode::PADDD | Opcode::PADDQ | Opcode::PADDSB | Opcode::PADDSW | Opcode::PADDUSB | Opcode::PADDUSW | Opcode::PADDW | Opcode::PAND | Opcode::PANDN | Opcode::PAVGB | Opcode::PAVGW | Opcode::PMADDWD | Opcode::PMULHUW | Opcode::PMULHW | Opcode::PMULLW | Opcode::PMULUDQ | Opcode::POR | Opcode::PSADBW | Opcode::PSHUFD | Opcode::PSHUFW | Opcode::PSHUFB | Opcode::PSLLD | Opcode::PSLLDQ | Opcode::PSLLQ | Opcode::PSLLW | Opcode::PSRAD | Opcode::PSRAW | Opcode::PSRLD | Opcode::PSRLDQ | Opcode::PSRLQ | Opcode::PSRLW | Opcode::PSUBB | Opcode::PSUBD | Opcode::PSUBQ | Opcode::PSUBSB | Opcode::PSUBSW | Opcode::PSUBUSB | Opcode::PSUBUSW | Opcode::PSUBW | Opcode::PXOR | Opcode::RSQRTPS | Opcode::SQRTPS | Opcode::SQRTPD | Opcode::SUBPS | Opcode::SUBPD | Opcode::XORPS | Opcode::XORPD | Opcode::RCPPS | Opcode::SHLD | Opcode::SLHD | Opcode::UCOMISD | Opcode::UCOMISS | Opcode::F2XM1 | Opcode::FABS | Opcode::FADD | Opcode::FADDP | Opcode::FCHS | Opcode::FCOS | Opcode::FDIV | Opcode::FDIVP | Opcode::FDIVR | Opcode::FDIVRP | Opcode::FIADD | Opcode::FIDIV | Opcode::FIDIVR | Opcode::FIMUL | Opcode::FISUB | Opcode::FISUBR | Opcode::FMUL | Opcode::FMULP | Opcode::FNCLEX | Opcode::FNINIT | Opcode::FPATAN | Opcode::FPREM | Opcode::FPREM1 | Opcode::FPTAN | Opcode::FRNDINT | Opcode::FSCALE | Opcode::FSIN | Opcode::FSINCOS | Opcode::FSQRT | Opcode::FSUB | Opcode::FSUBP | Opcode::FSUBR | Opcode::FSUBRP | Opcode::FXTRACT | Opcode::FYL2X | Opcode::FYL2XP1 | Opcode::AAA | Opcode::AAS | Opcode::DAS | Opcode::DAA | Opcode::AAD | Opcode::AAM | Opcode::KADDB | Opcode::KANDB | Opcode::KANDNB | Opcode::KNOTB | Opcode::KORB | Opcode::KSHIFTLB | Opcode::KSHIFTRB | Opcode::KXNORB | Opcode::KXORB | Opcode::KADDW | Opcode::KANDW | Opcode::KANDNW | Opcode::KNOTW | Opcode::KORW | Opcode::KSHIFTLW | Opcode::KSHIFTRW | Opcode::KXNORW | Opcode::KXORW | Opcode::KADDD | Opcode::KANDD | Opcode::KANDND | Opcode::KNOTD | Opcode::KORD | Opcode::KSHIFTLD | Opcode::KSHIFTRD | Opcode::KXNORD | Opcode::KXORD | Opcode::KADDQ | Opcode::KANDQ | Opcode::KANDNQ | Opcode::KNOTQ | Opcode::KORQ | Opcode::KSHIFTLQ | Opcode::KSHIFTRQ | Opcode::KXNORQ | Opcode::KXORQ | Opcode::IMUL => { write!(out, "{}", colors.arithmetic_op(self)) } Opcode::POPF | Opcode::PUSHF | Opcode::ENTER | Opcode::LEAVE | Opcode::PUSHA | Opcode::POPA | Opcode::PUSH | Opcode::POP => { write!(out, "{}", colors.stack_op(self)) } Opcode::WAIT | Opcode::FNOP | Opcode::FDISI8087_NOP | Opcode::FENI8087_NOP | Opcode::FSETPM287_NOP | Opcode::PREFETCHNTA | Opcode::PREFETCH0 | Opcode::PREFETCH1 | Opcode::PREFETCH2 | Opcode::PREFETCHW | Opcode::NOP => { write!(out, "{}", colors.nop_op(self)) } /* Control flow */ Opcode::HLT | Opcode::INT | Opcode::INTO | Opcode::IRET | Opcode::IRETD | Opcode::IRETQ | Opcode::RETF | Opcode::RETURN => { write!(out, "{}", colors.stop_op(self)) } Opcode::LOOPNZ | Opcode::LOOPZ | Opcode::LOOP | Opcode::JCXZ | Opcode::CALL | Opcode::CALLF | Opcode::JMP | Opcode::JMPF | Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JLE | Opcode::JG => { write!(out, "{}", colors.control_flow_op(self)) } /* Data transfer */ Opcode::PI2FW | Opcode::PI2FD | Opcode::PF2ID | Opcode::PF2IW | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2DQ | Opcode::VCVTPD2PS | Opcode::VCVTPH2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTPS2PH | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSI2SD | Opcode::VCVTSI2SS | Opcode::VCVTSS2SD | Opcode::VCVTSS2SI | Opcode::VCVTTSD2SI | Opcode::VCVTTSS2SI | Opcode::VCVTPD2UDQ | Opcode::VCVTTPD2UDQ | Opcode::VCVTPS2UDQ | Opcode::VCVTTPS2UDQ | Opcode::VCVTQQ2PD | Opcode::VCVTQQ2PS | Opcode::VCVTSD2USI | Opcode::VCVTTSD2USI | Opcode::VCVTSS2USI | Opcode::VCVTTSS2USI | Opcode::VCVTUDQ2PD | Opcode::VCVTUDQ2PS | Opcode::VCVTUSI2USD | Opcode::VCVTUSI2USS | Opcode::VCVTTPD2QQ | Opcode::VCVTPD2QQ | Opcode::VCVTTPD2UQQ | Opcode::VCVTPD2UQQ | Opcode::VCVTTPS2QQ | Opcode::VCVTPS2QQ | Opcode::VCVTTPS2UQQ | Opcode::VCVTPS2UQQ | Opcode::VCVTUQQ2PD | Opcode::VCVTUQQ2PS | Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VBLENDMPD | Opcode::VBLENDMPS | Opcode::VPBLENDMD | Opcode::VPBLENDMQ | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VPBLENDMB | Opcode::VPBLENDMW | Opcode::PBLENDVB | Opcode::PBLENDW | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::BLENDW | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VPBROADCASTM | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::EXTRACTPS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VGATHERPF0DPD | Opcode::VGATHERPF0DPS | Opcode::VGATHERPF0QPD | Opcode::VGATHERPF0QPS | Opcode::VGATHERPF1DPD | Opcode::VGATHERPF1DPS | Opcode::VGATHERPF1QPD | Opcode::VGATHERPF1QPS | Opcode::VSCATTERDD | Opcode::VSCATTERDQ | Opcode::VSCATTERQD | Opcode::VSCATTERQQ | Opcode::VPSCATTERDD | Opcode::VPSCATTERDQ | Opcode::VPSCATTERQD | Opcode::VPSCATTERQQ | Opcode::VSCATTERPF0DPD | Opcode::VSCATTERPF0DPS | Opcode::VSCATTERPF0QPD | Opcode::VSCATTERPF0QPS | Opcode::VSCATTERPF1DPD | Opcode::VSCATTERPF1DPS | Opcode::VSCATTERPF1QPD | Opcode::VSCATTERPF1QPS | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::INSERTPS | Opcode::VEXTRACTF32X4 | Opcode::VEXTRACTF64X2 | Opcode::VEXTRACTF64X4 | Opcode::VEXTRACTI32X4 | Opcode::VEXTRACTI64X2 | Opcode::VEXTRACTI64X4 | Opcode::VINSERTF32X4 | Opcode::VINSERTF64X2 | Opcode::VINSERTF64X4 | Opcode::VINSERTI64X2 | Opcode::VINSERTI64X4 | Opcode::VSHUFF32X4 | Opcode::VSHUFF64X2 | Opcode::VSHUFI32X4 | Opcode::VSHUFI64X2 | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::MOVDIR64B | Opcode::MOVDIRI | Opcode::MOVNTDQA | Opcode::VMOVQ | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMOVSD | Opcode::VMOVSS | Opcode::VMOVDQA32 | Opcode::VMOVDQA64 | Opcode::VMOVDQU32 | Opcode::VMOVDQU64 | Opcode::VPMOVM2B | Opcode::VPMOVM2W | Opcode::VPMOVB2M | Opcode::VPMOVW2M | Opcode::VPMOVSWB | Opcode::VPMOVUSWB | Opcode::VPMOVSQB | Opcode::VPMOVUSQB | Opcode::VPMOVSQW | Opcode::VPMOVUSQW | Opcode::VPMOVSQD | Opcode::VPMOVUSQD | Opcode::VPMOVSDB | Opcode::VPMOVUSDB | Opcode::VPMOVSDW | Opcode::VPMOVUSDW | Opcode::VPMOVM2D | Opcode::VPMOVM2Q | Opcode::VPMOVB2D | Opcode::VPMOVQ2M | Opcode::VMOVDQU8 | Opcode::VMOVDQU16 | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPCLMULQDQ | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::PMOVSXBD | Opcode::PMOVSXBQ | Opcode::PMOVSXBW | Opcode::PMOVSXDQ | Opcode::PMOVSXWD | Opcode::PMOVSXWQ | Opcode::PMOVZXBD | Opcode::PMOVZXBQ | Opcode::PMOVZXBW | Opcode::PMOVZXDQ | Opcode::PMOVZXWD | Opcode::PMOVZXWQ | Opcode::KUNPCKBW | Opcode::KUNPCKWD | Opcode::KUNPCKDQ | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::PACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VALIGND | Opcode::VALIGNQ | Opcode::VPALIGNR | Opcode::PALIGNR | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPERMI2D | Opcode::VPERMI2Q | Opcode::VPERMI2PD | Opcode::VPERMI2PS | Opcode::VPERMT2D | Opcode::VPERMT2Q | Opcode::VPERMT2PD | Opcode::VPERMT2PS | Opcode::VPERMI2B | Opcode::VPERMI2W | Opcode::VPERMW | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::PEXTRB | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::EXTRQ | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::INSERTQ | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VCOMPRESSPD | Opcode::VCOMPRESSPS | Opcode::VPCOMPRESSQ | Opcode::VPCOMPRESSD | Opcode::VEXPANDPD | Opcode::VEXPANDPS | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPHMINPOSUW | Opcode::PHMINPOSUW | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VFIXUPIMMPD | Opcode::VFIXUPIMMPS | Opcode::VFIXUPIMMSD | Opcode::VFIXUPIMMSS | Opcode::VREDUCEPD | Opcode::VREDUCEPS | Opcode::VREDUCESD | Opcode::VREDUCESS | Opcode::VGETEXPPD | Opcode::VGETEXPPS | Opcode::VGETEXPSD | Opcode::VGETEXPSS | Opcode::VGETMANTPD | Opcode::VGETMANTPS | Opcode::VGETMANTSD | Opcode::VGETMANTSS | Opcode::VLDDQU | Opcode::BSWAP | Opcode::CVTDQ2PD | Opcode::CVTDQ2PS | Opcode::CVTPS2DQ | Opcode::CVTPD2DQ | Opcode::CVTPI2PS | Opcode::CVTPI2PD | Opcode::CVTPS2PD | Opcode::CVTPD2PS | Opcode::CVTPS2PI | Opcode::CVTPD2PI | Opcode::CVTSD2SI | Opcode::CVTSD2SS | Opcode::CVTSI2SD | Opcode::CVTSI2SS | Opcode::CVTSS2SD | Opcode::CVTSS2SI | Opcode::CVTTPD2DQ | Opcode::CVTTPS2DQ | Opcode::CVTTPS2PI | Opcode::CVTTPD2PI | Opcode::CVTTSD2SI | Opcode::CVTTSS2SI | Opcode::MASKMOVQ | Opcode::MASKMOVDQU | Opcode::MOVAPS | Opcode::MOVAPD | Opcode::MOVD | Opcode::MOVHPS | Opcode::MOVHPD | Opcode::MOVHLPS | Opcode::MOVLPS | Opcode::MOVLPD | Opcode::MOVLHPS | Opcode::MOVMSKPS | Opcode::MOVMSKPD | Opcode::MOVNTI | Opcode::MOVNTPS | Opcode::MOVNTPD | Opcode::MOVNTSS | Opcode::MOVNTSD | Opcode::MOVNTQ | Opcode::MOVNTDQ | Opcode::MOVSD | Opcode::MOVSS | Opcode::MOVUPD | Opcode::PSHUFHW | Opcode::PSHUFLW | Opcode::PUNPCKHBW | Opcode::PUNPCKHDQ | Opcode::PUNPCKHWD | Opcode::PUNPCKLBW | Opcode::PUNPCKLDQ | Opcode::PUNPCKLWD | Opcode::PUNPCKLQDQ | Opcode::PUNPCKHQDQ | Opcode::PACKSSDW | Opcode::PACKSSWB | Opcode::PACKUSWB | Opcode::UNPCKHPS | Opcode::UNPCKHPD | Opcode::UNPCKLPS | Opcode::UNPCKLPD | Opcode::SHUFPD | Opcode::SHUFPS | Opcode::PMOVMSKB | Opcode::KMOVB | Opcode::KMOVW | Opcode::KMOVD | Opcode::KMOVQ | Opcode::BNDMOV | Opcode::LDDQU | Opcode::CMC | Opcode::CLC | Opcode::CLI | Opcode::CLD | Opcode::STC | Opcode::STI | Opcode::STD | Opcode::CBW | Opcode::CWDE | Opcode::CDQE | Opcode::CWD | Opcode::CDQ | Opcode::CQO | Opcode::MOVDDUP | Opcode::MOVSLDUP | Opcode::MOVDQ2Q | Opcode::MOVDQU | Opcode::MOVDQA | Opcode::MOVQ | Opcode::MOVQ2DQ | Opcode::MOVSHDUP | Opcode::MOVUPS | Opcode::PEXTRW | Opcode::PINSRW | Opcode::MOV | Opcode::MOVBE | Opcode::LODS | Opcode::STOS | Opcode::LAHF | Opcode::SAHF | Opcode::MOVS | Opcode::INS | Opcode::IN | Opcode::OUTS | Opcode::OUT | Opcode::MOVZX | Opcode::MOVSX | Opcode::MOVSXD | Opcode::FILD | Opcode::FBLD | Opcode::FBSTP | Opcode::FIST | Opcode::FISTP | Opcode::FISTTP | Opcode::FLD | Opcode::FLD1 | Opcode::FLDCW | Opcode::FLDENV | Opcode::FLDL2E | Opcode::FLDL2T | Opcode::FLDLG2 | Opcode::FLDLN2 | Opcode::FLDPI | Opcode::FLDZ | Opcode::FST | Opcode::FSTP | Opcode::FSTPNCE | Opcode::FNSAVE | Opcode::FNSTCW | Opcode::FNSTENV | Opcode::FNSTOR | Opcode::FNSTSW | Opcode::FRSTOR | Opcode::FXCH | Opcode::XCHG | Opcode::XLAT | Opcode::CMOVA | Opcode::CMOVB | Opcode::CMOVG | Opcode::CMOVGE | Opcode::CMOVL | Opcode::CMOVLE | Opcode::CMOVNA | Opcode::CMOVNB | Opcode::CMOVNO | Opcode::CMOVNP | Opcode::CMOVNS | Opcode::CMOVNZ | Opcode::CMOVO | Opcode::CMOVP | Opcode::CMOVS | Opcode::CMOVZ | Opcode::FCMOVB | Opcode::FCMOVBE | Opcode::FCMOVE | Opcode::FCMOVNB | Opcode::FCMOVNBE | Opcode::FCMOVNE | Opcode::FCMOVNU | Opcode::FCMOVU | Opcode::SALC | Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETBE | Opcode::SETA | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETLE | Opcode::SETG => { write!(out, "{}", colors.data_op(self)) } Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::KORTESTB | Opcode::KTESTB | Opcode::KORTESTW | Opcode::KTESTW | Opcode::KORTESTD | Opcode::KTESTD | Opcode::KORTESTQ | Opcode::KTESTQ | Opcode::VPTESTNMD | Opcode::VPTESTNMQ | Opcode::VPTERNLOGD | Opcode::VPTERNLOGQ | Opcode::VPTESTMD | Opcode::VPTESTMQ | Opcode::VPTESTNMB | Opcode::VPTESTNMW | Opcode::VPTESTMB | Opcode::VPTESTMW | Opcode::VPCMPD | Opcode::VPCMPUD | Opcode::VPCMPQ | Opcode::VPCMPUQ | Opcode::VPCMPB | Opcode::VPCMPUB | Opcode::VPCMPW | Opcode::VPCMPUW | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VPMAXSQ | Opcode::VPMAXUQ | Opcode::VPMINSQ | Opcode::VPMINUQ | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VFPCLASSPD | Opcode::VFPCLASSPS | Opcode::VFPCLASSSD | Opcode::VFPCLASSSS | Opcode::VRANGEPD | Opcode::VRANGEPS | Opcode::VRANGESD | Opcode::VRANGESS | Opcode::VPCONFLICTD | Opcode::VPCONFLICTQ | Opcode::VPTEST | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::PCMPEQB | Opcode::PCMPEQD | Opcode::PCMPEQQ | Opcode::PCMPEQW | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPGTB | Opcode::PCMPGTD | Opcode::PCMPGTQ | Opcode::PCMPGTW | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PTEST | Opcode::MAXPD | Opcode::MAXPS | Opcode::MAXSD | Opcode::MAXSS | Opcode::MINPD | Opcode::MINPS | Opcode::MINSD | Opcode::MINSS | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::PMAXSW | Opcode::PMAXUB | Opcode::PMAXUD | Opcode::PMAXUW | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMINSW | Opcode::PMINUB | Opcode::PMINUD | Opcode::PMINUW | Opcode::PFCMPGE | Opcode::PFMIN | Opcode::PFCMPGT | Opcode::PFMAX | Opcode::PFCMPEQ | Opcode::CMPS | Opcode::SCAS | Opcode::TEST | Opcode::FTST | Opcode::FXAM | Opcode::FUCOM | Opcode::FUCOMI | Opcode::FUCOMIP | Opcode::FUCOMP | Opcode::FUCOMPP | Opcode::FCOM | Opcode::FCOMI | Opcode::FCOMIP | Opcode::FCOMP | Opcode::FCOMPP | Opcode::FICOM | Opcode::FICOMP | Opcode::CMPSD | Opcode::CMPSS | Opcode::CMP | Opcode::CMPPS | Opcode::CMPPD | Opcode::CMPXCHG8B | Opcode::CMPXCHG16B | Opcode::CMPXCHG => { write!(out, "{}", colors.comparison_op(self)) } Opcode::WRMSR | Opcode::RDMSR | Opcode::RDTSC | Opcode::RDPMC | Opcode::RDPID | Opcode::RDFSBASE | Opcode::RDGSBASE | Opcode::WRFSBASE | Opcode::WRGSBASE | Opcode::FXSAVE | Opcode::FXRSTOR | Opcode::LDMXCSR | Opcode::STMXCSR | Opcode::VLDMXCSR | Opcode::VSTMXCSR | Opcode::XSAVE | Opcode::XSAVEC | Opcode::XSAVES | Opcode::XSAVEC64 | Opcode::XSAVES64 | Opcode::XRSTOR | Opcode::XRSTORS | Opcode::XRSTORS64 | Opcode::XSAVEOPT | Opcode::LFENCE | Opcode::MFENCE | Opcode::SFENCE | Opcode::CLFLUSH | Opcode::CLFLUSHOPT | Opcode::CLWB | Opcode::LDS | Opcode::LES | Opcode::SGDT | Opcode::SIDT | Opcode::LGDT | Opcode::LIDT | Opcode::SMSW | Opcode::LMSW | Opcode::SWAPGS | Opcode::RDTSCP | Opcode::INVEPT | Opcode::INVVPID | Opcode::INVPCID | Opcode::INVLPG | Opcode::INVLPGA | Opcode::INVLPGB | Opcode::TLBSYNC | Opcode::PSMASH | Opcode::PVALIDATE | Opcode::RMPADJUST | Opcode::RMPUPDATE | Opcode::CPUID | Opcode::WBINVD | Opcode::INVD | Opcode::SYSRET | Opcode::CLTS | Opcode::SYSCALL | Opcode::TDCALL | Opcode::SEAMRET | Opcode::SEAMOPS | Opcode::SEAMCALL | Opcode::TPAUSE | Opcode::UMONITOR | Opcode::UMWAIT | Opcode::LSL | Opcode::SLDT | Opcode::STR | Opcode::LLDT | Opcode::LTR | Opcode::VERR | Opcode::VERW | Opcode::JMPE | Opcode::EMMS | Opcode::FEMMS | Opcode::GETSEC | Opcode::LFS | Opcode::LGS | Opcode::LSS | Opcode::RSM | Opcode::SYSENTER | Opcode::SYSEXIT | Opcode::VMREAD | Opcode::VMWRITE | Opcode::VMCLEAR | Opcode::VMPTRLD | Opcode::VMPTRST | Opcode::VMXON | Opcode::VMCALL | Opcode::VMLAUNCH | Opcode::VMRESUME | Opcode::VMLOAD | Opcode::VMMCALL | Opcode::VMSAVE | Opcode::VMRUN | Opcode::VMXOFF | Opcode::PCONFIG | Opcode::MONITOR | Opcode::MWAIT | Opcode::MONITORX | Opcode::MWAITX | Opcode::SKINIT | Opcode::CLGI | Opcode::STGI | Opcode::CLAC | Opcode::STAC | Opcode::ENCLS | Opcode::ENCLV | Opcode::XGETBV | Opcode::XSETBV | Opcode::VMFUNC | Opcode::XEND | Opcode::XTEST | Opcode::XABORT | Opcode::XBEGIN | Opcode::ENCLU | Opcode::RDPKRU | Opcode::WRPKRU | Opcode::RDPRU | Opcode::CLZERO | Opcode::ENQCMD | Opcode::ENQCMDS | Opcode::PTWRITE | Opcode::UIRET | Opcode::TESTUI | Opcode::CLUI | Opcode::STUI | Opcode::SENDUIPI | Opcode::XSUSLDTRK | Opcode::XRESLDTRK | Opcode::BOUND | Opcode::ARPL | Opcode::BNDMK | Opcode::BNDCL | Opcode::BNDCU | Opcode::BNDCN | Opcode::BNDLDX | Opcode::BNDSTX | Opcode::LAR => { write!(out, "{}", colors.platform_op(self)) } Opcode::CRC32 | Opcode::RDSEED | Opcode::RDRAND | Opcode::SHA1RNDS4 | Opcode::SHA1NEXTE | Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA256RNDS2 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::FFREE | Opcode::FFREEP | Opcode::FDECSTP | Opcode::FINCSTP | Opcode::GF2P8MULB | Opcode::GF2P8AFFINEQB | Opcode::GF2P8AFFINEINVQB | Opcode::AESDEC128KL | Opcode::AESDEC256KL | Opcode::AESDECWIDE128KL | Opcode::AESDECWIDE256KL | Opcode::AESENC128KL | Opcode::AESENC256KL | Opcode::AESENCWIDE128KL | Opcode::AESENCWIDE256KL | Opcode::ENCODEKEY128 | Opcode::ENCODEKEY256 | Opcode::LOADIWKEY | Opcode::HRESET | Opcode::WRUSS | Opcode::WRSS | Opcode::INCSSP | Opcode::SAVEPREVSSP | Opcode::SETSSBSY | Opcode::CLRSSBSY | Opcode::RSTORSSP | Opcode::ENDBR64 | Opcode::ENDBR32 | Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST | Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { write!(out, "{}", colors.misc_op(self)) } Opcode::UD0 | Opcode::UD1 | Opcode::UD2 | Opcode::Invalid => { write!(out, "{}", colors.invalid_op(self)) } } } } impl fmt::Display for Instruction { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.display_with(DisplayStyle::Intel).colorize(&NoColors, fmt) } } impl<'instr> fmt::Display for InstructionDisplayer<'instr> { fn fmt(&self, fmt: &mut fmt::Formatter) -> fmt::Result { self.colorize(&NoColors, fmt) } } /// enum controlling how `Instruction::display_with` renders instructions. `Intel` is more or less /// intel syntax, though memory operand sizes are elided if they can be inferred from other /// operands. #[derive(Copy, Clone)] pub enum DisplayStyle { /// intel-style syntax for instructions, like /// `add eax, [edx + ecx * 2 + 0x1234]` Intel, /// C-style syntax for instructions, like /// `eax += [edx + ecx * 2 + 0x1234]` C, // one might imagine an ATT style here, which is mostly interesting for reversing operand // order. // well. // it also complicates memory operands in an offset-only operand, and is just kind of awful, so // it's just not implemented yet. // ATT, } /// implementation of [`Display`](fmt::Display) that renders instructions using a specified display /// style. pub struct InstructionDisplayer<'instr> { pub(crate) instr: &'instr Instruction, pub(crate) style: DisplayStyle, } /* * Can't implement this as accepting a formatter because rust * doesn't let me build one outside println! or write! or whatever. * * can't write this as an intermediate struct because i refuse to copy * all data into the struct, and having a function producing a struct with * some lifetimes gets really hairy if it's from a trait - same GAT kind * of nonsense as i saw with ContextRead, because someone could hold onto * the dang intermediate struct forever. * * so write to some Write thing i guess. bite me. i really just want to * stop thinking about how to support printing instructions... */ impl <'instr, T: fmt::Write, Y: YaxColors> Colorize for InstructionDisplayer<'instr> { fn colorize(&self, colors: &Y, out: &mut T) -> fmt::Result { // TODO: I DONT LIKE THIS, there is no address i can give contextualize here, // the address operand maybe should be optional.. self.contextualize(colors, 0, Some(&NoContext), out) } } /// No per-operand context when contextualizing an instruction! struct NoContext; impl Instruction { pub fn write_to(&self, out: &mut T) -> fmt::Result { self.display_with(DisplayStyle::Intel).contextualize(&NoColors, 0, Some(&NoContext), out) } } fn contextualize_intel(instr: &Instruction, colors: &Y, _address: u32, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { if instr.xacquire() { out.write_str("xacquire ")?; } if instr.xrelease() { out.write_str("xrelease ")?; } if instr.prefixes.lock() { out.write_str("lock ")?; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { if instr.prefixes.rep() { write!(out, "rep ")?; } else if instr.prefixes.repnz() { write!(out, "repnz ")?; } } } out.write_str(instr.opcode.name())?; if instr.opcode == Opcode::XBEGIN { if (instr.imm as i32) >= 0 { return write!(out, " $+{}", colors.number(signed_i32_hex(instr.imm as i32))); } else { return write!(out, " ${}", colors.number(signed_i32_hex(instr.imm as i32))); } } if instr.operand_count > 0 { out.write_str(" ")?; let x = Operand::from_spec(instr, instr.operands[0]); const RELATIVE_BRANCHES: [Opcode; 21] = [ Opcode::JMP, Opcode::JCXZ, Opcode::LOOP, Opcode::LOOPZ, Opcode::LOOPNZ, Opcode::JO, Opcode::JNO, Opcode::JB, Opcode::JNB, Opcode::JZ, Opcode::JNZ, Opcode::JNA, Opcode::JA, Opcode::JS, Opcode::JNS, Opcode::JP, Opcode::JNP, Opcode::JL, Opcode::JGE, Opcode::JLE, Opcode::JG, ]; if instr.operands[0] == OperandSpec::ImmI8 || instr.operands[0] == OperandSpec::ImmI32 { if RELATIVE_BRANCHES.contains(&instr.opcode) { return match x { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } _ => { unreachable!() } }; } } if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; for i in 1..instr.operand_count { match instr.opcode { _ => { match &instr.operands[i as usize] { &OperandSpec::Nothing => { return Ok(()); }, _ => { out.write_str(", ")?; let x = Operand::from_spec(instr, instr.operands[i as usize]); if x.is_memory() { out.write_str(MEM_SIZE_STRINGS[instr.mem_size as usize - 1])?; out.write_str(" ")?; } if let Some(prefix) = instr.segment_override_for_op(i) { write!(out, "{}:", prefix)?; } x.colorize(colors, out)?; if let Some(evex) = instr.prefixes.evex() { if evex.broadcast() && x.is_memory() { let scale = if instr.opcode == Opcode::VCVTPD2PS || instr.opcode == Opcode::VCVTTPD2UDQ || instr.opcode == Opcode::VCVTPD2UDQ || instr.opcode == Opcode::VCVTUDQ2PD || instr.opcode == Opcode::VCVTPS2PD || instr.opcode == Opcode::VCVTQQ2PS || instr.opcode == Opcode::VCVTDQ2PD || instr.opcode == Opcode::VCVTTPD2DQ || instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VFPCLASSPD || instr.opcode == Opcode::VCVTNEPS2BF16 || instr.opcode == Opcode::VCVTUQQ2PS || instr.opcode == Opcode::VCVTPD2DQ || instr.opcode == Opcode::VCVTTPS2UQQ || instr.opcode == Opcode::VCVTPS2UQQ || instr.opcode == Opcode::VCVTTPS2QQ || instr.opcode == Opcode::VCVTPS2QQ { if instr.opcode == Opcode::VFPCLASSPS || instr.opcode == Opcode::VCVTNEPS2BF16 { if evex.vex().l() { 8 } else if evex.lp() { 16 } else { 4 } } else if instr.opcode == Opcode::VFPCLASSPD { if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } else { // vcvtpd2ps is "cool": in broadcast mode, it can read a // double-precision float (qword), resize to single-precision, // then broadcast that to the whole destination register. this // means we need to show `xmm, qword [addr]{1to4}` if vector // size is 256. likewise, scale of 8 for the same truncation // reason if vector size is 512. // vcvtudq2pd is the same story. // vfpclassp{s,d} is a mystery to me. if evex.vex().l() { 4 } else if evex.lp() { 8 } else { 2 } } } else { // this should never be `None` - that would imply two // memory operands for a broadcasted operation. if let Some(width) = Operand::from_spec(instr, instr.operands[i as usize - 1]).width() { width / instr.mem_size } else { 0 } }; write!(out, "{{1to{}}}", scale)?; } } } } } } } } Ok(()) } fn contextualize_c(instr: &Instruction, colors: &Y, _address: u32, _context: Option<&NoContext>, out: &mut T) -> fmt::Result { let mut brace_count = 0; let mut prefixed = false; if instr.xacquire() { out.write_str("xacquire ")?; prefixed = true; } if instr.xrelease() { out.write_str("xrelease ")?; prefixed = true; } if instr.prefixes.lock() { out.write_str("lock ")?; prefixed = true; } if prefixed { out.write_str("{ ")?; brace_count += 1; } if instr.prefixes.rep_any() { if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&instr.opcode) { let word_str = match instr.mem_size { 1 => "byte", 2 => "word", 4 => "dword", 8 => "qword", _ => { unreachable!("invalid word size") } }; // only a few of you actually use the prefix... if instr.prefixes.rep() { out.write_str("rep ")?; } else if instr.prefixes.repnz() { out.write_str("repnz ")?; } // TODO: other rep kinds? out.write_str(word_str)?; out.write_str(" { ")?; brace_count += 1; } } fn write_jmp_operand(op: Operand, colors: &Y, out: &mut T) -> fmt::Result { match op { Operand::ImmediateI8(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel as i32))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel as i32))) } } Operand::ImmediateI32(rel) => { if rel >= 0 { write!(out, "$+{}", colors.number(signed_i32_hex(rel))) } else { write!(out, "${}", colors.number(signed_i32_hex(rel))) } } other => { write!(out, "{}", other) } } } match instr.opcode { Opcode::Invalid => { out.write_str("invalid")?; }, Opcode::MOVS => { out.write_str("es:[edi++] = ds:[esi++]")?; }, Opcode::CMPS => { out.write_str("eflags = flags(ds:[esi++] - es:[edi++])")?; }, Opcode::LODS => { // TODO: size out.write_str("rax = ds:[esi++]")?; }, Opcode::STOS => { // TODO: size out.write_str("es:[edi++] = rax")?; }, Opcode::INS => { // TODO: size out.write_str("es:[edi++] = port(dx)")?; }, Opcode::OUTS => { // TODO: size out.write_str("port(dx) = ds:[esi++]")?; } Opcode::ADD => { write!(out, "{} += {}", instr.operand(0), instr.operand(1))?; } Opcode::OR => { write!(out, "{} |= {}", instr.operand(0), instr.operand(1))?; } Opcode::ADC => { write!(out, "{} += {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADCX => { write!(out, "{} += {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::ADOX => { write!(out, "{} += {} + eflags.of", instr.operand(0), instr.operand(1))?; } Opcode::SBB => { write!(out, "{} -= {} + eflags.cf", instr.operand(0), instr.operand(1))?; } Opcode::AND => { write!(out, "{} &= {}", instr.operand(0), instr.operand(1))?; } Opcode::XOR => { write!(out, "{} ^= {}", instr.operand(0), instr.operand(1))?; } Opcode::SUB => { write!(out, "{} -= {}", instr.operand(0), instr.operand(1))?; } Opcode::CMP => { write!(out, "eflags = flags({} - {})", instr.operand(0), instr.operand(1))?; } Opcode::TEST => { write!(out, "eflags = flags({} & {})", instr.operand(0), instr.operand(1))?; } Opcode::XADD => { write!(out, "({}, {}) = ({} + {}, {})", instr.operand(0), instr.operand(1), instr.operand(0), instr.operand(1), instr.operand(0))?; } Opcode::BT => { write!(out, "bt")?; } Opcode::BTS => { write!(out, "bts")?; } Opcode::BTC => { write!(out, "btc")?; } Opcode::BSR => { write!(out, "{} = msb({})", instr.operand(0), instr.operand(1))?; } Opcode::BSF => { write!(out, "{} = lsb({}) (x86 bsf)", instr.operand(0), instr.operand(1))?; } Opcode::TZCNT => { write!(out, "{} = lsb({})", instr.operand(0), instr.operand(1))?; } Opcode::MOV => { write!(out, "{} = {}", instr.operand(0), instr.operand(1))?; } Opcode::SAR => { write!(out, "{} = {} >>> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SAL => { write!(out, "{} = {} <<< {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHR => { write!(out, "{} = {} >> {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHRX => { write!(out, "{} = {} >> {} (x86 shrx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::SHL => { write!(out, "{} = {} << {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::SHLX => { write!(out, "{} = {} << {} (x86 shlx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROR => { write!(out, "{} = {} ror {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RORX => { write!(out, "{} = {} ror {} (x86 rorx)", instr.operand(0), instr.operand(1), instr.operand(2))?; } Opcode::ROL => { write!(out, "{} = {} rol {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCR => { write!(out, "{} = {} rcr {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::RCL => { write!(out, "{} = {} rcl {}", instr.operand(0), instr.operand(0), instr.operand(1))?; } Opcode::PUSH => { write!(out, "push({})", instr.operand(0))?; } Opcode::POP => { write!(out, "{} = pop()", instr.operand(0))?; } Opcode::MOVD => { write!(out, "{} = movd({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVQ => { write!(out, "{} = movq({})", instr.operand(0), instr.operand(1))?; } Opcode::MOVNTQ => { write!(out, "{} = movntq({})", instr.operand(0), instr.operand(1))?; } Opcode::INC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}++", instr.operand(0))?; }, 2 => { write!(out, "word {}++", instr.operand(0))?; }, 4 => { write!(out, "dword {}++", instr.operand(0))?; }, _ => { write!(out, "qword {}++", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}++", instr.operand(0))?; } } Opcode::DEC => { if instr.operand(0).is_memory() { match instr.mem_size { 1 => { write!(out, "byte {}--", instr.operand(0))?; }, 2 => { write!(out, "word {}--", instr.operand(0))?; }, 4 => { write!(out, "dword {}--", instr.operand(0))?; }, _ => { write!(out, "qword {}--", instr.operand(0))?; }, // sizes that are not 1, 2, or 4, *better* be 8. } } else { write!(out, "{}--", instr.operand(0))?; } } Opcode::JMP => { out.write_str("jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JCXZ => { out.write_str("if cx == 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOP => { out.write_str("cx--; if cx != 0 then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPZ => { out.write_str("cx--; if cx != 0 and zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::LOOPNZ => { out.write_str("cx--; if cx != 0 and !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNO => { out.write_str("if _(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JB => { out.write_str("if /* unsigned */ below(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNB => { out.write_str("if /* unsigned */ above_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JZ => { out.write_str("if zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNZ => { out.write_str("if !zero(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNA => { out.write_str("if /* unsigned */ below_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JA => { out.write_str("if /* unsigned */ above(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JS => { out.write_str("if signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNS => { out.write_str("if !signed(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JP => { out.write_str("if parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JNP => { out.write_str("if !parity(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JL => { out.write_str("if /* signed */ less(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JGE => { out.write_str("if /* signed */ greater_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JLE => { out.write_str("if /* signed */ less_or_equal(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::JG => { out.write_str("if /* signed */ greater(rflags) then jmp ")?; write_jmp_operand(instr.operand(0), colors, out)?; }, Opcode::NOP => { write!(out, "nop")?; } _ => { if instr.operand_count() == 0 { write!(out, "{}()", instr.opcode())?; } else { write!(out, "{} = {}({}", instr.operand(0), instr.opcode(), instr.operand(0))?; let mut comma = true; for i in 1..instr.operand_count() { if comma { write!(out, ", ")?; } write!(out, "{}", instr.operand(i))?; comma = true; } write!(out, ")")?; } } } while brace_count > 0 { out.write_str(" }")?; brace_count -= 1; } Ok(()) } impl <'instr, T: fmt::Write, Y: YaxColors> ShowContextual for InstructionDisplayer<'instr> { fn contextualize(&self, colors: &Y, address: u32, context: Option<&NoContext>, out: &mut T) -> fmt::Result { let InstructionDisplayer { instr, style, } = self; match style { DisplayStyle::Intel => { contextualize_intel(instr, colors, address, context, out) } DisplayStyle::C => { contextualize_c(instr, colors, address, context, out) } } } } #[cfg(feature="std")] impl ShowContextual], T, Y> for Instruction { fn contextualize(&self, colors: &Y, _address: u64, context: Option<&[Option]>, out: &mut T) -> fmt::Result { if self.prefixes.lock() { write!(out, "lock ")?; } if [Opcode::MOVS, Opcode::CMPS, Opcode::LODS, Opcode::STOS, Opcode::INS, Opcode::OUTS].contains(&self.opcode) { // only a few of you actually use the prefix... if self.prefixes.rep() { write!(out, "rep ")?; } else if self.prefixes.repnz() { write!(out, "repnz ")?; } } self.opcode.colorize(colors, out)?; match context.and_then(|xs| xs[0].as_ref()) { Some(s) => { write!(out, " {}", s)?; }, None => { match self.operands[0] { OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, " ")?; if let Some(prefix) = self.segment_override_for_op(0) { write!(out, "{}:", prefix)?; } } } let x = Operand::from_spec(self, self.operands[0]); x.colorize(colors, out)?; } }; for i in 1..self.operand_count { let i = i as usize; match context.and_then(|xs| xs[i].as_ref()) { Some(s) => { write!(out, ", {}", s)? } None => { match &self.operands[i] { &OperandSpec::Nothing => { return Ok(()); }, _ => { write!(out, ", ")?; if let Some(prefix) = self.segment_override_for_op(1) { write!(out, "{}:", prefix)?; } let x = Operand::from_spec(self, self.operands[i]); x.colorize(colors, out)? } } } } } Ok(()) } } yaxpeax-x86-1.2.2/src/real_mode/evex.rs000064400000000000000000000007671046102023000157750ustar 00000000000000// use crate::long_mode::{OperandSpec, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::real_mode::{Arch, DecodeError, RegSpec, RegisterBank, Instruction, Opcode}; use crate::real_mode::{read_modrm, read_E_vex, read_imm_unsigned}; use yaxpeax_arch::Reader; const DEFAULT_EVEX_REGISTER_SIZE: RegisterBank = RegisterBank::D; const DEFAULT_EVEX_REGISTER_WIDTH: u8 = 4; fn isa_has_qwords() -> bool { false } include!("../shared/generated_evex.in"); include!("../shared/evex.in"); yaxpeax-x86-1.2.2/src/real_mode/mod.rs000064400000000000000000016633561046102023000156170ustar 00000000000000mod vex; mod evex; #[cfg(feature = "fmt")] mod display; pub mod uarch; pub use crate::MemoryAccessSize; #[cfg(feature = "fmt")] pub use self::display::{DisplayStyle, InstructionDisplayer}; use core::cmp::PartialEq; use crate::safer_unchecked::unreachable_kinda_unchecked as unreachable_unchecked; use yaxpeax_arch::{AddressDiff, Decoder, Reader, LengthedInstruction}; use yaxpeax_arch::annotation::{AnnotatingDecoder, DescriptionSink, NullSink}; use yaxpeax_arch::{DecodeError as ArchDecodeError}; use core::fmt; impl fmt::Display for DecodeError { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str(self.description()) } } /// an `x86` register, including its number and type. if `fmt` is enabled, name too. /// /// ``` /// use yaxpeax_x86::long_mode::{RegSpec, register_class}; /// /// assert_eq!(RegSpec::ecx().num(), 1); /// assert_eq!(RegSpec::ecx().class(), register_class::D); /// ``` /// /// some registers have classes of their own, and only one member: `eip` and `eflags`. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, PartialOrd, Ord, Eq, PartialEq)] pub struct RegSpec { num: u8, bank: RegisterBank } use core::hash::Hash; use core::hash::Hasher; impl Hash for RegSpec { fn hash(&self, state: &mut H) { let code = ((self.bank as u16) << 8) | (self.num as u16); code.hash(state); } } /// the condition for a conditional instruction. /// /// these are only obtained through [`Opcode::condition()`]: /// ``` /// use yaxpeax_x86::long_mode::{Opcode, ConditionCode}; /// /// assert_eq!(Opcode::JB.condition(), Some(ConditionCode::B)); /// ``` #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] pub enum ConditionCode { O, NO, B, AE, Z, NZ, A, BE, S, NS, P, NP, L, GE, G, LE, } macro_rules! register { ($bank:ident, $name:ident => $num:expr, $($tail:tt)+) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } register!($bank, $($tail)*); }; ($bank:ident, $name:ident => $num:expr) => { #[inline] pub const fn $name() -> RegSpec { RegSpec { bank: RegisterBank::$bank, num: $num } } }; } #[allow(non_snake_case)] impl RegSpec { /// the register `eip`. this register is in the class `eip`, which contains only it. pub const EIP: RegSpec = RegSpec::eip(); /// the number of this register in its `RegisterClass`. /// /// for many registers this is a number in the name, but for registers harkening back to /// `x86_32`, the first eight registers are `rax`, `rcx`, `rdx`, `rbx`, `rsp`, `rbp`, `rsi`, /// and `rdi` (or `eXX` for the 32-bit forms, `XX` for 16-bit forms). pub fn num(&self) -> u8 { self.num } /// the class of register this register is in. /// /// this corresponds to the register's size, but is by the register's usage in the instruction /// set; `rax` and `mm0` are the same size, but different classes (`Q`(word) and `MM` (mmx) /// respectively). pub fn class(&self) -> RegisterClass { RegisterClass { kind: self.bank } } #[cfg(feature = "fmt")] /// return a human-friendly name for this register. the returned name is the same as would be /// used to render this register in an instruction. pub fn name(&self) -> &'static str { display::regspec_label(self) } /// construct a `RegSpec` for x87 register `st(num)` #[inline] pub fn st(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x87 reg st({})", num); } RegSpec { num, bank: RegisterBank::ST } } /// construct a `RegSpec` for xmm reg `num` #[inline] pub fn xmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 xmm reg {}", num); } RegSpec { num, bank: RegisterBank::X } } /// construct a `RegSpec` for ymm reg `num` #[inline] pub fn ymm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 ymm reg {}", num); } RegSpec { num, bank: RegisterBank::Y } } /// construct a `RegSpec` for zmm reg `num` #[inline] pub fn zmm(num: u8) -> RegSpec { if num >= 32 { panic!("invalid x86 zmm reg {}", num); } RegSpec { num, bank: RegisterBank::Z } } /// construct a `RegSpec` for mask reg `num` #[inline] pub fn mask(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 mask reg {}", num); } RegSpec { num, bank: RegisterBank::K } } /// construct a `RegSpec` for dword reg `num` #[inline] pub fn d(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 dword reg {}", num); } RegSpec { num, bank: RegisterBank::D } } /// construct a `RegSpec` for word reg `num` #[inline] pub fn w(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 word reg {}", num); } RegSpec { num, bank: RegisterBank::W } } /// construct a `RegSpec` for byte reg `num` #[inline] pub fn b(num: u8) -> RegSpec { if num >= 8 { panic!("invalid x86 byte reg {}", num); } RegSpec { num, bank: RegisterBank::B } } #[inline] fn from_parts(num: u8, bank: RegisterBank) -> RegSpec { RegSpec { num: num, bank: bank } } register!(EIP, eip => 0); register!(EFlags, eflags => 0); register!(S, es => 0, cs => 1, ss => 2, ds => 3, fs => 4, gs => 5); register!(D, eax => 0, ecx => 1, edx => 2, ebx => 3, esp => 4, ebp => 5, esi => 6, edi => 7 ); register!(W, ax => 0, cx => 1, dx => 2, bx => 3, sp => 4, bp => 5, si => 6, di => 7 ); register!(B, al => 0, cl => 1, dl => 2, bl => 3, ah => 4, ch => 5, dh => 6, bh => 7 ); #[inline] pub const fn zmm0() -> RegSpec { RegSpec { bank: RegisterBank::Z, num: 0 } } #[inline] pub const fn ymm0() -> RegSpec { RegSpec { bank: RegisterBank::Y, num: 0 } } #[inline] pub const fn xmm0() -> RegSpec { RegSpec { bank: RegisterBank::X, num: 0 } } #[inline] pub const fn st0() -> RegSpec { RegSpec { bank: RegisterBank::ST, num: 0 } } #[inline] pub const fn mm0() -> RegSpec { RegSpec { bank: RegisterBank::MM, num: 0 } } /// return the size of this register, in bytes #[inline] pub fn width(&self) -> u8 { self.class().width() } } #[allow(non_camel_case_types)] #[allow(dead_code)] enum SizeCode { b, vd, } /// an operand for an `x86` instruction. /// /// `Operand::Nothing` should be unreachable in practice; any such instructions should have an /// operand count of 0 (or at least one fewer than the `Nothing` operand's position). #[derive(Clone, Debug, PartialEq)] #[non_exhaustive] pub enum Operand { /// a sign-extended byte ImmediateI8(i8), /// a zero-extended byte ImmediateU8(u8), /// a sign-extended word ImmediateI16(i16), /// a zero-extended word ImmediateU16(u16), /// a sign-extended dword ImmediateI32(i32), /// a zero-extended dword ImmediateU32(u32), /// a bare register operand, such as `rcx`. Register(RegSpec), /// an `avx512` register operand with optional mask register and merge mode, such as /// `zmm3{k4}{z}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMerge(RegSpec, RegSpec, MergeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, such as `zmm3{k4}{z}{rd-sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSae(RegSpec, RegSpec, MergeMode, SaeMode), /// an `avx512` register operand with optional mask register, merge mode, and suppressed /// exceptions, with no overridden rounding mode, such as `zmm3{k4}{z}{sae}`. /// /// if the mask register is `k0`, there is no masking applied, and the default x86 operation is /// `MergeMode::Merge`. RegisterMaskMergeSaeNoround(RegSpec, RegSpec, MergeMode), /// a memory access to a literal word address. it's extremely rare that a well-formed x86 /// instruction uses this mode. as an example, `[0x1133]` DisplacementU16(u16), /// a memory access to a literal qword address. it's relatively rare that a well-formed x86 /// instruction uses this mode, but plausible. for example, `fs:[0x14]`. segment overrides, /// however, are maintained on the instruction itself. DisplacementU32(u32), /// a simple dereference of the address held in some register. for example: `[esi]`. RegDeref(RegSpec), /// a dereference of the address held in some register with offset. for example: `[esi + 0x14]`. RegDisp(RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8. this is almost always used with the `lea` instruction. for example: `[edx * 4]`. RegScale(RegSpec, u8), /// a dereference of the address from summing two registers. for example: `[ebp + rax]` RegIndexBase(RegSpec, RegSpec), /// a dereference of the address from summing two registers with offset. for example: `[edi + ecx + 0x40]` RegIndexBaseDisp(RegSpec, RegSpec, i32), /// a dereference of the address held in some register scaled by 1, 2, 4, or 8 with offset. this is almost always used with the `lea` instruction. for example: `[eax * 4 + 0x30]`. RegScaleDisp(RegSpec, u8, i32), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8. for /// example: `[esi + ecx * 4]` RegIndexBaseScale(RegSpec, RegSpec, u8), /// a dereference of the address from summing a register and index register scaled by 1, 2, 4, /// or 8, with offset. for /// example: `[esi + ecx * 4 + 0x1234]` RegIndexBaseScaleDisp(RegSpec, RegSpec, u8, i32), /// an `avx512` dereference of register with optional masking. for example: `[edx]{k3}` RegDerefMasked(RegSpec, RegSpec), /// an `avx512` dereference of register plus offset, with optional masking. for example: `[esp + 0x40]{k3}` RegDispMasked(RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8, with optional masking. this /// seems extraordinarily unlikely to occur in practice. for example: `[esi * 4]{k2}` RegScaleMasked(RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional masking. /// for example: `[esi + eax * 4]{k6}` RegIndexBaseMasked(RegSpec, RegSpec, RegSpec), /// an `avx512` dereference of a register plus offset, with optional masking. for example: /// `[esi + eax + 0x1313]{k6}` RegIndexBaseDispMasked(RegSpec, RegSpec, i32, RegSpec), /// an `avx512` dereference of a register scaled by 1, 2, 4, or 8 plus offset, with optional /// masking. this seems extraordinarily unlikely to occur in practice. for example: `[esi * /// 4 + 0x1357]{k2}` RegScaleDispMasked(RegSpec, u8, i32, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8, with optional /// masking. for example: `[esi + eax * 4]{k6}` RegIndexBaseScaleMasked(RegSpec, RegSpec, u8, RegSpec), /// an `avx512` dereference of a register plus index scaled by 1, 2, 4, or 8 and offset, with /// optional masking. for example: `[esi + eax * 4 + 0x1313]{k6}` RegIndexBaseScaleDispMasked(RegSpec, RegSpec, u8, i32, RegSpec), /// no operand. it is a bug for `yaxpeax-x86` to construct an `Operand` of this kind for public /// use; the instruction's `operand_count` should be reduced so as to make this invisible to /// library clients. Nothing, /// absolute far call. this is only used for `9a` far calls with absolute `u16:u{16,32}` /// operand, and so only exists in 32- and 16-bit modes. AbsoluteFarAddress { segment: u16, address: u32 }, } impl OperandSpec { fn masked(self) -> Self { match self { OperandSpec::RegRRR => OperandSpec::RegRRR_maskmerge, OperandSpec::RegMMM => OperandSpec::RegMMM_maskmerge, OperandSpec::RegVex => OperandSpec::RegVex_maskmerge, OperandSpec::Deref => OperandSpec::Deref_mask, OperandSpec::RegDisp => OperandSpec::RegDisp_mask, OperandSpec::RegScale => OperandSpec::RegScale_mask, OperandSpec::RegScaleDisp => OperandSpec::RegScaleDisp_mask, OperandSpec::RegIndexBaseScale => OperandSpec::RegIndexBaseScale_mask, OperandSpec::RegIndexBaseScaleDisp => OperandSpec::RegIndexBaseScaleDisp_mask, o => o, } } fn is_memory(&self) -> bool { (*self as u8) & 0x80 != 0 } } /// an `avx512` merging mode. /// /// the behavior for non-`avx512` instructions is equivalent to `merge`. `zero` is only useful in /// conjunction with a mask register, where bits specified in the mask register correspond to /// unmodified items in the instruction's destination. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum MergeMode { Merge, Zero, } impl From for MergeMode { fn from(b: bool) -> Self { if b { MergeMode::Zero } else { MergeMode::Merge } } } /// an `avx512` custom rounding mode. #[derive(Debug, Copy, Clone, PartialEq, Eq)] pub enum SaeMode { RoundNearest, RoundDown, RoundUp, RoundZero, } const SAE_MODES: [SaeMode; 4] = [ SaeMode::RoundNearest, SaeMode::RoundDown, SaeMode::RoundUp, SaeMode::RoundZero, ]; impl SaeMode { /// a human-friendly label for this `SaeMode`: /// /// ``` /// use yaxpeax_x86::long_mode::SaeMode; /// /// assert_eq!(SaeMode::RoundNearest.label(), "{rne-sae}"); /// assert_eq!(SaeMode::RoundDown.label(), "{rd-sae}"); /// assert_eq!(SaeMode::RoundUp.label(), "{ru-sae}"); /// assert_eq!(SaeMode::RoundZero.label(), "{rz-sae}"); /// ``` pub fn label(&self) -> &'static str { match self { SaeMode::RoundNearest => "{rne-sae}", SaeMode::RoundDown => "{rd-sae}", SaeMode::RoundUp => "{ru-sae}", SaeMode::RoundZero => "{rz-sae}", } } fn from(l: bool, lp: bool) -> Self { let mut idx = 0; if l { idx |= 1; } if lp { idx |= 2; } SAE_MODES[idx] } } impl Operand { fn from_spec(inst: &Instruction, spec: OperandSpec) -> Operand { match spec { OperandSpec::Nothing => { Operand::Nothing } // the register in regs[0] OperandSpec::RegRRR => { Operand::Register(inst.regs[0]) } OperandSpec::RegRRR_maskmerge => { Operand::RegisterMaskMerge( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegRRR_maskmerge_sae => { Operand::RegisterMaskMergeSae( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), SaeMode::from(inst.prefixes.evex_unchecked().vex().l(), inst.prefixes.evex_unchecked().lp()), ) } OperandSpec::RegRRR_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[0], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } // the register in regs[1] (eg modrm mod bits were 11) OperandSpec::RegMMM => { Operand::Register(inst.regs[1]) } OperandSpec::RegMMM_maskmerge => { Operand::RegisterMaskMerge( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegMMM_maskmerge_sae_noround => { Operand::RegisterMaskMergeSaeNoround( inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::RegVex => { Operand::Register(inst.regs[3]) } OperandSpec::RegVex_maskmerge => { Operand::RegisterMaskMerge( inst.regs[3], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg()), MergeMode::from(inst.prefixes.evex_unchecked().merge()), ) } OperandSpec::Reg4 => { Operand::Register(RegSpec { num: inst.imm as u8, bank: inst.regs[3].bank }) } OperandSpec::ImmI8 => Operand::ImmediateI8(inst.imm as i8), OperandSpec::ImmU8 => Operand::ImmediateU8(inst.imm as u8), OperandSpec::ImmI16 => Operand::ImmediateI16(inst.imm as i16), OperandSpec::ImmU16 => Operand::ImmediateU16(inst.imm as u16), OperandSpec::ImmI32 => Operand::ImmediateI32(inst.imm as i32), OperandSpec::ImmInDispField => Operand::ImmediateU16(inst.disp as u16), OperandSpec::DispU16 => Operand::DisplacementU16(inst.disp as u16), OperandSpec::DispU32 => Operand::DisplacementU32(inst.disp), OperandSpec::Deref => { Operand::RegDeref(inst.regs[1]) } OperandSpec::Deref_si => { Operand::RegDeref(RegSpec::si()) } OperandSpec::Deref_di => { Operand::RegDeref(RegSpec::di()) } OperandSpec::Deref_esi => { Operand::RegDeref(RegSpec::esi()) } OperandSpec::Deref_edi => { Operand::RegDeref(RegSpec::edi()) } OperandSpec::RegDisp => { Operand::RegDisp(inst.regs[1], inst.disp as i32) } OperandSpec::RegScale => { Operand::RegScale(inst.regs[2], inst.scale) } OperandSpec::RegScaleDisp => { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::RegIndexBaseScale => { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } OperandSpec::RegIndexBaseScaleDisp => { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } OperandSpec::Deref_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDerefMasked(inst.regs[1], RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDeref(inst.regs[1]) } } OperandSpec::RegDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegDispMasked(inst.regs[1], inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegDisp(inst.regs[1], inst.disp as i32) } } OperandSpec::RegScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleMasked(inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScale(inst.regs[2], inst.scale) } } OperandSpec::RegScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegScaleDispMasked(inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegScaleDisp(inst.regs[2], inst.scale, inst.disp as i32) } } OperandSpec::RegIndexBaseScale_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleMasked(inst.regs[1], inst.regs[2], inst.scale, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScale(inst.regs[1], inst.regs[2], inst.scale) } } OperandSpec::RegIndexBaseScaleDisp_mask => { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Operand::RegIndexBaseScaleDispMasked(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32, RegSpec::mask(inst.prefixes.evex_unchecked().mask_reg())) } else { Operand::RegIndexBaseScaleDisp(inst.regs[1], inst.regs[2], inst.scale, inst.disp as i32) } } OperandSpec::AbsoluteFarAddress => { Operand::AbsoluteFarAddress { segment: inst.disp as u16, address: inst.imm as u32, } } } } /// returns `true` if this operand implies a memory access, `false` otherwise. /// /// notably, the `lea` instruction uses a memory operand without actually ever accessing /// memory. pub fn is_memory(&self) -> bool { match self { Operand::DisplacementU16(_) | Operand::DisplacementU32(_) | Operand::RegDeref(_) | Operand::RegDisp(_, _) | Operand::RegScale(_, _) | Operand::RegIndexBase(_, _) | Operand::RegIndexBaseDisp(_, _, _) | Operand::RegScaleDisp(_, _, _) | Operand::RegIndexBaseScale(_, _, _) | Operand::RegIndexBaseScaleDisp(_, _, _, _) | Operand::RegDerefMasked(_, _) | Operand::RegDispMasked(_, _, _) | Operand::RegScaleMasked(_, _, _) | Operand::RegIndexBaseMasked(_, _, _) | Operand::RegIndexBaseDispMasked(_, _, _, _) | Operand::RegScaleDispMasked(_, _, _, _) | Operand::RegIndexBaseScaleMasked(_, _, _, _) | Operand::RegIndexBaseScaleDispMasked(_, _, _, _, _) => { true }, Operand::ImmediateI8(_) | Operand::ImmediateU8(_) | Operand::ImmediateI16(_) | Operand::ImmediateU16(_) | Operand::ImmediateU32(_) | Operand::ImmediateI32(_) | Operand::Register(_) | Operand::RegisterMaskMerge(_, _, _) | Operand::RegisterMaskMergeSae(_, _, _, _) | Operand::RegisterMaskMergeSaeNoround(_, _, _) | Operand::AbsoluteFarAddress { .. } | Operand::Nothing => { false } } } /// return the width of this operand, in bytes. register widths are determined by the /// register's class. the widths of memory operands are recorded on the instruction this /// `Operand` came from; `None` here means the authoritative width is `instr.mem_size()`. pub fn width(&self) -> Option { match self { Operand::Register(reg) => { Some(reg.width()) } Operand::RegisterMaskMerge(reg, _, _) => { Some(reg.width()) } Operand::ImmediateI8(_) | Operand::ImmediateU8(_) => { Some(1) } Operand::ImmediateI16(_) | Operand::ImmediateU16(_) => { Some(2) } Operand::ImmediateI32(_) | Operand::ImmediateU32(_) => { Some(4) } // memory operands or `Nothing` _ => { None } } } } #[test] fn operand_size() { assert_eq!(core::mem::size_of::(), 1); assert_eq!(core::mem::size_of::(), 2); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 4); assert_eq!(core::mem::size_of::(), 8); // assert_eq!(core::mem::size_of::(), 4); // assert_eq!(core::mem::size_of::(), 40); } /// an `x86` register class - `qword`, `dword`, `xmmword`, `segment`, and so on. /// /// this is mostly useful for comparing a `RegSpec`'s [`RegSpec::class()`] with a constant out of /// [`register_class`]. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] pub struct RegisterClass { kind: RegisterBank, } const REGISTER_CLASS_NAMES: &[&'static str] = &[ "BUG. PLEASE REPORT", "byte", "word", "BUG. PLEASE REPORT", "dword", "cr", "dr", "segment", "xmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "ymm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "zmm", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "BUG. PLEASE REPORT.", "x87-stack", "mmx", "k", "eip", "eflags", ]; /// high-level register classes in an x86 machine, such as "2-byte general purpose", "xmm", "x87", /// and so on. constants in this module are useful for inspecting the register class of a decoded /// instruction. as an example: /// ``` /// use yaxpeax_x86::real_mode::{self as amd64}; /// use yaxpeax_x86::real_mode::{Opcode, Operand, RegisterClass}; /// use yaxpeax_arch::{Decoder, U8Reader}; /// /// let movsx_ax_cl = &[0x0f, 0xbe, 0xc1]; /// let decoder = amd64::InstDecoder::default(); /// let instruction = decoder /// .decode(&mut U8Reader::new(movsx_ax_cl)) /// .expect("can decode"); /// /// assert_eq!(instruction.opcode(), Opcode::MOVSX); /// /// fn show_register_class_info(regclass: RegisterClass) { /// match regclass { /// amd64::register_class::W => { /// println!(" and is a word register"); /// } /// amd64::register_class::B => { /// println!(" and is a byte register"); /// } /// other => { /// panic!("unexpected and invalid register class {:?}", other); /// } /// } /// } /// /// if let Operand::Register(regspec) = instruction.operand(0) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// /// if let Operand::Register(regspec) = instruction.operand(1) { /// #[cfg(feature="fmt")] /// println!("first operand is {}", regspec); /// show_register_class_info(regspec.class()); /// } /// ``` /// /// this is preferable to alternatives like checking register names against a known list: a /// register class is one byte and "is qword general-purpose" can then be a simple one-byte /// compare, instead of 16 string compares. /// /// `yaxpeax-x86` does not attempt to further distinguish between, for example, register /// suitability as operands. as an example, `cl` is only a byte register, with no additional /// register class to describe its use as an implicit shift operand. pub mod register_class { use super::{RegisterBank, RegisterClass}; /// doubleword registers: eax through edi. pub const D: RegisterClass = RegisterClass { kind: RegisterBank::D }; /// word registers: ax through di. pub const W: RegisterClass = RegisterClass { kind: RegisterBank::W }; /// byte registers: al, cl, dl, bl, ah, ch, dh, bh. pub const B: RegisterClass = RegisterClass { kind: RegisterBank::B }; /// control registers cr0 through cr7. pub const CR: RegisterClass = RegisterClass { kind: RegisterBank::CR}; /// debug registers dr0 through dr7. pub const DR: RegisterClass = RegisterClass { kind: RegisterBank::DR }; /// segment registers es, cs, ss, ds, fs, gs. pub const S: RegisterClass = RegisterClass { kind: RegisterBank::S }; /// xmm registers xmm0 through xmm31. pub const X: RegisterClass = RegisterClass { kind: RegisterBank::X }; /// ymm registers ymm0 through ymm31. pub const Y: RegisterClass = RegisterClass { kind: RegisterBank::Y }; /// zmm registers zmm0 through zmm31. pub const Z: RegisterClass = RegisterClass { kind: RegisterBank::Z }; /// x87 floating point stack entries st(0) through st(7). pub const ST: RegisterClass = RegisterClass { kind: RegisterBank::ST }; /// mmx registers mm0 through mm7. pub const MM: RegisterClass = RegisterClass { kind: RegisterBank::MM }; /// `AVX512` mask registers k0 through k7. pub const K: RegisterClass = RegisterClass { kind: RegisterBank::K }; /// the full instruction pointer register. pub const EIP: RegisterClass = RegisterClass { kind: RegisterBank::EIP }; /// the full cpu flags register. pub const EFLAGS: RegisterClass = RegisterClass { kind: RegisterBank::EFlags }; } impl RegisterClass { /// return a human-friendly name for this register class pub fn name(&self) -> &'static str { REGISTER_CLASS_NAMES[self.kind as usize] } /// return the size of this register class, in bytes pub fn width(&self) -> u8 { match self.kind { RegisterBank::D => 4, RegisterBank::W => 2, RegisterBank::B => 1, RegisterBank::CR | RegisterBank::DR => { 4 }, RegisterBank::S => { 2 }, RegisterBank::EIP => { 4 } RegisterBank::EFlags => { 4 } RegisterBank::X => { 16 } RegisterBank::Y => { 32 } RegisterBank::Z => { 64 } RegisterBank::ST => { 10 } RegisterBank::MM => { 8 } RegisterBank::K => { 8 } } } } #[allow(non_camel_case_types)] #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Copy, Clone, Debug, Ord, PartialOrd, Eq, PartialEq, Hash)] enum RegisterBank { D = 4, W = 2, B = 1, // Dword, Word, Byte CR = 5, DR = 6, S = 7, EIP = 23, EFlags = 24, // Control reg, Debug reg, Selector, ... X = 8, Y = 12, Z = 16, // XMM, YMM, ZMM ST = 20, MM = 21, // ST, MM regs (x87, mmx) K = 22, // AVX512 mask registers } /// the segment register used by the corresponding instruction. /// /// typically this will be `ds` but can be overridden. some instructions have specific segment /// registers used regardless of segment prefixes, and in these cases `yaxpeax-x86` will report the /// actual segment register a physical processor would use. #[derive(Copy, Clone, Debug, Eq, PartialEq, Hash)] pub enum Segment { DS = 0, CS, ES, FS, GS, SS } const BMI1: [Opcode; 6] = [ Opcode::ANDN, Opcode::BEXTR, Opcode::BLSI, Opcode::BLSMSK, Opcode::BLSR, Opcode::TZCNT, ]; const BMI2: [Opcode; 8] = [ Opcode::BZHI, Opcode::MULX, Opcode::PDEP, Opcode::PEXT, Opcode::RORX, Opcode::SARX, Opcode::SHRX, Opcode::SHLX, ]; #[allow(dead_code)] const XSAVE: [Opcode; 10] = [ Opcode::XGETBV, Opcode::XRSTOR, Opcode::XRSTORS, Opcode::XSAVE, Opcode::XSAVEC, Opcode::XSAVEC64, Opcode::XSAVEOPT, Opcode::XSAVES, Opcode::XSAVES64, Opcode::XSETBV, ]; #[allow(non_camel_case_types)] #[derive(Copy, Clone, Debug, Eq, PartialEq)] #[non_exhaustive] #[repr(u32)] pub enum Opcode { ADD = 0x1000, OR = 0x1001, ADC = 0x1002, SBB = 0x1003, AND = 0x1004, SUB = 0x1005, XOR = 0x1006, CMP = 7, ROL = 8, ROR, RCL, RCR, SHL, SHR, SAL, SAR = 0x0f, BTC = 0x1010, BTR = 0x1011, BTS = 0x1012, CMPXCHG = 0x1013, CMPXCHG8B = 0x1014, CMPXCHG16B = 0x1015, DEC = 0x1016, INC = 0x1017, NEG = 0x1018, NOT = 0x1019, XADD = 0x101a, XCHG = 0x101b, Invalid = 0x1c, // XADD, BT, // BTS, // BTC, // BTR, BSF, BSR, TZCNT, MOVSS, ADDSS, SUBSS, MULSS, DIVSS, MINSS, MAXSS, SQRTSS, MOVSD, SQRTSD, ADDSD, SUBSD, MULSD, DIVSD, MINSD, MAXSD, MOVSLDUP, MOVSHDUP, MOVDDUP, HADDPS, HSUBPS, ADDSUBPD, ADDSUBPS, CVTSI2SS, CVTSI2SD, CVTTSD2SI, CVTTPS2DQ, CVTPD2DQ, CVTPD2PS, CVTPS2DQ, CVTSD2SI, CVTSD2SS, CVTTSS2SI, CVTSS2SI, CVTSS2SD, CVTDQ2PD, LDDQU, MOVZX, MOVSX, MOVSXD, SHRD, // INC, // DEC, HLT, CALL, CALLF, JMP, JMPF, PUSH, POP, LEA, NOP, PREFETCHNTA, PREFETCH0, PREFETCH1, PREFETCH2, // XCHG, POPF, INT, INTO, IRET, IRETD, IRETQ, RETF, ENTER, LEAVE, MOV, RETURN, PUSHF, WAIT, CBW, CWDE, CDQE, CWD, CDQ, CQO, LODS, STOS, LAHF, SAHF, CMPS, SCAS, MOVS, TEST, INS, IN, OUTS, OUT, IMUL, JO, JNO, JB, JNB, JZ, JNZ, JA, JNA, JS, JNS, JP, JNP, JL, JGE, JLE, JG, CMOVA, CMOVB, CMOVG, CMOVGE, CMOVL, CMOVLE, CMOVNA, CMOVNB, CMOVNO, CMOVNP, CMOVNS, CMOVNZ, CMOVO, CMOVP, CMOVS, CMOVZ, DIV, IDIV, MUL, // NEG, // NOT, // CMPXCHG, SETO, SETNO, SETB, SETAE, SETZ, SETNZ, SETBE, SETA, SETS, SETNS, SETP, SETNP, SETL, SETGE, SETLE, SETG, CPUID, UD0, UD1, UD2, WBINVD, INVD, SYSRET, CLTS, SYSCALL, LSL, LAR, LES, LDS, SGDT, SIDT, LGDT, LIDT, SMSW, LMSW, SWAPGS, RDTSCP, INVLPG, FXSAVE, FXRSTOR, LDMXCSR, STMXCSR, XSAVE, XRSTOR, XSAVEOPT, LFENCE, MFENCE, SFENCE, CLFLUSH, CLFLUSHOPT, CLWB, WRMSR, RDTSC, RDMSR, RDPMC, SLDT, STR, LLDT, LTR, VERR, VERW, CMC, CLC, STC, CLI, STI, CLD, STD, JMPE, POPCNT, MOVDQU, MOVDQA, MOVQ, CMPSS, CMPSD, UNPCKLPS, UNPCKLPD, UNPCKHPS, UNPCKHPD, PSHUFHW, PSHUFLW, MOVUPS, MOVQ2DQ, MOVDQ2Q, RSQRTSS, RCPSS, ANDN, BEXTR, BLSI, BLSMSK, BLSR, VMCLEAR, VMXON, VMCALL, VMLAUNCH, VMRESUME, VMXOFF, PCONFIG, MONITOR, MWAIT, MONITORX, MWAITX, CLAC, STAC, ENCLS, ENCLV, XGETBV, XSETBV, VMFUNC, XABORT, XBEGIN, XEND, XTEST, ENCLU, RDPKRU, WRPKRU, RDPRU, CLZERO, RDSEED, RDRAND, ADDPS, ADDPD, ANDNPS, ANDNPD, ANDPS, ANDPD, BSWAP, CMPPD, CMPPS, COMISD, COMISS, CVTDQ2PS, CVTPI2PS, CVTPI2PD, CVTPS2PD, CVTPS2PI, CVTPD2PI, CVTTPS2PI, CVTTPD2PI, CVTTPD2DQ, DIVPS, DIVPD, EMMS, GETSEC, LFS, LGS, LSS, MASKMOVQ, MASKMOVDQU, MAXPS, MAXPD, MINPS, MINPD, MOVAPS, MOVAPD, MOVD, MOVLPS, MOVLPD, MOVHPS, MOVHPD, MOVLHPS, MOVHLPS, MOVUPD, MOVMSKPS, MOVMSKPD, MOVNTI, MOVNTPS, MOVNTPD, EXTRQ, INSERTQ, MOVNTSS, MOVNTSD, MOVNTQ, MOVNTDQ, MULPS, MULPD, ORPS, ORPD, PACKSSDW, PACKSSWB, PACKUSWB, PADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDW, PAND, PANDN, PAVGB, PAVGW, PCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTW, PINSRW, PMADDWD, PMAXSW, PMAXUB, PMINSW, PMINUB, PMOVMSKB, PMULHUW, PMULHW, PMULLW, PMULUDQ, POR, PSADBW, PSHUFW, PSHUFD, PSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW, PSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBW, PUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLWD, PUNPCKLQDQ, PUNPCKHQDQ, PXOR, RCPPS, RSM, RSQRTPS, SHLD, SHUFPD, SHUFPS, SLHD, SQRTPS, SQRTPD, SUBPS, SUBPD, SYSENTER, SYSEXIT, UCOMISD, UCOMISS, VMREAD, VMWRITE, XORPS, XORPD, VMOVDDUP, VPSHUFLW, VPSHUFHW, VHADDPS, VHSUBPS, VADDSUBPS, VCVTPD2DQ, VLDDQU, VCOMISD, VCOMISS, VUCOMISD, VUCOMISS, VADDPD, VADDPS, VADDSD, VADDSS, VADDSUBPD, VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VAESIMC, VAESKEYGENASSIST, VBLENDPD, VBLENDPS, VBLENDVPD, VBLENDVPS, VBROADCASTF128, VBROADCASTI128, VBROADCASTSD, VBROADCASTSS, VCMPSD, VCMPSS, VCMPPD, VCMPPS, VCVTDQ2PD, VCVTDQ2PS, VCVTPD2PS, VCVTPH2PS, VCVTPS2DQ, VCVTPS2PD, VCVTSS2SD, VCVTSI2SS, VCVTSI2SD, VCVTSD2SI, VCVTSD2SS, VCVTPS2PH, VCVTSS2SI, VCVTTPD2DQ, VCVTTPS2DQ, VCVTTSS2SI, VCVTTSD2SI, VDIVPD, VDIVPS, VDIVSD, VDIVSS, VDPPD, VDPPS, VEXTRACTF128, VEXTRACTI128, VEXTRACTPS, VFMADD132PD, VFMADD132PS, VFMADD132SD, VFMADD132SS, VFMADD213PD, VFMADD213PS, VFMADD213SD, VFMADD213SS, VFMADD231PD, VFMADD231PS, VFMADD231SD, VFMADD231SS, VFMADDSUB132PD, VFMADDSUB132PS, VFMADDSUB213PD, VFMADDSUB213PS, VFMADDSUB231PD, VFMADDSUB231PS, VFMSUB132PD, VFMSUB132PS, VFMSUB132SD, VFMSUB132SS, VFMSUB213PD, VFMSUB213PS, VFMSUB213SD, VFMSUB213SS, VFMSUB231PD, VFMSUB231PS, VFMSUB231SD, VFMSUB231SS, VFMSUBADD132PD, VFMSUBADD132PS, VFMSUBADD213PD, VFMSUBADD213PS, VFMSUBADD231PD, VFMSUBADD231PS, VFNMADD132PD, VFNMADD132PS, VFNMADD132SD, VFNMADD132SS, VFNMADD213PD, VFNMADD213PS, VFNMADD213SD, VFNMADD213SS, VFNMADD231PD, VFNMADD231PS, VFNMADD231SD, VFNMADD231SS, VFNMSUB132PD, VFNMSUB132PS, VFNMSUB132SD, VFNMSUB132SS, VFNMSUB213PD, VFNMSUB213PS, VFNMSUB213SD, VFNMSUB213SS, VFNMSUB231PD, VFNMSUB231PS, VFNMSUB231SD, VFNMSUB231SS, VGATHERDPD, VGATHERDPS, VGATHERQPD, VGATHERQPS, VHADDPD, VHSUBPD, VINSERTF128, VINSERTI128, VINSERTPS, VMASKMOVDQU, VMASKMOVPD, VMASKMOVPS, VMAXPD, VMAXPS, VMAXSD, VMAXSS, VMINPD, VMINPS, VMINSD, VMINSS, VMOVAPD, VMOVAPS, VMOVD, VMOVDQA, VMOVDQU, VMOVHLPS, VMOVHPD, VMOVHPS, VMOVLHPS, VMOVLPD, VMOVLPS, VMOVMSKPD, VMOVMSKPS, VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVNTPS, VMOVQ, VMOVSS, VMOVSD, VMOVSHDUP, VMOVSLDUP, VMOVUPD, VMOVUPS, VMPSADBW, VMULPD, VMULPS, VMULSD, VMULSS, VPABSB, VPABSD, VPABSW, VPACKSSDW, VPACKUSDW, VPACKSSWB, VPACKUSWB, VPADDB, VPADDD, VPADDQ, VPADDSB, VPADDSW, VPADDUSB, VPADDUSW, VPADDW, VPALIGNR, VANDPD, VANDPS, VORPD, VORPS, VANDNPD, VANDNPS, VPAND, VPANDN, VPAVGB, VPAVGW, VPBLENDD, VPBLENDVB, VPBLENDW, VPBROADCASTB, VPBROADCASTD, VPBROADCASTQ, VPBROADCASTW, VPCLMULQDQ, VPCMPEQB, VPCMPEQD, VPCMPEQQ, VPCMPEQW, VPCMPGTB, VPCMPGTD, VPCMPGTQ, VPCMPGTW, VPCMPESTRI, VPCMPESTRM, VPCMPISTRI, VPCMPISTRM, VPERM2F128, VPERM2I128, VPERMD, VPERMILPD, VPERMILPS, VPERMPD, VPERMPS, VPERMQ, VPEXTRB, VPEXTRD, VPEXTRQ, VPEXTRW, VPGATHERDD, VPGATHERDQ, VPGATHERQD, VPGATHERQQ, VPHADDD, VPHADDSW, VPHADDW, VPMADDUBSW, VPHMINPOSUW, VPHSUBD, VPHSUBSW, VPHSUBW, VPINSRB, VPINSRD, VPINSRQ, VPINSRW, VPMADDWD, VPMASKMOVD, VPMASKMOVQ, VPMAXSB, VPMAXSD, VPMAXSW, VPMAXUB, VPMAXUW, VPMAXUD, VPMINSB, VPMINSW, VPMINSD, VPMINUB, VPMINUW, VPMINUD, VPMOVMSKB, VPMOVSXBD, VPMOVSXBQ, VPMOVSXBW, VPMOVSXDQ, VPMOVSXWD, VPMOVSXWQ, VPMOVZXBD, VPMOVZXBQ, VPMOVZXBW, VPMOVZXDQ, VPMOVZXWD, VPMOVZXWQ, VPMULDQ, VPMULHRSW, VPMULHUW, VPMULHW, VPMULLQ, VPMULLD, VPMULLW, VPMULUDQ, VPOR, VPSADBW, VPSHUFB, VPSHUFD, VPSIGNB, VPSIGND, VPSIGNW, VPSLLD, VPSLLDQ, VPSLLQ, VPSLLVD, VPSLLVQ, VPSLLW, VPSRAD, VPSRAVD, VPSRAW, VPSRLD, VPSRLDQ, VPSRLQ, VPSRLVD, VPSRLVQ, VPSRLW, VPSUBB, VPSUBD, VPSUBQ, VPSUBSB, VPSUBSW, VPSUBUSB, VPSUBUSW, VPSUBW, VPTEST, VPUNPCKHBW, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLDQ, VPUNPCKLQDQ, VPUNPCKLWD, VPXOR, VRCPPS, VROUNDPD, VROUNDPS, VROUNDSD, VROUNDSS, VRSQRTPS, VRSQRTSS, VRCPSS, VSHUFPD, VSHUFPS, VSQRTPD, VSQRTPS, VSQRTSS, VSQRTSD, VSUBPD, VSUBPS, VSUBSD, VSUBSS, VTESTPD, VTESTPS, VUNPCKHPD, VUNPCKHPS, VUNPCKLPD, VUNPCKLPS, VXORPD, VXORPS, VZEROUPPER, VZEROALL, VLDMXCSR, VSTMXCSR, PCLMULQDQ, AESKEYGENASSIST, AESIMC, AESENC, AESENCLAST, AESDEC, AESDECLAST, PCMPGTQ, PCMPISTRM, PCMPISTRI, PCMPESTRI, PACKUSDW, PCMPESTRM, PCMPEQQ, PTEST, PHMINPOSUW, DPPS, DPPD, MPSADBW, PMOVZXDQ, PMOVSXDQ, PMOVZXBD, PMOVSXBD, PMOVZXWQ, PMOVSXWQ, PMOVZXBQ, PMOVSXBQ, PMOVSXWD, PMOVZXWD, PEXTRQ, PEXTRD, PEXTRW, PEXTRB, PMOVSXBW, PMOVZXBW, PINSRQ, PINSRD, PINSRB, EXTRACTPS, INSERTPS, ROUNDSS, ROUNDSD, ROUNDPS, ROUNDPD, PMAXSB, PMAXSD, PMAXUW, PMAXUD, PMINSD, PMINSB, PMINUD, PMINUW, BLENDW, PBLENDVB, PBLENDW, BLENDVPS, BLENDVPD, BLENDPS, BLENDPD, PMULDQ, MOVNTDQA, PMULLD, PALIGNR, PSIGNW, PSIGND, PSIGNB, PSHUFB, PMULHRSW, PMADDUBSW, PABSD, PABSW, PABSB, PHSUBSW, PHSUBW, PHSUBD, PHADDD, PHADDSW, PHADDW, HSUBPD, HADDPD, SHA1RNDS4, SHA1NEXTE, SHA1MSG1, SHA1MSG2, SHA256RNDS2, SHA256MSG1, SHA256MSG2, LZCNT, CLGI, STGI, SKINIT, VMLOAD, VMMCALL, VMSAVE, VMRUN, INVLPGA, INVLPGB, TLBSYNC, MOVBE, ADCX, ADOX, PREFETCHW, RDPID, // CMPXCHG8B, // CMPXCHG16B, VMPTRLD, VMPTRST, BZHI, MULX, SHLX, SHRX, SARX, PDEP, PEXT, RORX, XRSTORS, XRSTORS64, XSAVEC, XSAVEC64, XSAVES, XSAVES64, RDFSBASE, RDGSBASE, WRFSBASE, WRGSBASE, CRC32, SALC, XLAT, F2XM1, FABS, FADD, FADDP, FBLD, FBSTP, FCHS, FCMOVB, FCMOVBE, FCMOVE, FCMOVNB, FCMOVNBE, FCMOVNE, FCMOVNU, FCMOVU, FCOM, FCOMI, FCOMIP, FCOMP, FCOMPP, FCOS, FDECSTP, FDISI8087_NOP, FDIV, FDIVP, FDIVR, FDIVRP, FENI8087_NOP, FFREE, FFREEP, FIADD, FICOM, FICOMP, FIDIV, FIDIVR, FILD, FIMUL, FINCSTP, FIST, FISTP, FISTTP, FISUB, FISUBR, FLD, FLD1, FLDCW, FLDENV, FLDL2E, FLDL2T, FLDLG2, FLDLN2, FLDPI, FLDZ, FMUL, FMULP, FNCLEX, FNINIT, FNOP, FNSAVE, FNSTCW, FNSTENV, FNSTOR, FNSTSW, FPATAN, FPREM, FPREM1, FPTAN, FRNDINT, FRSTOR, FSCALE, FSETPM287_NOP, FSIN, FSINCOS, FSQRT, FST, FSTP, FSTPNCE, FSUB, FSUBP, FSUBR, FSUBRP, FTST, FUCOM, FUCOMI, FUCOMIP, FUCOMP, FUCOMPP, FXAM, FXCH, FXTRACT, FYL2X, FYL2XP1, LOOPNZ, LOOPZ, LOOP, JCXZ, PUSHA, POPA, BOUND, ARPL, AAS, AAA, DAS, DAA, AAM, AAD, // started shipping in Tremont, 2020 sept 23 MOVDIR64B, MOVDIRI, // started shipping in Tiger Lake, 2020 sept 2 AESDEC128KL, AESDEC256KL, AESDECWIDE128KL, AESDECWIDE256KL, AESENC128KL, AESENC256KL, AESENCWIDE128KL, AESENCWIDE256KL, ENCODEKEY128, ENCODEKEY256, LOADIWKEY, // unsure HRESET, // 3dnow FEMMS, PI2FW, PI2FD, PF2IW, PF2ID, PMULHRW, PFCMPGE, PFMIN, PFRCP, PFRSQRT, PFSUB, PFADD, PFCMPGT, PFMAX, PFRCPIT1, PFRSQIT1, PFSUBR, PFACC, PFCMPEQ, PFMUL, PFMULHRW, PFRCPIT2, PFNACC, PFPNACC, PSWAPD, PAVGUSB, // ENQCMD ENQCMD, ENQCMDS, // INVPCID INVEPT, INVVPID, INVPCID, // PTWRITE PTWRITE, // GFNI GF2P8AFFINEQB, GF2P8AFFINEINVQB, GF2P8MULB, // CET WRUSS, WRSS, INCSSP, SAVEPREVSSP, SETSSBSY, CLRSSBSY, RSTORSSP, ENDBR64, ENDBR32, // TDX TDCALL, SEAMRET, SEAMOPS, SEAMCALL, // WAITPKG TPAUSE, UMONITOR, UMWAIT, // UINTR UIRET, TESTUI, CLUI, STUI, SENDUIPI, // TSXLDTRK XSUSLDTRK, XRESLDTRK, // AVX512F VALIGND, VALIGNQ, VBLENDMPD, VBLENDMPS, VCOMPRESSPD, VCOMPRESSPS, VCVTPD2UDQ, VCVTTPD2UDQ, VCVTPS2UDQ, VCVTTPS2UDQ, VCVTQQ2PD, VCVTQQ2PS, VCVTSD2USI, VCVTTSD2USI, VCVTSS2USI, VCVTTSS2USI, VCVTUDQ2PD, VCVTUDQ2PS, VCVTUSI2USD, VCVTUSI2USS, VEXPANDPD, VEXPANDPS, VEXTRACTF32X4, VEXTRACTF64X4, VEXTRACTI32X4, VEXTRACTI64X4, VFIXUPIMMPD, VFIXUPIMMPS, VFIXUPIMMSD, VFIXUPIMMSS, VGETEXPPD, VGETEXPPS, VGETEXPSD, VGETEXPSS, VGETMANTPD, VGETMANTPS, VGETMANTSD, VGETMANTSS, VINSERTF32X4, VINSERTF64X4, VINSERTI64X4, VMOVDQA32, VMOVDQA64, VMOVDQU32, VMOVDQU64, VPBLENDMD, VPBLENDMQ, VPCMPD, VPCMPUD, VPCMPQ, VPCMPUQ, VPCOMPRESSQ, VPCOMPRESSD, VPERMI2D, VPERMI2Q, VPERMI2PD, VPERMI2PS, VPERMT2D, VPERMT2Q, VPERMT2PD, VPERMT2PS, VPMAXSQ, VPMAXUQ, VPMINSQ, VPMINUQ, VPMOVSQB, VPMOVUSQB, VPMOVSQW, VPMOVUSQW, VPMOVSQD, VPMOVUSQD, VPMOVSDB, VPMOVUSDB, VPMOVSDW, VPMOVUSDW, VPROLD, VPROLQ, VPROLVD, VPROLVQ, VPRORD, VPRORQ, VPRORRD, VPRORRQ, VPSCATTERDD, VPSCATTERDQ, VPSCATTERQD, VPSCATTERQQ, VPSRAQ, VPSRAVQ, VPTESTNMD, VPTESTNMQ, VPTERNLOGD, VPTERNLOGQ, VPTESTMD, VPTESTMQ, VRCP14PD, VRCP14PS, VRCP14SD, VRCP14SS, VRNDSCALEPD, VRNDSCALEPS, VRNDSCALESD, VRNDSCALESS, VRSQRT14PD, VRSQRT14PS, VRSQRT14SD, VRSQRT14SS, VSCALEDPD, VSCALEDPS, VSCALEDSD, VSCALEDSS, VSCATTERDD, VSCATTERDQ, VSCATTERQD, VSCATTERQQ, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2, // AVX512DQ VCVTTPD2QQ, VCVTPD2QQ, VCVTTPD2UQQ, VCVTPD2UQQ, VCVTTPS2QQ, VCVTPS2QQ, VCVTTPS2UQQ, VCVTPS2UQQ, VCVTUQQ2PD, VCVTUQQ2PS, VEXTRACTF64X2, VEXTRACTI64X2, VFPCLASSPD, VFPCLASSPS, VFPCLASSSD, VFPCLASSSS, VINSERTF64X2, VINSERTI64X2, VPMOVM2D, VPMOVM2Q, VPMOVB2D, VPMOVQ2M, VRANGEPD, VRANGEPS, VRANGESD, VRANGESS, VREDUCEPD, VREDUCEPS, VREDUCESD, VREDUCESS, // AVX512BW VDBPSADBW, VMOVDQU8, VMOVDQU16, VPBLENDMB, VPBLENDMW, VPCMPB, VPCMPUB, VPCMPW, VPCMPUW, VPERMW, VPERMI2B, VPERMI2W, VPMOVM2B, VPMOVM2W, VPMOVB2M, VPMOVW2M, VPMOVSWB, VPMOVUSWB, VPSLLVW, VPSRAVW, VPSRLVW, VPTESTNMB, VPTESTNMW, VPTESTMB, VPTESTMW, // AVX512CD VPBROADCASTM, VPCONFLICTD, VPCONFLICTQ, VPLZCNTD, VPLZCNTQ, KUNPCKBW, KUNPCKWD, KUNPCKDQ, KADDB, KANDB, KANDNB, KMOVB, KNOTB, KORB, KORTESTB, KSHIFTLB, KSHIFTRB, KTESTB, KXNORB, KXORB, KADDW, KANDW, KANDNW, KMOVW, KNOTW, KORW, KORTESTW, KSHIFTLW, KSHIFTRW, KTESTW, KXNORW, KXORW, KADDD, KANDD, KANDND, KMOVD, KNOTD, KORD, KORTESTD, KSHIFTLD, KSHIFTRD, KTESTD, KXNORD, KXORD, KADDQ, KANDQ, KANDNQ, KMOVQ, KNOTQ, KORQ, KORTESTQ, KSHIFTLQ, KSHIFTRQ, KTESTQ, KXNORQ, KXORQ, // AVX512ER VEXP2PD, VEXP2PS, VEXP2SD, VEXP2SS, VRCP28PD, VRCP28PS, VRCP28SD, VRCP28SS, VRSQRT28PD, VRSQRT28PS, VRSQRT28SD, VRSQRT28SS, // AVX512PF VGATHERPF0DPD, VGATHERPF0DPS, VGATHERPF0QPD, VGATHERPF0QPS, VGATHERPF1DPD, VGATHERPF1DPS, VGATHERPF1QPD, VGATHERPF1QPS, VSCATTERPF0DPD, VSCATTERPF0DPS, VSCATTERPF0QPD, VSCATTERPF0QPS, VSCATTERPF1DPD, VSCATTERPF1DPS, VSCATTERPF1QPD, VSCATTERPF1QPS, // MPX BNDMK, BNDCL, BNDCU, BNDCN, BNDMOV, BNDLDX, BNDSTX, VGF2P8AFFINEQB, VGF2P8AFFINEINVQB, VPSHRDQ, VPSHRDD, VPSHRDW, VPSHLDQ, VPSHLDD, VPSHLDW, VBROADCASTF32X8, VBROADCASTF64X4, VBROADCASTF32X4, VBROADCASTF64X2, VBROADCASTF32X2, VBROADCASTI32X8, VBROADCASTI64X4, VBROADCASTI32X4, VBROADCASTI64X2, VBROADCASTI32X2, VEXTRACTI32X8, VEXTRACTF32X8, VINSERTI32X8, VINSERTF32X8, VINSERTI32X4, V4FNMADDSS, V4FNMADDPS, VCVTNEPS2BF16, V4FMADDSS, V4FMADDPS, VCVTNE2PS2BF16, VP2INTERSECTD, VP2INTERSECTQ, VP4DPWSSDS, VP4DPWSSD, VPDPWSSDS, VPDPWSSD, VPDPBUSDS, VDPBF16PS, VPBROADCASTMW2D, VPBROADCASTMB2Q, VPMOVD2M, VPMOVQD, VPMOVWB, VPMOVDB, VPMOVDW, VPMOVQB, VPMOVQW, VGF2P8MULB, VPMADD52HUQ, VPMADD52LUQ, VPSHUFBITQMB, VPERMB, VPEXPANDD, VPEXPANDQ, VPABSQ, VPRORVD, VPRORVQ, VPMULTISHIFTQB, VPERMT2B, VPERMT2W, VPSHRDVQ, VPSHRDVD, VPSHRDVW, VPSHLDVQ, VPSHLDVD, VPSHLDVW, VPCOMPRESSB, VPCOMPRESSW, VPEXPANDB, VPEXPANDW, VPOPCNTD, VPOPCNTQ, VPOPCNTB, VPOPCNTW, VSCALEFSS, VSCALEFSD, VSCALEFPS, VSCALEFPD, VPDPBUSD, VCVTUSI2SD, VCVTUSI2SS, VPXORD, VPXORQ, VPORD, VPORQ, VPANDND, VPANDNQ, VPANDD, VPANDQ, PSMASH, PVALIDATE, RMPADJUST, RMPUPDATE, } impl PartialEq for Instruction { fn eq(&self, other: &Self) -> bool { if self.prefixes != other.prefixes { return false; } if self.opcode != other.opcode { return false; } if self.operand_count != other.operand_count { return false; } if self.mem_size != other.mem_size { return false; } for i in 0..self.operand_count { if self.operands[i as usize] != other.operands[i as usize] { return false; } if self.operand(i) != other.operand(i) { return false; } } true } } /// an `x86` instruction. /// /// typically an opcode will be inspected by [`Instruction::opcode()`], and an instruction has /// [`Instruction::operand_count()`] many operands. operands are provided by /// [`Instruction::operand()`]. #[derive(Debug, Clone, Copy, Eq)] pub struct Instruction { pub prefixes: Prefixes, regs: [RegSpec; 4], scale: u8, length: u8, operand_count: u8, operands: [OperandSpec; 4], imm: u32, disp: u32, opcode: Opcode, mem_size: u8, } impl yaxpeax_arch::Instruction for Instruction { fn well_defined(&self) -> bool { // TODO: this is incorrect! true } } #[derive(Debug, PartialEq, Eq, Copy, Clone)] #[non_exhaustive] pub enum DecodeError { ExhaustedInput, InvalidOpcode, InvalidOperand, InvalidPrefixes, TooLong, IncompleteDecoder, } impl yaxpeax_arch::DecodeError for DecodeError { fn data_exhausted(&self) -> bool { self == &DecodeError::ExhaustedInput } fn bad_opcode(&self) -> bool { self == &DecodeError::InvalidOpcode } fn bad_operand(&self) -> bool { self == &DecodeError::InvalidOperand } fn description(&self) -> &'static str { match self { DecodeError::ExhaustedInput => { "exhausted input" }, DecodeError::InvalidOpcode => { "invalid opcode" }, DecodeError::InvalidOperand => { "invalid operand" }, DecodeError::InvalidPrefixes => { "invalid prefixes" }, DecodeError::TooLong => { "too long" }, DecodeError::IncompleteDecoder => { "the decoder is incomplete" }, } } } #[cfg(feature = "std")] extern crate std; #[cfg(feature = "std")] impl std::error::Error for DecodeError { fn description(&self) -> &str { ::description(self) } } #[allow(non_camel_case_types)] #[derive(Debug, Copy, Clone, Eq, PartialEq)] enum OperandSpec { Nothing = 0, // the register in regs[0] RegRRR = 0x01, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed) RegRRR_maskmerge = 0x41, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed with a potentially // custom rounding mode. RegRRR_maskmerge_sae = 0x58, // the register in regs[0] and is EVEX-encoded (may have a mask register, is merged or // zeroed). additionally, this instruction has exceptions suppressed. RegRRR_maskmerge_sae_noround = 0x59, // the register in modrm_mmm (eg modrm mod bits were 11) RegMMM = 0x02, // same as `RegRRR`: the register is modrm's `mmm` bits, and may be masked. RegMMM_maskmerge = 0x42, RegMMM_maskmerge_sae_noround = 0x5a, // the register selected by vex-vvvv bits RegVex = 0x03, RegVex_maskmerge = 0x43, // the register selected by a handful of avx2 vex-coded instructions, // stuffed in imm4. Reg4 = 0x04, ImmI8 = 0x05, ImmI16 = 0x06, ImmI32 = 0x07, // ImmI64 = 0x08, not in 64b ImmU8 = 0x09, ImmU16 = 0x0a, // ENTER is a two-immediate instruction, where the first immediate is stored in the disp field. // for this case, a second immediate-style operand is needed. // turns out `insertq` and `extrq` are also two-immediate instructions, so this is generalized // to cover them too. ImmInDispField = 0x0b, DispU16 = 0x8c, DispU32 = 0x8d, Deref = 0x8e, Deref_si = 0x8f, Deref_di = 0x90, Deref_esi = 0x91, Deref_edi = 0x92, RegDisp = 0x93, RegScale = 0x94, RegScaleDisp = 0x95, RegIndexBaseScale = 0x96, RegIndexBaseScaleDisp = 0x97, Deref_mask = 0xce, RegDisp_mask = 0xd3, RegScale_mask = 0xd4, RegScaleDisp_mask = 0xd5, RegIndexBaseScale_mask = 0xd6, RegIndexBaseScaleDisp_mask = 0xd7, // u16:u{16,32} immediate address for a far call AbsoluteFarAddress = 0x98, } // the Hash, Eq, and PartialEq impls here are possibly misleading. // They exist because downstream some structs are spelled like // Foo for T == x86. This is only to access associated types // which themselves are bounded, but their #[derive] require T to // implement these traits. /// a trivial struct for `yaxpeax_arch::Arch` to be implemented on. it's only interesting for the /// associated type parameters. #[cfg_attr(feature="use-serde", derive(Serialize, Deserialize))] #[derive(Hash, Eq, PartialEq, Debug, Copy, Clone)] #[allow(non_camel_case_types)] pub struct Arch; impl yaxpeax_arch::Arch for Arch { type Address = u32; type Word = u8; type Instruction = Instruction; type DecodeError = DecodeError; type Decoder = InstDecoder; type Operand = Operand; } impl LengthedInstruction for Instruction { type Unit = AddressDiff; #[inline] fn len(&self) -> Self::Unit { AddressDiff::from_const(self.length.into()) } #[inline] fn min_size() -> Self::Unit { AddressDiff::from_const(1) } } /// an `x86` instruction decoder. /// /// fundamentally this is one or two primitives with no additional state kept during decoding. it /// can be copied cheaply, hashed cheaply, compared cheaply. if you really want to share an /// `InstDecoder` between threads, you could - but you might want to clone it instead. /// /// unless you're using an `Arc>`, which is _fine_ but i'd be very curious about /// the design requiring that. #[derive(PartialEq, Copy, Clone, Eq, Hash, PartialOrd, Ord)] pub struct InstDecoder { // extensions tracked here: // 0. SSE3 // 1. SSSE3 // 2. monitor (intel-only?) // 3. vmx (some atom chips still lack it) // 4. fma3 (intel haswell/broadwell+, amd piledriver+) // 5. cmpxchg16b (some amd are missing this one) // 6. sse4.1 // 7. sse4.2 // 8. movbe // 9. popcnt (independent of BMI) // 10. aesni // 11. xsave (xsave, xrestor, xsetbv, xgetbv) // 12. rdrand (intel ivybridge+, amd ..??) // 13. sgx (eadd, eblock, ecreate, edbgrd, edbgwr, einit, eldb, eldu, epa, eremove, etrace, // ewb, eenter, eexit, egetkey, ereport, eresume) // 14. bmi1 (intel haswell+, amd jaguar+) // 15. avx2 (intel haswell+, amd excavator+) // 16. bmi2 (intel ?, amd ?) // 17. invpcid // 18. mpx // 19. avx512_f // 20. avx512_dq // 21. rdseed // 22. adx // 23. avx512_fma // 24. pcommit // 25. clflushopt // 26. clwb // 27. avx512_pf // 28. avx512_er // 29. avx512_cd // 30. sha // 31. avx512_bw // 32. avx512_vl // 33. prefetchwt1 // 34. avx512_vbmi // 35. avx512_vbmi2 // 36. gfni (galois field instructions) // 37. vaes // 38. pclmulqdq // 39. avx_vnni // 40. avx512_bitalg // 41. avx512_vpopcntdq // 42. avx512_4vnniw // 43. avx512_4fmaps // 44. cx8 // cmpxchg8 - is this actually optional in x86? // 45. syscall // syscall/sysret - actually optional in x86? // 46. rdtscp // actually optional in x86? // 47. abm (lzcnt, popcnt) // 48. sse4a // 49. 3dnowprefetch // actually optional? // 50. xop // 51. skinit // 52. tbm // 53. intel quirks // 54. amd quirks // 55. avx (intel ?, amd ?) // 56. amd-v/svm // 57. lahfsahf // 58. cmov // 59. f16c // 60. fma4 // 61. prefetchw // 62. tsx // 63. lzcnt flags: u64, } impl InstDecoder { /// instantiates an x86 decoder that decodes the bare minimum of real-mode x86. /// /// pedantic and only decodes what the spec says is well-defined, rejecting undefined sequences /// and any instructions defined by extensions. pub fn minimal() -> Self { InstDecoder { flags: 0, } } /// helper to decode an instruction directly from a byte slice. /// /// this lets callers avoid the work of setting up a [`yaxpeax_arch::U8Reader`] for the slice /// to decode. pub fn decode_slice(&self, data: &[u8]) -> Result { let mut reader = yaxpeax_arch::U8Reader::new(data); self.decode(&mut reader) } pub fn sse3(&self) -> bool { self.flags & (1 << 0) != 0 } pub fn with_sse3(mut self) -> Self { self.flags |= 1 << 0; self } pub fn ssse3(&self) -> bool { self.flags & (1 << 1) != 0 } pub fn with_ssse3(mut self) -> Self { self.flags |= 1 << 1; self } pub fn monitor(&self) -> bool { self.flags & (1 << 2) != 0 } pub fn with_monitor(mut self) -> Self { self.flags |= 1 << 2; self } pub fn vmx(&self) -> bool { self.flags & (1 << 3) != 0 } pub fn with_vmx(mut self) -> Self { self.flags |= 1 << 3; self } pub fn fma3(&self) -> bool { self.flags & (1 << 4) != 0 } pub fn with_fma3(mut self) -> Self { self.flags |= 1 << 4; self } pub fn cmpxchg16b(&self) -> bool { self.flags & (1 << 5) != 0 } pub fn with_cmpxchg16b(mut self) -> Self { self.flags |= 1 << 5; self } pub fn sse4_1(&self) -> bool { self.flags & (1 << 6) != 0 } pub fn with_sse4_1(mut self) -> Self { self.flags |= 1 << 6; self } pub fn sse4_2(&self) -> bool { self.flags & (1 << 7) != 0 } pub fn with_sse4_2(mut self) -> Self { self.flags |= 1 << 7; self } pub fn with_sse4(self) -> Self { self .with_sse4_1() .with_sse4_2() } pub fn movbe(&self) -> bool { self.flags & (1 << 8) != 0 } pub fn with_movbe(mut self) -> Self { self.flags |= 1 << 8; self } pub fn popcnt(&self) -> bool { self.flags & (1 << 9) != 0 } pub fn with_popcnt(mut self) -> Self { self.flags |= 1 << 9; self } pub fn aesni(&self) -> bool { self.flags & (1 << 10) != 0 } pub fn with_aesni(mut self) -> Self { self.flags |= 1 << 10; self } pub fn xsave(&self) -> bool { self.flags & (1 << 11) != 0 } pub fn with_xsave(mut self) -> Self { self.flags |= 1 << 11; self } pub fn rdrand(&self) -> bool { self.flags & (1 << 12) != 0 } pub fn with_rdrand(mut self) -> Self { self.flags |= 1 << 12; self } pub fn sgx(&self) -> bool { self.flags & (1 << 13) != 0 } pub fn with_sgx(mut self) -> Self { self.flags |= 1 << 13; self } pub fn bmi1(&self) -> bool { self.flags & (1 << 14) != 0 } pub fn with_bmi1(mut self) -> Self { self.flags |= 1 << 14; self } pub fn avx2(&self) -> bool { self.flags & (1 << 15) != 0 } pub fn with_avx2(mut self) -> Self { self.flags |= 1 << 15; self } /// `bmi2` indicates support for the `BZHI`, `MULX`, `PDEP`, `PEXT`, `RORX`, `SARX`, `SHRX`, /// and `SHLX` instructions. `bmi2` is implemented in all x86 chips that implement `bmi`, /// except the amd `piledriver` and `steamroller` microarchitectures. pub fn bmi2(&self) -> bool { self.flags & (1 << 16) != 0 } pub fn with_bmi2(mut self) -> Self { self.flags |= 1 << 16; self } pub fn invpcid(&self) -> bool { self.flags & (1 << 17) != 0 } pub fn with_invpcid(mut self) -> Self { self.flags |= 1 << 17; self } pub fn mpx(&self) -> bool { self.flags & (1 << 18) != 0 } pub fn with_mpx(mut self) -> Self { self.flags |= 1 << 18; self } pub fn avx512_f(&self) -> bool { self.flags & (1 << 19) != 0 } pub fn with_avx512_f(mut self) -> Self { self.flags |= 1 << 19; self } pub fn avx512_dq(&self) -> bool { self.flags & (1 << 20) != 0 } pub fn with_avx512_dq(mut self) -> Self { self.flags |= 1 << 20; self } pub fn rdseed(&self) -> bool { self.flags & (1 << 21) != 0 } pub fn with_rdseed(mut self) -> Self { self.flags |= 1 << 21; self } pub fn adx(&self) -> bool { self.flags & (1 << 22) != 0 } pub fn with_adx(mut self) -> Self { self.flags |= 1 << 22; self } pub fn avx512_fma(&self) -> bool { self.flags & (1 << 23) != 0 } pub fn with_avx512_fma(mut self) -> Self { self.flags |= 1 << 23; self } pub fn pcommit(&self) -> bool { self.flags & (1 << 24) != 0 } pub fn with_pcommit(mut self) -> Self { self.flags |= 1 << 24; self } pub fn clflushopt(&self) -> bool { self.flags & (1 << 25) != 0 } pub fn with_clflushopt(mut self) -> Self { self.flags |= 1 << 25; self } pub fn clwb(&self) -> bool { self.flags & (1 << 26) != 0 } pub fn with_clwb(mut self) -> Self { self.flags |= 1 << 26; self } pub fn avx512_pf(&self) -> bool { self.flags & (1 << 27) != 0 } pub fn with_avx512_pf(mut self) -> Self { self.flags |= 1 << 27; self } pub fn avx512_er(&self) -> bool { self.flags & (1 << 28) != 0 } pub fn with_avx512_er(mut self) -> Self { self.flags |= 1 << 28; self } pub fn avx512_cd(&self) -> bool { self.flags & (1 << 29) != 0 } pub fn with_avx512_cd(mut self) -> Self { self.flags |= 1 << 29; self } pub fn sha(&self) -> bool { self.flags & (1 << 30) != 0 } pub fn with_sha(mut self) -> Self { self.flags |= 1 << 30; self } pub fn avx512_bw(&self) -> bool { self.flags & (1 << 31) != 0 } pub fn with_avx512_bw(mut self) -> Self { self.flags |= 1 << 31; self } pub fn avx512_vl(&self) -> bool { self.flags & (1 << 32) != 0 } pub fn with_avx512_vl(mut self) -> Self { self.flags |= 1 << 32; self } pub fn prefetchwt1(&self) -> bool { self.flags & (1 << 33) != 0 } pub fn with_prefetchwt1(mut self) -> Self { self.flags |= 1 << 33; self } pub fn avx512_vbmi(&self) -> bool { self.flags & (1 << 34) != 0 } pub fn with_avx512_vbmi(mut self) -> Self { self.flags |= 1 << 34; self } pub fn avx512_vbmi2(&self) -> bool { self.flags & (1 << 35) != 0 } pub fn with_avx512_vbmi2(mut self) -> Self { self.flags |= 1 << 35; self } pub fn gfni(&self) -> bool { self.flags & (1 << 36) != 0 } pub fn with_gfni(mut self) -> Self { self.flags |= 1 << 36; self } pub fn vaes(&self) -> bool { self.flags & (1 << 37) != 0 } pub fn with_vaes(mut self) -> Self { self.flags |= 1 << 37; self } pub fn pclmulqdq(&self) -> bool { self.flags & (1 << 38) != 0 } pub fn with_pclmulqdq(mut self) -> Self { self.flags |= 1 << 38; self } pub fn avx_vnni(&self) -> bool { self.flags & (1 << 39) != 0 } pub fn with_avx_vnni(mut self) -> Self { self.flags |= 1 << 39; self } pub fn avx512_bitalg(&self) -> bool { self.flags & (1 << 40) != 0 } pub fn with_avx512_bitalg(mut self) -> Self { self.flags |= 1 << 40; self } pub fn avx512_vpopcntdq(&self) -> bool { self.flags & (1 << 41) != 0 } pub fn with_avx512_vpopcntdq(mut self) -> Self { self.flags |= 1 << 41; self } pub fn avx512_4vnniw(&self) -> bool { self.flags & (1 << 42) != 0 } pub fn with_avx512_4vnniw(mut self) -> Self { self.flags |= 1 << 42; self } pub fn avx512_4fmaps(&self) -> bool { self.flags & (1 << 43) != 0 } pub fn with_avx512_4fmaps(mut self) -> Self { self.flags |= 1 << 43; self } /// returns `true` if this `InstDecoder` has **all** `avx512` features enabled. pub fn avx512(&self) -> bool { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); (self.flags & avx512_mask) == avx512_mask } /// enable all `avx512` features on this `InstDecoder`. no real CPU, at time of writing, /// actually has such a feature combination, but this is a useful overestimate for `avx512` /// generally. pub fn with_avx512(mut self) -> Self { let avx512_mask = (1 << 19) | (1 << 20) | (1 << 23) | (1 << 27) | (1 << 28) | (1 << 29) | (1 << 31) | (1 << 32) | (1 << 34) | (1 << 35) | (1 << 40) | (1 << 41) | (1 << 42) | (1 << 43); self.flags |= avx512_mask; self } pub fn cx8(&self) -> bool { self.flags & (1 << 44) != 0 } pub fn with_cx8(mut self) -> Self { self.flags |= 1 << 44; self } pub fn syscall(&self) -> bool { self.flags & (1 << 45) != 0 } pub fn with_syscall(mut self) -> Self { self.flags |= 1 << 45; self } pub fn rdtscp(&self) -> bool { self.flags & (1 << 46) != 0 } pub fn with_rdtscp(mut self) -> Self { self.flags |= 1 << 46; self } pub fn abm(&self) -> bool { self.flags & (1 << 47) != 0 } pub fn with_abm(mut self) -> Self { self.flags |= 1 << 47; self } pub fn sse4a(&self) -> bool { self.flags & (1 << 48) != 0 } pub fn with_sse4a(mut self) -> Self { self.flags |= 1 << 48; self } pub fn _3dnowprefetch(&self) -> bool { self.flags & (1 << 49) != 0 } pub fn with_3dnowprefetch(mut self) -> Self { self.flags |= 1 << 49; self } pub fn xop(&self) -> bool { self.flags & (1 << 50) != 0 } pub fn with_xop(mut self) -> Self { self.flags |= 1 << 50; self } pub fn skinit(&self) -> bool { self.flags & (1 << 51) != 0 } pub fn with_skinit(mut self) -> Self { self.flags |= 1 << 51; self } pub fn tbm(&self) -> bool { self.flags & (1 << 52) != 0 } pub fn with_tbm(mut self) -> Self { self.flags |= 1 << 52; self } pub fn intel_quirks(&self) -> bool { self.flags & (1 << 53) != 0 } pub fn with_intel_quirks(mut self) -> Self { self.flags |= 1 << 53; self } pub fn amd_quirks(&self) -> bool { self.flags & (1 << 54) != 0 } pub fn with_amd_quirks(mut self) -> Self { self.flags |= 1 << 54; self } pub fn avx(&self) -> bool { self.flags & (1 << 55) != 0 } pub fn with_avx(mut self) -> Self { self.flags |= 1 << 55; self } pub fn svm(&self) -> bool { self.flags & (1 << 56) != 0 } pub fn with_svm(mut self) -> Self { self.flags |= 1 << 56; self } /// `lahfsahf` is only unset for early revisions of 64-bit amd and intel chips. unfortunately /// the clearest documentation on when these instructions were reintroduced into 64-bit /// architectures seems to be /// [wikipedia](https://en.wikipedia.org/wiki/X86-64#Older_implementations): /// ```text /// Early AMD64 and Intel 64 CPUs lacked LAHF and SAHF instructions in 64-bit mode. AMD /// introduced these instructions (also in 64-bit mode) with their Athlon 64, Opteron and /// Turion 64 revision D processors in March 2005[48][49][50] while Intel introduced the /// instructions with the Pentium 4 G1 stepping in December 2005. The 64-bit version of Windows /// 8.1 requires this feature.[47] /// ``` /// /// this puts reintroduction of these instructions somewhere in the middle of prescott and k8 /// lifecycles, for intel and amd respectively. because there is no specific uarch where these /// features become enabled, prescott and k8 default to not supporting these instructions, /// where later uarches support these instructions. pub fn lahfsahf(&self) -> bool { self.flags & (1 << 57) != 0 } pub fn with_lahfsahf(mut self) -> Self { self.flags |= 1 << 57; self } pub fn cmov(&self) -> bool { self.flags & (1 << 58) != 0 } pub fn with_cmov(mut self) -> Self { self.flags |= 1 << 58; self } pub fn f16c(&self) -> bool { self.flags & (1 << 59) != 0 } pub fn with_f16c(mut self) -> Self { self.flags |= 1 << 59; self } pub fn fma4(&self) -> bool { self.flags & (1 << 60) != 0 } pub fn with_fma4(mut self) -> Self { self.flags |= 1 << 60; self } pub fn prefetchw(&self) -> bool { self.flags & (1 << 61) != 0 } pub fn with_prefetchw(mut self) -> Self { self.flags |= 1 << 61; self } pub fn tsx(&self) -> bool { self.flags & (1 << 62) != 0 } pub fn with_tsx(mut self) -> Self { self.flags |= 1 << 62; self } pub fn lzcnt(&self) -> bool { self.flags & (1 << 63) != 0 } pub fn with_lzcnt(mut self) -> Self { self.flags |= 1 << 63; self } /// Optionally reject or reinterpret instruction according to the decoder's /// declared extensions. fn revise_instruction(&self, inst: &mut Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex().is_some() { if !self.avx512() { return Err(DecodeError::InvalidOpcode); } else { return Ok(()); } } match inst.opcode { Opcode::TZCNT => { if !self.bmi1() { // tzcnt is only supported if bmi1 is enabled. without bmi1, this decodes as // bsf. inst.opcode = Opcode::BSF; } } Opcode::LDDQU | Opcode::ADDSUBPS | Opcode::ADDSUBPD | Opcode::HADDPS | Opcode::HSUBPS | Opcode::HADDPD | Opcode::HSUBPD | Opcode::MOVSHDUP | Opcode::MOVSLDUP | Opcode::MOVDDUP | Opcode::MONITOR | Opcode::MWAIT => { // via Intel section 5.7, SSE3 Instructions if !self.sse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PHADDW | Opcode::PHADDSW | Opcode::PHADDD | Opcode::PHSUBW | Opcode::PHSUBSW | Opcode::PHSUBD | Opcode::PABSB | Opcode::PABSW | Opcode::PABSD | Opcode::PMADDUBSW | Opcode::PMULHRSW | Opcode::PSHUFB | Opcode::PSIGNB | Opcode::PSIGNW | Opcode::PSIGND | Opcode::PALIGNR => { // via Intel section 5.8, SSSE3 Instructions if !self.ssse3() { return Err(DecodeError::InvalidOpcode); } } Opcode::PMULLD | Opcode::PMULDQ | Opcode::MOVNTDQA | Opcode::BLENDPD | Opcode::BLENDPS | Opcode::BLENDVPD | Opcode::BLENDVPS | Opcode::PBLENDVB | Opcode::BLENDW | Opcode::PMINUW | Opcode::PMINUD | Opcode::PMINSB | Opcode::PMINSD | Opcode::PMAXUW | Opcode::PMAXUD | Opcode::PMAXSB | Opcode::PMAXSD | Opcode::ROUNDPS | Opcode::ROUNDPD | Opcode::ROUNDSS | Opcode::ROUNDSD | Opcode::PBLENDW | Opcode::EXTRACTPS | Opcode::INSERTPS | Opcode::PINSRB | Opcode::PINSRD | Opcode::PINSRQ | Opcode::PMOVSXBW | Opcode::PMOVZXBW | Opcode::PMOVSXBD | Opcode::PMOVZXBD | Opcode::PMOVSXWD | Opcode::PMOVZXWD | Opcode::PMOVSXBQ | Opcode::PMOVZXBQ | Opcode::PMOVSXWQ | Opcode::PMOVZXWQ | Opcode::PMOVSXDQ | Opcode::PMOVZXDQ | Opcode::DPPS | Opcode::DPPD | Opcode::MPSADBW | Opcode::PHMINPOSUW | Opcode::PTEST | Opcode::PCMPEQQ | Opcode::PEXTRB | Opcode::PEXTRW | Opcode::PEXTRD | Opcode::PEXTRQ | Opcode::PACKUSDW => { // via Intel section 5.10, SSE4.1 Instructions if !self.sse4_1() { return Err(DecodeError::InvalidOpcode); } } Opcode::EXTRQ | Opcode::INSERTQ | Opcode::MOVNTSS | Opcode::MOVNTSD => { if !self.sse4a() { return Err(DecodeError::InvalidOpcode); } } Opcode::CRC32 | Opcode::PCMPESTRI | Opcode::PCMPESTRM | Opcode::PCMPISTRI | Opcode::PCMPISTRM | Opcode::PCMPGTQ => { // via Intel section 5.11, SSE4.2 Instructions if !self.sse4_2() { return Err(DecodeError::InvalidOpcode); } } Opcode::AESDEC | Opcode::AESDECLAST | Opcode::AESENC | Opcode::AESENCLAST | Opcode::AESIMC | Opcode::AESKEYGENASSIST => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::PCLMULQDQ => { // via Intel section 5.12. AESNI AND PCLMULQDQ if !self.pclmulqdq() { return Err(DecodeError::InvalidOpcode); } } Opcode::XABORT | Opcode::XBEGIN | Opcode::XEND | Opcode::XTEST => { if !self.tsx() { return Err(DecodeError::InvalidOpcode); } } Opcode::SHA1MSG1 | Opcode::SHA1MSG2 | Opcode::SHA1NEXTE | Opcode::SHA1RNDS4 | Opcode::SHA256MSG1 | Opcode::SHA256MSG2 | Opcode::SHA256RNDS2 => { if !self.sha() { return Err(DecodeError::InvalidOpcode); } } Opcode::ENCLV | Opcode::ENCLS | Opcode::ENCLU => { if !self.sgx() { return Err(DecodeError::InvalidOpcode); } } // AVX... Opcode::VMOVDDUP | Opcode::VPSHUFLW | Opcode::VPSHUFHW | Opcode::VHADDPS | Opcode::VHSUBPS | Opcode::VADDSUBPS | Opcode::VCVTPD2DQ | Opcode::VLDDQU | Opcode::VCOMISD | Opcode::VCOMISS | Opcode::VUCOMISD | Opcode::VUCOMISS | Opcode::VADDPD | Opcode::VADDPS | Opcode::VADDSD | Opcode::VADDSS | Opcode::VADDSUBPD | Opcode::VBLENDPD | Opcode::VBLENDPS | Opcode::VBLENDVPD | Opcode::VBLENDVPS | Opcode::VBROADCASTF128 | Opcode::VBROADCASTI128 | Opcode::VBROADCASTSD | Opcode::VBROADCASTSS | Opcode::VCMPSD | Opcode::VCMPSS | Opcode::VCMPPD | Opcode::VCMPPS | Opcode::VCVTDQ2PD | Opcode::VCVTDQ2PS | Opcode::VCVTPD2PS | Opcode::VCVTPS2DQ | Opcode::VCVTPS2PD | Opcode::VCVTSS2SD | Opcode::VCVTSI2SS | Opcode::VCVTSI2SD | Opcode::VCVTSD2SI | Opcode::VCVTSD2SS | Opcode::VCVTSS2SI | Opcode::VCVTTPD2DQ | Opcode::VCVTTPS2DQ | Opcode::VCVTTSS2SI | Opcode::VCVTTSD2SI | Opcode::VDIVPD | Opcode::VDIVPS | Opcode::VDIVSD | Opcode::VDIVSS | Opcode::VDPPD | Opcode::VDPPS | Opcode::VEXTRACTF128 | Opcode::VEXTRACTI128 | Opcode::VEXTRACTPS | Opcode::VFMADD132PD | Opcode::VFMADD132PS | Opcode::VFMADD132SD | Opcode::VFMADD132SS | Opcode::VFMADD213PD | Opcode::VFMADD213PS | Opcode::VFMADD213SD | Opcode::VFMADD213SS | Opcode::VFMADD231PD | Opcode::VFMADD231PS | Opcode::VFMADD231SD | Opcode::VFMADD231SS | Opcode::VFMADDSUB132PD | Opcode::VFMADDSUB132PS | Opcode::VFMADDSUB213PD | Opcode::VFMADDSUB213PS | Opcode::VFMADDSUB231PD | Opcode::VFMADDSUB231PS | Opcode::VFMSUB132PD | Opcode::VFMSUB132PS | Opcode::VFMSUB132SD | Opcode::VFMSUB132SS | Opcode::VFMSUB213PD | Opcode::VFMSUB213PS | Opcode::VFMSUB213SD | Opcode::VFMSUB213SS | Opcode::VFMSUB231PD | Opcode::VFMSUB231PS | Opcode::VFMSUB231SD | Opcode::VFMSUB231SS | Opcode::VFMSUBADD132PD | Opcode::VFMSUBADD132PS | Opcode::VFMSUBADD213PD | Opcode::VFMSUBADD213PS | Opcode::VFMSUBADD231PD | Opcode::VFMSUBADD231PS | Opcode::VFNMADD132PD | Opcode::VFNMADD132PS | Opcode::VFNMADD132SD | Opcode::VFNMADD132SS | Opcode::VFNMADD213PD | Opcode::VFNMADD213PS | Opcode::VFNMADD213SD | Opcode::VFNMADD213SS | Opcode::VFNMADD231PD | Opcode::VFNMADD231PS | Opcode::VFNMADD231SD | Opcode::VFNMADD231SS | Opcode::VFNMSUB132PD | Opcode::VFNMSUB132PS | Opcode::VFNMSUB132SD | Opcode::VFNMSUB132SS | Opcode::VFNMSUB213PD | Opcode::VFNMSUB213PS | Opcode::VFNMSUB213SD | Opcode::VFNMSUB213SS | Opcode::VFNMSUB231PD | Opcode::VFNMSUB231PS | Opcode::VFNMSUB231SD | Opcode::VFNMSUB231SS | Opcode::VGATHERDPD | Opcode::VGATHERDPS | Opcode::VGATHERQPD | Opcode::VGATHERQPS | Opcode::VHADDPD | Opcode::VHSUBPD | Opcode::VINSERTF128 | Opcode::VINSERTI128 | Opcode::VINSERTPS | Opcode::VMASKMOVDQU | Opcode::VMASKMOVPD | Opcode::VMASKMOVPS | Opcode::VMAXPD | Opcode::VMAXPS | Opcode::VMAXSD | Opcode::VMAXSS | Opcode::VMINPD | Opcode::VMINPS | Opcode::VMINSD | Opcode::VMINSS | Opcode::VMOVAPD | Opcode::VMOVAPS | Opcode::VMOVD | Opcode::VMOVDQA | Opcode::VMOVDQU | Opcode::VMOVHLPS | Opcode::VMOVHPD | Opcode::VMOVHPS | Opcode::VMOVLHPS | Opcode::VMOVLPD | Opcode::VMOVLPS | Opcode::VMOVMSKPD | Opcode::VMOVMSKPS | Opcode::VMOVNTDQ | Opcode::VMOVNTDQA | Opcode::VMOVNTPD | Opcode::VMOVNTPS | Opcode::VMOVQ | Opcode::VMOVSS | Opcode::VMOVSD | Opcode::VMOVSHDUP | Opcode::VMOVSLDUP | Opcode::VMOVUPD | Opcode::VMOVUPS | Opcode::VMPSADBW | Opcode::VMULPD | Opcode::VMULPS | Opcode::VMULSD | Opcode::VMULSS | Opcode::VPABSB | Opcode::VPABSD | Opcode::VPABSW | Opcode::VPACKSSDW | Opcode::VPACKUSDW | Opcode::VPACKSSWB | Opcode::VPACKUSWB | Opcode::VPADDB | Opcode::VPADDD | Opcode::VPADDQ | Opcode::VPADDSB | Opcode::VPADDSW | Opcode::VPADDUSB | Opcode::VPADDUSW | Opcode::VPADDW | Opcode::VPALIGNR | Opcode::VPAND | Opcode::VANDPD | Opcode::VANDPS | Opcode::VANDNPD | Opcode::VANDNPS | Opcode::VORPD | Opcode::VORPS | Opcode::VPANDN | Opcode::VPAVGB | Opcode::VPAVGW | Opcode::VPBLENDD | Opcode::VPBLENDVB | Opcode::VPBLENDW | Opcode::VPBROADCASTB | Opcode::VPBROADCASTD | Opcode::VPBROADCASTQ | Opcode::VPBROADCASTW | Opcode::VPCLMULQDQ | Opcode::VPCMPEQB | Opcode::VPCMPEQD | Opcode::VPCMPEQQ | Opcode::VPCMPEQW | Opcode::VPCMPGTB | Opcode::VPCMPGTD | Opcode::VPCMPGTQ | Opcode::VPCMPGTW | Opcode::VPCMPESTRI | Opcode::VPCMPESTRM | Opcode::VPCMPISTRI | Opcode::VPCMPISTRM | Opcode::VPERM2F128 | Opcode::VPERM2I128 | Opcode::VPERMD | Opcode::VPERMILPD | Opcode::VPERMILPS | Opcode::VPERMPD | Opcode::VPERMPS | Opcode::VPERMQ | Opcode::VPEXTRB | Opcode::VPEXTRD | Opcode::VPEXTRQ | Opcode::VPEXTRW | Opcode::VPGATHERDD | Opcode::VPGATHERDQ | Opcode::VPGATHERQD | Opcode::VPGATHERQQ | Opcode::VPHADDD | Opcode::VPHADDSW | Opcode::VPHADDW | Opcode::VPMADDUBSW | Opcode::VPHMINPOSUW | Opcode::VPHSUBD | Opcode::VPHSUBSW | Opcode::VPHSUBW | Opcode::VPINSRB | Opcode::VPINSRD | Opcode::VPINSRQ | Opcode::VPINSRW | Opcode::VPMADDWD | Opcode::VPMASKMOVD | Opcode::VPMASKMOVQ | Opcode::VPMAXSB | Opcode::VPMAXSD | Opcode::VPMAXSW | Opcode::VPMAXUB | Opcode::VPMAXUW | Opcode::VPMAXUD | Opcode::VPMINSB | Opcode::VPMINSW | Opcode::VPMINSD | Opcode::VPMINUB | Opcode::VPMINUW | Opcode::VPMINUD | Opcode::VPMOVMSKB | Opcode::VPMOVSXBD | Opcode::VPMOVSXBQ | Opcode::VPMOVSXBW | Opcode::VPMOVSXDQ | Opcode::VPMOVSXWD | Opcode::VPMOVSXWQ | Opcode::VPMOVZXBD | Opcode::VPMOVZXBQ | Opcode::VPMOVZXBW | Opcode::VPMOVZXDQ | Opcode::VPMOVZXWD | Opcode::VPMOVZXWQ | Opcode::VPMULDQ | Opcode::VPMULHRSW | Opcode::VPMULHUW | Opcode::VPMULHW | Opcode::VPMULLQ | Opcode::VPMULLD | Opcode::VPMULLW | Opcode::VPMULUDQ | Opcode::VPOR | Opcode::VPSADBW | Opcode::VPSHUFB | Opcode::VPSHUFD | Opcode::VPSIGNB | Opcode::VPSIGND | Opcode::VPSIGNW | Opcode::VPSLLD | Opcode::VPSLLDQ | Opcode::VPSLLQ | Opcode::VPSLLVD | Opcode::VPSLLVQ | Opcode::VPSLLW | Opcode::VPSRAD | Opcode::VPSRAVD | Opcode::VPSRAW | Opcode::VPSRLD | Opcode::VPSRLDQ | Opcode::VPSRLQ | Opcode::VPSRLVD | Opcode::VPSRLVQ | Opcode::VPSRLW | Opcode::VPSUBB | Opcode::VPSUBD | Opcode::VPSUBQ | Opcode::VPSUBSB | Opcode::VPSUBSW | Opcode::VPSUBUSB | Opcode::VPSUBUSW | Opcode::VPSUBW | Opcode::VPTEST | Opcode::VPUNPCKHBW | Opcode::VPUNPCKHDQ | Opcode::VPUNPCKHQDQ | Opcode::VPUNPCKHWD | Opcode::VPUNPCKLBW | Opcode::VPUNPCKLDQ | Opcode::VPUNPCKLQDQ | Opcode::VPUNPCKLWD | Opcode::VPXOR | Opcode::VRCPPS | Opcode::VROUNDPD | Opcode::VROUNDPS | Opcode::VROUNDSD | Opcode::VROUNDSS | Opcode::VRSQRTPS | Opcode::VRSQRTSS | Opcode::VRCPSS | Opcode::VSHUFPD | Opcode::VSHUFPS | Opcode::VSQRTPD | Opcode::VSQRTPS | Opcode::VSQRTSS | Opcode::VSQRTSD | Opcode::VSUBPD | Opcode::VSUBPS | Opcode::VSUBSD | Opcode::VSUBSS | Opcode::VTESTPD | Opcode::VTESTPS | Opcode::VUNPCKHPD | Opcode::VUNPCKHPS | Opcode::VUNPCKLPD | Opcode::VUNPCKLPS | Opcode::VXORPD | Opcode::VXORPS | Opcode::VZEROUPPER | Opcode::VZEROALL | Opcode::VLDMXCSR | Opcode::VSTMXCSR => { // TODO: check a table for these if !self.avx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VAESDEC | Opcode::VAESDECLAST | Opcode::VAESENC | Opcode::VAESENCLAST | Opcode::VAESIMC | Opcode::VAESKEYGENASSIST => { // TODO: check a table for these if !self.avx() || !self.aesni() { return Err(DecodeError::InvalidOpcode); } } Opcode::MOVBE => { if !self.movbe() { return Err(DecodeError::InvalidOpcode); } } Opcode::POPCNT => { /* * from the intel SDM: * ``` * Before an application attempts to use the POPCNT instruction, it must check that * the processor supports SSE4.2 (if CPUID.01H:ECX.SSE4_2[bit 20] = 1) and POPCNT * (if CPUID.01H:ECX.POPCNT[bit 23] = 1). * ``` */ if self.intel_quirks() && (self.sse4_2() || self.popcnt()) { return Ok(()); } else if !self.popcnt() { /* * elsewhere from the amd APM: * `Instruction Subsets and CPUID Feature Flags` on page 507 indicates that * popcnt is present when the popcnt bit is reported by cpuid. this seems to be * the less quirky default, so `intel_quirks` is considered the outlier, and * before this default. * */ return Err(DecodeError::InvalidOpcode); } } Opcode::LZCNT => { /* * amd APM, `LZCNT` page 212: * LZCNT is an Advanced Bit Manipulation (ABM) instruction. Support for the LZCNT * instruction is indicated by CPUID Fn8000_0001_ECX[ABM] = 1. * * meanwhile the intel SDM simply states: * ``` * CPUID.EAX=80000001H:ECX.LZCNT[bit 5]: if 1 indicates the processor supports the * LZCNT instruction. * ``` * * so that's considered the less-quirky (default) case here. * */ if self.amd_quirks() && !self.abm() { return Err(DecodeError::InvalidOpcode); } else if !self.lzcnt() { return Err(DecodeError::InvalidOpcode); } } Opcode::ADCX | Opcode::ADOX => { if !self.adx() { return Err(DecodeError::InvalidOpcode); } } Opcode::VMRUN | Opcode::VMLOAD | Opcode::VMSAVE | Opcode::CLGI | Opcode::VMMCALL | Opcode::INVLPGA => { if !self.svm() { return Err(DecodeError::InvalidOpcode); } } Opcode::STGI | Opcode::SKINIT => { if !self.svm() || !self.skinit() { return Err(DecodeError::InvalidOpcode); } } Opcode::LAHF | Opcode::SAHF => { if !self.lahfsahf() { return Err(DecodeError::InvalidOpcode); } } Opcode::VCVTPS2PH | Opcode::VCVTPH2PS => { /* * from intel SDM: * ``` * 14.4.1 Detection of F16C Instructions Application using float 16 instruction * must follow a detection sequence similar to AVX to ensure: • The OS has * enabled YMM state management support, • The processor support AVX as * indicated by the CPUID feature flag, i.e. CPUID.01H:ECX.AVX[bit 28] = 1. • * The processor support 16-bit floating-point conversion instructions via a * CPUID feature flag (CPUID.01H:ECX.F16C[bit 29] = 1). * ``` * * TODO: only the VEX-coded variant of this instruction should be gated on `f16c`. * the EVEX-coded variant should be gated on `avx512f` or `avx512vl` if not * EVEX.512-coded. */ if !self.avx() || !self.f16c() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDRAND => { if !self.rdrand() { return Err(DecodeError::InvalidOpcode); } } Opcode::RDSEED => { if !self.rdseed() { return Err(DecodeError::InvalidOpcode); } } Opcode::MONITORX | Opcode::MWAITX | // these are gated on the `monitorx` and `mwaitx` cpuid bits, but are AMD-only. Opcode::CLZERO | Opcode::RDPRU => { // again, gated on specific cpuid bits, but AMD-only. if !self.amd_quirks() { return Err(DecodeError::InvalidOpcode); } } other => { if !self.bmi1() { if BMI1.contains(&other) { return Err(DecodeError::InvalidOpcode); } } if !self.bmi2() { if BMI2.contains(&other) { return Err(DecodeError::InvalidOpcode); } } } } Ok(()) } } impl Default for InstDecoder { /// Instantiates an x86 decoder that probably decodes what you want. /// /// Attempts to match real processors in interpretation of undefined sequences, and decodes any /// instruction defined in any extension. fn default() -> Self { Self { flags: 0xffffffff_ffffffff, } } } impl Decoder for InstDecoder { fn decode::Address, ::Word>>(&self, words: &mut T) -> Result::DecodeError> { let mut instr = Instruction::invalid(); DecodeCtx::new().read_with_annotations(self, words, &mut instr, &mut NullSink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(&mut instr)?; } Ok(instr) } fn decode_into::Address, ::Word>>(&self, instr: &mut Instruction, words: &mut T) -> Result<(), ::DecodeError> { self.decode_with_annotation(instr, words, &mut NullSink) } } impl AnnotatingDecoder for InstDecoder { type FieldDescription = FieldDescription; fn decode_with_annotation< T: Reader<::Address, ::Word>, S: DescriptionSink >(&self, instr: &mut Instruction, words: &mut T, sink: &mut S) -> Result<(), ::DecodeError> { DecodeCtx::new().read_with_annotations(self, words, instr, sink)?; instr.length = words.offset() as u8; if words.offset() > 15 { return Err(DecodeError::TooLong); } if self != &InstDecoder::default() { self.revise_instruction(instr)?; } Ok(()) } } impl Opcode { /// check if the instruction is one of x86's sixteen conditional jump instructions. use this /// rather than `opcode.to_string().starts_with("j") && opcode != Opcode::JMP`, thank you. pub fn is_jcc(&self) -> bool { match self { Opcode::JO | Opcode::JNO | Opcode::JB | Opcode::JNB | Opcode::JZ | Opcode::JNZ | Opcode::JA | Opcode::JNA | Opcode::JS | Opcode::JNS | Opcode::JP | Opcode::JNP | Opcode::JL | Opcode::JGE | Opcode::JG | Opcode::JLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional move instructions. pub fn is_cmovcc(&self) -> bool { match self { Opcode::CMOVO | Opcode::CMOVNO | Opcode::CMOVB | Opcode::CMOVNB | Opcode::CMOVZ | Opcode::CMOVNZ | Opcode::CMOVA | Opcode::CMOVNA | Opcode::CMOVS | Opcode::CMOVNS | Opcode::CMOVP | Opcode::CMOVNP | Opcode::CMOVL | Opcode::CMOVGE | Opcode::CMOVG | Opcode::CMOVLE => true, _ => false, } } /// check if the instruction is one of x86's sixteen conditional set instructions. pub fn is_setcc(&self) -> bool { match self { Opcode::SETO | Opcode::SETNO | Opcode::SETB | Opcode::SETAE | Opcode::SETZ | Opcode::SETNZ | Opcode::SETA | Opcode::SETBE | Opcode::SETS | Opcode::SETNS | Opcode::SETP | Opcode::SETNP | Opcode::SETL | Opcode::SETGE | Opcode::SETG | Opcode::SETLE => true, _ => false } } /// get the [`ConditionCode`] for this instruction, if it is in fact conditional. x86's /// conditional instructions are `Jcc`, `CMOVcc`, andd `SETcc`. pub fn condition(&self) -> Option { match self { Opcode::JO | Opcode::CMOVO | Opcode::SETO => { Some(ConditionCode::O) }, Opcode::JNO | Opcode::CMOVNO | Opcode::SETNO => { Some(ConditionCode::NO) }, Opcode::JB | Opcode::CMOVB | Opcode::SETB => { Some(ConditionCode::B) }, Opcode::JNB | Opcode::CMOVNB | Opcode::SETAE => { Some(ConditionCode::AE) }, Opcode::JZ | Opcode::CMOVZ | Opcode::SETZ => { Some(ConditionCode::Z) }, Opcode::JNZ | Opcode::CMOVNZ | Opcode::SETNZ => { Some(ConditionCode::NZ) }, Opcode::JA | Opcode::CMOVA | Opcode::SETA => { Some(ConditionCode::A) }, Opcode::JNA | Opcode::CMOVNA | Opcode::SETBE => { Some(ConditionCode::BE) }, Opcode::JS | Opcode::CMOVS | Opcode::SETS => { Some(ConditionCode::S) }, Opcode::JNS | Opcode::CMOVNS | Opcode::SETNS => { Some(ConditionCode::NS) }, Opcode::JP | Opcode::CMOVP | Opcode::SETP => { Some(ConditionCode::P) }, Opcode::JNP | Opcode::CMOVNP | Opcode::SETNP => { Some(ConditionCode::NP) }, Opcode::JL | Opcode::CMOVL | Opcode::SETL => { Some(ConditionCode::L) }, Opcode::JGE | Opcode::CMOVGE | Opcode::SETGE => { Some(ConditionCode::GE) }, Opcode::JG | Opcode::CMOVG | Opcode::SETG => { Some(ConditionCode::G) }, Opcode::JLE | Opcode::CMOVLE | Opcode::SETLE => { Some(ConditionCode::LE) }, _ => None, } } } impl Default for Instruction { fn default() -> Self { Instruction::invalid() } } impl Instruction { /// get the `Opcode` of this instruction. pub fn opcode(&self) -> Opcode { self.opcode } /// get the `Operand` at the provided index. /// /// panics if the index is `>= 4`. pub fn operand(&self, i: u8) -> Operand { assert!(i < 4); Operand::from_spec(self, self.operands[i as usize]) } /// get the number of operands in this instruction. useful in iterating an instruction's /// operands generically. pub fn operand_count(&self) -> u8 { self.operand_count } /// check if operand `i` is an actual operand or not. will be `false` for `i >= /// inst.operand_count()`. pub fn operand_present(&self, i: u8) -> bool { assert!(i < 4); if i >= self.operand_count { return false; } if let OperandSpec::Nothing = self.operands[i as usize] { false } else { true } } /// get the memory access information for this instruction, if it accesses memory. /// /// the corresponding `MemoryAccessSize` may report that the size of accessed memory is /// indeterminate; this is the case for `xsave/xrestor`-style instructions whose operation size /// varies based on physical processor. /// /// ## NOTE /// /// the reported size is correct for displayed operand sizes (`word [ptr]` will have a /// `MemoryAccessSize` indicating two bytes) but is _not_ sufficient to describe all accesses /// of all instructions. the most notable exception is for operand-size-prefixed `call`, where /// `66ff10` is the instruction `call dword [eax]`, but will push a four-byte `eip`. tools /// must account for these inconsistent sizes internally. pub fn mem_size(&self) -> Option { if self.mem_size != 0 { Some(MemoryAccessSize { size: self.mem_size }) } else { None } } /// build a new instruction representing nothing in particular. this is primarily useful as a /// default to pass to `decode_into`. pub fn invalid() -> Instruction { Instruction { prefixes: Prefixes::new(0), opcode: Opcode::NOP, mem_size: 0, regs: [RegSpec::ax(); 4], scale: 0, length: 0, disp: 0, imm: 0, operand_count: 0, operands: [OperandSpec::Nothing; 4], } } /// get the `Segment` that will *actually* be used for accessing the operand at index `i`. /// /// `stos`, `lods`, `movs`, and `cmps` specifically name some segments for use regardless of /// prefixes. pub fn segment_override_for_op(&self, op: u8) -> Option { match self.opcode { Opcode::STOS | Opcode::SCAS => { if op == 0 { Some(Segment::ES) } else { None } } Opcode::LODS => { if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::MOVS => { if op == 0 { Some(Segment::ES) } else if op == 1 { Some(self.prefixes.segment) } else { None } } Opcode::CMPS => { if op == 0 { Some(self.prefixes.segment) } else if op == 1 { Some(Segment::ES) } else { None } }, _ => { // most operands are pretty simple: if self.operands[op as usize].is_memory() && self.prefixes.segment != Segment::DS { Some(self.prefixes.segment) } else { None } } } } #[cfg(feature = "fmt")] /// wrap a reference to this instruction with a `DisplayStyle` to format the instruction with /// later. see the documentation on [`display::DisplayStyle`] for more. /// /// ``` /// use yaxpeax_x86::long_mode::{InstDecoder, DisplayStyle}; /// /// let decoder = InstDecoder::default(); /// let inst = decoder.decode_slice(&[0x33, 0xc1]).unwrap(); /// /// assert_eq!("eax ^= ecx", inst.display_with(DisplayStyle::C).to_string()); /// assert_eq!("xor eax, ecx", inst.display_with(DisplayStyle::Intel).to_string()); /// ``` pub fn display_with<'a>(&'a self, style: display::DisplayStyle) -> display::InstructionDisplayer<'a> { display::InstructionDisplayer { style, instr: self, } } /// does this instruction include the `xacquire` hint for hardware lock elision? pub fn xacquire(&self) -> bool { if self.prefixes.repnz() { // xacquire is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else { false } } else { false } } /// does this instruction include the `xrelease` hint for hardware lock elision? pub fn xrelease(&self) -> bool { if self.prefixes.rep() { // xrelease is permitted on typical `lock` instructions, OR `xchg` with memory operand, // regardless of `lock` prefix. additionally, xrelease is permitted on some forms of mov. if self.prefixes.lock() { true } else if self.opcode == Opcode::XCHG { self.operands[0] != OperandSpec::RegMMM && self.operands[1] != OperandSpec::RegMMM } else if self.opcode == Opcode::MOV { self.operands[0] != OperandSpec::RegMMM && ( self.operands[1] == OperandSpec::RegRRR || self.operands[1] == OperandSpec::ImmI8 || self.operands[1] == OperandSpec::ImmI16 || self.operands[1] == OperandSpec::ImmI32 ) } else { false } } else { false } } } #[derive(Debug, Copy, Clone, Eq, PartialEq)] struct EvexData { // data: present, z, b, Lp, Rp. aaa bits: u8, } /// the prefixes on an instruction. /// /// `rep`, `repnz`, `lock`, and segment override prefixes are directly accessible here. `vex` and /// `evex` prefixes are available through their associated helpers. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct Prefixes { bits: u8, vex: PrefixVex, segment: Segment, evex_data: EvexData, } #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixEvex { vex: PrefixVex, evex_data: EvexData, } impl PrefixEvex { fn present(&self) -> bool { self.evex_data.present() } /// the `evex` prefix's parts that overlap with `vex` definitions - `L`, `W`, `R`, `X`, and `B` /// bits. pub fn vex(&self) -> &PrefixVex { &self.vex } /// the `avx512` mask register in use. `0` indicates "no mask register". pub fn mask_reg(&self) -> u8 { self.evex_data.aaa() } pub fn broadcast(&self) -> bool { self.evex_data.b() } pub fn merge(&self) -> bool { self.evex_data.z() } /// the `evex` `L'` bit. pub fn lp(&self) -> bool { self.evex_data.lp() } /// the `evex` `R'` bit. pub fn rp(&self) -> bool { self.evex_data.rp() } } /// bits specified in an avx/avx2 [`vex`](https://en.wikipedia.org/wiki/VEX_prefix) prefix, `L`, `W`, `R`, `X`, and `B`. #[derive(Debug, Copy, Clone, Eq, PartialEq)] pub struct PrefixVex { bits: u8, } #[allow(dead_code)] impl PrefixVex { #[inline] pub fn b(&self) -> bool { (self.bits & 0x01) == 0x01 } #[inline] pub fn x(&self) -> bool { (self.bits & 0x02) == 0x02 } #[inline] pub fn r(&self) -> bool { (self.bits & 0x04) == 0x04 } #[inline] pub fn w(&self) -> bool { (self.bits & 0x08) == 0x08 } #[inline] pub fn l(&self) -> bool { (self.bits & 0x10) == 0x10 } #[inline] fn present(&self) -> bool { (self.bits & 0x80) == 0x80 } #[inline] fn compressed_disp(&self) -> bool { (self.bits & 0x20) == 0x20 } } #[allow(dead_code)] impl Prefixes { fn new(bits: u8) -> Prefixes { Prefixes { bits: bits, vex: PrefixVex { bits: 0 }, segment: Segment::DS, evex_data: EvexData { bits: 0 }, } } fn vex_from(&mut self, bits: u8) { self.vex = PrefixVex { bits }; } #[inline] pub fn rep(&self) -> bool { self.bits & 0x30 == 0x10 } #[inline] fn set_rep(&mut self) { self.bits = (self.bits & 0xcf) | 0x10 } #[inline] pub fn repnz(&self) -> bool { self.bits & 0x30 == 0x30 } #[inline] fn set_repnz(&mut self) { self.bits = (self.bits & 0xcf) | 0x30 } #[inline] pub fn rep_any(&self) -> bool { self.bits & 0x30 != 0x00 } #[inline] fn operand_size(&self) -> bool { self.bits & 0x1 == 1 } #[inline] fn set_operand_size(&mut self) { self.bits = self.bits | 0x1 } #[inline] fn unset_operand_size(&mut self) { self.bits = self.bits & !0x1 } #[inline] fn address_size(&self) -> bool { self.bits & 0x2 == 2 } #[inline] fn set_address_size(&mut self) { self.bits = self.bits | 0x2 } #[inline] fn set_lock(&mut self) { self.bits |= 0x4 } #[inline] pub fn lock(&self) -> bool { self.bits & 0x4 == 4 } #[deprecated(since = "0.0.1", note = "pub fn cs has never returned `bool` indicating the current selector is `cs`. use `selects_cs` for this purpose, until 2.x that will correct `pub fn cs`.")] #[inline] pub fn cs(&mut self) {} #[inline] pub fn selects_cs(&self) -> bool { self.segment == Segment::CS } #[inline] fn set_cs(&mut self) { self.segment = Segment::CS } #[inline] pub fn ds(&self) -> bool { self.segment == Segment::DS } #[inline] fn set_ds(&mut self) { self.segment = Segment::DS } #[inline] pub fn es(&self) -> bool { self.segment == Segment::ES } #[inline] fn set_es(&mut self) { self.segment = Segment::ES } #[inline] pub fn fs(&self) -> bool { self.segment == Segment::FS } #[inline] fn set_fs(&mut self) { self.segment = Segment::FS } #[inline] pub fn gs(&self) -> bool { self.segment == Segment::GS } #[inline] fn set_gs(&mut self) { self.segment = Segment::GS } #[inline] pub fn ss(&self) -> bool { self.segment == Segment::SS } #[inline] fn set_ss(&mut self) { self.segment = Segment::SS } #[inline] fn vex_unchecked(&self) -> PrefixVex { PrefixVex { bits: self.vex.bits } } #[inline] fn vex_invalid(&self) -> bool { /* * if instruction.prefixes.rex_unchecked().present() // but no rex outside 64-bit mode * || instruction.prefixes.lock() * || instruction.prefixes.operand_size() * || instruction.prefixes.rep() * || instruction.prefixes.repnz() { */ (self.bits & 0b1100_0101) > 0 } #[inline] pub fn vex(&self) -> Option { let vex = self.vex_unchecked(); if vex.present() { Some(vex) } else { None } } #[inline] fn evex_unchecked(&self) -> PrefixEvex { PrefixEvex { vex: PrefixVex { bits: self.vex.bits }, evex_data: self.evex_data } } #[inline] pub fn evex(&self) -> Option { let evex = self.evex_unchecked(); if evex.present() { Some(evex) } else { None } } #[inline] fn apply_compressed_disp(&mut self, state: bool) { if state { self.vex.bits |= 0x20; } else { self.vex.bits &= 0xdf; } } #[inline] fn vex_from_c5(&mut self, bits: u8) { // collect rex bits let r = bits & 0x80; let wrxb = (r >> 5) ^ 0x04; let l = (bits & 0x04) << 2; let synthetic_rex = wrxb | l | 0x80; self.vex = PrefixVex { bits: synthetic_rex }; } #[inline] fn vex_from_c4(&mut self, high: u8, low: u8) { let w = low & 0x80; let rxb = (high >> 5) ^ 0x07; let wrxb = rxb | w >> 4; let l = (low & 0x04) << 2; let synthetic_vex = wrxb | l | 0x80; self.vex = PrefixVex { bits: synthetic_vex }; } #[inline] fn evex_from(&mut self, b1: u8, b2: u8, b3: u8) { let w = b2 & 0x80; let rxb = ((b1 >> 5) & 0b111) ^ 0b111; // `rxb` is provided in inverted form let wrxb = rxb | (w >> 4); let l = (b3 & 0x20) >> 1; let synthetic_vex = wrxb | l | 0x80; self.vex_from(synthetic_vex); // R' is provided in inverted form let rp = ((b1 & 0x10) >> 4) ^ 1; let lp = (b3 & 0x40) >> 6; let aaa = b3 & 0b111; let z = (b3 & 0x80) >> 7; let b = (b3 & 0x10) >> 4; self.evex_data.from(rp, lp, z, b, aaa); } } impl EvexData { fn from(&mut self, rp: u8, lp: u8, z: u8, b: u8, aaa: u8) { let mut bits = 0; bits |= aaa; bits |= b << 3; bits |= z << 4; bits |= lp << 5; bits |= rp << 6; bits |= 0x80; self.bits = bits; } } impl EvexData { pub(crate) fn present(&self) -> bool { self.bits & 0b1000_0000 != 0 } pub(crate) fn aaa(&self) -> u8 { self.bits & 0b111 } pub(crate) fn b(&self) -> bool { (self.bits & 0b0000_1000) != 0 } pub(crate) fn z(&self) -> bool { (self.bits & 0b0001_0000) != 0 } pub(crate) fn lp(&self) -> bool { (self.bits & 0b0010_0000) != 0 } pub(crate) fn rp(&self) -> bool { (self.bits & 0b0100_0000) != 0 } } #[derive(Debug)] struct OperandCodeBuilder { bits: u16 } #[allow(non_camel_case_types)] enum ZOperandCategory { Zv_R = 0, Zv_AX = 1, Zb_Ib_R = 2, Zv_Iv_R = 3, } struct ZOperandInstructions { bits: u16 } impl ZOperandInstructions { fn category(&self) -> u8 { (self.bits >> 4) as u8 & 0b11 } fn reg(&self) -> u8 { (self.bits & 0b111) as u8 } } struct EmbeddedOperandInstructions { bits: u16 } impl EmbeddedOperandInstructions { #[allow(unused)] fn bits(&self) -> u16 { self.bits } } #[allow(non_snake_case)] impl OperandCodeBuilder { const fn new() -> Self { OperandCodeBuilder { bits: 0 } } const fn bits(&self) -> u16 { self.bits } const fn from_bits(bits: u16) -> Self { Self { bits } } const fn read_modrm(mut self) -> Self { self.bits |= 0x8000; self } // deny ModRM `mod=11` const fn deny_regmmm(mut self) -> Self { self.bits |= 0x2000; self } const fn denies_regmmm(&self) -> bool { self.bits & 0x2000 != 0 } const fn set_embedded_instructions(mut self) -> Self { self.bits |= 0x4000; self } fn has_embedded_instructions(&self) -> bool { self.bits & 0x4000 != 0 } fn get_embedded_instructions(&self) -> Option { // 0x4000 indicates embedded instructions // 0x3fff > 0x0080 indicates the embedded instructions are a Z-style operand if self.has_embedded_instructions() { Some(ZOperandInstructions { bits: self.bits }) } else { None } } fn operand_case_handler_index(&self) -> OperandCase { unsafe { core::mem::transmute(self.bits as u8) } } const fn operand_case(mut self, case: OperandCase) -> Self { // leave 0x4000 unset self.bits |= case as u8 as u16; self } const fn op0_is_rrr_and_Z_operand(mut self, category: ZOperandCategory, reg_num: u8) -> Self { self = self.set_embedded_instructions(); // if op0 is rrr, 0x2000 unset indicates the operand category written in bits 11:10 // further, reg number is bits 0:2 // // when 0x2000 is unset: // 0x1cf8 are all unused bits, so far // // if you're counting, that's 8 bits remaining. // it also means one of those (0x0400?) can be used to pick some other interpretation // scheme. self.bits |= (category as u8 as u16) << 4; self.bits |= reg_num as u16 & 0b111; self } const fn read_E(mut self) -> Self { self.bits |= 0x1000; self } const fn has_read_E(&self) -> bool { self.bits & 0x1000 != 0 } const fn byte_operands(mut self) -> Self { self.bits |= 0x0800; self } const fn mem_reg(mut self) -> Self { self.bits |= 0x0400; self } const fn reg_mem(self) -> Self { // 0x0400 unset self } const fn has_byte_operands(&self) -> bool { (self.bits & 0x0800) != 0 } const fn has_reg_mem(&self) -> bool { (self.bits & 0x0400) == 0 } const fn only_modrm_operands(mut self) -> Self { self.bits |= 0x0200; self } const fn is_only_modrm_operands(&self) -> bool { self.bits & 0x0200 != 0 } // WHEN AN IMMEDIATE IS PRESENT, THERE ARE ONLY 0x3F ALLOWED SPECIAL CASES. // WHEN NO IMMEDIATE IS PRESENT, THERE ARE 0xFF ALLOWED SPECIAL CASES. // SIZE IS DECIDED BY THE FOLLOWING TABLE: // 0: 1 BYTE // 1: 4 BYTES const fn only_imm(mut self) -> Self { self.bits |= 0x100; self } fn has_imm(&self) -> bool { self.bits & 0x100 != 0 } } /// a wrapper to hide internal library implementation details. this is only useful for the inner /// content's `Display` impl, which itself is unstable and suitable only for human consumption. #[derive(Copy, Clone, Debug, PartialEq, Eq)] pub struct OperandCodeWrapper { code: OperandCode } #[allow(non_camel_case_types)] #[derive(Debug, PartialEq, Copy, Clone)] #[repr(u8)] enum OperandCase { Internal = 0, // handled internally and completely by embedded rules. Gv_M = 1, // "internal", but must be distinguished from Gv_Ev Ibs = 2, Jvds = 3, Nothing = 4, // no operands. this is distinct from `Internal`: `Internal` may specify one or two operands depending on embedded rules. SingleMMMOper = 5, // one operand, disregard rrr bits of modrm. BaseOpWithI8 = 6, BaseOpWithIv = 7, MovI8 = 8, MovIv = 9, BitwiseWithI8 = 10, // BitwiseWithIv = 9, ShiftBy1_b, ShiftBy1_v, BitwiseByCL, ModRM_0x8f, ModRM_0xf6, ModRM_0xf7, ModRM_0xfe, ModRM_0xff, Gv_Eb, Gv_Ew, // Gdq_Ed, I_3, E_G_xmm, G_M_xmm, G_E_xmm, G_E_xmm_Ib, AL_Ibs, AX_Ivd, Ivs, ModRM_0x83, Ed_G_xmm, G_Ed_xmm, /* Nothing = Nothing, Eb_R0 = SingleMMMOper, Ev = SingleMMMOper, ModRM_0x80_Eb_Ib = BaseOpWithI8, ModRM_0x81_Ev_Ivs = BaseOpWithIv, ModRM_0xc6_Eb_Ib = MovI8, ModRM_0xc7_Ev_Iv = MovIv, ModRM_0xc0_Eb_Ib = BitwiseWithI8, ModRM_0xc1_Ev_Ib = BitwiseWithIv, ModRM_0xd0_Eb_1 = ShiftBy1_b, ModRM_0xd1_Ev_1 = ShiftBy1_v, ModRM_0x8f_Ev = ModRM_0x8f, ModRM_0xd2_Eb_CL = BitwiseByCL, ModRM_0xd3_Ev_CL = BitwiseByCL, ModRM_0xf6 = ModRM_0xf6_0xf7, ModRM_0xf7 = ModRM_0xf6_0xf7, ModRM_0xfe_Eb = ModRM_0xfe, ModRM_0xff_Ev = ModRM_0xff, Gv_Eb = Gv_Eb, Gv_Ew = Gv_Ew, Gdq_Ed = Gdq_Ed, I_3 = I_3, E_G_xmm = E_G_xmm, G_M_xmm = G_M_xmm, G_E_xmm = G_E_xmm, G_E_xmm_Ib = G_E_xmm_Ib, AL_Ibs = AL_Ibs, AX_Ivd = AX_Ivd, Ivs = Ivs, ModRM_0x83_Ev_Ibs = ModRM_0x83, Ed_G_xmm = Ed_G_xmm, G_Ed_xmm = G_Ed_xmm, */ Ib, x87_d8, x87_d9, x87_da, x87_db, x87_dc, x87_dd, x87_de, x87_df, AL_Ib, AX_Ib, Ib_AL, Ib_AX, Gv_Ew_LAR, Gv_Ew_LSL, // Gdq_Ev, Gd_Ev, Gv_Ev_Ib, Gv_Ev_Iv, AX_DX, AL_DX, DX_AX, DX_AL, MOVQ_f30f, Yv_Xv, Gd_Ed, // Mdq_Gdq, Md_Gd, AL_Ob, AL_Xb, AX_Ov, G_xmm_E_mm, G_xmm_U_mm, G_mm_U_xmm, Rv_Gmm_Ib, G_xmm_Ed, G_mm_E_xmm, Gd_U_xmm, Gd_Eq_xmm, Gv_E_xmm, G_xmm_Ew_Ib, G_E_xmm_Ub, G_U_xmm_Ub, G_U_xmm, M_G_xmm, G_E_mm, G_U_mm, E_G_mm, Ed_G_mm, G_mm_Ed, G_mm_E, Ev_Gv_Ib, Ev_Gv_CL, G_mm_U_mm, G_Mq_mm, G_mm_Ew_Ib, G_E_q, E_G_q, CVT_AA, CVT_DA, Rq_Cq_0, Rq_Dq_0, Cq_Rq_0, Dq_Rq_0, FS, GS, Yb_DX, Yv_DX, DX_Xb, DX_Xv, AH, AX_Xv, Ew_Sw, Fw, I_1, Iw, Iw_Ib, Ob_AL, Ov_AX, Sw_Ew, Yb_AL, Yb_Xb, Yv_AX, Ew_Gw, ES, CS, SS, DS, ModRM_0x62, ModRM_0xc4, ModRM_0xc5, INV_Gv_M, PMOVX_G_E_xmm, PMOVX_E_G_xmm, G_Ev_xmm_Ib, G_E_mm_Ib, AbsFar, MOVDIR64B, ModRM_0x0f00, ModRM_0x0f01, ModRM_0x0f0d, ModRM_0x0f0f, ModRM_0x0f12, ModRM_0x0f16, ModRM_0x0f18, ModRM_0x0f71, ModRM_0x0f72, ModRM_0x0f73, ModRM_0x0fae, ModRM_0x0fba, ModRM_0x0fc7, ModRM_0x660f78, ModRM_0xf20f78, ModRM_0xf30f1e, ModRM_0xf30f38d8, ModRM_0xf30f38dc, ModRM_0xf30f38dd, ModRM_0xf30f38de, ModRM_0xf30f38df, ModRM_0xf30f38fa, ModRM_0xf30f38fb, ModRM_0xf30f3af0, } #[allow(non_camel_case_types)] #[repr(u16)] #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum OperandCode { Ivs = OperandCodeBuilder::new().operand_case(OperandCase::Ivs).bits(), I_3 = OperandCodeBuilder::new().operand_case(OperandCase::I_3).bits(), Nothing = OperandCodeBuilder::new().operand_case(OperandCase::Nothing).bits(), Ib = OperandCodeBuilder::new().operand_case(OperandCase::Ib).bits(), Ibs = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Ibs).bits(), Jvds = OperandCodeBuilder::new().only_imm().operand_case(OperandCase::Jvds).bits(), Yv_Xv = OperandCodeBuilder::new().operand_case(OperandCase::Yv_Xv).bits(), x87_d8 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d8).bits(), x87_d9 = OperandCodeBuilder::new().operand_case(OperandCase::x87_d9).bits(), x87_da = OperandCodeBuilder::new().operand_case(OperandCase::x87_da).bits(), x87_db = OperandCodeBuilder::new().operand_case(OperandCase::x87_db).bits(), x87_dc = OperandCodeBuilder::new().operand_case(OperandCase::x87_dc).bits(), x87_dd = OperandCodeBuilder::new().operand_case(OperandCase::x87_dd).bits(), x87_de = OperandCodeBuilder::new().operand_case(OperandCase::x87_de).bits(), x87_df = OperandCodeBuilder::new().operand_case(OperandCase::x87_df).bits(), Eb_R0 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::SingleMMMOper) .bits(), AL_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ib).bits(), AX_Ib = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ib).bits(), Ib_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AL).bits(), Ib_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ib_AX).bits(), AX_DX = OperandCodeBuilder::new().operand_case(OperandCase::AX_DX).bits(), AL_DX = OperandCodeBuilder::new().operand_case(OperandCase::AL_DX).bits(), DX_AX = OperandCodeBuilder::new().operand_case(OperandCase::DX_AX).bits(), DX_AL = OperandCodeBuilder::new().operand_case(OperandCase::DX_AL).bits(), MOVQ_f30f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::MOVQ_f30f).bits(), // Unsupported = OperandCodeBuilder::new().operand_case(49).bits(), ModRM_0x0f00 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f00).bits(), ModRM_0x0f01 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0f01).bits(), ModRM_0x0f0d = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0d).bits(), ModRM_0x0f0f = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f0f).bits(), // 3dnow ModRM_0x0fae = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fae).bits(), ModRM_0x0fba = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fba).bits(), // ModRM_0xf30fae = OperandCodeBuilder::new().read_modrm().operand_case(46).bits(), // ModRM_0x660fae = OperandCodeBuilder::new().read_modrm().operand_case(47).bits(), // ModRM_0xf30fc7 = OperandCodeBuilder::new().read_modrm().operand_case(48).bits(), // ModRM_0x660f38 = OperandCodeBuilder::new().read_modrm().operand_case(49).bits(), // ModRM_0xf20f38 = OperandCodeBuilder::new().read_modrm().operand_case(50).bits(), // ModRM_0xf30f38 = OperandCodeBuilder::new().read_modrm().operand_case(51).bits(), ModRM_0xf30f38d8 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38d8).bits(), ModRM_0xf30f38dc = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dc).bits(), ModRM_0xf30f38dd = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38dd).bits(), ModRM_0xf30f38de = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38de).bits(), ModRM_0xf30f38df = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38df).bits(), ModRM_0xf30f38fa = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fa).bits(), ModRM_0xf30f38fb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0xf30f38fb).bits(), ModRM_0xf30f3af0 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf30f3af0).bits(), // ModRM_0x660f3a = OperandCodeBuilder::new().read_modrm().operand_case(52).bits(), // ModRM_0x0f38 = OperandCodeBuilder::new().read_modrm().operand_case(53).bits(), // ModRM_0x0f3a = OperandCodeBuilder::new().read_modrm().operand_case(54).bits(), ModRM_0x0f71 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f71).bits(), ModRM_0x0f72 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f72).bits(), ModRM_0x0f73 = OperandCodeBuilder::new().read_E().operand_case(OperandCase::ModRM_0x0f73).bits(), ModRM_0xf20f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0xf20f78).bits(), ModRM_0x660f78 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x660f78).bits(), ModRM_0xf30f1e = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xf30f1e).bits(), // ModRM_0x660f72 = OperandCodeBuilder::new().read_modrm().operand_case(61).bits(), // ModRM_0x660f73 = OperandCodeBuilder::new().read_modrm().operand_case(62).bits(), // ModRM_0x660fc7 = OperandCodeBuilder::new().read_modrm().operand_case(63).bits(), ModRM_0x0fc7 = OperandCodeBuilder::new().read_modrm().operand_case(OperandCase::ModRM_0x0fc7).bits(), // xmmword? ModRM_0x0f12 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f12) .bits(), // xmmword? ModRM_0x0f16 = OperandCodeBuilder::new() .read_modrm() .read_E() .reg_mem() .operand_case(OperandCase::ModRM_0x0f16) .bits(), // encode immediates? ModRM_0xc0_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xc1_Ev_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseWithI8) .bits(), ModRM_0xd0_Eb_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ShiftBy1_b) .bits(), ModRM_0xd1_Ev_1 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ShiftBy1_v) .bits(), ModRM_0xd2_Eb_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0xd3_Ev_CL = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BitwiseByCL) .bits(), ModRM_0x80_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::BaseOpWithI8) .bits(), ModRM_0x83_Ev_Ibs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x83) .bits(), // this would be Eb_Ivs, 0x8e ModRM_0x81_Ev_Ivs = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::BaseOpWithIv) .bits(), ModRM_0xc6_Eb_Ib = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::MovI8) .bits(), ModRM_0xc7_Ev_Iv = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::MovIv) .bits(), ModRM_0xfe_Eb = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xfe) .bits(), ModRM_0x8f_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x8f) .bits(), // gap, 0x94 ModRM_0xff_Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xff) .bits(), ModRM_0x0f18 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0x0f18) .bits(), ModRM_0xf6 = OperandCodeBuilder::new() .read_modrm() .read_E() .byte_operands() .operand_case(OperandCase::ModRM_0xf6) .bits(), ModRM_0xf7 = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::ModRM_0xf7) .bits(), Ev = OperandCodeBuilder::new() .read_modrm() .read_E() .operand_case(OperandCase::SingleMMMOper) .bits(), Zv_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 0).bits(), Zv_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 1).bits(), Zv_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 2).bits(), Zv_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 3).bits(), Zv_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 4).bits(), Zv_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 5).bits(), Zv_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 6).bits(), Zv_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_R, 7).bits(), // Zv_AX_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 0).bits(), Zv_AX_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 1).bits(), Zv_AX_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 2).bits(), Zv_AX_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 3).bits(), Zv_AX_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 4).bits(), Zv_AX_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 5).bits(), Zv_AX_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 6).bits(), Zv_AX_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_AX, 7).bits(), Zb_Ib_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 0).bits(), Zb_Ib_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 1).bits(), Zb_Ib_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 2).bits(), Zb_Ib_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 3).bits(), Zb_Ib_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 4).bits(), Zb_Ib_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 5).bits(), Zb_Ib_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 6).bits(), Zb_Ib_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zb_Ib_R, 7).bits(), Zv_Iv_R0 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 0).bits(), Zv_Iv_R1 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 1).bits(), Zv_Iv_R2 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 2).bits(), Zv_Iv_R3 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 3).bits(), Zv_Iv_R4 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 4).bits(), Zv_Iv_R5 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 5).bits(), Zv_Iv_R6 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 6).bits(), Zv_Iv_R7 = OperandCodeBuilder::new().op0_is_rrr_and_Z_operand(ZOperandCategory::Zv_Iv_R, 7).bits(), Gv_Eb = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Eb).bits(), Gv_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew).bits(), Gv_Ew_LAR = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LAR).bits(), Gv_Ew_LSL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gv_Ew_LSL).bits(), // Gdq_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gdq_Ed).bits(), Gd_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ed).bits(), Md_Gd = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::Md_Gd).bits(), // Edq_Gdq = OperandCodeBuilder::new().read_E().operand_case(49).bits(), Gd_Ev = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Gd_Ev).bits(), // Md_Gd = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Md_Gd).bits(), G_E_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ib).bits(), G_E_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_xmm_Ub).bits(), G_U_xmm_Ub = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_U_xmm_Ub).bits(), AL_Ob = OperandCodeBuilder::new().operand_case(OperandCase::AL_Ob).bits(), AL_Xb = OperandCodeBuilder::new().operand_case(OperandCase::AL_Xb).bits(), AX_Ov = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ov).bits(), AL_Ibs = OperandCodeBuilder::new().byte_operands().operand_case(OperandCase::AL_Ibs).bits(), AX_Ivd = OperandCodeBuilder::new().operand_case(OperandCase::AX_Ivd).bits(), Eb_Gb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Ev_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().operand_case(OperandCase::Internal).bits(), Gb_Eb = OperandCodeBuilder::new().read_E().byte_operands().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_Ev = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().operand_case(OperandCase::Internal).bits(), Gv_M = OperandCodeBuilder::new().read_E().only_modrm_operands().reg_mem().deny_regmmm().operand_case(OperandCase::Gv_M).bits(), MOVDIR64B = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::MOVDIR64B).bits(), M_Gv = OperandCodeBuilder::new().read_E().only_modrm_operands().mem_reg().deny_regmmm().operand_case(OperandCase::Internal).bits(), Gv_Ev_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Ib).bits(), Gv_Ev_Iv = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_Ev_Iv).bits(), Rv_Gmm_Ib = OperandCodeBuilder::new().read_modrm().read_E().reg_mem().operand_case(OperandCase::Rv_Gmm_Ib).bits(), // gap, 0x9a G_xmm_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_E_mm).bits(), G_xmm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_U_mm).bits(), G_mm_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_xmm).bits(), G_xmm_Ed = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Ed).bits(), G_mm_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_E_xmm).bits(), Gd_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gd_U_xmm).bits(), Gd_Eq_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gd_Eq_xmm).bits(), Gv_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::Gv_E_xmm).bits(), //= 0x816f, // mirror G_xmm_Ed, but also read an immediate G_xmm_Ew_Ib = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_xmm_Ew_Ib).bits(), G_U_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_xmm).bits(), G_M_xmm = OperandCodeBuilder::new().read_E().reg_mem().deny_regmmm().operand_case(OperandCase::G_M_xmm).bits(), G_E_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_xmm).bits(), E_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_xmm).bits(), G_Ed_xmm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Ed_xmm).bits(), Ed_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Ed_G_xmm).bits(), M_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().deny_regmmm().operand_case(OperandCase::M_G_xmm).bits(), G_E_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_E_mm).bits(), G_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_U_mm).bits(), E_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::E_G_mm).bits(), Ed_G_mm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Ed_G_mm).bits(), // Edq_G_xmm = OperandCodeBuilder::new().read_E().mem_reg().operand_case(OperandCase::Edq_G_xmm).bits(), G_mm_Ed = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Ed).bits(), G_mm_E = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_E).bits(), Ev_Gv_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_Ib).bits(), Ev_Gv_CL = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ev_Gv_CL).bits(), G_mm_U_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_mm_U_mm).bits(), G_Mq_mm = OperandCodeBuilder::new().read_E().reg_mem().operand_case(OperandCase::G_Mq_mm).bits(), G_mm_Ew_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_mm_Ew_Ib).bits(), G_E_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_q).bits(), E_G_q = OperandCodeBuilder::new().read_E().operand_case(OperandCase::E_G_q).bits(), CVT_AA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_AA).bits(), CVT_DA = OperandCodeBuilder::new().operand_case(OperandCase::CVT_DA).bits(), Rq_Cq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Cq_0).bits(), Rq_Dq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Rq_Dq_0).bits(), Cq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Cq_Rq_0).bits(), Dq_Rq_0 = OperandCodeBuilder::new().operand_case(OperandCase::Dq_Rq_0).bits(), FS = OperandCodeBuilder::new().operand_case(OperandCase::FS).bits(), GS = OperandCodeBuilder::new().operand_case(OperandCase::GS).bits(), Yb_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yb_DX).bits(), Yv_DX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_DX).bits(), DX_Xb = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xb).bits(), DX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::DX_Xv).bits(), AH = OperandCodeBuilder::new().operand_case(OperandCase::AH).bits(), AX_Xv = OperandCodeBuilder::new().operand_case(OperandCase::AX_Xv).bits(), Ew_Sw = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Ew_Sw).bits(), Fw = OperandCodeBuilder::new().operand_case(OperandCase::Fw).bits(), I_1 = OperandCodeBuilder::new().operand_case(OperandCase::I_1).bits(), Iw = OperandCodeBuilder::new().operand_case(OperandCase::Iw).bits(), Iw_Ib = OperandCodeBuilder::new().operand_case(OperandCase::Iw_Ib).bits(), Ob_AL = OperandCodeBuilder::new().operand_case(OperandCase::Ob_AL).bits(), Ov_AX = OperandCodeBuilder::new().operand_case(OperandCase::Ov_AX).bits(), Sw_Ew = OperandCodeBuilder::new().read_E().operand_case(OperandCase::Sw_Ew).read_E().bits(), Yb_AL = OperandCodeBuilder::new().operand_case(OperandCase::Yb_AL).bits(), Yb_Xb = OperandCodeBuilder::new().operand_case(OperandCase::Yb_Xb).bits(), Yv_AX = OperandCodeBuilder::new().operand_case(OperandCase::Yv_AX).bits(), Ew_Gw = OperandCodeBuilder::new().operand_case(OperandCase::Ew_Gw).bits(), ES = OperandCodeBuilder::new().operand_case(OperandCase::ES).bits(), CS = OperandCodeBuilder::new().operand_case(OperandCase::CS).bits(), SS = OperandCodeBuilder::new().operand_case(OperandCase::SS).bits(), DS = OperandCodeBuilder::new().operand_case(OperandCase::DS).bits(), ModRM_0x62 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0x62).bits(), INV_Gv_M = OperandCodeBuilder::new().read_E().deny_regmmm().operand_case(OperandCase::INV_Gv_M).bits(), PMOVX_G_E_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_G_E_xmm).bits(), PMOVX_E_G_xmm = OperandCodeBuilder::new().read_E().operand_case(OperandCase::PMOVX_E_G_xmm).bits(), G_Ev_xmm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_Ev_xmm_Ib).bits(), G_E_mm_Ib = OperandCodeBuilder::new().read_E().operand_case(OperandCase::G_E_mm_Ib).bits(), AbsFar = OperandCodeBuilder::new().operand_case(OperandCase::AbsFar).bits(), ModRM_0xc4 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xc4).bits(), ModRM_0xc5 = OperandCodeBuilder::new().operand_case(OperandCase::ModRM_0xc5).bits(), } fn base_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ADD, 1 => Opcode::OR, 2 => Opcode::ADC, 3 => Opcode::SBB, 4 => Opcode::AND, 5 => Opcode::SUB, 6 => Opcode::XOR, 7 => Opcode::CMP, _ => { unsafe { unreachable_unchecked() } } } } fn bitwise_opcode_map(v: u8) -> Opcode { match v { 0 => Opcode::ROL, 1 => Opcode::ROR, 2 => Opcode::RCL, 3 => Opcode::RCR, 4 => Opcode::SHL, 5 => Opcode::SHR, 6 => Opcode::SAL, 7 => Opcode::SAR, _ => { unsafe { unreachable_unchecked() } } } } #[derive(Copy, Clone, Debug, PartialEq, Eq)] enum Interpretation { Instruction(Opcode), Prefix, } #[derive(Copy, Clone, Debug, PartialEq)] // this should be a 32-byte struct.. struct OpcodeRecord(u64); //Interpretation, u32); // OperandCode); impl OpcodeRecord { const fn new(interp: Interpretation, code: OperandCode) -> Self { let interp_bits = unsafe { core::mem::transmute::(interp) as u64 }; let code_bits = code as u16 as u64; let stored_bits = interp_bits | (code_bits << 32); OpcodeRecord(stored_bits) } const fn interp(&self) -> Interpretation { unsafe { core::mem::transmute(self.0 as u32) } } const fn operand(&self) -> OperandCode { unsafe { core::mem::transmute((self.0 >> 32) as u16) } } } const OPCODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADD), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::ES), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::ES), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::OR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::CS), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADC), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::SS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::SS), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SBB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::DS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::DS), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::AND), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::DAA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUB), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::DAS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::XOR), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMP), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAS), OperandCode::Nothing), // 0x40: OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::INC), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::DEC), OperandCode::Zv_R7), // 0x50: OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::Zv_R7), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSHA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPA), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BOUND), OperandCode::ModRM_0x62), OpcodeRecord::new(Interpretation::Instruction(Opcode::ARPL), OperandCode::Ew_Gw), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yb_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::INS), OperandCode::Yv_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUTS), OperandCode::DX_Xv), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Ibs), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x80_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x81_Ev_Ivs), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x83_Ev_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gb_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ew_Sw), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEA), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Sw_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x8f_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::XCHG), OperandCode::Zv_AX_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_AA), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::CVT_DA), OpcodeRecord::new(Interpretation::Instruction(Opcode::CALLF), OperandCode::AbsFar), OpcodeRecord::new(Interpretation::Instruction(Opcode::WAIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSHF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAHF), OperandCode::AH), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AL_Ob), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::AX_Ov), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ob_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Ov_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yb_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPS), OperandCode::Yv_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AL_Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::TEST), OperandCode::AX_Ivd), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::STOS), OperandCode::Yv_AX), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AL_Xb), OpcodeRecord::new(Interpretation::Instruction(Opcode::LODS), OperandCode::AX_Xv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yb_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::SCAS), OperandCode::Yv_AX), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zb_Ib_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Zv_Iv_R7), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc0_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xc1_Ev_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETURN), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::LES), OperandCode::ModRM_0xc4), OpcodeRecord::new(Interpretation::Instruction(Opcode::LDS), OperandCode::ModRM_0xc5), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc6_Eb_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::ModRM_0xc7_Ev_Iv), OpcodeRecord::new(Interpretation::Instruction(Opcode::ENTER), OperandCode::Iw_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::LEAVE), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Iw), OpcodeRecord::new(Interpretation::Instruction(Opcode::RETF), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_3), OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::INTO), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::IRET), OperandCode::Fw), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd0_Eb_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd1_Ev_1), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd2_Eb_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xd3_Ev_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAM), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::AAD), OperandCode::Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SALC), OperandCode::Nothing), // XLAT OpcodeRecord::new(Interpretation::Instruction(Opcode::XLAT), OperandCode::Nothing), // x86 d8 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d8), // x86 d9 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_d9), // x86 da OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_da), // x86 db OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_db), // x86 dc OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dc), // x86 dd OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_dd), // x86 de OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_de), // x86 df OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::x87_df), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPNZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOPZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::LOOP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::JCXZ), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::Ib_AX), // 0xe8 OpcodeRecord::new(Interpretation::Instruction(Opcode::CALL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::JMP), OperandCode::Ibs), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AL_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::IN), OperandCode::AX_DX), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AL), OpcodeRecord::new(Interpretation::Instruction(Opcode::OUT), OperandCode::DX_AX), // 0xf0 OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // ICEBP? OpcodeRecord::new(Interpretation::Instruction(Opcode::INT), OperandCode::I_1), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), OpcodeRecord::new(Interpretation::Prefix, OperandCode::Nothing), // 0xf4 OpcodeRecord::new(Interpretation::Instruction(Opcode::HLT), OperandCode::Nothing), // CMC OpcodeRecord::new(Interpretation::Instruction(Opcode::CMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf6), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf7), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STI), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::STD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xfe_Eb), // TODO: test 0xff /3 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xff_Ev), ]; #[allow(non_snake_case)] #[inline(always)] pub(self) fn read_E< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_st< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { instr.regs[1] = RegSpec { bank: RegisterBank::ST, num: modrm & 7 }; Ok(OperandSpec::RegMMM) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_xmm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::X, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_ymm< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, RegisterBank::Y, sink) } else { read_M(words, instr, modrm, sink) } } #[allow(non_snake_case)] pub(self) fn read_E_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instr: &mut Instruction, modrm: u8, bank: RegisterBank, sink: &mut S) -> Result { if modrm >= 0b11000000 { read_modrm_reg(instr, words, modrm, bank, sink) } else { let res = read_M(words, instr, modrm, sink)?; if (modrm & 0b01_000_000) == 0b01_000_000 { instr.prefixes.apply_compressed_disp(true); } Ok(res) } } #[allow(non_snake_case)] #[inline(always)] fn read_modrm_reg< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &mut Instruction, words: &mut T, modrm: u8, reg_bank: RegisterBank, sink: &mut S) -> Result { instr.regs[1] = RegSpec::from_parts(modrm & 7, reg_bank); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 6, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(words.offset() as u32 * 8 - 8 + 2) ); Ok(OperandSpec::RegMMM) } #[inline(always)] fn read_sib_disp< T: Reader<::Address, ::Word>, S: DescriptionSink, >(instr: &Instruction, words: &mut T, modrm: u8, sibbyte: u8, sink: &mut S) -> Result { let sib_start = words.offset() as u32 * 8 - 8; let modbit_addr = words.offset() as u32 * 8 - 10; let disp_start = words.offset() as u32 * 8; let disp = if modrm < 0b01_000_000 { // modbits == 0b00 if (sibbyte & 7) == 0b101 { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); sink.record(sib_start, sib_start + 2, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { 0 } } else if modrm < 0b10_000_000 { // modbits == 0b01 sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("1-byte displacement").with_id(sib_start + 0)); if instr.prefixes.evex().is_some() { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("EVEX prefix implies displacement is scaled by vector size") .with_id(sib_start + 0)); } let disp = read_num(words, 1)? as i8 as i32; sink.record(disp_start, disp_start + 7, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp } else { sink.record(modbit_addr, modbit_addr + 1, InnerDescription::Misc("4-byte displacement").with_id(sib_start + 0)); let disp = read_num(words, 4)? as i32; sink.record(disp_start, disp_start + 31, InnerDescription::Number("displacement", disp as i64).with_id(sib_start + 1)); disp }; Ok(disp) } #[allow(non_snake_case)] #[inline(always)] fn read_sib< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let sib_start = words.offset() as u32 * 8; let sibbyte = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let disp = read_sib_disp(instr, words, modrm, sibbyte, sink)?; instr.disp = disp as u32; instr.regs[1].num |= sibbyte & 7; instr.regs[2].num |= (sibbyte >> 3) & 7; let scale = 1u8 << (sibbyte >> 6); instr.scale = scale; let op_spec = if disp == 0 { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address, but displacement is 0") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::Deref } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register") .with_id(sib_start + 0) ); OperandSpec::RegScale } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); OperandSpec::Deref } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScale } } } else { if (sibbyte & 7) == 0b101 { sink.record( sib_start, sib_start + 2, InnerDescription::Misc("bbb selects displacement in address") .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, absolute [disp32] only") .with_id(sib_start + 0) ); OperandSpec::DispU32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegDisp } } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); if modrm < 0b01_000_000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits select no base register, [index+disp] only") .with_id(sib_start + 0) ); OperandSpec::RegScaleDisp } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::RegisterNumber("mod", 0b101, instr.regs[1]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } } else { sink.record( sib_start + 0, sib_start + 2, InnerDescription::RegisterNumber("bbb", instr.regs[1].num, instr.regs[2]) .with_id(sib_start + 0) ); if instr.regs[2].num == 0b0100 { sink.record( sib_start + 3, sib_start + 5, InnerDescription::Misc("iii selects no index register") .with_id(sib_start + 0) ); OperandSpec::RegDisp } else { sink.record( sib_start + 3, sib_start + 5, InnerDescription::RegisterNumber("iii", instr.regs[2].num, instr.regs[2]) .with_id(sib_start + 0) ); OperandSpec::RegIndexBaseScaleDisp } } }; Ok(op_spec) } #[allow(non_snake_case)] fn read_M_16bit< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; let modbits = modrm >> 6; let mmm = modrm & 7; if modbits == 0b00 && mmm == 0b110 { instr.disp = read_num(words, 2)? as u16 as u32; return Ok(OperandSpec::DispU16); } match mmm { 0b000 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx + si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); instr.regs[2] = RegSpec::si(); }, 0b001 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx + di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); instr.regs[2] = RegSpec::di(); }, 0b010 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp + si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); instr.regs[2] = RegSpec::si(); }, 0b011 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp + di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); instr.regs[2] = RegSpec::di(); }, 0b100 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `si`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::si(); }, 0b101 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `di`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::di(); }, 0b110 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bp`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bp(); }, 0b111 => { sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("memory address includes `bx`") .with_id(modrm_start + 2) ); instr.regs[1] = RegSpec::bx(); }, _ => { unreachable!("impossible bit pattern"); } } match modbits { 0b00 => { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)] with no displacement, register(s) selected by `mmm` (mod bits: 00)") .with_id(modrm_start + 0) ); if mmm > 3 { Ok(OperandSpec::Deref) } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScale) } }, 0b01 => { let disp_start = words.offset() as u32 * 8; instr.disp = read_num(words, 1)? as i8 as i32 as u32; let disp_end = words.offset() as u32 * 8; sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)+disp8] indexed by register(s) selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); sink.record( disp_start, disp_end - 1, InnerDescription::Number("displacement", instr.disp as i64) .with_id(disp_start + 3) ); if mmm > 3 { if instr.disp != 0 { Ok(OperandSpec::RegDisp) } else { Ok(OperandSpec::Deref) } } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScaleDisp) } }, 0b10 => { let disp_start = words.offset() as u32 * 8; instr.disp = read_num(words, 2)? as i16 as i32 as u32; let disp_end = words.offset() as u32 * 8; sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg(s)+disp16] indexed by register(s) selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); sink.record( disp_start, disp_end - 1, InnerDescription::Number("displacement", instr.disp as i64) .with_id(disp_start + 3) ); if mmm > 3 { if instr.disp != 0 { Ok(OperandSpec::RegDisp) } else { Ok(OperandSpec::Deref) } } else { instr.scale = 1; Ok(OperandSpec::RegIndexBaseScaleDisp) } }, _ => { unreachable!("read_M_16but but mod bits were not a memory operand"); } } } #[allow(non_snake_case)] fn read_M< T: Reader<::Address, ::Word>, S: DescriptionSink >(words: &mut T, instr: &mut Instruction, modrm: u8, sink: &mut S) -> Result { let modrm_start = words.offset() as u32 * 8 - 8; // by default read M as a 16-bit size address if !instr.prefixes.address_size() { return read_M_16bit(words, instr, modrm, sink); } instr.regs[1].bank = RegisterBank::D; let modbits = modrm >> 6; let mmm = modrm & 7; let op_spec = if mmm == 4 { sink.record( modrm_start, modrm_start + 2, InnerDescription::Misc("`mmm` field selects sib access") .with_id(modrm_start + 2) ); return read_sib(words, instr, modrm, sink); } else if mmm == 5 && modbits == 0b00 { // TODO: uhhhh sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("absolute disp32") .with_id(modrm_start + 0) ); sink.record( modrm_start + 0, modrm_start + 2, InnerDescription::Misc("absolute disp32") .with_id(modrm_start + 0) ); instr.disp = read_num(words, 4)?; OperandSpec::DispU32 } else { instr.regs[1].num |= mmm; sink.record( modrm_start, modrm_start + 2, InnerDescription::RegisterNumber("mmm", modrm & 7, instr.regs[1]) .with_id(modrm_start + 2) ); if modbits == 0b00 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg] with no displacement, register selected by `mmm` (mod bits: 00)") .with_id(modrm_start + 0) ); OperandSpec::Deref } else { let disp_start = words.offset(); let disp = if modbits == 0b01 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp8] indexed by register selected by `mmm` (mod bits: 01)") .with_id(modrm_start + 0) ); read_num(words, 1)? as i8 as i32 } else { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("memory operand is [reg+disp32] indexed by register(s) selected by `mmm` (mod bits: 10)") .with_id(modrm_start + 0) ); read_num(words, 4)? as i32 }; let disp_end = words.offset(); sink.record( disp_start as u32 * 8, disp_end as u32 * 8 - 1, InnerDescription::Number("displacement", disp as i64) .with_id(words.offset() as u32 * 8 + 3) ); if disp == 0 { OperandSpec::Deref } else { instr.disp = disp as i32 as u32; OperandSpec::RegDisp } } }; Ok(op_spec) } /// the actual description for a selection of bits involved in decoding a [`real_mode::Instruction`]. /// /// some prefixes are only identified as an `InnerDescription::Misc` string, while some are full /// `InnerDescription::SegmentPrefix(Segment)`. generally, strings should be considered unstable /// and only useful for displaying for human consumption. #[derive(Clone, Debug, PartialEq, Eq)] pub enum InnerDescription { /// the literal byte read for a `rex` prefix, `0x4_`. while 32-bit code does not have `rex` /// prefixes, this description is also used for the implied `rex`-type bits in `vex` and `evex` /// prefixes. RexPrefix(u8), /// the segment selected by a segment override prefix. this is not necessarily the actual /// segement used in the instruction's memory accesses, if any are made. SegmentPrefix(Segment), /// the opcode read for this instruction. this may be reported multiple times in an instruction /// if multiple spans of bits are necessary to determine the opcode. it is a bug if two /// different `Opcode` are indicated by different `InnerDescription::Opcode` reported from /// decoding the same instruction. this invariant is not well-tested, and may occur in /// practice. Opcode(Opcode), /// the operand code indicating how to read operands for this instruction. this is an internal /// detail of `yaxpeax-x86` but is typically named in a manner that can aid understanding the /// decoding process. `OperandCode` names are unstable, and this variant is only useful for /// displaying for human consumption. OperandCode(OperandCodeWrapper), /// a decoded register: a name for the bits used to decode it, the register number those bits /// specify, and the fully-constructed [`long_mode::RegSpec`] that was decoded. RegisterNumber(&'static str, u8, RegSpec), /// a miscellaneous string describing some bits of the instruction. this may describe a prefix, /// internal details of a prefix, error or constraints on an opcode, operand encoding details, /// or other items involved in an instruction. Misc(&'static str), /// a number involved in the instruction: typically either a disaplacement or immediate. the /// string describes which. the `i64` member is typically a sign-extended value from the /// appropriate original size, meaning there may be incorrect cases of a `65535u16` sign /// extending to `-1`. bug reports are highly encouraged for unexpected values. Number(&'static str, i64), /// a boundary between two logically distinct sections of an instruction. these typically /// separate the leading prefix string (if any), opcode, and operands (if any). the included /// string describes which boundary this is. boundary names should not be considered stable, /// and are useful at most for displaying for human consumption. Boundary(&'static str), } impl InnerDescription { fn with_id(self, id: u32) -> FieldDescription { FieldDescription { desc: self, id, } } } cfg_if::cfg_if! { if #[cfg(feature="fmt")] { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { match self { InnerDescription::RexPrefix(bits) => { write!(f, "rex prefix: {}{}{}{}", if bits & 0x8 != 0 { "w" } else { "-" }, if bits & 0x4 != 0 { "r" } else { "-" }, if bits & 0x2 != 0 { "x" } else { "-" }, if bits & 0x1 != 0 { "b" } else { "-" }, ) } InnerDescription::SegmentPrefix(segment) => { write!(f, "segment override: {}", segment) } InnerDescription::Misc(text) => { f.write_str(text) } InnerDescription::Number(text, num) => { write!(f, "{}: {:#x}", text, num) } InnerDescription::Opcode(opc) => { write!(f, "opcode `{}`", opc) } InnerDescription::OperandCode(OperandCodeWrapper { code }) => { write!(f, "operand code `{:?}`", code) } InnerDescription::RegisterNumber(name, num, reg) => { write!(f, "`{}` (`{}` selects register number {})", reg, name, num) } InnerDescription::Boundary(desc) => { write!(f, "{}", desc) } } } } } else { impl fmt::Display for InnerDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { f.write_str("non-fmt build") } } } } // TODO: this derive ought to be `feature=fmt`.. #[derive(Clone, PartialEq, Eq, Debug)] pub struct FieldDescription { desc: InnerDescription, id: u32, } impl FieldDescription { /// the actual description associated with this bitfield. pub fn desc(&self) -> &InnerDescription { &self.desc } } impl yaxpeax_arch::annotation::FieldDescription for FieldDescription { fn id(&self) -> u32 { self.id } fn is_separator(&self) -> bool { if let InnerDescription::Boundary(_) = &self.desc { true } else { false } } } impl fmt::Display for FieldDescription { fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result { fmt::Display::fmt(&self.desc, f) } } #[inline(always)] fn record_opcode_record_found< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, sink: &mut S, opc: Opcode, code: OperandCode, opc_length: u32) { let offset = words.offset() as u32; let opcode_start_bit = (offset - opc_length) * 8; let opcode_end_bit = offset * 8 - 1; if offset > opc_length { sink.record( opcode_start_bit - 1, opcode_start_bit - 1, InnerDescription::Boundary("prefixes end") .with_id(opcode_start_bit) ); } if opc != Opcode::Invalid { sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::Opcode(opc), id: offset * 8 - opc_length * 8, }); } sink.record(opcode_start_bit, opcode_end_bit, FieldDescription { desc: InnerDescription::OperandCode(OperandCodeWrapper { code }), id: offset * 8 - opc_length * 8 + 1, }); } #[derive(Copy, Clone)] struct DecodeCtx { check_lock: bool, rrr: u8, } impl DecodeCtx { fn new() -> Self { DecodeCtx { check_lock: false, rrr: 0 } } fn read_opc_hotpath< T: Reader<::Address, ::Word>, S: DescriptionSink, >(&mut self, mut b: u8, nextb: &mut u8, record: &mut OpcodeRecord, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result { if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 32 bits)"), id: words.offset() as u32 * 8 - 8, }); b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; *record = OPCODES[b as usize]; instruction.prefixes.set_operand_size(); } if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); instruction.opcode = opc; return Ok(true); } else if b == 0x0f { if words.offset() > 1 { sink.record( words.offset() as u32 * 8 - 8 - 1, words.offset() as u32 * 8 - 8 - 1, InnerDescription::Boundary("prefixes end") .with_id(words.offset() as u32 * 8 - 9) ); } let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (r, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, &mut instruction.prefixes), 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, &mut instruction.prefixes), 3) } else { (self.read_0f_opcode(b, &mut instruction.prefixes), 2) }; *record = r; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); instruction.opcode = opc; } else { unsafe { unreachable_unchecked(); } } return Ok(true); } else { *nextb = b; return Ok(false); } } fn read_with_annotations< T: Reader<::Address, ::Word>, S: DescriptionSink, >(&mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { words.mark(); let mut nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let mut next_rec = OPCODES[nextb as usize]; instruction.prefixes = Prefixes::new(0); // default registers to `[eax; 4]` // instruction.regs = unsafe { core::mem::transmute(0u64) }; // default operands to [RegRRR, Nothing, Nothing, Nothing] // instruction.operands = unsafe { core::mem::transmute(0x00_00_00_01) }; instruction.regs[1] = RegSpec::ax(); instruction.regs[2] = RegSpec::ax(); let record: OperandCode = if self.read_opc_hotpath(nextb, &mut nextb, &mut next_rec, words, instruction, sink)? { next_rec.operand() } else { let prefixes = &mut instruction.prefixes; let record = loop { let record = next_rec; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), 1); break record; } else { let b = nextb; if b == 0x0f { if words.offset() > 1 { sink.record( words.offset() as u32 * 8 - 8 - 1, words.offset() as u32 * 8 - 8 - 1, InnerDescription::Boundary("prefixes end") .with_id(words.offset() as u32 * 8 - 9) ); } let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let (rec, len) = if b == 0x38 { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f38_opcode(b, prefixes), 3) } else if b == 0x3a { let b = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; (self.read_0f3a_opcode(b, prefixes), 3) } else { (self.read_0f_opcode(b, prefixes), 2) }; if let Interpretation::Instruction(opc) = record.interp() { record_opcode_record_found(words, sink, opc, record.operand(), len); } break rec; } if b == 0x66 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("operand size override (to 32 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_operand_size(); } else if b == 0x67 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("address size override (to 32 bits)"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_address_size(); } else if b == 0xf2 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("repnz prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_repnz(); } else if b == 0xf3 { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("rep prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_rep(); } else { match b { 0x26 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::ES), id: words.offset() as u32 * 8 - 8, }); prefixes.set_es(); }, 0x2e => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::CS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_cs(); }, 0x36 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::SS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_ss(); }, 0x3e => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::DS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_ds(); }, 0x64 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::FS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_fs(); }, 0x65 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::SegmentPrefix(Segment::GS), id: words.offset() as u32 * 8 - 8, }); prefixes.set_gs(); }, 0xf0 => { sink.record((words.offset() - 1) as u32 * 8, (words.offset() - 1) as u32 * 8 + 7, FieldDescription { desc: InnerDescription::Misc("lock prefix"), id: words.offset() as u32 * 8 - 8, }); prefixes.set_lock(); self.check_lock = true; }, // unlike 64-bit mode, the vex/evex prefixes are not recorded as prefixes - // they are LES/LDS/BOUND with special-case operand decoding. so we've // actually handled all possible prefixes at this point. _ => { unsafe { unreachable_unchecked(); } } } } nextb = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; next_rec = OPCODES[nextb as usize]; } if words.offset() >= 15 { return Err(DecodeError::TooLong); } }; if let Interpretation::Instruction(opcode) = record.interp() { instruction.opcode = opcode; } else { unsafe { unreachable_unchecked(); } } record.operand() }; self.read_operands(decoder, words, instruction, record, sink)?; if self.check_lock { if (instruction.opcode as u32) < 0x1000 || !instruction.operands[0].is_memory() { return Err(DecodeError::InvalidPrefixes); } } Ok(()) } fn read_operands< T: Reader<::Address, ::Word>, S: DescriptionSink >(&mut self, decoder: &InstDecoder, words: &mut T, instruction: &mut Instruction, operand_code: OperandCode, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 1, words.offset() as u32 * 8 - 1, InnerDescription::Boundary("opcode ends/operands begin (typically)") .with_id(words.offset() as u32 * 8 - 1) ); let operand_code = OperandCodeBuilder::from_bits(operand_code as u16); let modrm_start = words.offset() as u32 * 8; let opcode_start = modrm_start - 8; if operand_code.is_only_modrm_operands() { let bank; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E bank = if instruction.prefixes.operand_size() || instruction.opcode == Opcode::ADCX || instruction.opcode == Opcode::ADOX { RegisterBank::D } else { RegisterBank::W }; instruction.mem_size = bank as u8; } else { bank = RegisterBank::B; instruction.mem_size = 1; }; let modrm = read_modrm(words)?; instruction.regs[0].bank = bank; instruction.regs[0].num = (modrm >> 3) & 7; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", (modrm >> 3) & 7, instruction.regs[0]) .with_id(modrm_start + 3) ); } let mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } instruction.operand_count = 2; return Ok(()); } if operand_code.has_imm() { instruction.mem_size = 0; if operand_code.operand_case_handler_index() == OperandCase::Ibs { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmI8; } else { instruction.imm = read_imm_signed(words, 2)? as u32; sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 1, InnerDescription::Number("2-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); if instruction.opcode == Opcode::CALL { instruction.mem_size = 2; } instruction.operands[0] = OperandSpec::ImmI32; } instruction.operand_count = 1; return Ok(()); } let mut mem_oper = OperandSpec::Nothing; if operand_code.has_read_E() { let bank; // cool! we can precompute width and know we need to read_E. if !operand_code.has_byte_operands() { // further, this is an vdq E, but adcx is always 32-bit operands bank = if instruction.prefixes.operand_size() || instruction.opcode == Opcode::ADCX || instruction.opcode == Opcode::ADOX { RegisterBank::D } else { RegisterBank::W }; instruction.mem_size = bank as u8; } else { bank = RegisterBank::B; instruction.mem_size = 1; }; let modrm = read_modrm(words)?; instruction.regs[0].bank = bank; let rrr = (modrm >> 3) & 7; self.rrr = rrr; instruction.regs[0].num = rrr; // for some encodings, the rrr field selects an opcode, not an operand if operand_code.bits() != OperandCode::ModRM_0xc1_Ev_Ib as u16 && operand_code.bits() != OperandCode::ModRM_0xff_Ev as u16 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start + 3) ); } mem_oper = if modrm >= 0b11000000 { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mmm field is a register number (mod bits: 11)") .with_id(modrm_start + 0) ); if operand_code.denies_regmmm() { return Err(DecodeError::InvalidOperand); } read_modrm_reg(instruction, words, modrm, bank, sink)? } else { read_M(words, instruction, modrm, sink)? }; if !operand_code.has_reg_mem() { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; } else { instruction.operands[1] = mem_oper; instruction.operands[0] = OperandSpec::RegRRR; } } else { instruction.mem_size = 0; } if let Some(z_operand_code) = operand_code.get_embedded_instructions() { instruction.operands[0] = OperandSpec::RegRRR; let reg = z_operand_code.reg(); match z_operand_code.category() { 0 => { // these are Zv_R let bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[0] = RegSpec::from_parts(reg, bank); instruction.mem_size = 2; sink.record( opcode_start + 0, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); instruction.operand_count = 1; } 1 => { // Zv_AX let bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[0] = RegSpec::from_parts(0, bank); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(reg, bank); sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("opcode selects `ax` operand") .with_id(opcode_start + 2) ); if instruction.prefixes.operand_size() { sink.record( opcode_start + 3, opcode_start + 7, InnerDescription::Misc("operand-size prefix override selects `eax`") .with_id(opcode_start + 2) ); } instruction.operand_count = 2; } 2 => { // these are Zb_Ib_R instruction.regs[0] = RegSpec { num: reg, bank: RegisterBank::B, }; sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 1) ); instruction.imm = read_imm_unsigned(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8)); instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } 3 => { // category == 3, Zv_Iv_R if !instruction.prefixes.operand_size() { instruction.regs[0] = RegSpec::from_parts(reg, RegisterBank::W); instruction.imm = read_num(words, 2)? as u16 as u32; instruction.operands[1] = OperandSpec::ImmI16; let width = 2; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } else { instruction.regs[0] = RegSpec::from_parts(reg, RegisterBank::D); instruction.imm = read_num(words, 4)? as u32; instruction.operands[1] = OperandSpec::ImmI32; let width = 4; sink.record( words.offset() as u32 * 8 - (8 * width as u32), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (8 * width as u32) + 1) ); } sink.record( opcode_start, opcode_start + 2, InnerDescription::RegisterNumber("zzz", reg, instruction.regs[0]) .with_id(opcode_start + 2) ); instruction.operand_count = 2; } _ => { unreachable!("bad category"); } } return Ok(()); } if !operand_code.has_read_E() { instruction.operands = [OperandSpec::RegRRR, OperandSpec::Nothing, OperandSpec::Nothing, OperandSpec::Nothing]; } instruction.operand_count = 2; // match operand_code { match operand_code.operand_case_handler_index() { // these operand cases are all `only_*`, and are unreachable here.. OperandCase::Internal | OperandCase::Gv_M | OperandCase::Ibs | OperandCase::Jvds => { } OperandCase::SingleMMMOper => { instruction.operands[0] = mem_oper; instruction.operand_count = 1; }, OperandCase::BaseOpWithI8 => { instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); } OperandCase::BaseOpWithIv => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if !instruction.prefixes.operand_size() { let opwidth = 2; instruction.imm = read_imm_signed(words, opwidth)? as u32; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); instruction.operands[1] = OperandSpec::ImmI16; } else { let opwidth = 4; instruction.imm = read_imm_signed(words, opwidth)? as u32; sink.record( words.offset() as u32 * 8 - (opwidth as u32 * 8), words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - (opwidth as u32 * 8)) ); instruction.operands[1] = OperandSpec::ImmI32; } }, OperandCase::MovI8 => { if self.rrr != 0 { if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XABORT; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8) ); instruction.operands[0] = OperandSpec::ImmI8; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 1 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } OperandCase::MovIv => { if self.rrr != 0 { let opwidth = instruction.regs[0].bank as u8; if mem_oper == OperandSpec::RegMMM && instruction.regs[1].num & 0b0111 == 0 { instruction.opcode = Opcode::XBEGIN; instruction.imm = if opwidth == 2 { let imm = read_imm_signed(words, 2)? as i16 as i32 as u32; sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 16) ); imm } else { let imm = read_imm_signed(words, 4)? as i32 as u32; sink.record( words.offset() as u32 * 8 - 32, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 32) ); imm }; instruction.operands[0] = OperandSpec::ImmI32; instruction.operand_count = 1; return Ok(()); } sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr field: must be zero") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOperand); // Err("Invalid modr/m for opcode 0xc7".to_string()); } instruction.operands[0] = mem_oper; instruction.opcode = Opcode::MOV; if !instruction.prefixes.operand_size() { instruction.imm = read_imm_signed(words, 2)? as u32; sink.record( modrm_start + 8, modrm_start + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI16; } else { instruction.imm = read_imm_signed(words, 4)? as u32; sink.record( modrm_start + 8, modrm_start + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI32; } }, OperandCase::BitwiseWithI8 => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = read_num(words, 1)?; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", num as i64) .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::ShiftBy1_v | OperandCase::ShiftBy1_b => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); let num = 1; sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Misc("opcode specifies integer immediate 1") .with_id(modrm_start - 8) ); instruction.imm = num; instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::BitwiseByCL => { instruction.operands[0] = mem_oper; instruction.opcode = bitwise_opcode_map(self.rrr); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.regs[0] = RegSpec::cl(); sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::RegisterNumber("reg", 1, instruction.regs[0]) .with_id(modrm_start - 7) ); instruction.operands[1] = OperandSpec::RegRRR; }, OperandCase::ModRM_0xf6 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { instruction.opcode = Opcode::TEST; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; sink.record( modrm_start + 8, modrm_start + 8 + 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xf7 => { instruction.operands[0] = mem_oper; const TABLE: [Opcode; 8] = [ Opcode::TEST, Opcode::TEST, Opcode::NOT, Opcode::NEG, Opcode::MUL, Opcode::IMUL, Opcode::DIV, Opcode::IDIV, ]; instruction.opcode = TABLE[self.rrr as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); if self.rrr < 2 { if !instruction.prefixes.operand_size() { instruction.imm = read_imm_signed(words, 2)? as u32; instruction.operands[1] = OperandSpec::ImmI16; sink.record( modrm_start + 8, modrm_start + 8 + 2 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); } else { instruction.imm = read_imm_signed(words, 4)? as u32; sink.record( modrm_start + 8, modrm_start + 8 + 4 as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(modrm_start + 8) ); instruction.operands[1] = OperandSpec::ImmI32; }; } else { instruction.operand_count = 1; } }, OperandCase::ModRM_0xfe => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 2 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("invalid rrr: opcode requires rrr < 0b010") .with_id(modrm_start - 8) ); return Err(DecodeError::InvalidOpcode); } instruction.opcode = [ Opcode::INC, Opcode::DEC, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operand_count = 1; } OperandCase::ModRM_0xff => { instruction.operands[0] = mem_oper; let r = self.rrr; if r == 7 { return Err(DecodeError::InvalidOpcode); } const TABLE: [Opcode; 7] = [ Opcode::INC, Opcode::DEC, Opcode::CALL, Opcode::CALLF, Opcode::JMP, Opcode::JMPF, Opcode::PUSH, ]; let opcode = TABLE[r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(opcode) .with_id(modrm_start - 8) ); if instruction.operands[0] == OperandSpec::RegMMM { // in real mode, `xed` reports that operand-size does in fact override from word to // dword. unlikely larger modes, operand-size can't shrink the call operand down. if opcode == Opcode::CALL { instruction.mem_size = 2; } else if opcode == Opcode::PUSH || opcode == Opcode::POP { if !instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { return Err(DecodeError::InvalidOperand); } } else { if opcode == Opcode::CALL || opcode == Opcode::JMP || opcode == Opcode::PUSH || opcode == Opcode::POP { if !instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } } else if opcode == Opcode::CALLF || opcode == Opcode::JMPF { instruction.mem_size = 4; } } instruction.opcode = opcode; instruction.operand_count = 1; } OperandCase::Gv_Eb => { let w = RegisterBank::B; instruction.operands[1] = mem_oper; // crc32 is always 32-bits in the first operand if instruction.opcode == Opcode::CRC32 { instruction.regs[0].bank = RegisterBank::D; } sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = w; } else { instruction.mem_size = 1; } instruction.operand_count = 2; } OperandCase::Gv_Ew => { let w = RegisterBank::W; instruction.operands[1] = mem_oper; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); if instruction.operands[1] == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = w; } else { instruction.mem_size = 2; } instruction.operand_count = 2; }, OperandCase::E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if instruction.operands[0] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, OperandCase::G_M_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 16; } OperandCase::G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; if instruction.operands[1] == OperandSpec::RegMMM { sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to xmm") .with_id(modrm_start as u32 + 1) ); // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { if instruction.opcode == Opcode::MOVDDUP { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } }, OperandCase::G_E_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; sink.record( modrm_start as u32 + 3, modrm_start as u32 + 5, InnerDescription::RegisterNumber("rrr", self.rrr, instruction.regs[0]) .with_id(modrm_start as u32 + 3) ); instruction.imm = read_num(words, 1)? as u8 as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - 8 + 1) ); if instruction.operands[1] != OperandSpec::RegMMM { if instruction.opcode == Opcode::CMPSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::CMPSD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; }, OperandCase::AL_Ibs => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.operands[1] = OperandSpec::ImmI8; } OperandCase::AX_Ivd => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; sink.record( modrm_start as u32 - 8, modrm_start as u32 - 1, InnerDescription::RegisterNumber("reg", 0, instruction.regs[0]) .with_id(modrm_start as u32 - 1) ); instruction.imm = read_imm_signed(words, bank as u8)? as u32; instruction.operands[1] = match bank as u8 { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, _ => unsafe { unreachable_unchecked() } }; sink.record( words.offset() as u32 * 8 - bank as u8 as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - bank as u8 as u32 * 8 + 1) ); } OperandCase::Ivs => { if instruction.prefixes.operand_size() { instruction.imm = read_imm_unsigned(words, 4)?; instruction.operands[0] = OperandSpec::ImmI32; let opwidth = 4; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } else { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmI16; let opwidth = 2; sink.record( words.offset() as u32 * 8 - opwidth as u32 * 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("imm", instruction.imm as i64) .with_id(words.offset() as u32 * 8 - opwidth as u32 * 8 + 1) ); } instruction.operand_count = 1; }, OperandCase::ModRM_0x83 => { instruction.operands[0] = mem_oper; instruction.opcode = base_opcode_map(self.rrr); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operands[1] = OperandSpec::ImmI8; }, OperandCase::I_3 => { sink.record( modrm_start - 8, modrm_start - 1, InnerDescription::Number("int", 3 as i64) .with_id(modrm_start - 1) ); instruction.imm = 3; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Nothing => { if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } if instruction.opcode == Opcode::RETURN { instruction.mem_size = 2; } else if instruction.opcode == Opcode::RETF { instruction.mem_size = 4; } // TODO: leave? instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); }, OperandCase::Ed_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; if instruction.operands[0] == OperandSpec::RegMMM { // fix the register to XMM sink.record( modrm_start + 6, modrm_start + 7, InnerDescription::Misc("mod bits 0b11 select register operand, width fixed to dword") .with_id(modrm_start as u32 + 1) ); instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } }, OperandCase::ModRM_0x8f => { instruction.operands[0] = mem_oper; let r = self.rrr; if r >= 1 { sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Misc("rrr field > 0b000 for this opcode is illegal, except with XOP extensions") .with_id(modrm_start - 8) ); // TODO: this is where XOP decoding would occur return Err(DecodeError::IncompleteDecoder); } instruction.opcode = [ Opcode::POP, ][r as usize]; sink.record( modrm_start + 3, modrm_start + 5, InnerDescription::Opcode(instruction.opcode) .with_id(modrm_start - 8) ); instruction.operand_count = 1; } OperandCase::G_Ed_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operand_count = 2; if instruction.operands[1] == OperandSpec::RegMMM { // fix the register to XMM instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } }, OperandCase::G_E_mm_Ib => { instruction.operands[1] = mem_oper; instruction.imm = read_num(words, 1)? as u8 as u32; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; instruction.mem_size = 0; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_Ev_xmm_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u32; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = match instruction.opcode { Opcode::PEXTRB => 1, Opcode::PEXTRW => 2, Opcode::PEXTRD => 4, Opcode::EXTRACTPS => 4, Opcode::INSERTPS => 4, Opcode::PINSRB => 1, Opcode::PINSRW => 2, Opcode::PINSRD => 4, _ => 8, }; } else { instruction.regs[1].bank = RegisterBank::X; } instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::PMOVX_E_G_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { if [].contains(&instruction.opcode) { instruction.mem_size = 2; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD || instruction.opcode == Opcode::MOVHPS { return Err(DecodeError::InvalidOperand); } } } OperandCase::PMOVX_G_E_xmm => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { if [Opcode::PMOVSXBQ, Opcode::PMOVZXBQ].contains(&instruction.opcode) { instruction.mem_size = 2; } else if [Opcode::PMOVZXBD, Opcode::UCOMISS, Opcode::COMISS, Opcode::CVTSS2SD].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } else { instruction.regs[1].bank = RegisterBank::X; if instruction.opcode == Opcode::MOVLPD || instruction.opcode == Opcode::MOVHPD { return Err(DecodeError::InvalidOperand); } } } OperandCase::INV_Gv_M => { instruction.regs[0].bank = RegisterBank::D; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if [Opcode::LFS, Opcode::LGS, Opcode::LSS].contains(&instruction.opcode) { if !instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } else if [Opcode::ENQCMD, Opcode::ENQCMDS].contains(&instruction.opcode) { instruction.regs[0].bank = RegisterBank::W; instruction.mem_size = 64; } else { instruction.mem_size = 16; } } OperandCase::ModRM_0xc4 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if modrm & 0b11000000 == 0b11000000 { // interpret the c4 as a vex prefix if instruction.prefixes.vex_invalid() { // prefixes and then vex is invalid! reject it. return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("three-byte vex prefix (0xc4)") .with_id(words.offset() as u32 * 8 - 16) ); vex::three_byte_vex(words, modrm, instruction, sink)?; if decoder != &InstDecoder::default() { decoder.revise_instruction(instruction)?; } return Ok(()); } } else { // LES instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; if !instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } }, OperandCase::ModRM_0xc5 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if (modrm & 0b1100_0000) == 0b1100_0000 { // interpret the c5 as a vex prefix if instruction.prefixes.vex_invalid() { // prefixes and then vex is invalid! reject it. return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("two-byte vex prefix (0xc5)") .with_id(words.offset() as u32 * 8 - 16) ); vex::two_byte_vex(words, modrm, instruction, sink)?; if decoder != &InstDecoder::default() { decoder.revise_instruction(instruction)?; } return Ok(()); } } else { // LDS instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; if !instruction.prefixes.operand_size() { instruction.mem_size = 4; } else { instruction.mem_size = 6; } } }, OperandCase::G_U_xmm_Ub => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::ModRM_0xf20f78 => { instruction.opcode = Opcode::INSERTQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u32; instruction.disp = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operands[3] = OperandSpec::ImmInDispField; instruction.operand_count = 4; } OperandCase::ModRM_0x660f78 => { instruction.opcode = Opcode::EXTRQ; let modrm = read_modrm(words)?; if modrm < 0b11_000_000 { return Err(DecodeError::InvalidOperand); } if modrm >= 0b11_001_000 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegMMM; instruction.regs[1] = RegSpec::from_parts(modrm & 7, RegisterBank::X); instruction.imm = read_num(words, 1)? as u8 as u32; instruction.disp = read_num(words, 1)? as u8 as u32; instruction.operands[1] = OperandSpec::ImmU8; instruction.operands[2] = OperandSpec::ImmInDispField; instruction.operand_count = 3; } OperandCase::ModRM_0xf30f1e => { let modrm = read_modrm(words)?; match modrm { 0xfa => { instruction.opcode = Opcode::ENDBR64; instruction.operand_count = 0; }, 0xfb => { instruction.opcode = Opcode::ENDBR32; instruction.operand_count = 0; }, _ => { let bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; instruction.mem_size = bank as u8; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); instruction.operand_count = 2; } }; } OperandCase::G_E_xmm_Ub => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } OperandCase::Gd_Ed => { instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } instruction.operands[1] = mem_oper; } OperandCase::Md_Gd => { instruction.regs[0].bank = RegisterBank::D; instruction.mem_size = 4; } /* OperandCase::Edq_Gdq => { let bank = if instruction.prefixes.rex_unchecked().w() { RegisterBank::Q } else { RegisterBank::D }; instruction.regs[0].bank = bank; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = bank; } instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.operand_count = 2; } */ OperandCase::G_U_xmm => { if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::X; instruction.regs[1].bank = RegisterBank::X; }, OperandCase::Gv_Ev_Ib => { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Gv_Ev_Iv => { let opwidth = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.imm = read_imm_signed(words, opwidth as u8)? as u32; instruction.operands[2] = match opwidth as u8 { 2 => OperandSpec::ImmI16, 4 => OperandSpec::ImmI32, _ => unsafe { unreachable_unchecked() } }; instruction.operand_count = 3; } OperandCase::Ev_Gv_Ib => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::Ev_Gv_CL => { instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[3] = RegSpec::cl(); instruction.operand_count = 3; } OperandCase::G_mm_Ew_Ib => { instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } instruction.imm = read_num(words, 1)? as u8 as u32; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; } OperandCase::G_E_mm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num = self.rrr; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if [Opcode::PUNPCKLBW, Opcode::PUNPCKLWD, Opcode::PUNPCKLDQ].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } }, OperandCase::G_U_mm => { instruction.regs[0].bank = RegisterBank::D; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; }, OperandCase::Gv_Ew_LAR => { instruction.operands[1] = mem_oper; // lar is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword/qword for // larger modes even though the upper 16 bits would be ignored. // // so the registers are correct by the time we're here, we might just need to override // mem size as well. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; }, OperandCase::Gv_Ew_LSL => { instruction.operands[1] = mem_oper; // lsl is weird. a segment selector is taken from the source register, which means // either we read the low 16-bits of a register or read 16 bits from a memory operand. // for whatever reason, the intel manual writes a source register as a dword for larger // modes even though the upper 16 bits would be ignored. if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.regs[0].bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; }, OperandCase::Gd_Ev => { instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } if instruction.regs[0].bank == RegisterBank::W { instruction.regs[0].bank = RegisterBank::D; }; instruction.operand_count = 2; }, op @ OperandCase::AL_Ob | op @ OperandCase::AX_Ov => { match op { OperandCase::AL_Ob => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::AX_Ov => { let b = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if !instruction.prefixes.address_size() { 2 } else { 4 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; if !instruction.prefixes.address_size() { instruction.operands[1] = OperandSpec::DispU16; } else { instruction.operands[1] = OperandSpec::DispU32; }; instruction.operand_count = 2; } op @ OperandCase::Ob_AL | op @ OperandCase::Ov_AX => { match op { OperandCase::Ob_AL => { instruction.mem_size = 1; instruction.regs[0] = RegSpec::al(); } OperandCase::Ov_AX => { let b = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = b as u8; instruction.regs[0].num = 0; instruction.regs[0].bank = b; } _ => { unsafe { unreachable_unchecked() } } }; let addr_width = if !instruction.prefixes.address_size() { 2 } else { 4 }; let imm = read_num(words, addr_width)?; instruction.disp = imm; instruction.operands[0] = if !instruction.prefixes.address_size() { OperandSpec::DispU16 } else { OperandSpec::DispU32 }; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::I_1 => { instruction.imm = 1; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } /* OperandCase::Unsupported => { return Err(DecodeError::IncompleteDecoder); } */ OperandCase::Iw_Ib => { instruction.disp = read_num(words, 2)? as u32; instruction.imm = read_num(words, 1)? as u32; instruction.operands[0] = OperandSpec::ImmInDispField; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Fw => { if !instruction.prefixes.operand_size() { instruction.opcode = Opcode::IRET; } else { instruction.opcode = Opcode::IRETD; } instruction.operand_count = 0; } OperandCase::G_mm_U_mm => { instruction.regs[0].bank = RegisterBank::MM; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::E_G_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0].bank = RegisterBank::D; instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } else { instruction.regs[1].bank = RegisterBank::D; } } OperandCase::G_E_q => { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.regs[0].bank = RegisterBank::D; instruction.operand_count = 2; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } else { instruction.regs[1].bank = RegisterBank::D; } } OperandCase::G_Mq_mm => { instruction.operands[1] = instruction.operands[0]; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } instruction.regs[0].num &= 0b111; instruction.operand_count = 2; }, OperandCase::MOVQ_f30f => { // if rex.w is set, the f3 prefix no longer applies and this becomes an 0f7e movq, // rather than f30f7e movq. // // the difference here is that 0f7e movq has reversed operand order from f30f7e movq, // in addition to the selected register banks being different. // // anyway, there are two operands, and the primary concern here is "what are they?". instruction.operand_count = 2; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].bank = RegisterBank::X; } } OperandCase::ModRM_0x0f0d => { let r = instruction.regs[0].num & 0b111; let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; match r { 1 => { instruction.opcode = Opcode::PREFETCHW; } _ => { instruction.opcode = Opcode::NOP; } } instruction.operands[0] = mem_oper; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 64; } else { instruction.regs[1].bank = bank; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f0f => { // 3dnow instructions are WILD, the opcode is encoded as an imm8 trailing the // instruction. instruction.operands[1] = mem_oper; instruction.regs[0].num &= 0b0111; instruction.regs[0].bank = RegisterBank::MM; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } else { instruction.regs[1].num &= 0b0111; instruction.regs[1].bank = RegisterBank::MM; } let opcode = read_modrm(words)?; match opcode { 0x0c => { instruction.opcode = Opcode::PI2FW; } 0x0d => { instruction.opcode = Opcode::PI2FD; } 0x1c => { instruction.opcode = Opcode::PF2IW; } 0x1d => { instruction.opcode = Opcode::PF2ID; } 0x8a => { instruction.opcode = Opcode::PFNACC; } 0x8e => { instruction.opcode = Opcode::PFPNACC; } 0x90 => { instruction.opcode = Opcode::PFCMPGE; } 0x94 => { instruction.opcode = Opcode::PFMIN; } 0x96 => { instruction.opcode = Opcode::PFRCP; } 0x97 => { instruction.opcode = Opcode::PFRSQRT; } 0x9a => { instruction.opcode = Opcode::PFSUB; } 0x9e => { instruction.opcode = Opcode::PFADD; } 0xa0 => { instruction.opcode = Opcode::PFCMPGT; } 0xa4 => { instruction.opcode = Opcode::PFMAX; } 0xa6 => { instruction.opcode = Opcode::PFRCPIT1; } 0xa7 => { instruction.opcode = Opcode::PFRSQIT1; } 0xaa => { instruction.opcode = Opcode::PFSUBR; } 0xae => { instruction.opcode = Opcode::PFACC; } 0xb0 => { instruction.opcode = Opcode::PFCMPEQ; } 0xb4 => { instruction.opcode = Opcode::PFMUL; } 0xb6 => { instruction.opcode = Opcode::PFRCPIT2; } 0xb7 => { instruction.opcode = Opcode::PMULHRW; } 0xbb => { instruction.opcode = Opcode::PSWAPD; } 0xbf => { instruction.opcode = Opcode::PAVGUSB; } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0x0fc7 => { if instruction.prefixes.repnz() { let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } if instruction.prefixes.operand_size() { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } return Ok(()); } 6 => { instruction.opcode = Opcode::VMCLEAR; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // dword-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::D, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDRAND; } else { instruction.mem_size = 8; } instruction.operand_count = 1; return Ok(()); } 7 => { instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // this would be invalid as `vmclear`, so fall back to the parse as // 66-prefixed rdrand. this is a register operand, so just demote it to the // dword-form operand: instruction.regs[1] = RegSpec { bank: RegisterBank::D, num: instruction.regs[1].num }; instruction.opcode = Opcode::RDSEED; } else { return Err(DecodeError::InvalidOpcode); } instruction.operand_count = 1; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } if instruction.prefixes.rep() { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 7; match r { 1 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.opcode = Opcode::CMPXCHG8B; instruction.mem_size = 8; instruction.operand_count = 1; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; } } 6 => { instruction.opcode = Opcode::VMXON; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { // invalid as `vmxon`, reg-form is `senduipi` instruction.opcode = Opcode::SENDUIPI; // and the operand is always a dword register instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 8; } instruction.operand_count = 1; } 7 => { instruction.opcode = Opcode::RDPID; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } let modrm = read_modrm(words)?; let is_reg = (modrm & 0xc0) == 0xc0; let r = (modrm >> 3) & 0b111; let opcode = match r { 0b001 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; Opcode::CMPXCHG8B } } 0b011 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XRSTORS } } 0b100 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XSAVEC } } 0b101 => { if is_reg { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 63; Opcode::XSAVES } } 0b110 => { if is_reg { Opcode::RDRAND } else { instruction.mem_size = 8; Opcode::VMPTRLD } } 0b111 => { if is_reg { Opcode::RDSEED } else { instruction.mem_size = 8; Opcode::VMPTRST } } _ => { return Err(DecodeError::InvalidOperand); } }; instruction.opcode = opcode; instruction.operand_count = 1; let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; }, OperandCase::ModRM_0x0f71 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLW, Opcode::Invalid, Opcode::PSRAW, Opcode::Invalid, Opcode::PSLLW, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; }, OperandCase::ModRM_0x0f72 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::PSRLD, Opcode::Invalid, Opcode::PSRAD, Opcode::Invalid, Opcode::PSLLD, Opcode::Invalid, ]; let opc = TBL[r as usize]; if opc == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.opcode = opc; if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0x0f73 => { if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } let r = instruction.regs[0].num & 0b0111; match r { 2 => { instruction.opcode = Opcode::PSRLQ; } 3 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSRLDQ; } 6 => { instruction.opcode = Opcode::PSLLQ; } 7 => { if !instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } if instruction.prefixes.operand_size() { instruction.regs[1].bank = RegisterBank::X; } else { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b0111; } instruction.operands[0] = mem_oper; instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmU8; }, OperandCase::ModRM_0xf30f38d8 => { instruction.operand_count = 1; let r = instruction.regs[0].num & 0b111; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } match r { 0b000 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESENCWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b001 => { instruction.mem_size = 48; instruction.opcode = Opcode::AESDECWIDE128KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b010 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESENCWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } 0b011 => { instruction.mem_size = 64; instruction.opcode = Opcode::AESDECWIDE256KL; instruction.operands[0] = mem_oper; return Ok(()); } _ => { return Err(DecodeError::InvalidOpcode); } } } OperandCase::ModRM_0xf30f38dc => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::LOADIWKEY; } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESENC128KL; } } OperandCase::ModRM_0xf30f38dd => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 48; instruction.opcode = Opcode::AESDEC128KL; } } OperandCase::ModRM_0xf30f38de => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESENC256KL; } } OperandCase::ModRM_0xf30f38df => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 64; instruction.opcode = Opcode::AESDEC256KL; } } OperandCase::ModRM_0xf30f38fa => { instruction.opcode = Opcode::ENCODEKEY128; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f38fb => { instruction.opcode = Opcode::ENCODEKEY256; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOpcode); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::D; } OperandCase::ModRM_0xf30f3af0 => { let modrm = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOpcode); // invalid } instruction.opcode = Opcode::HRESET; instruction.imm = read_num(words, 1)?; instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::G_mm_Ed => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } OperandCase::G_mm_E => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; instruction.operands[1] = mem_oper; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } OperandCase::Ed_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } OperandCase::E_G_mm => { instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { instruction.mem_size = 8; } } OperandCase::G_xmm_Ew_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u32; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } }, OperandCase::G_xmm_Ed => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } }, OperandCase::G_mm_E_xmm => { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 16; } }, op @ OperandCase::G_xmm_U_mm | op @ OperandCase::G_xmm_E_mm => { instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { if op == OperandCase::G_xmm_U_mm { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } } }, OperandCase::Rv_Gmm_Ib => { instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; instruction.imm = read_num(words, 1)? as u32; instruction.regs[0].bank = RegisterBank::D; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::MM; instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } OperandCase::G_mm_U_xmm => { instruction.regs[1].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.regs[0].bank = RegisterBank::MM; instruction.regs[0].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } // sure hope these aren't backwards huh OperandCase::AL_Xb => { instruction.regs[0] = RegSpec::al(); if !instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::si(); } else { instruction.regs[1] = RegSpec::esi(); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_Xb => { if !instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_di; instruction.operands[1] = OperandSpec::Deref_si; } else { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::Yb_AL => { instruction.regs[0] = RegSpec::al(); if !instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::di(); } else { instruction.regs[1] = RegSpec::edi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = 1; instruction.operand_count = 2; } OperandCase::AX_Xv => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if !instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::si(); } else { instruction.regs[1] = RegSpec::esi(); } instruction.operands[1] = OperandSpec::Deref; instruction.mem_size = bank as u8; } OperandCase::Yv_AX => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.regs[0].num = 0; instruction.regs[0].bank = bank; if !instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::di(); } else { instruction.regs[1] = RegSpec::edi(); } instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = bank as u8; } OperandCase::Yv_Xv => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; instruction.mem_size = bank as u8; if !instruction.prefixes.address_size() { instruction.operands[0] = OperandSpec::Deref_di; instruction.operands[1] = OperandSpec::Deref_si; } else { instruction.operands[0] = OperandSpec::Deref_edi; instruction.operands[1] = OperandSpec::Deref_esi; } } OperandCase::ModRM_0x0f12 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.regs[1].bank = RegisterBank::X; instruction.opcode = Opcode::MOVHLPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVLPD; } else { instruction.opcode = Opcode::MOVLPS; } } } OperandCase::ModRM_0x0f16 => { instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::MOVLHPS; } else { instruction.mem_size = 8; if instruction.prefixes.operand_size() { instruction.opcode = Opcode::MOVHPD; } else { instruction.opcode = Opcode::MOVHPS; } } } OperandCase::ModRM_0x0f18 => { let rrr = instruction.regs[0].num & 0b111; instruction.operands[0] = mem_oper; instruction.operand_count = 1; // only PREFETCH* are invalid on reg operand instruction.opcode = if mem_oper == OperandSpec::RegMMM && rrr < 4 { Opcode::NOP } else { match rrr { 0 => Opcode::PREFETCHNTA, 1 => Opcode::PREFETCH0, 2 => Opcode::PREFETCH1, 3 => Opcode::PREFETCH2, _ => Opcode::NOP, } }; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 64; } } OperandCase::Gd_U_xmm => { if instruction.operands[1] != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::D; instruction.regs[1].bank = RegisterBank::X; } OperandCase::Gd_Eq_xmm => { // in real-mode the register is always dword, regardless of prefixing instruction.regs[0].bank = RegisterBank::D; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } } OperandCase::Gv_E_xmm => { // in real-mode the register is always dword, regardless of prefixing instruction.regs[0].bank = RegisterBank::D; if instruction.operands[1] == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } } OperandCase::M_G_xmm => { // in real-mode the register is always dword, regardless of prefixing instruction.regs[0].bank = RegisterBank::D; if instruction.opcode == Opcode::MOVNTSS { instruction.mem_size = 4; } else if instruction.opcode == Opcode::MOVNTPD || instruction.opcode == Opcode::MOVNTDQ || instruction.opcode == Opcode::MOVNTPS { instruction.mem_size = 16; } else { instruction.mem_size = 8; } instruction.regs[0].bank = RegisterBank::X; } OperandCase::Ew_Sw => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[0] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::Sw_Ew => { // check r let r = instruction.regs[0].num; if r > 5 { // return Err(()); //Err("Invalid r".to_owned()); return Err(DecodeError::InvalidOperand); } // quoth the manual: // ``` // The MOV instruction cannot be used to load the CS register. Attempting to do so // results in an invalid opcode excep-tion (#UD). To load the CS register, use the far // JMP, CALL, or RET instruction. // ``` if r == 1 { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::S; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::W; } else { instruction.mem_size = 2; } }, OperandCase::CVT_AA => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = if instruction.prefixes.operand_size() { Opcode::CWDE } else { Opcode::CBW }; } OperandCase::CVT_DA => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; instruction.opcode = if instruction.prefixes.operand_size() { Opcode::CDQ } else { Opcode::CWD }; } OperandCase::Ib => { instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operand_count = 1; } OperandCase::Iw => { instruction.imm = read_imm_unsigned(words, 2)?; instruction.operands[0] = OperandSpec::ImmU16; if instruction.opcode == Opcode::RETURN { instruction.mem_size = 4; } else { instruction.mem_size = 6; } instruction.operand_count = 1; } OperandCase::ModRM_0x0f00 => { instruction.operand_count = 1; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { instruction.opcode = Opcode::SLDT; } else if r == 1 { instruction.opcode = Opcode::STR; } else if r == 2 { instruction.opcode = Opcode::LLDT; } else if r == 3 { instruction.opcode = Opcode::LTR; } else if r == 4 { instruction.opcode = Opcode::VERR; } else if r == 5 { instruction.opcode = Opcode::VERW; } else if r == 6 { // TODO: this would be jmpe for x86-on-itanium systems. instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else if r == 7 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } else { unreachable!("r <= 8"); } instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCase::ModRM_0x0f01 => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; if r == 0 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; const TBL: [Opcode; 8] = [ Opcode::ENCLV, Opcode::VMCALL, Opcode::VMLAUNCH, Opcode::VMRESUME, Opcode::VMXOFF, Opcode::PCONFIG, Opcode::Invalid, Opcode::Invalid, ]; instruction.opcode = TBL[m as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::SGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 1 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; if instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } if instruction.prefixes.operand_size() { match m { 0b100 => { instruction.opcode = Opcode::TDCALL; } 0b101 => { instruction.opcode = Opcode::SEAMRET; } 0b110 => { instruction.opcode = Opcode::SEAMOPS; } 0b111 => { instruction.opcode = Opcode::SEAMCALL; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { match m { 0b000 => { instruction.opcode = Opcode::MONITOR; } 0b001 => { instruction.opcode = Opcode::MWAIT; }, 0b010 => { instruction.opcode = Opcode::CLAC; } 0b011 => { instruction.opcode = Opcode::STAC; } 0b111 => { instruction.opcode = Opcode::ENCLS; } _ => { return Err(DecodeError::InvalidOpcode); } } } } else { instruction.opcode = Opcode::SIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 2 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if instruction.prefixes.rep() || instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match m { 0b000 => { instruction.opcode = Opcode::XGETBV; } 0b001 => { instruction.opcode = Opcode::XSETBV; } 0b100 => { instruction.opcode = Opcode::VMFUNC; } 0b101 => { instruction.opcode = Opcode::XEND; } 0b110 => { instruction.opcode = Opcode::XTEST; } 0b111 => { instruction.opcode = Opcode::ENCLU; } _ => { return Err(DecodeError::InvalidOpcode); } } } else { instruction.opcode = Opcode::LGDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 3 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { match m { 0b000 => { instruction.opcode = Opcode::VMRUN; instruction.operand_count = 1; instruction.regs[0] = RegSpec::ax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b001 => { instruction.opcode = Opcode::VMMCALL; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b010 => { instruction.opcode = Opcode::VMLOAD; instruction.operand_count = 1; instruction.regs[0] = RegSpec::ax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b011 => { instruction.opcode = Opcode::VMSAVE; instruction.operand_count = 1; instruction.regs[0] = RegSpec::ax(); instruction.operands[0] = OperandSpec::RegRRR; }, 0b100 => { instruction.opcode = Opcode::STGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b101 => { instruction.opcode = Opcode::CLGI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; }, 0b110 => { instruction.opcode = Opcode::SKINIT; instruction.operand_count = 1; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::eax(); }, 0b111 => { instruction.opcode = Opcode::INVLPGA; instruction.operand_count = 2; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.regs[0] = RegSpec::ax(); instruction.regs[1] = RegSpec::ecx(); }, _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOperand); } } } else { instruction.opcode = Opcode::LIDT; instruction.operand_count = 1; instruction.mem_size = 63; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else if r == 4 { // TODO: this permits storing only to word-size registers // spec suggets this might do something different for f.ex rdi? instruction.opcode = Opcode::SMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 5 { let mod_bits = modrm >> 6; if mod_bits != 0b11 { if !instruction.prefixes.rep() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RSTORSSP; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.mem_size = 8; instruction.operand_count = 1; return Ok(()); } let m = modrm & 7; match m { 0b000 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XSUSLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SETSSBSY; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b001 => { if instruction.prefixes.repnz() { instruction.opcode = Opcode::XRESLDTRK; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b010 => { if !instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::SAVEPREVSSP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b100 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::UIRET; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b101 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::TESTUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } 0b110 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::CLUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::RDPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } 0b111 => { if instruction.prefixes.rep() { instruction.opcode = Opcode::STUI; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::WRPKRU; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } _ => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; return Err(DecodeError::InvalidOpcode); } } } else if r == 6 { instruction.opcode = Opcode::LMSW; instruction.operand_count = 1; instruction.mem_size = 2; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; } else if r == 7 { let mod_bits = modrm >> 6; let m = modrm & 7; if mod_bits == 0b11 { if m == 0 { // swapgs is not valid in modes other than 64-bit return Err(DecodeError::InvalidOpcode); } else if m == 1 { instruction.opcode = Opcode::RDTSCP; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 2 { instruction.opcode = Opcode::MONITORX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 3 { instruction.opcode = Opcode::MWAITX; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 4 { instruction.opcode = Opcode::CLZERO; instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } else if m == 5 { instruction.opcode = Opcode::RDPRU; instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::ecx(); instruction.operand_count = 1; } else if m == 6 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPADJUST; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::RMPUPDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::INVLPGB; instruction.operand_count = 3; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operands[2] = OperandSpec::RegVex; instruction.regs[0] = RegSpec::ax(); instruction.regs[1] = RegSpec::dx(); instruction.regs[3] = RegSpec::cx(); } else if m == 7 { if instruction.prefixes.rep() { if instruction.prefixes.repnz() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PSMASH; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.repnz() { if instruction.prefixes.rep() || instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::PVALIDATE; instruction.operand_count = 0; return Ok(()); } else if instruction.prefixes.operand_size() { return Err(DecodeError::InvalidOperand); } instruction.opcode = Opcode::TLBSYNC; instruction.operand_count = 0; } else { return Err(DecodeError::InvalidOpcode); } } else { instruction.opcode = Opcode::INVLPG; instruction.operand_count = 1; instruction.mem_size = 1; instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; } } else { unreachable!("r <= 8"); } } OperandCase::ModRM_0x0fae => { let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; let m = modrm & 7; if instruction.prefixes.operand_size() && !(instruction.prefixes.rep() || instruction.prefixes.repnz()) { instruction.prefixes.unset_operand_size(); if modrm < 0xc0 { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::CLWB } 7 => { Opcode::CLFLUSHOPT } _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::B /* opwidth */, sink)?; instruction.mem_size = 64; instruction.operand_count = 1; } else { instruction.opcode = match (modrm >> 3) & 7 { 6 => { Opcode::TPAUSE } _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; } return Ok(()); } if instruction.prefixes.repnz() { if (modrm & 0xc0) == 0xc0 { match r { 6 => { instruction.opcode = Opcode::UMWAIT; instruction.regs[0] = RegSpec { bank: RegisterBank::D, num: m, }; instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } } if instruction.prefixes.rep() { if r == 4 { if instruction.prefixes.operand_size() { // xed specifically rejects this. seeems out of line since rep takes // precedence elsewhere, but ok i guess return Err(DecodeError::InvalidOpcode); } instruction.opcode = Opcode::PTWRITE; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 1; return Ok(()); } if (modrm & 0xc0) == 0xc0 { match r { 0 => { instruction.opcode = Opcode::RDFSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 1 => { instruction.opcode = Opcode::RDGSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 2 => { instruction.opcode = Opcode::WRFSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 3 => { instruction.opcode = Opcode::WRGSBASE; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 5 => { instruction.opcode = Opcode::INCSSP; instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } 6 => { instruction.opcode = Opcode::UMONITOR; if !instruction.prefixes.address_size() { instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::W); } else { instruction.regs[1] = RegSpec::from_parts(m, RegisterBank::D); } instruction.operands[0] = OperandSpec::RegMMM; instruction.operand_count = 1; } _ => { return Err(DecodeError::InvalidOpcode); } } return Ok(()); } else { match r { 6 => { instruction.opcode = Opcode::CLRSSBSY; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; instruction.mem_size = 8; return Ok(()); } _ => { return Err(DecodeError::InvalidOperand); } } } } let mod_bits = modrm >> 6; // all the 0b11 instructions are err or no-operands if mod_bits == 0b11 { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; match r { // invalid rrr for 0x0fae, mod: 11 0 | 1 | 2 | 3 | 4 => { return Err(DecodeError::InvalidOpcode); }, 5 => { instruction.opcode = Opcode::LFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 6 => { instruction.opcode = Opcode::MFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, 7 => { instruction.opcode = Opcode::SFENCE; // Intel's manual accepts m != 0, AMD supports m != 0 though the manual // doesn't say (tested on threadripper) if !decoder.amd_quirks() && !decoder.intel_quirks() { if m != 0 { return Err(DecodeError::InvalidOperand); } } }, _ => { unsafe { unreachable_unchecked() } /* r <=7 */ } } } else { // these can't be prefixed, so says `xed` i guess. if instruction.prefixes.operand_size() || instruction.prefixes.rep() || instruction.prefixes.repnz() { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 1; let (opcode, mem_size) = [ (Opcode::FXSAVE, 63), (Opcode::FXRSTOR, 63), (Opcode::LDMXCSR, 4), (Opcode::STMXCSR, 4), (Opcode::XSAVE, 63), (Opcode::XRSTOR, 63), (Opcode::XSAVEOPT, 63), (Opcode::CLFLUSH, 64), ][r as usize]; instruction.opcode = opcode; instruction.mem_size = mem_size; instruction.operands[0] = read_M(words, instruction, modrm, sink)?; } } OperandCase::ModRM_0x0fba => { let bank = if !instruction.prefixes.operand_size() { RegisterBank::W } else { RegisterBank::D }; let modrm = read_modrm(words)?; let r = (modrm >> 3) & 7; const TBL: [Opcode; 8] = [ Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::Invalid, Opcode::BT, Opcode::BTS, Opcode::BTR, Opcode::BTC ]; instruction.opcode = TBL[r as usize]; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } instruction.operands[0] = read_E(words, instruction, modrm, bank, sink)?; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.imm = read_imm_signed(words, 1)? as u32; instruction.operands[1] = OperandSpec::ImmI8; instruction.operand_count = 2; } op @ OperandCase::Rq_Cq_0 | op @ OperandCase::Rq_Dq_0 | op @ OperandCase::Cq_Rq_0 | op @ OperandCase::Dq_Rq_0 => { let modrm = read_modrm(words)?; let m = modrm & 7; let r = (modrm >> 3) & 7; let bank = match op { OperandCase::Rq_Cq_0 | OperandCase::Cq_Rq_0 => { if r != 0 && r != 2 && r != 3 && r != 4 { return Err(DecodeError::InvalidOperand); } RegisterBank::CR }, OperandCase::Rq_Dq_0 | OperandCase::Dq_Rq_0 => { if r > 7 { // unreachable but mirrors x86_64 code return Err(DecodeError::InvalidOperand); } RegisterBank::DR }, _ => unsafe { unreachable_unchecked() } }; let (rrr, mmm) = match op { OperandCase::Rq_Cq_0 | OperandCase::Rq_Dq_0 => (1, 0), OperandCase::Cq_Rq_0 | OperandCase::Dq_Rq_0 => (0, 1), _ => unsafe { unreachable_unchecked() } }; instruction.regs[0] = RegSpec { bank: bank, num: r }; instruction.regs[1] = RegSpec { bank: RegisterBank::D, num: m }; instruction.operands[mmm] = OperandSpec::RegMMM; instruction.operands[rrr] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::CS => { instruction.regs[0] = RegSpec::cs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::DS => { instruction.regs[0] = RegSpec::ds(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::ES => { instruction.regs[0] = RegSpec::es(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::SS => { instruction.regs[0] = RegSpec::ss(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::FS => { instruction.regs[0] = RegSpec::fs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::GS => { instruction.regs[0] = RegSpec::gs(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operand_count = 1; } OperandCase::AL_Ib => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::AX_Ib => { instruction.regs[0].num = 0; instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::ImmU8; instruction.operand_count = 2; } OperandCase::Ib_AL => { instruction.regs[0] = RegSpec::al(); instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Ib_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.imm = read_imm_signed(words, 1)? as u32; sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Number("1-byte immediate", instruction.imm as i64) .with_id(words.offset() as u32 * 8), ); instruction.operands[0] = OperandSpec::ImmU8; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::AX_DX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::AL_DX => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegMMM; instruction.operand_count = 2; } OperandCase::DX_AX => { instruction.regs[0].num = 0; instruction.regs[0].bank = if instruction.prefixes.operand_size() { RegisterBank::D } else { RegisterBank::W }; instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::DX_AL => { instruction.regs[0] = RegSpec::al(); instruction.regs[1] = RegSpec::dx(); instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } OperandCase::Yb_DX => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::di(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::Yv_DX => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::di(); instruction.operands[0] = OperandSpec::Deref; instruction.operands[1] = OperandSpec::RegRRR; if !instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::DX_Xb => { instruction.regs[0] = RegSpec::dl(); instruction.regs[1] = RegSpec::si(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; instruction.operand_count = 2; instruction.mem_size = 1; } OperandCase::AH => { instruction.operands[0] = OperandSpec::Nothing; instruction.operand_count = 0; } OperandCase::DX_Xv => { instruction.regs[0] = RegSpec::dx(); instruction.regs[1] = RegSpec::si(); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::Deref; if !instruction.prefixes.operand_size() { instruction.mem_size = 2; } else { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCase::x87_d8 | OperandCase::x87_d9 | OperandCase::x87_da | OperandCase::x87_db | OperandCase::x87_dc | OperandCase::x87_dd | OperandCase::x87_de | OperandCase::x87_df => { return decode_x87(words, instruction, operand_code.operand_case_handler_index(), sink); } OperandCase::MOVDIR64B => { instruction.mem_size = 64; if !instruction.prefixes.address_size() { instruction.regs[0].bank = RegisterBank::W; } else { instruction.regs[0].bank = RegisterBank::D; } } OperandCase::ModRM_0x62 => { let modrm = read_modrm(words)?; if modrm < 0xc0 { instruction.regs[0] = RegSpec { bank: RegisterBank::D, num: (modrm >> 3) & 7 }; if !instruction.prefixes.operand_size() { instruction.regs[0].bank = RegisterBank::W; instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = read_M(words, instruction, modrm, sink)?; instruction.operand_count = 2; } else { let prefixes = &instruction.prefixes; if prefixes.lock() || prefixes.operand_size() || prefixes.rep_any() { return Err(DecodeError::InvalidPrefixes); } else { sink.record( words.offset() as u32 * 8 - 16, words.offset() as u32 * 8 - 9, InnerDescription::Misc("evex prefix (0x62)") .with_id(words.offset() as u32 * 8 - 16) ); evex::read_evex(words, instruction, Some(modrm), sink)?; } } } OperandCase::AbsFar => { instruction.operands[0] = OperandSpec::AbsoluteFarAddress; instruction.operand_count = 1; instruction.mem_size = 0; // read segment let addr_size = if !instruction.prefixes.operand_size() { 2 } else { 4 }; instruction.imm = read_num(words, addr_size)?; instruction.disp = read_num(words, 2)? as u16 as u32; } OperandCase::Ew_Gw => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec { bank: RegisterBank::W, num: (modrm >> 3) & 7 }; instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.mem_size = 2; instruction.operand_count = 2; }, }; Ok(()) } #[inline(always)] fn read_0f_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { // seems like f2 takes priority, then f3, then 66, then "no prefix". for SOME instructions an // invalid prefix is in fact an invalid instruction. so just duplicate for the four kinds of // opcode lists. if prefixes.repnz() { REPNZ_0F_CODES[opcode as usize] } else if prefixes.rep() { REP_0F_CODES[opcode as usize] } else if prefixes.operand_size() { OPERAND_SIZE_0F_CODES[opcode as usize] } else { NORMAL_0F_CODES[opcode as usize] } } fn read_0f38_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { return match opcode { 0xd8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38d8), 0xdc => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dc), 0xdd => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38dd), 0xde => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38de), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38df), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ADOX), OperandCode::Gv_Ev), 0xf8 => { prefixes.unset_operand_size(); OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMDS), OperandCode::INV_Gv_M) }, 0xfa => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fa), 0xfb => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf30f38fb), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.repnz() { return match opcode { 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gv_Eb), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::CRC32), OperandCode::Gd_Ev), 0xf8 => { prefixes.unset_operand_size(); OpcodeRecord::new(Interpretation::Instruction(Opcode::ENQCMD), OperandCode::INV_Gv_M) }, _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.operand_size() { // leave operand size present for `movbe` if opcode != 0xf0 && opcode != 0xf1 { prefixes.unset_operand_size(); } return match opcode { 0x00 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_xmm), 0x01 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_xmm), 0x02 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_xmm), 0x03 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_xmm), 0x04 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_xmm), 0x05 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_xmm), 0x06 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_xmm), 0x07 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_xmm), 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_xmm), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_xmm), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_xmm), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_xmm), 0x10 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDVB), OperandCode::G_E_xmm), 0x14 => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPS), OperandCode::G_E_xmm), 0x15 => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDVPD), OperandCode::G_E_xmm), 0x17 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PTEST), OperandCode::G_E_xmm), 0x1c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_xmm), 0x1d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_xmm), 0x1e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_xmm), 0x20 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBW), OperandCode::PMOVX_G_E_xmm), 0x21 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBD), OperandCode::PMOVX_G_E_xmm), 0x22 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXBQ), OperandCode::PMOVX_G_E_xmm), 0x23 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWD), OperandCode::PMOVX_G_E_xmm), 0x24 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXWQ), OperandCode::PMOVX_G_E_xmm), 0x25 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVSXDQ), OperandCode::PMOVX_G_E_xmm), 0x28 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULDQ), OperandCode::G_E_xmm), 0x29 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQQ), OperandCode::G_E_xmm), 0x2a => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQA), OperandCode::G_M_xmm), 0x2b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSDW), OperandCode::G_E_xmm), 0x30 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBW), OperandCode::PMOVX_G_E_xmm), 0x31 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBD), OperandCode::PMOVX_G_E_xmm), 0x32 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXBQ), OperandCode::PMOVX_G_E_xmm), 0x33 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWD), OperandCode::PMOVX_G_E_xmm), 0x34 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXWQ), OperandCode::PMOVX_G_E_xmm), 0x35 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVZXDQ), OperandCode::PMOVX_G_E_xmm), 0x37 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTQ), OperandCode::G_E_xmm), 0x38 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSB), OperandCode::G_E_xmm), 0x39 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSD), OperandCode::G_E_xmm), 0x3a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUW), OperandCode::G_E_xmm), 0x3b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUD), OperandCode::G_E_xmm), 0x3c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSB), OperandCode::G_E_xmm), 0x3d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSD), OperandCode::G_E_xmm), 0x3e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUW), OperandCode::G_E_xmm), 0x3f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUD), OperandCode::G_E_xmm), 0x40 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLD), OperandCode::G_E_xmm), 0x41 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHMINPOSUW), OperandCode::G_E_xmm), 0x80 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVEPT), OperandCode::INV_Gv_M), 0x81 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVVPID), OperandCode::INV_Gv_M), 0x82 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INVPCID), OperandCode::INV_Gv_M), 0xcf => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8MULB), OperandCode::G_E_xmm), 0xdb => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESIMC), OperandCode::G_E_xmm), 0xdc => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENC), OperandCode::G_E_xmm), 0xdd => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESENCLAST), OperandCode::G_E_xmm), 0xde => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDEC), OperandCode::G_E_xmm), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESDECLAST), OperandCode::G_E_xmm), 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), 0xf5 => OpcodeRecord::new(Interpretation::Instruction(Opcode::WRUSS), OperandCode::Md_Gd), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ADCX), OperandCode::Gv_Ev), 0xf8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIR64B), OperandCode::MOVDIR64B), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } else { return match opcode { 0x00 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFB), OperandCode::G_E_mm), 0x01 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDW), OperandCode::G_E_mm), 0x02 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDD), OperandCode::G_E_mm), 0x03 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHADDSW), OperandCode::G_E_mm), 0x04 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDUBSW), OperandCode::G_E_mm), 0x05 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBW), OperandCode::G_E_mm), 0x06 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBD), OperandCode::G_E_mm), 0x07 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PHSUBSW), OperandCode::G_E_mm), 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNB), OperandCode::G_E_mm), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGNW), OperandCode::G_E_mm), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::PSIGND), OperandCode::G_E_mm), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHRSW), OperandCode::G_E_mm), 0x1c => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSB), OperandCode::G_E_mm), 0x1d => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSW), OperandCode::G_E_mm), 0x1e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PABSD), OperandCode::G_E_mm), 0xc8 => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1NEXTE), OperandCode::G_E_xmm), 0xc9 => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG1), OperandCode::G_E_xmm), 0xca => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1MSG2), OperandCode::G_E_xmm), 0xcb => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256RNDS2), OperandCode::G_E_xmm), 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG1), OperandCode::G_E_xmm), 0xcd => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA256MSG2), OperandCode::G_E_xmm), 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::Gv_M), 0xf1 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVBE), OperandCode::M_Gv), 0xf6 => OpcodeRecord::new(Interpretation::Instruction(Opcode::WRSS), OperandCode::Md_Gd), 0xf9 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDIRI), OperandCode::Md_Gd), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } } fn read_0f3a_opcode(&mut self, opcode: u8, prefixes: &mut Prefixes) -> OpcodeRecord { if prefixes.rep() { if prefixes != &Prefixes::new(0x10) { return OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); } return match opcode { 0xf0 => OpcodeRecord::new(Interpretation::Instruction(Opcode::HRESET), OperandCode::ModRM_0xf30f3af0), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } if prefixes.repnz() { return OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing); } if prefixes.operand_size() { return match opcode { 0x08 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPS), OperandCode::G_E_xmm_Ib), 0x09 => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDPD), OperandCode::G_E_xmm_Ib), 0x0a => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSS), OperandCode::G_E_xmm_Ib), 0x0b => OpcodeRecord::new(Interpretation::Instruction(Opcode::ROUNDSD), OperandCode::G_E_xmm_Ib), 0x0c => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPS), OperandCode::G_E_xmm_Ib), 0x0d => OpcodeRecord::new(Interpretation::Instruction(Opcode::BLENDPD), OperandCode::G_E_xmm_Ib), 0x0e => OpcodeRecord::new(Interpretation::Instruction(Opcode::PBLENDW), OperandCode::G_E_xmm_Ib), 0x0f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_xmm_Ib), 0x14 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRB), OperandCode::G_Ev_xmm_Ib), 0x15 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_Ev_xmm_Ib), 0x16 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRD), OperandCode::G_Ev_xmm_Ib), 0x17 => OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRACTPS), OperandCode::G_Ev_xmm_Ib), 0x20 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRB), OperandCode::G_Ev_xmm_Ib), 0x21 => OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTPS), OperandCode::G_Ev_xmm_Ib), 0x22 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRD), OperandCode::G_Ev_xmm_Ib), 0x40 => OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPS), OperandCode::G_E_xmm_Ib), 0x41 => OpcodeRecord::new(Interpretation::Instruction(Opcode::DPPD), OperandCode::G_E_xmm_Ib), 0x42 => OpcodeRecord::new(Interpretation::Instruction(Opcode::MPSADBW), OperandCode::G_E_xmm_Ib), 0x44 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCLMULQDQ), OperandCode::G_E_xmm_Ib), 0x60 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRM), OperandCode::G_E_xmm_Ib), 0x61 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPESTRI), OperandCode::G_E_xmm_Ib), 0x62 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRM), OperandCode::G_E_xmm_Ib), 0x63 => OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPISTRI), OperandCode::G_E_xmm_Ib), 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ib), 0xce => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEQB), OperandCode::G_E_xmm_Ub), 0xcf => OpcodeRecord::new(Interpretation::Instruction(Opcode::GF2P8AFFINEINVQB), OperandCode::G_E_xmm_Ub), 0xdf => OpcodeRecord::new(Interpretation::Instruction(Opcode::AESKEYGENASSIST), OperandCode::G_E_xmm_Ub), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } return match opcode { 0xcc => OpcodeRecord::new(Interpretation::Instruction(Opcode::SHA1RNDS4), OperandCode::G_E_xmm_Ub), 0x0f => OpcodeRecord::new(Interpretation::Instruction(Opcode::PALIGNR), OperandCode::G_E_mm_Ib), _ => OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), }; } } fn decode_x87< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: OperandCase, sink: &mut S) -> Result<(), DecodeError> { sink.record( words.offset() as u32 * 8 - 8, words.offset() as u32 * 8 - 1, InnerDescription::Misc("x87 opcode") .with_id(words.offset() as u32 * 8 - 1) ); #[allow(non_camel_case_types)] enum OperandCodeX87 { Est, St_Est, St_Edst, St_Eqst, St_Ew, St_Mw, St_Md, St_Mq, St_Mm, Ew, Est_St, Edst_St, Eqst_St, Ed_St, Mw_St, Md_St, Mq_St, Mm_St, Ex87S, Nothing, } // every x87 instruction is conditional on rrr bits let modrm = read_modrm(words)?; let r = (modrm >> 3) & 0b111; let (opcode, x87_operands) = match operand_code { OperandCase::x87_d8 => { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Edst), 1 => (Opcode::FMUL, OperandCodeX87::St_Edst), 2 => (Opcode::FCOM, OperandCodeX87::St_Edst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Edst), 4 => (Opcode::FSUB, OperandCodeX87::St_Edst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Edst), 6 => (Opcode::FDIV, OperandCodeX87::St_Edst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Edst), _ => { unreachable!("impossible r"); } } } OperandCase::x87_d9 => { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Edst), 1 => { if modrm >= 0xc0 { (Opcode::FXCH, OperandCodeX87::St_Est) } else { return Err(DecodeError::InvalidOpcode); } }, 2 => { if modrm >= 0xc0 { if modrm == 0xd0 { (Opcode::FNOP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } else { (Opcode::FST, OperandCodeX87::Ed_St) } } 3 => { if modrm >= 0xc0 { (Opcode::FSTPNCE, OperandCodeX87::Est_St) } else { (Opcode::FSTP, OperandCodeX87::Edst_St) } }, 4 => { if modrm >= 0xc0 { match modrm { 0xe0 => (Opcode::FCHS, OperandCodeX87::Nothing), 0xe1 => (Opcode::FABS, OperandCodeX87::Nothing), 0xe2 => { return Err(DecodeError::InvalidOpcode); }, 0xe3 => { return Err(DecodeError::InvalidOpcode); }, 0xe4 => (Opcode::FTST, OperandCodeX87::Nothing), 0xe5 => (Opcode::FXAM, OperandCodeX87::Nothing), 0xe6 => { return Err(DecodeError::InvalidOpcode); }, 0xe7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDENV, OperandCodeX87::Ex87S) // x87 state } }, 5 => { if modrm >= 0xc0 { match modrm { 0xe8 => (Opcode::FLD1, OperandCodeX87::Nothing), 0xe9 => (Opcode::FLDL2T, OperandCodeX87::Nothing), 0xea => (Opcode::FLDL2E, OperandCodeX87::Nothing), 0xeb => (Opcode::FLDPI, OperandCodeX87::Nothing), 0xec => (Opcode::FLDLG2, OperandCodeX87::Nothing), 0xed => (Opcode::FLDLN2, OperandCodeX87::Nothing), 0xee => (Opcode::FLDZ, OperandCodeX87::Nothing), 0xef => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FLDCW, OperandCodeX87::Ew) } } 6 => { if modrm >= 0xc0 { match modrm { 0xf0 => (Opcode::F2XM1, OperandCodeX87::Nothing), 0xf1 => (Opcode::FYL2X, OperandCodeX87::Nothing), 0xf2 => (Opcode::FPTAN, OperandCodeX87::Nothing), 0xf3 => (Opcode::FPATAN, OperandCodeX87::Nothing), 0xf4 => (Opcode::FXTRACT, OperandCodeX87::Nothing), 0xf5 => (Opcode::FPREM1, OperandCodeX87::Nothing), 0xf6 => (Opcode::FDECSTP, OperandCodeX87::Nothing), 0xf7 => (Opcode::FINCSTP, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTENV, OperandCodeX87::Ex87S) // x87 state } } 7 => { if modrm >= 0xc0 { match modrm { 0xf8 => (Opcode::FPREM, OperandCodeX87::Nothing), 0xf9 => (Opcode::FYL2XP1, OperandCodeX87::Nothing), 0xfa => (Opcode::FSQRT, OperandCodeX87::Nothing), 0xfb => (Opcode::FSINCOS, OperandCodeX87::Nothing), 0xfc => (Opcode::FRNDINT, OperandCodeX87::Nothing), 0xfd => (Opcode::FSCALE, OperandCodeX87::Nothing), 0xfe => (Opcode::FSIN, OperandCodeX87::Nothing), 0xff => (Opcode::FCOS, OperandCodeX87::Nothing), _ => { unreachable!("invalid modrm"); } } } else { (Opcode::FNSTCW, OperandCodeX87::Ew) } } _ => { unreachable!("impossible r"); } } } OperandCase::x87_da => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVU, OperandCodeX87::St_Est), _ => { if modrm == 0xe9 { (Opcode::FUCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOpcode); } } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Md), // 0xd9d0 -> fnop 1 => (Opcode::FIMUL, OperandCodeX87::St_Md), 2 => (Opcode::FICOM, OperandCodeX87::St_Md), // FCMOVE 3 => (Opcode::FICOMP, OperandCodeX87::St_Md), // FCMOVBE 4 => (Opcode::FISUB, OperandCodeX87::St_Md), 5 => (Opcode::FISUBR, OperandCodeX87::St_Md), // FUCOMPP 6 => (Opcode::FIDIV, OperandCodeX87::St_Md), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Md), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_db => { if modrm >= 0xc0 { match r { 0 => (Opcode::FCMOVNB, OperandCodeX87::St_Est), 1 => (Opcode::FCMOVNE, OperandCodeX87::St_Est), 2 => (Opcode::FCMOVNBE, OperandCodeX87::St_Est), 3 => (Opcode::FCMOVNU, OperandCodeX87::St_Est), 4 => { match modrm { 0xe0 => (Opcode::FENI8087_NOP, OperandCodeX87::Nothing), 0xe1 => (Opcode::FDISI8087_NOP, OperandCodeX87::Nothing), 0xe2 => (Opcode::FNCLEX, OperandCodeX87::Nothing), 0xe3 => (Opcode::FNINIT, OperandCodeX87::Nothing), 0xe4 => (Opcode::FSETPM287_NOP, OperandCodeX87::Nothing), _ => { return Err(DecodeError::InvalidOpcode); } } } 5 => (Opcode::FUCOMI, OperandCodeX87::St_Est), 6 => (Opcode::FCOMI, OperandCodeX87::St_Est), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Md), 1 => (Opcode::FISTTP, OperandCodeX87::Md_St), 2 => (Opcode::FIST, OperandCodeX87::Md_St), 3 => (Opcode::FISTP, OperandCodeX87::Md_St), 5 => (Opcode::FLD, OperandCodeX87::St_Mm), // 80bit 7 => (Opcode::FSTP, OperandCodeX87::Mm_St), // 80bit _ => { return Err(DecodeError::InvalidOpcode); } } } } OperandCase::x87_dc => { // mod=11 swaps operand order for some instructions if modrm >= 0xc0 { match r { 0 => (Opcode::FADD, OperandCodeX87::Eqst_St), 1 => (Opcode::FMUL, OperandCodeX87::Eqst_St), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUBR, OperandCodeX87::Eqst_St), 5 => (Opcode::FSUB, OperandCodeX87::Eqst_St), 6 => (Opcode::FDIVR, OperandCodeX87::Eqst_St), 7 => (Opcode::FDIV, OperandCodeX87::Eqst_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FADD, OperandCodeX87::St_Eqst), 1 => (Opcode::FMUL, OperandCodeX87::St_Eqst), 2 => (Opcode::FCOM, OperandCodeX87::St_Eqst), 3 => (Opcode::FCOMP, OperandCodeX87::St_Eqst), 4 => (Opcode::FSUB, OperandCodeX87::St_Eqst), 5 => (Opcode::FSUBR, OperandCodeX87::St_Eqst), 6 => (Opcode::FDIV, OperandCodeX87::St_Eqst), 7 => (Opcode::FDIVR, OperandCodeX87::St_Eqst), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_dd => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREE, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FST, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => (Opcode::FUCOM, OperandCodeX87::St_Est), 5 => (Opcode::FUCOMP, OperandCodeX87::St_Est), 6 => (Opcode::Invalid, OperandCodeX87::Nothing), 7 => (Opcode::Invalid, OperandCodeX87::Nothing), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FLD, OperandCodeX87::St_Eqst), 1 => (Opcode::FISTTP, OperandCodeX87::Eqst_St), 2 => (Opcode::FST, OperandCodeX87::Eqst_St), 3 => (Opcode::FSTP, OperandCodeX87::Eqst_St), 4 => (Opcode::FRSTOR, OperandCodeX87::Ex87S), 5 => (Opcode::Invalid, OperandCodeX87::Nothing), 6 => (Opcode::FNSAVE, OperandCodeX87::Ex87S), 7 => (Opcode::FNSTSW, OperandCodeX87::Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_de => { if modrm >= 0xc0 { match r { 0 => (Opcode::FADDP, OperandCodeX87::Est_St), 1 => (Opcode::FMULP, OperandCodeX87::Est_St), // undocumented in intel manual, argument order inferred from // by xed and capstone. TODO: check amd manual. 2 => (Opcode::FCOMP, OperandCodeX87::St_Est), 3 => { if modrm == 0xd9 { (Opcode::FCOMPP, OperandCodeX87::Nothing) } else { return Err(DecodeError::InvalidOperand); } }, 4 => (Opcode::FSUBRP, OperandCodeX87::Est_St), 5 => (Opcode::FSUBP, OperandCodeX87::Est_St), 6 => (Opcode::FDIVRP, OperandCodeX87::Est_St), 7 => (Opcode::FDIVP, OperandCodeX87::Est_St), _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FIADD, OperandCodeX87::St_Ew), 1 => (Opcode::FIMUL, OperandCodeX87::St_Ew), 2 => (Opcode::FICOM, OperandCodeX87::St_Ew), 3 => (Opcode::FICOMP, OperandCodeX87::St_Ew), 4 => (Opcode::FISUB, OperandCodeX87::St_Ew), 5 => (Opcode::FISUBR, OperandCodeX87::St_Ew), 6 => (Opcode::FIDIV, OperandCodeX87::St_Ew), 7 => (Opcode::FIDIVR, OperandCodeX87::St_Ew), _ => { unreachable!("impossible r"); } } } } OperandCase::x87_df => { if modrm >= 0xc0 { match r { 0 => (Opcode::FFREEP, OperandCodeX87::Est), 1 => (Opcode::FXCH, OperandCodeX87::St_Est), 2 => (Opcode::FSTP, OperandCodeX87::Est_St), 3 => (Opcode::FSTP, OperandCodeX87::Est_St), 4 => { if modrm == 0xe0 { (Opcode::FNSTSW, OperandCodeX87::Ew) } else { return Err(DecodeError::InvalidOpcode); } }, 5 => (Opcode::FUCOMIP, OperandCodeX87::St_Est), 6 => (Opcode::FCOMIP, OperandCodeX87::St_Est), 7 => { return Err(DecodeError::InvalidOpcode); }, _ => { unreachable!("impossible r"); } } } else { match r { 0 => (Opcode::FILD, OperandCodeX87::St_Mw), 1 => (Opcode::FISTTP, OperandCodeX87::Mw_St), 2 => (Opcode::FIST, OperandCodeX87::Mw_St), 3 => (Opcode::FISTP, OperandCodeX87::Mw_St), 4 => (Opcode::FBLD, OperandCodeX87::St_Mm), 5 => (Opcode::FILD, OperandCodeX87::St_Mq), 6 => (Opcode::FBSTP, OperandCodeX87::Mm_St), 7 => (Opcode::FISTP, OperandCodeX87::Mq_St), _ => { unreachable!("impossible r"); } } } } other => { panic!("invalid x87 operand dispatch, operand code is {:?}", other); } }; instruction.opcode = opcode; if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } match x87_operands { OperandCodeX87::Est => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 1; } OperandCodeX87::St_Est => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; instruction.operand_count = 2; } OperandCodeX87::St_Edst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::St_Eqst => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E_st(words, instruction, modrm, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 2; } OperandCodeX87::St_Ew => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; if instruction.operands[1] != OperandSpec::RegMMM { instruction.mem_size = 2; } instruction.operand_count = 2; } OperandCodeX87::St_Mm => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operand_count = 2; } OperandCodeX87::St_Mq => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operand_count = 2; } OperandCodeX87::St_Md => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operand_count = 2; } OperandCodeX87::St_Mw => { instruction.operands[0] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operands[1] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[1] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operand_count = 2; } OperandCodeX87::Ew => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::W, sink)?; instruction.operand_count = 1; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 2; } } OperandCodeX87::Est_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Edst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } } OperandCodeX87::Eqst_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 8; } } OperandCodeX87::Ed_St => { instruction.operands[0] = read_E_st(words, instruction, modrm, sink)?; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); if instruction.operands[0] != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; } OperandCodeX87::Mm_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 10; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mq_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 8; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Md_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 4; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Mw_St => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 2; instruction.operands[1] = OperandSpec::RegRRR; instruction.regs[0] = RegSpec::st(0); instruction.operand_count = 2; } OperandCodeX87::Ex87S => { instruction.operands[0] = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operand_count = 1; if instruction.operands[0] == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.mem_size = 63; } OperandCodeX87::Nothing => { instruction.operand_count = 0; }, } Ok(()) } #[inline] fn read_num::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { match width { 1 => { bytes.next().ok().ok_or(DecodeError::ExhaustedInput).map(|x| x as u32) } 2 => { let mut buf = [0u8; 2]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u16::from_le_bytes(buf) as u32) } 4 => { let mut buf = [0u8; 4]; bytes.next_n(&mut buf).ok().ok_or(DecodeError::ExhaustedInput)?; Ok(u32::from_le_bytes(buf) as u32) } _ => { unsafe { unreachable_unchecked(); } } } } #[inline] fn read_imm_signed::Address, ::Word>>(bytes: &mut T, num_width: u8) -> Result { if num_width == 1 { Ok(read_num(bytes, 1)? as i8 as i32) } else if num_width == 2 { Ok(read_num(bytes, 2)? as i16 as i32) } else { Ok(read_num(bytes, 4)? as i32) } } #[inline] fn read_imm_unsigned::Address, ::Word>>(bytes: &mut T, width: u8) -> Result { read_num(bytes, width) } #[inline] fn read_modrm::Address, ::Word>>(words: &mut T) -> Result { words.next().ok().ok_or(DecodeError::ExhaustedInput) } const REPNZ_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDDUP), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), // 0x20 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SD), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSD2SI), OperandCode::Gd_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SI), OperandCode::Gd_Eq_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSD2SS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFLW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f2-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0xf20f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::INSERTQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), // cmpxchg permits an f2 prefix, which is the only reason this entry is not `Nothing` OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQ2Q), OperandCode::G_mm_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::LDDQU), OperandCode::G_M_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const REP_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSS), OperandCode::Ed_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSLDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSHDUP), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::ModRM_0xf30f1e), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSI2SS), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTSS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SI), OperandCode::Gv_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTSS2SD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVSS), OperandCode::G_Ed_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXSS), OperandCode::G_Ed_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::G_E_xmm), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFHW), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f71 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f72 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // no f3-0f73 instructions, so we can stop early OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::MOVQ_f30f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQU), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::POPCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::TZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::LZCNT), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPSS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ2DQ), OperandCode::G_xmm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const OPERAND_SIZE_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPD), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPD), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PD), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPD), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPD), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPD2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHQDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::G_xmm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x660f78), OpcodeRecord::new(Interpretation::Instruction(Opcode::EXTRQ), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::HADDPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::HSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Ed_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVDQA), OperandCode::E_G_xmm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_xmm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::G_U_xmm_Ub), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPD), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDSUBPD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_xmm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPD2DQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTDQ), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_xmm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVDQU), OperandCode::G_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; const NORMAL_0F_CODES: [OpcodeRecord; 256] = [ OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f00), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f01), OpcodeRecord::new(Interpretation::Instruction(Opcode::LAR), OperandCode::Gv_Ew_LAR), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSL), OperandCode::Gv_Ew_LSL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSCALL), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::CLTS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSRET), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::INVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::WBINVD), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD2), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0d), OpcodeRecord::new(Interpretation::Instruction(Opcode::FEMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f0f), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVUPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f12), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVLPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKLPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UNPCKHPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f16), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVHPS), OperandCode::PMOVX_E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f18), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::NOP), OperandCode::Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Cq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Rq_Dq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Cq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOV), OperandCode::Dq_Rq_0), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVAPS), OperandCode::E_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPI2PS), OperandCode::G_xmm_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTPS), OperandCode::M_G_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PI), OperandCode::G_mm_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UCOMISS), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::COMISS), OperandCode::PMOVX_G_E_xmm), // 0x30 OpcodeRecord::new(Interpretation::Instruction(Opcode::WRMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDTSC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDMSR), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::RDPMC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSENTER), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::SYSEXIT), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::GETSEC), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // handled before getting to `read_0f_opcode` OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // 0x40 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNO), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNB), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNZ), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVA), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNS), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVNP), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVL), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVGE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVLE), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMOVG), OperandCode::Gv_Ev), // 0x50 OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVMSKPS), OperandCode::Gd_U_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSQRTPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::RCPPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ANDNPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::XORPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::ADDPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MULPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTPS2PD), OperandCode::PMOVX_G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::CVTDQ2PS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::SUBPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MINPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::DIVPS), OperandCode::G_E_xmm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MAXPS), OperandCode::G_E_xmm), // 0x60 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKLDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPGTD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKUSWB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUNPCKHDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PACKSSDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::G_mm_Ed), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::G_mm_E), // 0x70 OpcodeRecord::new(Interpretation::Instruction(Opcode::PSHUFW), OperandCode::G_E_mm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f71), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f72), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0f73), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PCMPEQD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::EMMS), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMREAD), OperandCode::E_G_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::VMWRITE), OperandCode::G_E_q), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVD), OperandCode::Ed_G_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVQ), OperandCode::E_G_mm), // 0x80 OpcodeRecord::new(Interpretation::Instruction(Opcode::JO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNO), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNB), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNZ), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JA), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNS), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JNP), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JL), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JGE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JLE), OperandCode::Jvds), OpcodeRecord::new(Interpretation::Instruction(Opcode::JG), OperandCode::Jvds), // 0x90 OpcodeRecord::new(Interpretation::Instruction(Opcode::SETO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNO), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETB), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETAE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNZ), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETBE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETA), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNS), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETNP), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETL), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETGE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETLE), OperandCode::Eb_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::SETG), OperandCode::Eb_R0), // 0xa0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::FS), OpcodeRecord::new(Interpretation::Instruction(Opcode::CPUID), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BT), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHLD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PUSH), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::POP), OperandCode::GS), OpcodeRecord::new(Interpretation::Instruction(Opcode::RSM), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTS), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHRD), OperandCode::Ev_Gv_CL), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fae), OpcodeRecord::new(Interpretation::Instruction(Opcode::IMUL), OperandCode::Gv_Ev), // 0xb0 OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPXCHG), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LSS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTR), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::LFS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::LGS), OperandCode::INV_Gv_M), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVZX), OperandCode::Gv_Ew), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), // JMPE, ITANIUM OpcodeRecord::new(Interpretation::Instruction(Opcode::UD1), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fba), OpcodeRecord::new(Interpretation::Instruction(Opcode::BTC), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSF), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSR), OperandCode::Gv_Ev), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Eb), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVSX), OperandCode::Gv_Ew), // 0xc0 OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Eb_Gb), OpcodeRecord::new(Interpretation::Instruction(Opcode::XADD), OperandCode::Ev_Gv), OpcodeRecord::new(Interpretation::Instruction(Opcode::CMPPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTI), OperandCode::Md_Gd), OpcodeRecord::new(Interpretation::Instruction(Opcode::PINSRW), OperandCode::G_mm_Ew_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::PEXTRW), OperandCode::Rv_Gmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::SHUFPS), OperandCode::G_E_xmm_Ib), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::ModRM_0x0fc7), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R0), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R1), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R2), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R3), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R4), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R5), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R6), OpcodeRecord::new(Interpretation::Instruction(Opcode::BSWAP), OperandCode::Zv_R7), // 0xd0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMOVMSKB), OperandCode::G_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAND), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDUSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXUB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PANDN), OperandCode::G_E_mm), // 0xe0 OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSRAD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PAVGW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHUW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULHW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::MOVNTQ), OperandCode::G_Mq_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMINSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::POR), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMAXSW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PXOR), OperandCode::G_E_mm), // 0xf0 OpcodeRecord::new(Interpretation::Instruction(Opcode::Invalid), OperandCode::Nothing), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSLLQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMULUDQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PMADDWD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSADBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::MASKMOVQ), OperandCode::G_mm_U_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PSUBQ), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDB), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDW), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::PADDD), OperandCode::G_E_mm), OpcodeRecord::new(Interpretation::Instruction(Opcode::UD0), OperandCode::Gd_Ed), ]; yaxpeax-x86-1.2.2/src/real_mode/uarch.rs000064400000000000000000000204021046102023000161140ustar 00000000000000pub mod amd { //! most information about instruction set extensions for microarchitectures here was sourced //! from //! [https://en.wikipedia.org/wiki/AMD_Accelerated_Processing_Unit#Feature_overview](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/real_mode/uarch/intel/index.html) //! and //! [https://en.wikipedia.org/wiki/Template:AMD_x86_CPU_features](https://docs.rs/yaxpeax-x86/0.0.12/yaxpeax_x86/real_mode/uarch/intel/index.html). //! these mappings are best-effort but fairly unused, so a critical eye should be kept towards //! these decoders rejecting instructions they should not, or incorrectly accepting //! instructions. //! //! microarchitectures as defined here are with respect to flags reported by CPUID. notably, //! `Zen` does not report `FMA4` support by `CPUID`, but instructions in that extension //! reportedly function correctly (agner p217). //! //! [agner](https://www.agner.org/optimize/microarchitecture.pdf) //! as retrieved 2020 may 19, //! `sha256: 87ff152ae18c017dcbfb9f7ee6e88a9f971f6250fd15a70a3dd87c3546323bd5` use crate::real_mode::InstDecoder; /// `k8` was the first AMD microarchitecture to implement x86_64, launched in 2003. while later /// `k8`-based processors supported SSE3, these predefined decoders pick the lower end of /// support - SSE2 and no later. pub fn k8() -> InstDecoder { InstDecoder::minimal() } /// `k10` was the successor to `k8`, launched in 2007. `k10` cores extended SSE support through /// to SSE4.2a, as well as consistent `cmov` support, among other features. pub fn k10() -> InstDecoder { k8() .with_cmov() .with_cmpxchg16b() .with_svm() .with_abm() .with_lahfsahf() .with_sse3() .with_ssse3() .with_sse4() .with_sse4_2() .with_sse4a() } /// `Bulldozer` was the successor to `K10`, launched in 2011. `Bulldozer` cores include AVX /// support among other extensions, and are notable for including `AESNI`. pub fn bulldozer() -> InstDecoder { k10() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_avx() .with_fma4() .with_xop() } /// `Piledriver` was the successor to `Bulldozer`, launched in 2012. pub fn piledriver() -> InstDecoder { bulldozer() .with_tbm() .with_fma3() .with_fma4() } /// `Steamroller` was the successor to `Piledriver`, launched in 2014. unlike `Piledriver` /// cores, these cores do not support `TBM` or `FMA3`. pub fn steamroller() -> InstDecoder { bulldozer() } /// `Excavator` was the successor to `Steamroller`, launched in 2015. pub fn excavator() -> InstDecoder { steamroller() .with_movbe() .with_bmi2() .with_rdrand() .with_avx() .with_xop() .with_bmi2() .with_sha() .with_rdrand() .with_avx2() } /// `Zen` was the successor to `Excavator`, launched in 2017. `Zen` cores extend SIMD /// instructions to AVX2 and discarded FMA4, TBM, and XOP extensions. they also gained ADX, /// SHA, RDSEED, and other extensions. pub fn zen() -> InstDecoder { k10() .with_avx() .with_avx2() .with_bmi1() .with_aesni() .with_pclmulqdq() .with_f16c() .with_movbe() .with_bmi2() .with_rdrand() .with_adx() .with_sha() .with_rdseed() .with_fma3() // TODO: XSAVEC, XSAVES, XRSTORS, CLFLUSHOPT, CLZERO? } } pub mod intel { //! sourced by walking wikipedia pages. seriously! this stuff is kinda hard to figure out! use crate::real_mode::InstDecoder; /// `Netburst` was the first Intel microarchitecture to implement x86_64, beginning with the /// `Prescott` family launched in 2004. while the wider `Netburst` family launched in 2000 /// with only SSE2, the first `x86_64`-supporting incarnation was `Prescott` which indeed /// included SSE3. pub fn netburst() -> InstDecoder { InstDecoder::minimal() .with_cmov() .with_sse3() } /// `Core` was the successor to `Netburst`, launched in 2006. it included up to SSE4, with /// processors using this architecture shipped under the names "Merom", "Conroe", and /// "Woodcrest", for mobile, desktop, and server processors respectively. not to be confused /// with the later `Nehalem` microarchitecture that introduced the `Core i*` product lines, /// `Core 2 *` processors used the `Core` architecture. pub fn core() -> InstDecoder { netburst() .with_ssse3() .with_sse4() } /// `Penryn` was the successor to `Core`, launched in early 2008. it added SSE4.1, along with /// virtualization extensions. pub fn penryn() -> InstDecoder { core() .with_sse4_1() } /// `Nehalem` was the successor to `Penryn`, launched in late 2008. not to be confused with the /// earlier `Core` microarchitecture, the `Core i*` products were based on `Nehalem` cores. /// `Nehalem` added SSE4.2 extensions, along with the `POPCNT` instruction. pub fn nehalem() -> InstDecoder { penryn() .with_sse4_2() .with_popcnt() } /// `Westmere` was the successor to `Nehalem`, launched in 2010. it added AES-NI and CLMUL /// extensions. pub fn westmere() -> InstDecoder { nehalem() .with_aesni() .with_pclmulqdq() } /// `Sandy Bridge` was the successor to `Westmere`, launched in 2011. it added AVX /// instructions. pub fn sandybridge() -> InstDecoder { westmere() .with_avx() } /// `Ivy Bridge` was the successor to `Sandy Bridge`, launched in 2012. it added F16C /// extensions for 16-bit floating point conversion, and the RDRAND instruction. pub fn ivybridge() -> InstDecoder { sandybridge() .with_f16c() .with_rdrand() } /// `Haswell` was the successor to `Ivy Bridge`, launched in 2013. it added several instruction /// set extensions: AVX2, BMI1, BMI2, ABM, and FMA3. pub fn haswell() -> InstDecoder { ivybridge() .with_bmi1() .with_bmi2() .with_abm() .with_fma3() .with_avx2() } /// `Haswell-EX` was a variant of `Haswell` launched in 2015 with functional TSX. these cores /// were shipped as `E7-48xx/E7-88xx v3` models of processors. pub fn haswell_ex() -> InstDecoder { haswell() .with_tsx() } /// `Broadwell` was the successor to `Haswell`, launched in late 2014. it added ADX, RDSEED, /// and PREFETCHW, as well as broadly rolling out TSX. TSX is enabled on this decoder because /// some chips of this microarchitecture rolled out with TSX, and lack of TSX seems to be /// reported as an errata (for example, the `Broadwell-Y` line of parts). pub fn broadwell() -> InstDecoder { haswell_ex() .with_adx() .with_rdseed() .with_prefetchw() } /// `Skylake` was the successor to `Broadwell`, launched in mid 2015. it added MPX and SGX /// extensions, as well as a mixed rollout of AVX512 in different subsets for different product /// lines. /// /// AVX512 is not enabled on this decoder by default because there doesn't seem to be a lowest /// common denominator: if you want a `Skylake` decoder with AVX512, something like the /// following: /// ``` /// yaxpeax_x86::real_mode::uarch::intel::skylake() /// .with_avx512_f() /// .with_avx512_dq(); /// ``` /// is likely your best option. pub fn skylake() -> InstDecoder { broadwell() .with_mpx() .with_sgx() } /// `Kaby Lake` was the successor to `Sky Lake`, launched in 2016. it adds no extensions to /// x86_64 implementaiton beyond `skylake`. pub fn kabylake() -> InstDecoder { skylake() } // ice lake is shipping so that should probably be included... } yaxpeax-x86-1.2.2/src/real_mode/vex.rs000064400000000000000000003477161046102023000156400ustar 00000000000000use yaxpeax_arch::Reader; use yaxpeax_arch::annotation::DescriptionSink; use crate::real_mode::Arch; use crate::real_mode::OperandSpec; use crate::real_mode::DecodeError; use crate::real_mode::FieldDescription; use crate::real_mode::RegSpec; use crate::real_mode::RegisterBank; use crate::real_mode::InnerDescription; use crate::real_mode::Instruction; use crate::real_mode::Opcode; use crate::real_mode::read_modrm; use crate::real_mode::read_E; use crate::real_mode::read_E_xmm; use crate::real_mode::read_E_ymm; use crate::real_mode::read_imm_unsigned; #[derive(Debug)] enum VEXOpcodeMap { Map0F, Map0F38, Map0F3A, } #[derive(Debug)] enum VEXOpcodePrefix { None, Prefix66, PrefixF3, PrefixF2, } #[allow(non_camel_case_types)] #[derive(Debug)] enum VEXOperandCode { Nothing, VPS_71, VPS_72, VPS_73, VMOVSS_10, VMOVSD_10, VMOVSD_11, VMOVSS_11, VMOVLPS_12, VMOVHPS_16, M_G_xmm, G_M_xmm, G_U_xmm, Gd_U_xmm, E_G_xmm_imm8, Ud_G_xmm_imm8, Ud_G_xyLmm, M_G_xyLmm, M_G_ymm, G_E_ymm, G_M_ymm, Gd_U_ymm, E_xmm_G_ymm_imm8, Ev_G_xmm_imm8, G_ExyL_V_xyLmm, G_E_xmm, G_E_xmm_imm8, G_E_ymm_imm8, G_xmm_E_xmm, G_xmm_E_ymm, G_ymm_E_xmm, G_ymm_M_xmm, G_ymm_E_ymm, G_V_ymm_E_xmm, M_V_G_xmm, M_V_G_ymm, G_V_xmm_Ed, G_V_E_xyLmm, G_E_xyLmm, E_G_xyLmm, G_E_xyLmm_imm8, G_V_E_xyLmm_imm8, G_V_E_xmm, G_V_E_xmm_imm8, G_V_E_xmm_xmm4, G_V_Ed_xmm, G_V_Eq_xmm, G_V_E_ymm, G_V_E_ymm_imm8, G_V_E_ymm_ymm4, G_V_xmm_Ev_imm8, G_V_M_xmm, G_V_M_ymm, G_ymm_V_ymm_E_xmm_imm8, Ed_G_xmm, G_xmm_Ed, G_E_V, G_V_E, G_E_Ib, VCVT_Gd_Ed_xmm, VCVT_Gd_Eq_xmm, BMI1_F3, MXCSR, } #[inline(always)] pub(crate) fn three_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, vex_byte_one: u8, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8 - 8; let vex_byte_two = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let p = vex_byte_two & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; sink.record( vex_start + 8, vex_start + 9, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); let m = vex_byte_one & 0b11111; sink.record( vex_start + 0, vex_start + 4, InnerDescription::Misc(match m { 0b00001 => "vex.mmmmm indicates opcode escape of 0f", 0b00010 => "vex.mmmmm indicates opcode escape of 0f38", 0b00011 => "vex.mmmmm indicates opcode escape of 0f3a", _ => "vex.mmmmm indicates illegal opcode escape and is invalid", }) .with_id(vex_start) ); let m = match m { 0b00001 => VEXOpcodeMap::Map0F, 0b00010 => VEXOpcodeMap::Map0F38, 0b00011 => VEXOpcodeMap::Map0F3A, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte_two >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 11, vex_start + 14, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte_one & 0b10000000 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 6, vex_start + 6, InnerDescription::Misc(if vex_byte_one & 0b01000000 == 0 { "vex.x extends extends index reg (if used) by 0b1000" } else { "vex.x does not alter index reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 5, vex_start + 5, InnerDescription::Misc(if vex_byte_one & 0b00100000 == 0 { "vex.b extends extends base reg (if used) by 0b1000" } else { "vex.b does not alter base reg" }) .with_id(vex_start + 1) ); sink.record( vex_start + 10, vex_start + 10, InnerDescription::Misc(if vex_byte_two & 0b100 == 0 { "vex.l selects 128-bit vector sizes" } else { "vex.l selects 256-bit vector sizes" }) .with_id(vex_start + 1) ); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Misc(if vex_byte_two & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c4(vex_byte_one, vex_byte_two); sink.record( vex_start + 23, vex_start + 23, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 23) ); read_vex_instruction(m, words, instruction, p, sink)?; instruction.regs[3].num &= 0b0111; // ignore bit 4 in 32-bit mode Ok(()) } #[inline(always)] pub(crate) fn two_byte_vex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, vex_byte: u8, instruction: &mut Instruction, sink: &mut S) -> Result<(), DecodeError> { let vex_start = words.offset() as u32 * 8 - 8; let p = vex_byte & 0x03; let p = match p { 0x00 => VEXOpcodePrefix::None, 0x01 => VEXOpcodePrefix::Prefix66, 0x02 => VEXOpcodePrefix::PrefixF3, 0x03 => VEXOpcodePrefix::PrefixF2, _ => { unreachable!("p is two bits"); } }; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: ((vex_byte >> 3) & 0b1111) ^ 0b1111, }; sink.record( vex_start + 0, vex_start + 1, InnerDescription::Misc(match p { VEXOpcodePrefix::None => "vex.p indicates no opcode prefix", VEXOpcodePrefix::Prefix66 => "vex.p indicates opcode prefix 66", VEXOpcodePrefix::PrefixF3 => "vex.p indicates opcode prefix f3", VEXOpcodePrefix::PrefixF2 => "vex.p indicates opcode prefix f2", }) .with_id(vex_start) ); sink.record( vex_start + 3, vex_start + 6, InnerDescription::RegisterNumber("vvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(vex_start + 2) ); sink.record( vex_start + 2, vex_start + 2, InnerDescription::Misc(if vex_byte & 0b100 == 0 { "vex.r extends extends rrr by 0b1000" } else { "vex.r does not alter rrr" }) .with_id(vex_start + 1) ); sink.record( vex_start + 7, vex_start + 7, InnerDescription::Misc(if vex_byte & 0b10000000 != 0 { "vex.w selects 64-bit operand size" } else { "vex.w leaves default operand size" }) .with_id(vex_start + 1) ); instruction.prefixes.vex_from_c5(vex_byte); sink.record( vex_start + 15, vex_start + 15, InnerDescription::Boundary("vex prefix ends/opcode begins") .with_id(vex_start + 15) ); read_vex_instruction(VEXOpcodeMap::Map0F, words, instruction, p, sink)?; instruction.regs[3].num &= 0b0111; // ignore bit 4 in 32-bit mode Ok(()) } #[inline(always)] fn read_vex_operands< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: VEXOperandCode, sink: &mut S) -> Result<(), DecodeError> { // println!("operand code: {:?}", operand_code); match operand_code { VEXOperandCode::VPS_71 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let rrr = (modrm >> 3) & 0b111; if rrr == 0b001 && L { return Err(DecodeError::InvalidOpcode); } instruction.opcode = match rrr { 0b001 => Opcode::VPSLLW, 0b010 => Opcode::VPSRLW, 0b100 => Opcode::VPSRAW, 0b110 => Opcode::VPSLLW, _ => { return Err(DecodeError::InvalidOpcode); } }; instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_72 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLD; } 0b100 => { instruction.opcode = Opcode::VPSRAD; } 0b110 => { instruction.opcode = Opcode::VPSLLD; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VPS_73 => { let modrm = read_modrm(words)?; if modrm & 0xc0 != 0xc0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; match (modrm >> 3) & 0b111 { 0b010 => { instruction.opcode = Opcode::VPSRLQ; } 0b011 => { instruction.opcode = Opcode::VPSRLDQ; } 0b110 => { instruction.opcode = Opcode::VPSLLQ; } 0b111 => { instruction.opcode = Opcode::VPSLLDQ; } _ => { return Err(DecodeError::InvalidOpcode); } } instruction.regs[0] = RegSpec::from_parts(modrm & 7, bank); instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVSS_10 | VEXOperandCode::VMOVSD_10 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegMMM; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[1] = other; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVSS_11 | VEXOperandCode::VMOVSD_11 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[2] = OperandSpec::RegRRR; match mem_oper { OperandSpec::RegMMM => { instruction.operands[0] = OperandSpec::RegMMM; instruction.operands[1] = OperandSpec::RegVex; instruction.operand_count = 3; }, other => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } if instruction.opcode == Opcode::VMOVSS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } instruction.operands[0] = other; instruction.operands[1] = instruction.operands[2]; instruction.operand_count = 2; } } Ok(()) }, VEXOperandCode::VMOVLPS_12 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVHLPS } else { instruction.mem_size = 8; Opcode::VMOVLPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::VMOVHPS_16 => { let modrm = read_modrm(words)?; instruction.opcode = if modrm & 0xc0 == 0xc0 { Opcode::VMOVLHPS } else { instruction.mem_size = 8; Opcode::VMOVHPS }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = read_E_xmm(words, instruction, modrm, sink)?; instruction.operand_count = 3; Ok(()) } VEXOperandCode::Nothing => { if instruction.opcode == Opcode::VZEROUPPER || instruction.opcode == Opcode::VZEROALL { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } } instruction.operand_count = 0; Ok(()) }, VEXOperandCode::Ev_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPEXTRB => { instruction.mem_size = 1; } Opcode::VPEXTRW => { instruction.mem_size = 2; } Opcode::VEXTRACTPS | Opcode::VPEXTRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } instruction.operand_count = 3; instruction.imm = read_imm_unsigned(words, 1)?; Ok(()) }, VEXOperandCode::G_xmm_Ed => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ed_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Ed_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::VCVT_Gd_Eq_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::M_G_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Ud_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_xmm_G_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::Gd_U_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } VEXOperandCode::Gd_U_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::D); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_xmm | op @ VEXOperandCode::G_U_xmm | op @ VEXOperandCode::G_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_U_xmm, 0xc0) => { /* this is the only accepted operand */ } (VEXOperandCode::G_U_xmm, _) | (VEXOperandCode::G_M_xmm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_xmm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VMOVDDUP, Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_xmm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_ymm_M_xmm | op @ VEXOperandCode::G_ymm_E_xmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { if let VEXOperandCode::G_ymm_M_xmm = op { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VBROADCASTSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VBROADCASTSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_ymm_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::M_G_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::M_G_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::M_G_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_M_ymm | op @ VEXOperandCode::G_E_ymm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; match (op, modrm & 0xc0) { (VEXOperandCode::G_M_ymm, 0xc0) => { return Err(DecodeError::InvalidOperand); } (VEXOperandCode::G_M_ymm, _) | // otherwise it's memory-constrained and a memory operand (_, _) => { // ... or unconstrained /* and this is always accepted */ } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 2; Ok(()) } op @ VEXOperandCode::G_V_E_ymm | op @ VEXOperandCode::G_V_M_ymm => { let modrm = read_modrm(words)?; if let VEXOperandCode::G_V_M_ymm = op { if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_ymm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_M_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::E_G_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VMOVLPD || instruction.opcode == Opcode::VMOVHPD || instruction.opcode == Opcode::VMOVHPS { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm_imm8 => { // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_E_xyLmm => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } if instruction.opcode == Opcode::VMOVDDUP && !L { instruction.mem_size = 8; } else if [Opcode::VBROADCASTSS, Opcode::VUCOMISS, Opcode::VCOMISS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VUCOMISD, Opcode::VCOMISD, Opcode::VCVTPS2PD, Opcode::VMOVD].contains(&instruction.opcode) { instruction.mem_size = 8; }; } instruction.operand_count = 2; Ok(()) } VEXOperandCode::G_V_E_xyLmm => { let modrm = read_modrm(words)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { if L { instruction.mem_size = 32; } else { instruction.mem_size = 16; } } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { if [Opcode::VSQRTSS, Opcode::VADDSS, Opcode::VMULSS, Opcode::VSUBSS, Opcode::VMINSS, Opcode::VDIVSS, Opcode::VMAXSS].contains(&instruction.opcode) { instruction.mem_size = 4; } else if [Opcode::VSQRTSD, Opcode::VADDSD, Opcode::VMULSD, Opcode::VSUBSD, Opcode::VMINSD, Opcode::VDIVSD, Opcode::VMAXSD].contains(&instruction.opcode) { instruction.mem_size = 8; } else { instruction.mem_size = 16; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Ed_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_Eq_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ed => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::M_V_G_xmm => { let modrm = read_modrm(words)?; if modrm & 0xc0 == 0xc0 { return Err(DecodeError::InvalidOperand); } instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_ExyL_V_xyLmm => { #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L && instruction.opcode != Opcode::VGATHERQPS && instruction.opcode != Opcode::VPGATHERQD { RegisterBank::Y } else { RegisterBank::X }; let index_bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; if instruction.opcode == Opcode::VPGATHERDQ { instruction.regs[2].bank = RegisterBank::X; } else { instruction.regs[2].bank = index_bank; } instruction.regs[3].bank = bank; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { if instruction.opcode == Opcode::VPGATHERDD || instruction.opcode == Opcode::VPGATHERQD || instruction.opcode == Opcode::VGATHERDPS || instruction.opcode == Opcode::VGATHERQPS { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_V => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); instruction.regs[3].bank = bank; let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operands[2] = OperandSpec::RegVex; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_Ib => { let modrm = read_modrm(words)?; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::BMI1_F3 => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 1 => { Opcode::BLSR } 2 => { Opcode::BLSMSK } 3 => { Opcode::BLSI } _ => { return Err(DecodeError::InvalidOpcode); } }; let bank = RegisterBank::D; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegVex; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = bank as u8; } instruction.regs[3].bank = bank; Ok(()) } VEXOperandCode::MXCSR => { let modrm = read_modrm(words)?; instruction.opcode = match (modrm >> 3) & 7 { 2 => { Opcode::VLDMXCSR } 3 => { Opcode::VSTMXCSR } _ => { return Err(DecodeError::InvalidOpcode); } }; let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; if let OperandSpec::RegMMM = mem_oper { return Err(DecodeError::InvalidOperand); } if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 4; } instruction.operands[0] = mem_oper; instruction.operand_count = 1; Ok(()) } VEXOperandCode::G_E_xyLmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); let bank = if L { RegisterBank::Y } else { RegisterBank::X }; let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, bank); let mem_oper = read_E(words, instruction, modrm, bank, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_xmm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); if L { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::X); let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_E_ymm_imm8 => { if instruction.regs[3].num != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7, RegisterBank::Y); let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_E_ymm_ymm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_ymm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 32; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_E_xmm_xmm4 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)? >> 4; instruction.operands[3] = OperandSpec::Reg4; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 4; Ok(()) } VEXOperandCode::G_V_ymm_E_xmm => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::Y); instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_xmm(words, instruction, modrm, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 16; } instruction.operand_count = 3; Ok(()) } VEXOperandCode::G_V_xmm_Ev_imm8 => { let modrm = read_modrm(words)?; instruction.regs[0] = RegSpec::from_parts((modrm >> 3) & 7,RegisterBank::X); instruction.regs[3].bank = RegisterBank::X; // TODO: but the memory access is word-sized let mem_oper = read_E(words, instruction, modrm, RegisterBank::D, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmI8; if mem_oper != OperandSpec::RegMMM { match instruction.opcode { Opcode::VPINSRB => { instruction.mem_size = 1; } Opcode::VPINSRW => { instruction.mem_size = 2; } Opcode::VINSERTPS | Opcode::VPINSRD => { instruction.mem_size = 4; } _ => { instruction.mem_size = 8; } } } instruction.operand_count = 4; Ok(()) } } } #[inline(never)] fn read_vex_instruction< T: Reader<::Address, ::Word>, S: DescriptionSink, >(opcode_map: VEXOpcodeMap, words: &mut T, instruction: &mut Instruction, p: VEXOpcodePrefix, sink: &mut S) -> Result<(), DecodeError> { let opcode_start = words.offset() as u32 * 8; let opc = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; // the name of this bit is `L` in the documentation, so use the same name here. #[allow(non_snake_case)] let L = instruction.prefixes.vex_unchecked().l(); // println!("reading vex instruction from opcode prefix {:?}, L: {}, opc: {:#x}, map:{:?}", p, L, opc, opcode_map); // println!("w? {}", instruction.prefixes.vex_unchecked().w()); // several combinations simply have no instructions. check for those first. let (opcode, operand_code) = match opcode_map { VEXOpcodeMap::Map0F => { match p { VEXOpcodePrefix::None => { match opc { 0x10 => (Opcode::VMOVUPS, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPS, VEXOperandCode::E_G_xyLmm), 0x12 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVLPS_12 }), 0x13 => (Opcode::VMOVLPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPS, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPS, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::VMOVHPS_16 }), 0x17 => (Opcode::VMOVHPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPS, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPS, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPS, if L { VEXOperandCode::M_G_ymm } else { VEXOperandCode::M_G_xmm }), 0x2e => (Opcode::VUCOMISS, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISS, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPS, VEXOperandCode::Ud_G_xyLmm), 0x51 => (Opcode::VSQRTPS, VEXOperandCode::G_E_xyLmm), 0x52 => (Opcode::VRSQRTPS, VEXOperandCode::G_E_xyLmm), 0x53 => (Opcode::VRCPPS, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPS, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPS, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPS, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPS, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPS, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPS, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPS2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x5B => (Opcode::VCVTDQ2PS, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPS, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPS, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPS, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPS, VEXOperandCode::G_V_E_xyLmm), 0x77 => if L { (Opcode::VZEROALL, VEXOperandCode::Nothing) } else { (Opcode::VZEROUPPER, VEXOperandCode::Nothing) }, 0xAE => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::MXCSR }), 0xC2 => (Opcode::VCMPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC6 => (Opcode::VSHUFPS, VEXOperandCode::G_V_E_xyLmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } }, VEXOpcodePrefix::Prefix66 => { match opc { // 0x0a => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), // 0x0b => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x10 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x11 => (Opcode::VMOVUPD, VEXOperandCode::G_E_xyLmm), 0x12 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x13 => (Opcode::VMOVLPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x14 => (Opcode::VUNPCKLPD, VEXOperandCode::G_V_E_xyLmm), 0x15 => (Opcode::VUNPCKHPD, VEXOperandCode::G_V_E_xyLmm), 0x16 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_M_xmm }), 0x17 => (Opcode::VMOVHPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::M_G_xmm }), 0x28 => (Opcode::VMOVAPD, VEXOperandCode::G_E_xyLmm), 0x29 => (Opcode::VMOVAPD, VEXOperandCode::E_G_xyLmm), 0x2B => (Opcode::VMOVNTPD, VEXOperandCode::M_G_xyLmm), 0x2e => (Opcode::VUCOMISD, VEXOperandCode::G_E_xmm), 0x2f => (Opcode::VCOMISD, VEXOperandCode::G_E_xmm), 0x50 => (Opcode::VMOVMSKPD, if L { VEXOperandCode::Gd_U_ymm } else { VEXOperandCode::Gd_U_xmm }), 0x51 => (Opcode::VSQRTPD, VEXOperandCode::G_E_xyLmm), 0x54 => (Opcode::VANDPD, VEXOperandCode::G_V_E_xyLmm), 0x55 => (Opcode::VANDNPD, VEXOperandCode::G_V_E_xyLmm), 0x56 => (Opcode::VORPD, VEXOperandCode::G_V_E_xyLmm), 0x57 => (Opcode::VXORPD, VEXOperandCode::G_V_E_xyLmm), 0x58 => (Opcode::VADDPD, VEXOperandCode::G_V_E_xyLmm), 0x59 => (Opcode::VMULPD, VEXOperandCode::G_V_E_xyLmm), 0x5A => (Opcode::VCVTPD2PS, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5B => (Opcode::VCVTPS2DQ, VEXOperandCode::G_E_xyLmm), 0x5C => (Opcode::VSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x5D => (Opcode::VMINPD, VEXOperandCode::G_V_E_xyLmm), 0x5E => (Opcode::VDIVPD, VEXOperandCode::G_V_E_xyLmm), 0x5F => (Opcode::VMAXPD, VEXOperandCode::G_V_E_xyLmm), 0x60 => (Opcode::VPUNPCKLBW, VEXOperandCode::G_V_E_xyLmm), 0x61 => (Opcode::VPUNPCKLWD, VEXOperandCode::G_V_E_xyLmm), 0x62 => (Opcode::VPUNPCKLDQ, VEXOperandCode::G_V_E_xyLmm), 0x63 => (Opcode::VPACKSSWB, VEXOperandCode::G_V_E_xyLmm), 0x64 => (Opcode::VPCMPGTB, VEXOperandCode::G_V_E_xyLmm), 0x65 => (Opcode::VPCMPGTW, VEXOperandCode::G_V_E_xyLmm), 0x66 => (Opcode::VPCMPGTD, VEXOperandCode::G_V_E_xyLmm), 0x67 => (Opcode::VPACKUSWB, VEXOperandCode::G_V_E_xyLmm), 0x68 => (Opcode::VPUNPCKHBW, VEXOperandCode::G_V_E_xyLmm), 0x69 => (Opcode::VPUNPCKHWD, VEXOperandCode::G_V_E_xyLmm), 0x6A => (Opcode::VPUNPCKHDQ, VEXOperandCode::G_V_E_xyLmm), 0x6B => (Opcode::VPACKSSDW, VEXOperandCode::G_V_E_xyLmm), 0x6C => (Opcode::VPUNPCKLQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6D => (Opcode::VPUNPCKHQDQ, VEXOperandCode::G_V_E_xyLmm), 0x6E => { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_xmm_Ed }) }, 0x6F => (Opcode::VMOVDQA, VEXOperandCode::G_E_xyLmm), 0x70 => (Opcode::VPSHUFD, VEXOperandCode::G_E_xyLmm_imm8), 0x71 => (Opcode::Invalid, VEXOperandCode::VPS_71), 0x72 => (Opcode::Invalid, VEXOperandCode::VPS_72), 0x73 => (Opcode::Invalid, VEXOperandCode::VPS_73), 0x74 => (Opcode::VPCMPEQB, VEXOperandCode::G_V_E_xyLmm), 0x75 => (Opcode::VPCMPEQW, VEXOperandCode::G_V_E_xyLmm), 0x76 => (Opcode::VPCMPEQD, VEXOperandCode::G_V_E_xyLmm), 0x7C => (Opcode::VHADDPD, VEXOperandCode::G_V_E_xyLmm), 0x7D => (Opcode::VHSUBPD, VEXOperandCode::G_V_E_xyLmm), 0x7E => { (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ed_G_xmm }) } 0x7F => (Opcode::VMOVDQA, VEXOperandCode::E_G_xyLmm), 0xC2 => (Opcode::VCMPPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xC4 => (Opcode::VPINSRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0xC5 => (Opcode::VPEXTRW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ud_G_xmm_imm8 }), 0xC6 => (Opcode::VSHUFPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0xD0 => (Opcode::VADDSUBPD, VEXOperandCode::G_V_E_xyLmm), 0xD1 => (Opcode::VPSRLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD2 => (Opcode::VPSRLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD3 => (Opcode::VPSRLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xD4 => (Opcode::VPADDQ, VEXOperandCode::G_V_E_xyLmm), 0xD5 => (Opcode::VPMULLW, VEXOperandCode::G_V_E_xyLmm), 0xD6 => (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xD7 => (Opcode::VPMOVMSKB, VEXOperandCode::Ud_G_xyLmm), 0xD8 => (Opcode::VPSUBUSB, VEXOperandCode::G_V_E_xyLmm), 0xD9 => (Opcode::VPSUBUSW, VEXOperandCode::G_V_E_xyLmm), 0xDA => (Opcode::VPMINUB, VEXOperandCode::G_V_E_xyLmm), 0xDB => (Opcode::VPAND, VEXOperandCode::G_V_E_xyLmm), 0xDC => (Opcode::VPADDUSB, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VPADDUSW, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VPMAXUB, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VPANDN, VEXOperandCode::G_V_E_xyLmm), 0xE0 => (Opcode::VPAVGB, VEXOperandCode::G_V_E_xyLmm), 0xE1 => (Opcode::VPSRAW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE2 => (Opcode::VPSRAD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xE3 => (Opcode::VPAVGW, VEXOperandCode::G_V_E_xyLmm), 0xE4 => (Opcode::VPMULHUW, VEXOperandCode::G_V_E_xyLmm), 0xE5 => (Opcode::VPMULHW, VEXOperandCode::G_V_E_xyLmm), 0xE6 => (Opcode::VCVTTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_E_xmm }), 0xE7 => (Opcode::VMOVNTDQ, VEXOperandCode::M_G_xyLmm), 0xE8 => (Opcode::VPSUBSB, VEXOperandCode::G_V_E_xyLmm), 0xE9 => (Opcode::VPSUBSW, VEXOperandCode::G_V_E_xyLmm), 0xEA => (Opcode::VPMINSW, VEXOperandCode::G_V_E_xyLmm), 0xEB => (Opcode::VPOR, VEXOperandCode::G_V_E_xyLmm), 0xEC => (Opcode::VPADDSB, VEXOperandCode::G_V_E_xyLmm), 0xED => (Opcode::VPADDSW, VEXOperandCode::G_V_E_xyLmm), 0xEE => (Opcode::VPMAXSW, VEXOperandCode::G_V_E_xyLmm), 0xEF => (Opcode::VPXOR, VEXOperandCode::G_V_E_xyLmm), 0xF1 => (Opcode::VPSLLW, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF2 => (Opcode::VPSLLD, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF3 => (Opcode::VPSLLQ, if L { VEXOperandCode::G_V_ymm_E_xmm } else { VEXOperandCode::G_V_E_xmm }), 0xF4 => (Opcode::VPMULUDQ, VEXOperandCode::G_V_E_xyLmm), 0xF5 => (Opcode::VPMADDWD, VEXOperandCode::G_V_E_xyLmm), 0xF6 => (Opcode::VPSADBW, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::VMASKMOVDQU, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_U_xmm }), 0xF8 => (Opcode::VPSUBB, VEXOperandCode::G_V_E_xyLmm), 0xF9 => (Opcode::VPSUBW, VEXOperandCode::G_V_E_xyLmm), 0xFA => (Opcode::VPSUBD, VEXOperandCode::G_V_E_xyLmm), 0xFB => (Opcode::VPSUBQ, VEXOperandCode::G_V_E_xyLmm), 0xFC => (Opcode::VPADDB, VEXOperandCode::G_V_E_xyLmm), 0xFD => (Opcode::VPADDW, VEXOperandCode::G_V_E_xyLmm), 0xFE => (Opcode::VPADDD, VEXOperandCode::G_V_E_xyLmm), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF2 => { match opc { 0x10 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_10), 0x11 => (Opcode::VMOVSD, VEXOperandCode::VMOVSD_11), 0x12 => (Opcode::VMOVDDUP, VEXOperandCode::G_E_xyLmm), 0x2a => (Opcode::VCVTSI2SD, { VEXOperandCode::G_V_xmm_Ed // 32-bit last operand }), 0x2c => (Opcode::VCVTTSD2SI, { VEXOperandCode::VCVT_Gd_Eq_xmm }), 0x2d => (Opcode::VCVTSD2SI, { VEXOperandCode::VCVT_Gd_Eq_xmm }), 0x51 => (Opcode::VSQRTSD, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSD, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSD, VEXOperandCode::G_V_E_xmm), 0x5a => (Opcode::VCVTSD2SS, VEXOperandCode::G_V_Eq_xmm), 0x5c => (Opcode::VSUBSD, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSD, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSD, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSD, VEXOperandCode::G_V_E_xmm), 0x70 => (Opcode::VPSHUFLW, VEXOperandCode::G_E_xyLmm_imm8), 0x7c => (Opcode::VHADDPS, VEXOperandCode::G_V_E_xyLmm), 0x7d => (Opcode::VHSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xc2 => (Opcode::VCMPSD, VEXOperandCode::G_V_E_xmm_imm8), 0xd0 => (Opcode::VADDSUBPS, VEXOperandCode::G_V_E_xyLmm), 0xe6 => (Opcode::VCVTPD2DQ, if L { VEXOperandCode::G_xmm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0xf0 => (Opcode::VLDDQU, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } VEXOpcodePrefix::PrefixF3 => { match opc { 0x10 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_10), 0x11 => (Opcode::VMOVSS, VEXOperandCode::VMOVSS_11), 0x12 => (Opcode::VMOVSLDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x16 => (Opcode::VMOVSHDUP, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x2a => (Opcode::VCVTSI2SS, { VEXOperandCode::G_V_xmm_Ed }), 0x2c => (Opcode::VCVTTSS2SI, { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x2d => (Opcode::VCVTSS2SI, { VEXOperandCode::VCVT_Gd_Ed_xmm }), 0x51 => (Opcode::VSQRTSS, VEXOperandCode::G_V_E_xmm), 0x52 => (Opcode::VRSQRTSS, VEXOperandCode::G_V_E_xmm), 0x53 => (Opcode::VRCPSS, VEXOperandCode::G_V_E_xmm), 0x58 => (Opcode::VADDSS, VEXOperandCode::G_V_E_xmm), 0x59 => (Opcode::VMULSS, VEXOperandCode::G_V_Ed_xmm), 0x5a => (Opcode::VCVTSS2SD, VEXOperandCode::G_V_Ed_xmm), 0x5b => (Opcode::VCVTTPS2DQ, if L { VEXOperandCode::G_ymm_E_ymm } else { VEXOperandCode::G_xmm_E_xmm }), 0x5c => (Opcode::VSUBSS, VEXOperandCode::G_V_E_xmm), 0x5d => (Opcode::VMINSS, VEXOperandCode::G_V_E_xmm), 0x5e => (Opcode::VDIVSS, VEXOperandCode::G_V_E_xmm), 0x5f => (Opcode::VMAXSS, VEXOperandCode::G_V_E_xmm), 0x6f => (Opcode::VMOVDQU, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_xmm }), 0x70 => (Opcode::VPSHUFHW, VEXOperandCode::G_E_xyLmm_imm8), 0x7e => (Opcode::VMOVD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x7f => (Opcode::VMOVDQU, VEXOperandCode::E_G_xyLmm), 0xc2 => (Opcode::VCMPSS, VEXOperandCode::G_V_E_xmm_imm8), 0xe6 => (Opcode::VCVTDQ2PD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_xmm_E_xmm }), _ => { return Err(DecodeError::InvalidOpcode); } } } } } VEXOpcodeMap::Map0F38 => { // TODO: verify rejecting invalid W bit if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPSHUFB, VEXOperandCode::G_V_E_xyLmm), 0x01 => (Opcode::VPHADDW, VEXOperandCode::G_V_E_xyLmm), 0x02 => (Opcode::VPHADDD, VEXOperandCode::G_V_E_xyLmm), 0x03 => (Opcode::VPHADDSW, VEXOperandCode::G_V_E_xyLmm), 0x04 => (Opcode::VPMADDUBSW, VEXOperandCode::G_V_E_xyLmm), 0x05 => (Opcode::VPHSUBW, VEXOperandCode::G_V_E_xyLmm), 0x06 => (Opcode::VPHSUBD, VEXOperandCode::G_V_E_xyLmm), 0x07 => (Opcode::VPHSUBSW, VEXOperandCode::G_V_E_xyLmm), 0x08 => (Opcode::VPSIGNB, VEXOperandCode::G_V_E_xyLmm), 0x09 => (Opcode::VPSIGNW, VEXOperandCode::G_V_E_xyLmm), 0x0A => (Opcode::VPSIGND, VEXOperandCode::G_V_E_xyLmm), 0x0B => (Opcode::VPMULHRSW, VEXOperandCode::G_V_E_xyLmm), 0x0C => (Opcode::VPERMILPS, VEXOperandCode::G_V_E_xyLmm), 0x0D => (Opcode::VPERMILPD, VEXOperandCode::G_V_E_xyLmm), 0x0E => (Opcode::VTESTPS, VEXOperandCode::G_E_xyLmm), 0x0F => (Opcode::VTESTPD, VEXOperandCode::G_E_xyLmm), 0x13 => (Opcode::VCVTPH2PS, VEXOperandCode::G_E_xyLmm), 0x16 => (Opcode::VPERMPS, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x17 => (Opcode::VPTEST, VEXOperandCode::G_E_xyLmm), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSS, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VBROADCASTSD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }) } 0x1A => (Opcode::VBROADCASTF128, if L { VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x1C => (Opcode::VPABSB, VEXOperandCode::G_E_xyLmm), 0x1D => (Opcode::VPABSW, VEXOperandCode::G_E_xyLmm), 0x1E => (Opcode::VPABSD, VEXOperandCode::G_E_xyLmm), 0x20 => (Opcode::VPMOVSXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x21 => (Opcode::VPMOVSXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x22 => (Opcode::VPMOVSXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x23 => (Opcode::VPMOVSXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x24 => (Opcode::VPMOVSXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x25 => (Opcode::VPMOVSXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x28 => (Opcode::VPMULDQ, VEXOperandCode::G_V_E_xyLmm), 0x29 => (Opcode::VPCMPEQQ, VEXOperandCode::G_V_E_xyLmm), 0x2A => (Opcode::VMOVNTDQA, if L { VEXOperandCode::G_M_ymm } else { VEXOperandCode::G_M_xmm }), 0x2B => (Opcode::VPACKUSDW, VEXOperandCode::G_V_E_xyLmm), 0x2C => (Opcode::VMASKMOVPS, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2D => (Opcode::VMASKMOVPD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }), 0x2E => (Opcode::VMASKMOVPS, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x2F => (Opcode::VMASKMOVPD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }), 0x30 => (Opcode::VPMOVZXBW, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x31 => (Opcode::VPMOVZXBD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x32 => (Opcode::VPMOVZXBQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x33 => (Opcode::VPMOVZXWD, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x34 => (Opcode::VPMOVZXWQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x35 => (Opcode::VPMOVZXDQ, if L { VEXOperandCode::G_ymm_E_xmm } else { VEXOperandCode::G_E_xmm }), 0x36 => (Opcode::VPERMD, if L { VEXOperandCode::G_V_E_ymm } else { return Err(DecodeError::InvalidOpcode); }), 0x37 => (Opcode::VPCMPGTQ, VEXOperandCode::G_V_E_xyLmm), 0x38 => (Opcode::VPMINSB, VEXOperandCode::G_V_E_xyLmm), 0x39 => (Opcode::VPMINSD, VEXOperandCode::G_V_E_xyLmm), 0x3A => (Opcode::VPMINUW, VEXOperandCode::G_V_E_xyLmm), 0x3B => (Opcode::VPMINUD, VEXOperandCode::G_V_E_xyLmm), 0x3C => (Opcode::VPMAXSB, VEXOperandCode::G_V_E_xyLmm), 0x3D => (Opcode::VPMAXSD, VEXOperandCode::G_V_E_xyLmm), 0x3E => (Opcode::VPMAXUW, VEXOperandCode::G_V_E_xyLmm), 0x3F => (Opcode::VPMAXUD, VEXOperandCode::G_V_E_xyLmm), 0x40 => (Opcode::VPMULLD, VEXOperandCode::G_V_E_xyLmm), 0x41 => (Opcode::VPHMINPOSUW, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0x45 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSRLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSRLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x46 => (Opcode::VPSRAVD, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm } else { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_xmm }), 0x47 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VPSLLVQ, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VPSLLVD, VEXOperandCode::G_V_E_xyLmm) }, 0x58 => (Opcode::VPBROADCASTD, VEXOperandCode::G_E_xyLmm), 0x59 => (Opcode::VPBROADCASTQ, VEXOperandCode::G_E_xyLmm), 0x5A => (Opcode::VBROADCASTI128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_ymm_M_xmm } else { return Err(DecodeError::InvalidOpcode); }), 0x78 => (Opcode::VPBROADCASTB, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x79 => (Opcode::VPBROADCASTW, if L { VEXOperandCode::G_E_ymm } else { VEXOperandCode::G_E_ymm }), 0x8C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::G_V_M_ymm } else { VEXOperandCode::G_V_M_xmm }) } }, 0x8E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPMASKMOVQ, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } else { (Opcode::VPMASKMOVD, if L { VEXOperandCode::M_V_G_ymm } else { VEXOperandCode::M_V_G_xmm }) } }, 0x90 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERDQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERDD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x91 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VPGATHERQQ, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VPGATHERQD, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x92 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERDPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERDPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x93 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VGATHERQPD, VEXOperandCode::G_ExyL_V_xyLmm) } else { (Opcode::VGATHERQPS, VEXOperandCode::G_ExyL_V_xyLmm) } }, 0x96 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x97 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x98 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x99 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9A => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9B => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9C => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9D => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0x9E => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB132PS, VEXOperandCode::G_V_E_xyLmm) } }, 0x9F => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB132SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB132SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xA6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xA9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xAE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB213PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xAF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB213SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB213SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xB6 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADDSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADDSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB7 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUBADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUBADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB8 => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xB9 => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBA => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBB => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBC => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMADD231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBD => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMADD231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMADD231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xBE => { if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231PD, VEXOperandCode::G_V_E_xyLmm) } else { (Opcode::VFNMSUB231PS, VEXOperandCode::G_V_E_xyLmm) } }, 0xBF => if instruction.prefixes.vex_unchecked().w() { (Opcode::VFNMSUB231SD, VEXOperandCode::G_V_E_xmm /* 64bit */) } else { (Opcode::VFNMSUB231SS, VEXOperandCode::G_V_E_xmm /* 64bit */) }, 0xDB => (Opcode::VAESIMC, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_xmm }), 0xDC => (Opcode::VAESENC, VEXOperandCode::G_V_E_xyLmm), 0xDD => (Opcode::VAESENCLAST, VEXOperandCode::G_V_E_xyLmm), 0xDE => (Opcode::VAESDEC, VEXOperandCode::G_V_E_xyLmm), 0xDF => (Opcode::VAESDECLAST, VEXOperandCode::G_V_E_xyLmm), 0xF7 => (Opcode::SHLX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF5 => (Opcode::PDEP, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF6 => (Opcode::MULX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SHRX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF3 = p { match opc { 0xF5 => (Opcode::PEXT, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF7 => (Opcode::SARX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { match opc { 0xF2 => (Opcode::ANDN, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E }), 0xF3 => (Opcode::Invalid, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::BMI1_F3 }), 0xF5 => (Opcode::BZHI, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), 0xF7 => (Opcode::BEXTR, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_V }), _ => { return Err(DecodeError::InvalidOpcode); } } } } VEXOpcodeMap::Map0F3A => { if let VEXOpcodePrefix::Prefix66 = p { // possibly valid! match opc { 0x00 => (Opcode::VPERMQ, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x01 => (Opcode::VPERMPD, if L { if !instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x02 => (Opcode::VPBLENDD, if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xyLmm_imm8 }), 0x04 => (Opcode::VPERMILPS, VEXOperandCode::G_E_xyLmm_imm8), 0x05 => (Opcode::VPERMILPD, VEXOperandCode::G_E_xyLmm_imm8), 0x06 => (Opcode::VPERM2F128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x08 => (Opcode::VROUNDPS, VEXOperandCode::G_E_xyLmm_imm8), 0x09 => (Opcode::VROUNDPD, VEXOperandCode::G_E_xyLmm_imm8), 0x0A => (Opcode::VROUNDSS, VEXOperandCode::G_V_E_xmm_imm8), 0x0B => (Opcode::VROUNDSD, VEXOperandCode::G_V_E_xmm_imm8), 0x0C => (Opcode::VBLENDPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0D => (Opcode::VBLENDPD, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0E => (Opcode::VPBLENDW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x0F => (Opcode::VPALIGNR, VEXOperandCode::G_V_E_xyLmm_imm8), 0x14 => (Opcode::VPEXTRB, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x15 => (Opcode::VPEXTRW, if L || instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x16 => { (Opcode::VPEXTRD, if L { return Err(DecodeError::InvalidOpcode); } else { // varies on W VEXOperandCode::Ev_G_xmm_imm8 }) }, 0x17 => (Opcode::VEXTRACTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::Ev_G_xmm_imm8 }), 0x18 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VINSERTF128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x19 => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VEXTRACTF128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }) }, 0x1D => (Opcode::VCVTPS2PH, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { VEXOperandCode::E_G_xmm_imm8 }), 0x20 => (Opcode::VPINSRB, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }), 0x21 => (Opcode::VINSERTPS, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x22 => { (Opcode::VPINSRD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_xmm_Ev_imm8 }) }, 0x38 => (Opcode::VINSERTI128, if L { VEXOperandCode::G_ymm_V_ymm_E_xmm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x39 => (Opcode::VEXTRACTI128, if L { VEXOperandCode::E_xmm_G_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x40 => (Opcode::VDPPS, VEXOperandCode::G_V_E_xyLmm_imm8), 0x41 => (Opcode::VDPPD, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x42 => (Opcode::VMPSADBW, VEXOperandCode::G_V_E_xyLmm_imm8), 0x44 => (Opcode::VPCLMULQDQ, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_V_E_xmm_imm8 }), 0x46 => (Opcode::VPERM2I128, if L { if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } VEXOperandCode::G_V_E_ymm_imm8 } else { return Err(DecodeError::InvalidOpcode); }), 0x4A => (Opcode::VBLENDVPS, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4B => (Opcode::VBLENDVPD, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }), 0x4C => if instruction.prefixes.vex_unchecked().w() { return Err(DecodeError::InvalidOpcode); } else { (Opcode::VPBLENDVB, if L { VEXOperandCode::G_V_E_ymm_ymm4 } else { VEXOperandCode::G_V_E_xmm_xmm4 }) }, 0x60 => (Opcode::VPCMPESTRM, VEXOperandCode::G_E_xmm_imm8), 0x61 => (Opcode::VPCMPESTRI, VEXOperandCode::G_E_xmm_imm8), 0x62 => (Opcode::VPCMPISTRM, VEXOperandCode::G_E_xmm_imm8), 0x63 => (Opcode::VPCMPISTRI, VEXOperandCode::G_E_xmm_imm8), 0xDF => (Opcode::VAESKEYGENASSIST, VEXOperandCode::G_E_xmm_imm8), _ => { return Err(DecodeError::InvalidOpcode); } } } else if let VEXOpcodePrefix::PrefixF2 = p { match opc { 0xF0 => (Opcode::RORX, if L { return Err(DecodeError::InvalidOpcode); } else { VEXOperandCode::G_E_Ib }), _ => { return Err(DecodeError::InvalidOpcode); } } } else { // the only VEX* 0f3a instructions have an implied 66 prefix. return Err(DecodeError::InvalidOpcode); } } }; instruction.opcode = opcode; sink.record( opcode_start, opcode_start + 7, InnerDescription::Opcode(instruction.opcode) .with_id(opcode_start) ); sink.record( opcode_start + 7, opcode_start + 7, InnerDescription::Boundary("vex opcode ends/operands begin") .with_id(opcode_start + 7) ); read_vex_operands(words, instruction, operand_code, sink) } yaxpeax-x86-1.2.2/src/safer_unchecked.rs000064400000000000000000000013511046102023000161760ustar 00000000000000use core::slice::SliceIndex; pub trait GetSaferUnchecked { unsafe fn get_kinda_unchecked(&self, index: I) -> &>::Output where I: SliceIndex<[T]>; } impl GetSaferUnchecked for [T] { #[inline(always)] unsafe fn get_kinda_unchecked(&self, index: I) -> &>::Output where I: SliceIndex<[T]>, { if cfg!(debug_assertions) { &self[index] } else { self.get_unchecked(index) } } } #[inline(always)] pub unsafe fn unreachable_kinda_unchecked() -> ! { if cfg!(debug_assertions) { panic!("UB: Unreachable unchecked was executed") } else { core::hint::unreachable_unchecked() } } yaxpeax-x86-1.2.2/src/shared/evex.in000064400000000000000000005611531046102023000152770ustar 00000000000000use super::OperandSpec; use super::FieldDescription; use super::InnerDescription; use yaxpeax_arch::annotation::DescriptionSink; // `evex_byte_one` is an option because the caller *may* have already read it, // but may have not. `long_mode` can decide immediately that `0x62` should be read // as an `EVEX` instruction, but for other modes we can only make this // determination when reading a `bound`'s `modrm` byte. #[inline(never)] pub(crate) fn read_evex< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, evex_byte_one: Option, sink: &mut S) -> Result<(), DecodeError> { let evex_byte_one = if let Some(b) = evex_byte_one { b } else { words.next().ok().ok_or(DecodeError::ExhaustedInput)? }; let evex_start = words.offset() as u32 * 8 - 8; let evex_byte_two = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let evex_byte_three = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let p = evex_byte_two & 0x03; sink.record( evex_start + 8, evex_start + 9, InnerDescription::Misc(match p { 0b00 => "evex.p indicates no opcode prefix", 0b01 => "evex.p indicates opcode prefix 66", 0b10 => "evex.p indicates opcode prefix f3", _ => "evex.p indicates opcode prefix f2", }) .with_id(evex_start + 1) ); if evex_byte_one & 0x0c != 0 { // the two bits above `m` are reserved and must be 0 return Err(DecodeError::InvalidOpcode); } sink.record( evex_start + 2, evex_start + 3, InnerDescription::Misc("reserved bit pattern in evex prefix") .with_id(evex_start + 0) ); if evex_byte_two & 0x04 == 0 { // the one bit above `p` is reserved and must be 1 return Err(DecodeError::InvalidOpcode); } sink.record( evex_start + 10, evex_start + 10, InnerDescription::Misc("reserved bit pattern in evex prefix") .with_id(evex_start + 0) ); let m = evex_byte_one & 0x03; sink.record( evex_start + 0, evex_start + 1, InnerDescription::Misc(match m { 0b00 => "evex.m indicates no opcode escape (invalid)", 0b01 => "evex.m indicates opcode escape `0f`", 0b10 => "evex.m indicates opcode escape `0f38`", _ => "evex.m indicates opcode escape `0f3a`", }) .with_id(evex_start + 0) ); if m == 0 { return Err(DecodeError::InvalidOpcode); } let m = m - 1; // instead of enums for the lookup bits, these are used to select a TABLES entry in the first // place /* let p = [ EVEXOpcodePrefix::None, EVEXOpcodePrefix::Prefix66, EVEXOpcodePrefix::PrefixF3, EVEXOpcodePrefix::PrefixF2, ][p]; let m = [ Ok(EVEXOpcodeMap::Map0F), Ok(EVEXOpcodeMap::Map0F38), Ok(EVEXOpcodeMap::Map0F3A), Err(DecodeError::InvalidOpcode), ][m - 1]?; */ let vp = ((evex_byte_three >> 3) & 1) << 4; let vvvvv = ((evex_byte_two >> 3) & 0b1111) | vp; instruction.regs[3] = RegSpec { bank: RegisterBank::X, num: vvvvv ^ 0b11111 // `vvvvv` is provided in inverted form }; instruction.prefixes.evex_from(evex_byte_one, evex_byte_two, evex_byte_three); let evex_rex = ((evex_byte_two & 0x80) >> 4) | (((evex_byte_one >> 5) & 0b111) ^ 0b111); sink.record( evex_start + 5, evex_start + 7, InnerDescription::RexPrefix(evex_rex) .with_id(evex_start + 5) ); sink.record( evex_start + 15, evex_start + 15, InnerDescription::RexPrefix(evex_rex) .with_id(evex_start + 5) ); sink.record( evex_start + 4, evex_start + 4, InnerDescription::Misc(if ((evex_byte_one >> 4) & 1) ^ 1 != 0 { "evex.r' is set (stored inverted)" } else { "evex.r' is not set (stored inverted)" }) .with_id(evex_start + 4) ); sink.record( evex_start + 20, evex_start + 20, InnerDescription::Misc(if ((evex_byte_three >> 4) & 1) != 0 { "evex.b (broadcast) is set" } else { "evex.b (broadcast) is not set" }) .with_id(evex_start + 4) ); sink.record( evex_start + 23, evex_start + 23, InnerDescription::Misc(if ((evex_byte_three >> 7) & 1) != 0 { "evex.z is set (masking behavior: zero)" } else { "evex.z is unset (masking behavior: merge)" }) .with_id(evex_start + 4) ); let lpl = (evex_byte_three >> 5) & 0b11; sink.record( evex_start + 21, evex_start + 22, InnerDescription::Misc(match lpl { 0b00 => "evex.l'l is `0b00` (vector size 128 or rne-sae)", 0b01 => "evex.l'l is `0b01` (vector size 256 or rd-sae)", 0b10 => "evex.l'l is `0b10` (vector size 512 or ru-sae)", _ => "evex.l'l is `0b11` (vector size 512 + rz-sae)", }) .with_id(evex_start + 22) ); sink.record( evex_start + 16, evex_start + 18, InnerDescription::RegisterNumber("evex.aaa", evex_byte_three & 0b111, RegSpec::mask(evex_byte_three & 0b111)) .with_id(evex_start + 16) ); sink.record( evex_start + 23, evex_start + 23, InnerDescription::Boundary("evex prefix ends/opcode begins") .with_id(evex_start + 23) ); let opc = words.next().ok().ok_or(DecodeError::ExhaustedInput)?; let table_idx = ((m << 2) | p) as usize; let table = generated::TABLES[table_idx]; if table as *const [_] == &generated::DUMMY[..] as *const [_] { return Err(DecodeError::InvalidOpcode); } let mut index_lower = 0; if instruction.prefixes.evex_unchecked().vex().l() { index_lower |= 1; } if instruction.prefixes.evex_unchecked().lp() { index_lower |= 2; } if let Ok(entry) = table.binary_search_by_key(&opc, |x| x.0) { let (opcode, operand_code) = table[entry].1[index_lower]; instruction.opcode = opcode; sink.record( evex_start + 24, evex_start + 31, InnerDescription::Opcode(instruction.opcode) .with_id(evex_start + 24) ); read_evex_operands(words, instruction, operand_code, sink)?; if instruction.prefixes.evex_unchecked().rp() { instruction.regs[0].num |= 0b10000; if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[0].bank) { return Err(DecodeError::InvalidOperand); } } if instruction.prefixes.evex_unchecked().vex().x() { if instruction.operands.contains(&OperandSpec::RegMMM) { instruction.regs[1].num |= 0b10000; if ![RegisterBank::X, RegisterBank::Y, RegisterBank::Z].contains(&instruction.regs[1].bank) { return Err(DecodeError::InvalidOperand); } } } // have to wait til after `read_evex_operands` to report evex register // because its size may be updated as part of reading operands. sink.record( evex_start + 11, evex_start + 14, InnerDescription::RegisterNumber("evex.vvvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(evex_start + 11) ); sink.record( evex_start + 19, evex_start + 19, InnerDescription::RegisterNumber("evex.vvvvv", instruction.regs[3].num, instruction.regs[3]) .with_id(evex_start + 11) ); if instruction.prefixes.evex_unchecked().vex().compressed_disp() { let overridden_size = match instruction.opcode { Opcode::VPEXPANDB => Some(1), Opcode::VPEXPANDW => Some(2), Opcode::VPEXPANDD => Some(4), Opcode::VPEXPANDQ => Some(8), Opcode::VPCOMPRESSB => Some(1), Opcode::VPCOMPRESSW => Some(2), Opcode::VPCOMPRESSD => Some(4), Opcode::VPCOMPRESSQ => Some(8), Opcode::VEXPANDPS => Some(4), Opcode::VEXPANDPD => Some(8), Opcode::VCOMPRESSPS => Some(4), Opcode::VCOMPRESSPD => Some(8), _ => None }; if let Some(size) = overridden_size { instruction.disp = instruction.disp.wrapping_mul(size); } else { instruction.disp = instruction.disp.wrapping_mul(instruction.mem_size.into()); } instruction.prefixes.apply_compressed_disp(false); } if instruction.opcode == Opcode::Invalid { return Err(DecodeError::InvalidOpcode); } // TODO: apply rp and bp? } else { return Err(DecodeError::InvalidOpcode); } Ok(()) } #[inline(always)] fn deny_broadcast(inst: &Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex_unchecked().broadcast() { Err(DecodeError::InvalidOperand) } else { Ok(()) } } #[inline(always)] fn deny_z(inst: &Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex_unchecked().merge() { Err(DecodeError::InvalidOperand) } else { Ok(()) } } #[inline(always)] fn deny_vex_reg(inst: &Instruction) -> Result<(), DecodeError> { if inst.regs[3].num != 0 { Err(DecodeError::InvalidOperand) } else { Ok(()) } } #[allow(non_snake_case)] #[inline(always)] fn ensure_W(inst: &Instruction, w: u8) -> Result<(), DecodeError> { if inst.prefixes.evex_unchecked().vex().w() ^ (w != 0) { Err(DecodeError::InvalidOpcode) } else { Ok(()) } } #[inline(always)] fn deny_mask_reg(inst: &Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex_unchecked().mask_reg() != 0 { Err(DecodeError::InvalidOperand) } else { Ok(()) } } #[inline(always)] fn check_mask_reg(inst: &Instruction) -> Result<(), DecodeError> { // if an operand is to be zeroed on mask bits but mask register 0 is // selected, this instruction is nonsense and will #UD if inst.prefixes.evex_unchecked().merge() && inst.prefixes.evex_unchecked().mask_reg() == 0 { Err(DecodeError::InvalidOperand) } else { Ok(()) } } #[inline(always)] fn apply_broadcast(inst: &mut Instruction, item_size: u8, reg_size: u8) { if inst.prefixes.evex_unchecked().broadcast() { inst.mem_size = item_size; } else { inst.mem_size = reg_size; } } #[inline(always)] fn set_rrr(inst: &mut Instruction, modrm: u8) { inst.regs[0].num = (modrm >> 3) & 7; if inst.prefixes.evex_unchecked().vex().r() { inst.regs[0].num |= 8; } if inst.prefixes.evex_unchecked().rp() { inst.regs[0].num |= 16; } } #[inline(always)] fn set_reg_sizes(inst: &mut Instruction, size: RegisterBank) { inst.regs[0].bank = size; inst.regs[3].bank = size; for i in 0..inst.operand_count { if [OperandSpec::RegMMM, OperandSpec::RegMMM_maskmerge, OperandSpec::RegMMM_maskmerge_sae_noround].contains(&inst.operands[i as usize]) { inst.regs[1].bank = size; } } } #[inline(always)] fn regs_size(inst: &Instruction) -> u8 { if inst.prefixes.evex_unchecked().lp() { 64 } else if inst.prefixes.evex_unchecked().vex().l() { 32 } else { 16 } } #[inline(always)] fn set_reg_sizes_from_ll(inst: &mut Instruction) -> Result<(), DecodeError> { if inst.prefixes.evex_unchecked().lp() { if inst.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } set_reg_sizes(inst, RegisterBank::Z); } else if inst.prefixes.evex_unchecked().vex().l() { set_reg_sizes(inst, RegisterBank::Y); } else { set_reg_sizes(inst, RegisterBank::X); } Ok(()) } pub(crate) fn read_evex_operands< T: Reader<::Address, ::Word>, S: DescriptionSink, >(words: &mut T, instruction: &mut Instruction, operand_code: generated::EVEXOperandCode, sink: &mut S) -> Result<(), DecodeError> { match operand_code { generated::EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast => { check_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VRANGEPS { instruction.opcode = Opcode::VRANGEPD; } else if instruction.opcode == Opcode::VFIXUPIMMPS { instruction.opcode = Opcode::VFIXUPIMMPD; } } if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { if [Opcode::VRANGEPS, Opcode::VRANGEPD, Opcode::VFIXUPIMMPS, Opcode::VFIXUPIMMPD].contains(&instruction.opcode) { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } } else { let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_V_Ed_xmm => { check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VRSQRT14SS { instruction.opcode = Opcode::VRSQRT14SD; } } if let OperandSpec::RegMMM = mem_oper { instruction.mem_size = 0; } else { if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_Eq_xmm_sae_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } instruction.mem_size = 0; } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } instruction.mem_size = 8; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast => { check_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VGETEXPSS { instruction.opcode = Opcode::VGETEXPSD; } } if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } } else { if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_Ed_LL_sae => { check_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VFMADD132SS { instruction.opcode = Opcode::VFMADD132SD; } else if instruction.opcode == Opcode::VFMSUB132SS { instruction.opcode = Opcode::VFMSUB132SD; } else if instruction.opcode == Opcode::VFNMADD132SS { instruction.opcode = Opcode::VFNMADD132SD; } else if instruction.opcode == Opcode::VFNMSUB132SS { instruction.opcode = Opcode::VFNMSUB132SD; } else if instruction.opcode == Opcode::VFMADD213SS { instruction.opcode = Opcode::VFMADD213SD; } else if instruction.opcode == Opcode::VFMSUB213SS { instruction.opcode = Opcode::VFMSUB213SD; } else if instruction.opcode == Opcode::VFNMADD213SS { instruction.opcode = Opcode::VFNMADD213SD; } else if instruction.opcode == Opcode::VFNMSUB213SS { instruction.opcode = Opcode::VFNMSUB213SD; } else if instruction.opcode == Opcode::VFMADD231SS { instruction.opcode = Opcode::VFMADD231SD; } else if instruction.opcode == Opcode::VFMSUB231SS { instruction.opcode = Opcode::VFMSUB231SD; } else if instruction.opcode == Opcode::VFNMADD231SS { instruction.opcode = Opcode::VFNMADD231SD; } else if instruction.opcode == Opcode::VFNMSUB231SS { instruction.opcode = Opcode::VFNMSUB231SD; } } set_reg_sizes(instruction, RegisterBank::X); if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } } generated::EVEXOperandCode::Gm_V_E_LL_sae_bcast => { check_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VSCALEFPS { instruction.opcode = Opcode::VSCALEFPD; } else if instruction.opcode == Opcode::VFNMADD132PS { instruction.opcode = Opcode::VFNMADD132PD; } else if instruction.opcode == Opcode::VFNMSUB132PS { instruction.opcode = Opcode::VFNMSUB132PD; } else if instruction.opcode == Opcode::VFMADDSUB132PS { instruction.opcode = Opcode::VFMADDSUB132PD; } else if instruction.opcode == Opcode::VFMSUBADD132PS { instruction.opcode = Opcode::VFMSUBADD132PD; } else if instruction.opcode == Opcode::VFMADD132PS { instruction.opcode = Opcode::VFMADD132PD; } else if instruction.opcode == Opcode::VFMSUB132PS { instruction.opcode = Opcode::VFMSUB132PD; } else if instruction.opcode == Opcode::VFMADDSUB213PS { instruction.opcode = Opcode::VFMADDSUB213PD; } else if instruction.opcode == Opcode::VFMSUBADD213PS { instruction.opcode = Opcode::VFMSUBADD213PD; } else if instruction.opcode == Opcode::VFMADD213PS { instruction.opcode = Opcode::VFMADD213PD; } else if instruction.opcode == Opcode::VFMSUB213PS { instruction.opcode = Opcode::VFMSUB213PD; } else if instruction.opcode == Opcode::VFNMADD213PS { instruction.opcode = Opcode::VFNMADD213PD; } else if instruction.opcode == Opcode::VFNMSUB213PS { instruction.opcode = Opcode::VFNMSUB213PD; } else if instruction.opcode == Opcode::VFMADDSUB231PS { instruction.opcode = Opcode::VFMADDSUB231PD; } else if instruction.opcode == Opcode::VFMSUBADD231PS { instruction.opcode = Opcode::VFMSUBADD231PD; } else if instruction.opcode == Opcode::VFMADD231PS { instruction.opcode = Opcode::VFMADD231PD; } else if instruction.opcode == Opcode::VFMSUB231PS { instruction.opcode = Opcode::VFMSUB231PD; } else if instruction.opcode == Opcode::VFNMADD231PS { instruction.opcode = Opcode::VFNMADD231PD; } else if instruction.opcode == Opcode::VFNMSUB231PS { instruction.opcode = Opcode::VFNMSUB231PD; } } if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } } else { let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_E_LL_imm8_sae => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = Opcode::VREDUCEPD; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { instruction.mem_size = 0; instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } } else { let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_E_LL_imm8_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { // this mode is only used for `vcvtps2ph` and `vrndscaleps`, neither use sae rounding instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } } else { let sz = regs_size(instruction); apply_broadcast(instruction, 4, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_E_LL_imm8_sae_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { if instruction.prefixes.evex_unchecked().broadcast() { // this mode is only used for `vrndscalepd`, does not use sae rounding instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } } else { let sz = regs_size(instruction); apply_broadcast(instruction, 8, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Mq_G_xmm_W1 => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; instruction.mem_size = 8; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::G_V_Ed_xmm_imm8_W0 => { deny_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::G_V_xmm_Edq_sae => { deny_mask_reg(instruction)?; deny_z(instruction)?; let (sz, bank) = if instruction.prefixes.evex_unchecked().vex().w() { (DEFAULT_EVEX_REGISTER_WIDTH, DEFAULT_EVEX_REGISTER_SIZE) } else { (4, RegisterBank::D) }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = bank; instruction.mem_size = 0; } else { instruction.mem_size = sz; } if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper == OperandSpec::RegMMM { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { return Err(DecodeError::InvalidOperand); } } else { instruction.operands[0] = OperandSpec::RegRRR; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; } generated::EVEXOperandCode::G_V_xmm_Edq_imm8 => { deny_mask_reg(instruction)?; let (sz, bank) = if instruction.prefixes.evex_unchecked().vex().w() { if isa_has_qwords() { instruction.opcode = Opcode::VPINSRQ; } (DEFAULT_EVEX_REGISTER_WIDTH, DEFAULT_EVEX_REGISTER_SIZE) } else { (4, RegisterBank::D) }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = bank; instruction.mem_size = 0; } else { instruction.mem_size = sz; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::G_V_xmm_Ebd_imm8 => { deny_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; instruction.mem_size = 0; } else { instruction.mem_size = 1; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::G_V_Mq_xmm_W1 => { deny_mask_reg(instruction)?; ensure_W(instruction, 1)?; instruction.mem_size = 8; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_E_LL_bcast_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); // specifically for vunpcklpd!!! probably need to reconsider. apply_broadcast(instruction, 8, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::M_G_LL_W0 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; instruction.mem_size = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::M_G_LL_W1 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; ensure_W(instruction, 1)?; instruction.mem_size = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Em_G_LL_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; instruction.mem_size = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::G_Ed_xmm_sae_W0 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; // vucomiss and vcomiss both are W=0 ensure_W(instruction, 0)?; instruction.mem_size = 4; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; // in specific support of vcomisd/vucomisd if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_Eq_xmm_sae_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; // vucomisd and vcomisd both are W=1 ensure_W(instruction, 1)?; instruction.mem_size = 8; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; // in specific support of vcomisd/vucomisd if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_E_LL_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; instruction.mem_size = regs_size(instruction); if instruction.opcode == Opcode::VMOVDDUP && instruction.mem_size == 16 { instruction.mem_size = 8; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::VCVTUDQ2PD => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTUDQ2PD { instruction.opcode = Opcode::VCVTUQQ2PD; } else if instruction.opcode == Opcode::VCVTDQ2PD { instruction.opcode = Opcode::VCVTQQ2PD; } } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; if !instruction.prefixes.evex_unchecked().vex().w() { if instruction.regs[0].bank == RegisterBank::Z { instruction.regs[1].bank = RegisterBank::Y; } else if instruction.regs[0].bank == RegisterBank::Y { instruction.regs[1].bank = RegisterBank::X; } } } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz / 2); } } } generated::EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, sz); set_reg_sizes_from_ll(instruction)?; } instruction.regs[0].bank = RegisterBank::K; if instruction.regs[0].num > 7 { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::Gm_E_LL_sae_bcast_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_E_LL_sae_bcast_W1 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_V_Ed_LL_bcast => { check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPERMPS { instruction.opcode = Opcode::VPERMPD; } else if instruction.opcode == Opcode::VBLENDMPS { instruction.opcode = Opcode::VBLENDMPD; } else if instruction.opcode == Opcode::VPERMI2PS { instruction.opcode = Opcode::VPERMI2PD; } else if instruction.opcode == Opcode::VPERMT2PS { instruction.opcode = Opcode::VPERMT2PD } } let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } else { instruction.mem_size = 0; } } else { if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } } set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_Ed_LL_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } else { instruction.mem_size = 0; } } else { apply_broadcast(instruction, 4, sz); } set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = sz; } set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = sz; } set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_sae_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.mem_size = sz; set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VMINPS || instruction.opcode == Opcode::VMAXPS { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 4, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VMINPD || instruction.opcode == Opcode::VMAXPD { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, sz); set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::G_V_E_LL => { deny_mask_reg(instruction)?; if [Opcode::VAESDECLAST, Opcode::VAESDEC, Opcode::VAESENC, Opcode::VAESENCLAST].contains(&instruction.opcode) { deny_z(instruction)?; } let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); instruction.opcode = if instruction.opcode == Opcode::VPANDD { Opcode::VPANDQ } else if instruction.opcode == Opcode::VPANDND { Opcode::VPANDNQ } else if instruction.opcode == Opcode::VPORD { Opcode::VPORQ } else if instruction.opcode == Opcode::VPXORD { Opcode::VPXORQ } else if instruction.opcode == Opcode::VPRORVD { Opcode::VPRORVQ } else if instruction.opcode == Opcode::VPROLVD { Opcode::VPROLVQ } else if instruction.opcode == Opcode::VPERMD { Opcode::VPERMQ } else if instruction.opcode == Opcode::VPMINSD { Opcode::VPMINSQ } else if instruction.opcode == Opcode::VPMINUD { Opcode::VPMINUQ } else if instruction.opcode == Opcode::VPMAXSD { Opcode::VPMAXSQ } else if instruction.opcode == Opcode::VPMAXUD { Opcode::VPMAXUQ } else if instruction.opcode == Opcode::VPSRLVD { Opcode::VPSRLVQ } else if instruction.opcode == Opcode::VPSRAVD { Opcode::VPSRAVQ } else if instruction.opcode == Opcode::VPSLLVD { Opcode::VPSLLVQ } else if instruction.opcode == Opcode::VPMULLD { Opcode::VPMULLQ } else if instruction.opcode == Opcode::VPBLENDMD { Opcode::VPBLENDMQ } else if instruction.opcode == Opcode::VPSHLDVD { Opcode::VPSHLDVQ } else if instruction.opcode == Opcode::VPSHRDVD { Opcode::VPSHRDVQ } else if instruction.opcode == Opcode::VPERMI2D { Opcode::VPERMI2Q } else if instruction.opcode == Opcode::VPERMT2D { Opcode::VPERMT2Q } else { instruction.opcode }; } else { apply_broadcast(instruction, 4, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_E_LL_imm8_bcast_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); apply_broadcast(instruction, 4, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_E_LL_imm8_bcast_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); apply_broadcast(instruction, 8, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_Ed_LL_imm8_sae_noround_bcast => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VGETMANTPS { instruction.opcode = Opcode::VGETMANTPD; } apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_Ed_LL_sae_noround_bcast_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[1] = mem_oper; instruction.operand_count = 2; apply_broadcast(instruction, 4, sz); if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_noround_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_Ed_xmm_sae => { check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VSCALEFSS { instruction.opcode = Opcode::VSCALEFSD; } else if instruction.opcode == Opcode::VRCP14SS { instruction.opcode = Opcode::VRCP14SD; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_Ed_xmm_sae_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VMINSS || instruction.opcode == Opcode::VMAXSS { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { deny_broadcast(instruction)?; instruction.mem_size = 4; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Eqm_G_xmm_imm8_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { // sae sets this to `vcvtps2ph ymm, zmm, imm8` instruction.regs[1].bank = RegisterBank::Y; instruction.regs[0].bank = RegisterBank::Z; instruction.operands[0] = OperandSpec::RegMMM_maskmerge_sae_noround; } else { instruction.regs[1].bank = RegisterBank::X; instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = OperandSpec::RegMMM_maskmerge; } } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; instruction.regs[0].bank = RegisterBank::X; instruction.operands[0] = mem_oper.masked(); } } instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } generated::EVEXOperandCode::Em_xmm_G_ymm_imm8_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { // sae sets this to `vcvtps2ph ymm, zmm, imm8` instruction.regs[1].bank = RegisterBank::Y; instruction.regs[0].bank = RegisterBank::Z; instruction.operands[0] = OperandSpec::RegMMM_maskmerge_sae_noround; } else { instruction.regs[1].bank = RegisterBank::X; instruction.regs[0].bank = RegisterBank::Y; instruction.operands[0] = OperandSpec::RegMMM_maskmerge; } } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::Y; instruction.operands[0] = mem_oper.masked(); } } instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.mem_size = 16; instruction.operand_count = 3; } generated::EVEXOperandCode::Em_ymm_G_zmm_imm8_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Z; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegMMM_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegMMM_maskmerge; } } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOperand); } else { instruction.operands[0] = mem_oper.masked(); } } instruction.mem_size = 32; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_V_zmm_E_xmm_imm8 => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; instruction.opcode = if instruction.prefixes.evex_unchecked().vex().w() { Opcode::VINSERTI64X2 } else { Opcode::VINSERTI32X4 }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Z; instruction.regs[3].bank = RegisterBank::Z; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR.masked(); instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::Gm_V_ymm_E_xmm_imm8 => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; instruction.opcode = if instruction.prefixes.evex_unchecked().vex().w() { Opcode::VINSERTI64X2 } else { Opcode::VINSERTI32X4 }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Y; instruction.regs[3].bank = RegisterBank::Y; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR.masked(); instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::Gm_V_zmm_E_ymm_imm8 => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VINSERTF32X8 { instruction.opcode = Opcode::VINSERTF64X4; } else if instruction.opcode == Opcode::VINSERTI32X8 { instruction.opcode = Opcode::VINSERTI64X4; } }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Z; instruction.regs[3].bank = RegisterBank::Z; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.mem_size = 32; instruction.operands[0] = OperandSpec::RegRRR.masked(); instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::Em_ymm_G_zmm_imm8 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VEXTRACTF32X8 { instruction.opcode = Opcode::VEXTRACTF64X4; } else if instruction.opcode == Opcode::VEXTRACTI32X8 { instruction.opcode = Opcode::VEXTRACTI64X4; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Z; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.mem_size = 32; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_zmm_Eq_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_Ed_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_Ew_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 2; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_E_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_Eq_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_Ed_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_E_ymm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 32; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_E_ymm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 32; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_E_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_E_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_Eq_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_Eq_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Em_ymm_G_zmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.regs[0].bank = RegisterBank::Z; instruction.mem_size = 32; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Em_xmm_G_zmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; instruction.mem_size = 16; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Em_xmm_G_ymm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; instruction.mem_size = 16; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Eqm_xmm_G_zmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; instruction.mem_size = 8; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Eqm_xmm_G_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 8; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Edm_xmm_G_ymm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; instruction.mem_size = 4; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Edm_xmm_G_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 4; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Ewm_xmm_G_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; instruction.mem_size = 2; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Eqm_xmm_G_ymm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; instruction.mem_size = 8; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_Ed_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_Ed_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_M_ymm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VBROADCASTF32X8 { instruction.opcode = Opcode::VBROADCASTF64X4; } else if instruction.opcode == Opcode::VBROADCASTI32X8 { instruction.opcode = Opcode::VBROADCASTI64X4; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 32; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_M_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VBROADCASTF32X4 { instruction.opcode = Opcode::VBROADCASTF64X2; } else if instruction.opcode == Opcode::VBROADCASTI32X4 { instruction.opcode = Opcode::VBROADCASTI64X2; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_ymm_M_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VBROADCASTF32X4 { instruction.opcode = Opcode::VBROADCASTF64X2; } else if instruction.opcode == Opcode::VBROADCASTI32X4 { instruction.opcode = Opcode::VBROADCASTI64X2; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_Ed_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = Opcode::VBROADCASTSD; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::VBROADCASTF32X2_Gm_ymm_Ed_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = Opcode::VBROADCASTSD; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Y; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_zmm_Ed_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::Z; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Em_xmm_G_LL_imm8 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = if instruction.opcode == Opcode::VEXTRACTF32X4 { Opcode::VEXTRACTF64X2 } else if instruction.opcode == Opcode::VEXTRACTI32X4 { Opcode::VEXTRACTI64X2 } else { instruction.opcode } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); if instruction.prefixes.evex_unchecked().lp() { instruction.regs[0].bank = RegisterBank::Z; } else { instruction.regs[0].bank = RegisterBank::Y; } let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.mem_size = 16; instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_V_LL_E_xmm_imm8 => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; instruction.opcode = if instruction.prefixes.evex_unchecked().vex().w() { Opcode::VINSERTF64X2 } else { Opcode::VINSERTF32X4 }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); set_reg_sizes_from_ll(instruction)?; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.mem_size = 16; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::Gm_V_LL_E_xmm_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); set_reg_sizes_from_ll(instruction)?; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.mem_size = 16; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_V_LL_E_xmm_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); set_reg_sizes_from_ll(instruction)?; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.mem_size = 16; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_V_LL_E_xmm => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = if instruction.opcode == Opcode::VPSRAD { Opcode::VPSRAQ } else { instruction.opcode }; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); set_reg_sizes_from_ll(instruction)?; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.mem_size = 16; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; } generated::EVEXOperandCode::VPEXTRW => { deny_mask_reg(instruction)?; deny_z(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::D; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::X; } else { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; } generated::EVEXOperandCode::VPINSRW => { deny_mask_reg(instruction)?; deny_z(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; } generated::EVEXOperandCode::VMOVQ_G_Ed_xmm => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::VMOVQ_Ed_G_xmm => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 8; } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; } generated::EVEXOperandCode::VMOVQ_7e => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper != OperandSpec::RegMMM { instruction.mem_size = 8; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::VMOVD_7e => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().vex().w() { if isa_has_qwords() { instruction.opcode = Opcode::VMOVQ; } if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.mem_size = DEFAULT_EVEX_REGISTER_WIDTH; } } else { if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR_maskmerge; instruction.operand_count = 2; } generated::EVEXOperandCode::VMOVD_6e => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().vex().w() { if isa_has_qwords() { instruction.opcode = Opcode::VMOVQ; } if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.mem_size = DEFAULT_EVEX_REGISTER_WIDTH; } } else { if mem_oper == OperandSpec::RegMMM { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Mask_V_E_LL_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VP2INTERSECTD { instruction.opcode = Opcode::VP2INTERSECTQ; } else if instruction.opcode == Opcode::VPTESTNMD { instruction.opcode = Opcode::VPTESTNMQ; } else if instruction.opcode == Opcode::VPTESTMD { instruction.opcode = Opcode::VPTESTMQ; } apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL_bcast_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); apply_broadcast(instruction, 8, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); apply_broadcast(instruction, 4, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Em_G_LL => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VMOVDQA32 { instruction.opcode = Opcode::VMOVDQA64; } else if instruction.opcode == Opcode::VMOVDQU32 { instruction.opcode = Opcode::VMOVDQU64; } else if instruction.opcode == Opcode::VMOVDQU8 { instruction.opcode = Opcode::VMOVDQU16; } else if instruction.opcode == Opcode::VPCOMPRESSB { instruction.opcode = Opcode::VPCOMPRESSW; } else if instruction.opcode == Opcode::VPCOMPRESSD { instruction.opcode = Opcode::VPCOMPRESSQ; } else if instruction.opcode == Opcode::VCOMPRESSPS { instruction.opcode = Opcode::VCOMPRESSPD; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Mask_U_LL => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPMOVB2M { instruction.opcode = Opcode::VPMOVW2M; } else { instruction.opcode = Opcode::VPMOVQ2M; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[0].bank = RegisterBank::K; if instruction.regs[0].num > 7 { return Err(DecodeError::InvalidOperand); } } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::G_LL_Mask => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPMOVM2B { instruction.opcode = Opcode::VPMOVM2W; } else { instruction.opcode = Opcode::VPMOVM2Q; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::K; // only 8 mask registers, `xed` suggests that any invalid bits are masked out??? instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::G_LL_Mask_W1 => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::K; // only 8 mask registers, `xed` suggests that any invalid bits are masked out??? instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::G_LL_Mask_W0 => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::K; // only 8 mask registers, `xed` suggests that any invalid bits are masked out??? instruction.regs[1].num &= 0b111; } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::G_E_LL_W0 => { deny_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::E_G_LL_W0 => { deny_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Em_G_LL_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = mem_oper.masked(); instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Operands_72_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; let (r_sz, m_sz, m_data_sz) = match ( instruction.prefixes.evex_unchecked().lp(), instruction.prefixes.evex_unchecked().vex().l(), ) { (true, true) => { return Err(DecodeError::InvalidOpcode); }, (true, false) => (RegisterBank::Y, RegisterBank::Z, 64), (false, true) => (RegisterBank::X, RegisterBank::Y, 32), (false, false) => (RegisterBank::X, RegisterBank::X, 16), }; instruction.regs[0].bank = r_sz; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = m_sz; } else { apply_broadcast(instruction, 4, m_data_sz); } } generated::EVEXOperandCode::Gm_E_LL_bcast => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPLZCNTD { instruction.opcode = Opcode::VPLZCNTQ; } else if instruction.opcode == Opcode::VRCP14PS { instruction.opcode = Opcode::VRCP14PD; } else if instruction.opcode == Opcode::VPOPCNTD { instruction.opcode = Opcode::VPOPCNTQ; } else if instruction.opcode == Opcode::VPCONFLICTD { instruction.opcode = Opcode::VPCONFLICTQ; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } instruction.mem_size = 0; } else { if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_E_LL_bcast_W1 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } instruction.mem_size = 0; } else { apply_broadcast(instruction, 8, sz); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_E_LL_bcast_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } instruction.mem_size = 0; } else { apply_broadcast(instruction, 4, sz); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_LL_Ud => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() && isa_has_qwords() { if instruction.opcode == Opcode::VPBROADCASTD { instruction.opcode = Opcode::VPBROADCASTQ; } } let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[1].bank = RegisterBank::D; } } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::Gm_LL_Ud_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::D; } else { return Err(DecodeError::InvalidOperand); } } generated::EVEXOperandCode::Gm_LL_Eq_xmm => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = Opcode::VPBROADCASTQ; } else { instruction.opcode = Opcode::VBROADCASTI32X2; } let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 8; } } generated::EVEXOperandCode::Gm_LL_Ed_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 4; } } generated::EVEXOperandCode::Gm_LL_Ew_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 2; } } generated::EVEXOperandCode::Gm_LL_Eb_xmm_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; instruction.regs[1].bank = RegisterBank::X; } else { instruction.mem_size = 1; } } generated::EVEXOperandCode::Gm_E_LL_W0 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_E_LL_imm8 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VMOVDQA32 { instruction.opcode = Opcode::VMOVDQA64; } else if instruction.opcode == Opcode::VMOVDQU32 { instruction.opcode = Opcode::VMOVDQU64; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gd_Ed_xmm_sae => { deny_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[0].bank = RegisterBank::D; } let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper == OperandSpec::RegMMM { if instruction.opcode == Opcode::VCVTSS2USI || instruction.opcode == Opcode::VCVTSD2SI || instruction.opcode == Opcode::VCVTSD2USI { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } } else { return Err(DecodeError::InvalidOperand); } } else { if instruction.prefixes.evex_unchecked().lp() && instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } } if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { deny_broadcast(instruction)?; if instruction.opcode == Opcode::VCVTTSD2SI || instruction.opcode == Opcode::VCVTSD2SI || instruction.opcode == Opcode::VCVTTSD2USI || instruction.opcode == Opcode::VCVTSD2USI { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_E_LL_sae_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VGETEXPPS { instruction.opcode = Opcode::VGETEXPPD; } else if instruction.opcode == Opcode::VRSQRT14PS { instruction.opcode = Opcode::VRSQRT14PD; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper != OperandSpec::RegMMM { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; apply_broadcast(instruction, if instruction.prefixes.evex_unchecked().vex().w() { 8 } else { 4 }, sz); } else { if instruction.opcode == Opcode::VSQRTPS || instruction.opcode == Opcode::VCVTPS2DQ { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } set_reg_sizes(instruction, RegisterBank::Z); } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_E_LL => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VMOVDQA32 { instruction.opcode = Opcode::VMOVDQA64; } else if instruction.opcode == Opcode::VMOVDQU32 { instruction.opcode = Opcode::VMOVDQU64; } else if instruction.opcode == Opcode::VMOVDQU8 { instruction.opcode = Opcode::VMOVDQU16; } else if instruction.opcode == Opcode::VPOPCNTB { instruction.opcode = Opcode::VPOPCNTW; } else if instruction.opcode == Opcode::VPEXPANDB { instruction.opcode = Opcode::VPEXPANDW; } else if instruction.opcode == Opcode::VEXPANDPS { instruction.opcode = Opcode::VEXPANDPD; } else if instruction.opcode == Opcode::VPEXPANDD { instruction.opcode = Opcode::VPEXPANDQ; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_Ed_LL_imm8_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VSHUFF32X4 { instruction.opcode = Opcode::VSHUFF64X2; } apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); apply_broadcast(instruction, 4, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPBLENDMB { instruction.opcode = Opcode::VPBLENDMW; } else if instruction.opcode == Opcode::VPERMI2B { instruction.opcode = Opcode::VPERMI2W; } else if instruction.opcode == Opcode::VPERMT2B { instruction.opcode = Opcode::VPERMT2W; } else if instruction.opcode == Opcode::VPERMB { instruction.opcode = Opcode::VPERMW; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Mask_V_E_LL_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPTESTNMB { instruction.opcode = Opcode::VPTESTNMW; } else if instruction.opcode == Opcode::VPTESTMB { instruction.opcode = Opcode::VPTESTMW; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { deny_broadcast(instruction)?; instruction.mem_size = 8; } if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes(instruction, RegisterBank::X); if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Maskm_V_Ed_xmm_imm8_sae_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; deny_broadcast(instruction)?; } if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes(instruction, RegisterBank::X); if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL_imm8 => { check_mask_reg(instruction)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPCMPUB { instruction.opcode = Opcode::VPCMPUW; } else if instruction.opcode == Opcode::VPCMPB { instruction.opcode = Opcode::VPCMPW; } }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_Ed_xmm_imm8 => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; deny_z(instruction)?; deny_broadcast(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = if instruction.opcode == Opcode::VFPCLASSSS { Opcode::VFPCLASSSD } else { instruction.opcode }; }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_E_LL_imm8_bcast => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 8, sz); } else { instruction.mem_size = sz; } instruction.opcode = if instruction.opcode == Opcode::VFPCLASSPS { Opcode::VFPCLASSPD } else { instruction.opcode }; } else { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 4, sz); } else { instruction.mem_size = sz; } }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 8, sz); } else { instruction.mem_size = sz; } } else { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 4, sz); } else { instruction.mem_size = sz; } }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { set_reg_sizes_from_ll(instruction)?; } instruction.mem_size = 0; } else { set_reg_sizes_from_ll(instruction)?; } if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Mask_V_E_LL_imm8_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); if instruction.prefixes.evex_unchecked().vex().w() { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 8, sz); } else { instruction.mem_size = sz; } // this operand code is used in a few places, apply `w` as appropriate instruction.opcode = if instruction.opcode == Opcode::VPCMPUD { Opcode::VPCMPUQ } else { Opcode::VPCMPQ }; } else { if instruction.prefixes.evex_unchecked().broadcast() { apply_broadcast(instruction, 4, sz); } else { instruction.mem_size = sz; } }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; instruction.mem_size = 0; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; if instruction.regs[0].num >= 8 { return Err(DecodeError::InvalidOperand); } else { instruction.regs[0].bank = RegisterBank::K; } } generated::EVEXOperandCode::Opcode_72_Gm_E_LL_imm8_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; let rrr = (modrm >> 3) & 7; let item_size = if instruction.prefixes.evex_unchecked().vex().w() { instruction.opcode = [ Ok(Opcode::VPRORQ), Ok(Opcode::VPROLQ), Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), Ok(Opcode::VPSRAQ), Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), ][rrr as usize]?; 8 } else { instruction.opcode = [ Ok(Opcode::VPRORD), Ok(Opcode::VPROLD), Ok(Opcode::VPSRLD), Err(DecodeError::InvalidOpcode), Ok(Opcode::VPSRAD), Ok(Opcode::VPSLLD), Err(DecodeError::InvalidOpcode), Err(DecodeError::InvalidOpcode), ][rrr as usize]?; 4 }; apply_broadcast(instruction, item_size, sz); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegVex_maskmerge; instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; deny_broadcast(instruction)?; let sz = regs_size(instruction); instruction.mem_size = sz; /* instruction.opcode = if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); if instruction.opcode == Opcode::VALIGND { Opcode::VALIGNQ } else if instruction.opcode == Opcode::VPTERNLOGD { Opcode::VPTERNLOGQ } else if instruction.opcode == Opcode::VSHUFI32X4 { Opcode::VSHUFI64X2 } else { instruction.opcode } } else { apply_broadcast(instruction, 4, sz); instruction.opcode }; */ let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8_bcast => { check_mask_reg(instruction)?; let sz = regs_size(instruction); instruction.opcode = if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); if instruction.opcode == Opcode::VALIGND { Opcode::VALIGNQ } else if instruction.opcode == Opcode::VPTERNLOGD { Opcode::VPTERNLOGQ } else if instruction.opcode == Opcode::VSHUFI32X4 { Opcode::VSHUFI64X2 } else if instruction.opcode == Opcode::VPSHLDD { Opcode::VPSHLDQ } else if instruction.opcode == Opcode::VPSHRDD { Opcode::VPSHRDQ } else { instruction.opcode } } else { apply_broadcast(instruction, 4, sz); instruction.opcode }; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { deny_broadcast(instruction)?; } else { instruction.mem_size = sz; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W0 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let sz = regs_size(instruction); if instruction.opcode == Opcode::VSHUFPS { apply_broadcast(instruction, 4, sz); } else { apply_broadcast(instruction, 8, sz); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::G_V_E_LL_imm8 => { check_mask_reg(instruction)?; instruction.mem_size = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8 => { check_mask_reg(instruction)?; instruction.mem_size = regs_size(instruction); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let sz = regs_size(instruction); apply_broadcast(instruction, 8, sz); let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes_from_ll(instruction)?; } generated::EVEXOperandCode::Gm_ymm_E_zmm_sae_bcast_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Z, sink)?; instruction.regs[0].bank = RegisterBank::Y; instruction.operands[1] = mem_oper; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper != OperandSpec::RegMMM { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, 64); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.mem_size = 64; } instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_E_ymm_sae_bcast_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Y, sink)?; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper != OperandSpec::RegMMM { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, 32); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; instruction.regs[0].bank = RegisterBank::Y; instruction.regs[1].bank = RegisterBank::Z; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.mem_size = 32; } instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_xmm_E_xmm_sae_bcast_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[0].bank = RegisterBank::X; instruction.operands[1] = mem_oper; if instruction.prefixes.evex_unchecked().broadcast() { if mem_oper != OperandSpec::RegMMM { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; apply_broadcast(instruction, 8, 16); } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; instruction.regs[0].bank = RegisterBank::Y; instruction.regs[1].bank = RegisterBank::Z; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.mem_size = 16; } instruction.operand_count = 2; } generated::EVEXOperandCode::VCVTTPS2UQQ => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTTPS2UQQ { instruction.opcode = Opcode::VCVTTPD2UQQ; } else if instruction.opcode == Opcode::VCVTPS2UQQ { instruction.opcode = Opcode::VCVTPD2UQQ; } else if instruction.opcode == Opcode::VCVTTPS2QQ { instruction.opcode = Opcode::VCVTTPD2QQ; } else if instruction.opcode == Opcode::VCVTPS2QQ { instruction.opcode = Opcode::VCVTPD2QQ; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 0; let mut lp = 0; if instruction.prefixes.evex_unchecked().lp() { lp |= 2; } if instruction.prefixes.evex_unchecked().vex().l() { lp |= 1; } if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VCVTPD2UQQ || instruction.opcode == Opcode::VCVTPS2UQQ || instruction.opcode == Opcode::VCVTPD2QQ || instruction.opcode == Opcode::VCVTPS2QQ { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } instruction.regs[0].bank = RegisterBank::Z; if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[1].bank = RegisterBank::Z; } else { instruction.regs[1].bank = RegisterBank::Y; } } else { let (r_sz, m_sz) = if instruction.prefixes.evex_unchecked().vex().w() { [ Ok((RegisterBank::X, RegisterBank::X)), Ok((RegisterBank::Y, RegisterBank::Y)), Ok((RegisterBank::Z, RegisterBank::Z)), Err(DecodeError::InvalidOperand), ][lp]? } else { [ Ok((RegisterBank::X, RegisterBank::X)), Ok((RegisterBank::Y, RegisterBank::X)), Ok((RegisterBank::Z, RegisterBank::Y)), Err(DecodeError::InvalidOperand), ][lp]? }; instruction.regs[0].bank = r_sz; instruction.regs[1].bank = m_sz; } } else { let (r_sz, m_sz) = if instruction.prefixes.evex_unchecked().vex().w() { [ Ok((RegisterBank::X, 16)), Ok((RegisterBank::Y, 32)), Ok((RegisterBank::Z, 64)), Err(DecodeError::InvalidOperand), ][lp]? } else { [ Ok((RegisterBank::X, 8)), Ok((RegisterBank::Y, 16)), Ok((RegisterBank::Z, 32)), Err(DecodeError::InvalidOperand), ][lp]? }; instruction.regs[0].bank = r_sz; if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, m_sz); } else { apply_broadcast(instruction, 4, m_sz); } } } generated::EVEXOperandCode::VCVTPH2PS => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; if instruction.opcode == Opcode::VCVTPS2PD { if instruction.prefixes.evex_unchecked().vex().w() { return Err(DecodeError::InvalidOpcode); } } else if instruction.opcode == Opcode::VCVTTPS2UQQ { instruction.opcode = Opcode::VCVTTPD2UQQ; } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 0; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; instruction.regs[0].bank = RegisterBank::Z; if instruction.opcode == Opcode::VCVTTPD2UQQ { instruction.regs[1].bank = RegisterBank::Z; } else { instruction.regs[1].bank = RegisterBank::Y; } } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } (false, true) => (RegisterBank::Z, RegisterBank::Y), (true, false) => (RegisterBank::Y, RegisterBank::X), (false, false) => (RegisterBank::X, RegisterBank::X), }; instruction.regs[0].bank = r_sz; instruction.regs[1].bank = m_sz; } } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } (true, false) => (RegisterBank::Y, 16), (false, true) => (RegisterBank::Z, 32), (false, false) => (RegisterBank::X, 8), }; instruction.regs[0].bank = r_sz; if instruction.opcode == Opcode::VCVTPS2PD { apply_broadcast(instruction, 4, m_sz); } else { apply_broadcast(instruction, 8, m_sz); } } } generated::EVEXOperandCode::VCVTDQ2PS => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTDQ2PS { instruction.opcode = Opcode::VCVTQQ2PS; } else if instruction.opcode == Opcode::VCVTUDQ2PS { instruction.opcode = Opcode::VCVTUQQ2PS; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 0; let mut lp = 0; if instruction.prefixes.evex_unchecked().lp() { lp |= 2; } if instruction.prefixes.evex_unchecked().vex().l() { lp |= 1; } if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = RegisterBank::Y; } else { instruction.regs[0].bank = RegisterBank::Z; } instruction.regs[1].bank = RegisterBank::Z; } else { let (r_sz, m_sz) = if instruction.prefixes.evex_unchecked().vex().w() { [ Ok((RegisterBank::X, RegisterBank::X)), Ok((RegisterBank::X, RegisterBank::Y)), Ok((RegisterBank::Y, RegisterBank::Z)), Err(DecodeError::InvalidOperand), ][lp]? } else { [ Ok((RegisterBank::X, RegisterBank::X)), Ok((RegisterBank::Y, RegisterBank::Y)), Ok((RegisterBank::Z, RegisterBank::Z)), Err(DecodeError::InvalidOperand), ][lp]? }; instruction.regs[0].bank = r_sz; instruction.regs[1].bank = m_sz; } } else { let (r_sz, m_sz, item_sz) = if instruction.prefixes.evex_unchecked().vex().w() { [ Ok((RegisterBank::X, 16, 8)), Ok((RegisterBank::X, 32, 8)), Ok((RegisterBank::Y, 64, 8)), Err(DecodeError::InvalidOperand), ][lp]? } else { [ Ok((RegisterBank::X, 16, 4)), Ok((RegisterBank::Y, 32, 4)), Ok((RegisterBank::Z, 64, 4)), Err(DecodeError::InvalidOperand), ][lp]? }; instruction.regs[0].bank = r_sz; apply_broadcast(instruction, item_sz, m_sz); } } generated::EVEXOperandCode::VCVTTPS2UDQ => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 0; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTTPS2UDQ { instruction.opcode = Opcode::VCVTTPD2UDQ; } else if instruction.opcode == Opcode::VCVTPS2UDQ { instruction.opcode = Opcode::VCVTPD2UDQ; } } if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VCVTTPD2UDQ || instruction.opcode == Opcode::VCVTTPS2UDQ { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = RegisterBank::Y; } else { instruction.regs[0].bank = RegisterBank::Z; } instruction.regs[1].bank = RegisterBank::Z; } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } (false, true) => (if instruction.prefixes.evex_unchecked().vex().w() { RegisterBank::Y } else { RegisterBank::Z }, RegisterBank::Z), (true, false) => (if instruction.prefixes.evex_unchecked().vex().w() { RegisterBank::X } else { RegisterBank::Y }, RegisterBank::Y), (false, false) => (RegisterBank::X, RegisterBank::X), }; instruction.regs[0].bank = r_sz; instruction.regs[1].bank = m_sz; } } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } // (true, false) => (RegisterBank::Y, 32), (true, false) => (if instruction.prefixes.evex_unchecked().vex().w() { RegisterBank::X } else { RegisterBank::Y }, 32), (false, true) => (if instruction.prefixes.evex_unchecked().vex().w() { RegisterBank::Y } else { RegisterBank::Z }, 64), (false, false) => (RegisterBank::X, 16), }; instruction.regs[0].bank = r_sz; if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, m_sz); } else { apply_broadcast(instruction, 4, m_sz); } } if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTDQ2PS { instruction.opcode = Opcode::VCVTQQ2PS; } } } generated::EVEXOperandCode::VCVTTPD2DQ => { check_mask_reg(instruction)?; deny_vex_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 0; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTTPS2UDQ { instruction.opcode = Opcode::VCVTTPD2UDQ; } } if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VCVTDQ2PS || instruction.opcode == Opcode::VCVTPD2DQ { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } if instruction.opcode == Opcode::VCVTDQ2PS && !instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = RegisterBank::Z; } else { instruction.regs[0].bank = RegisterBank::Y; } instruction.regs[1].bank = RegisterBank::Z; } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } (false, true) => (RegisterBank::Y, RegisterBank::Z), (true, false) => (RegisterBank::X, RegisterBank::Y), (false, false) => (RegisterBank::X, RegisterBank::X), }; instruction.regs[0].bank = r_sz; instruction.regs[1].bank = m_sz; } } else { let (r_sz, m_sz) = match ( instruction.prefixes.evex_unchecked().vex().l(), instruction.prefixes.evex_unchecked().lp() ) { (true, true) => { return Err(DecodeError::InvalidOperand); } (true, false) => (RegisterBank::X, 32), (false, true) => (RegisterBank::Y, 64), (false, false) => (RegisterBank::X, 16), }; instruction.regs[0].bank = r_sz; apply_broadcast(instruction, 8, m_sz); } if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VCVTDQ2PS { instruction.opcode = Opcode::VCVTQQ2PS; } } } generated::EVEXOperandCode::Gm_ymm_U_zmm_sae_W1 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Z, sink)?; instruction.regs[0].bank = RegisterBank::Y; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = mem_oper; if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operand_count = 2; } generated::EVEXOperandCode::Gm_V_E_xmm_sae_W1 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { if instruction.opcode == Opcode::VMINSD || instruction.opcode == Opcode::VMAXSD { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } } else { instruction.mem_size = 8; } } generated::EVEXOperandCode::Gm_V_E_xmm_sae => { check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VEXP2SS { instruction.opcode = Opcode::VEXP2SD; } else if instruction.opcode == Opcode::VRCP28SS { instruction.opcode = Opcode::VRCP28SD; } else if instruction.opcode == Opcode::VRSQRT28SS { instruction.opcode = Opcode::VRSQRT28SD; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } } else { if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = 8; } else { instruction.mem_size = 4; } } } generated::EVEXOperandCode::Gm_E_zmm_sae_bcast => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VEXP2PS { instruction.opcode = Opcode::VEXP2PD; } else if instruction.opcode == Opcode::VRCP28PS { instruction.opcode = Opcode::VRCP28PD; } else if instruction.opcode == Opcode::VRSQRT28PS { instruction.opcode = Opcode::VRSQRT28PD; } } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::Z, sink)?; instruction.operands[1] = mem_oper; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; set_reg_sizes(instruction, RegisterBank::Z); } else { let sz = regs_size(instruction); if sz < 64 { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; set_reg_sizes_from_ll(instruction)?; } } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; let sz = regs_size(instruction); if sz < 64 { return Err(DecodeError::InvalidOperand); } if instruction.prefixes.evex_unchecked().vex().w() { apply_broadcast(instruction, 8, sz); } else { apply_broadcast(instruction, 4, sz); } set_reg_sizes_from_ll(instruction)?; } } generated::EVEXOperandCode::Gm_U_zmm_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; set_reg_sizes(instruction, RegisterBank::Z); } generated::EVEXOperandCode::Gm_U_zmm_imm8_sae_W0 => { deny_vex_reg(instruction)?; check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } if mem_oper != OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[1] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::Z); } generated::EVEXOperandCode::Edd_G_xmm_imm8 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if instruction.prefixes.evex_unchecked().vex().w() { if isa_has_qwords() { instruction.opcode = Opcode::VPEXTRQ; } else { instruction.opcode = Opcode::VPEXTRD; } if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.mem_size = DEFAULT_EVEX_REGISTER_WIDTH; } } else { instruction.opcode = Opcode::VPEXTRD; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } } generated::EVEXOperandCode::VCVTUSI2SD => { deny_mask_reg(instruction)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; instruction.regs[3].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; if mem_oper == OperandSpec::RegMMM { if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[1].bank = RegisterBank::D; } if instruction.prefixes.evex_unchecked().vex().w() { if instruction.prefixes.evex_unchecked().broadcast() { if isa_has_qwords() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } else { if instruction.prefixes.evex_unchecked().lp() || !instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOpcode); } } } } else { if instruction.prefixes.evex_unchecked().broadcast() { return Err(DecodeError::InvalidOpcode); } if instruction.prefixes.evex_unchecked().vex().w() { instruction.mem_size = DEFAULT_EVEX_REGISTER_WIDTH; } else { instruction.mem_size = 4; } } instruction.operand_count = 3; } generated::EVEXOperandCode::VEXTRACTPS => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 4; } } generated::EVEXOperandCode::Ewd_G_xmm_imm8 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 2; } } generated::EVEXOperandCode::Ebd_G_xmm_imm8 => { deny_vex_reg(instruction)?; deny_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::X; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[2] = OperandSpec::ImmU8; instruction.operand_count = 3; if let OperandSpec::RegMMM = mem_oper { instruction.regs[1].bank = RegisterBank::D; } else { instruction.mem_size = 1; } } generated::EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae => { check_mask_reg(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; let item_size = if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VRNDSCALESS { return Err(DecodeError::InvalidOpcode); } else if instruction.opcode == Opcode::VRANGESS { instruction.opcode = Opcode::VRANGESD; 8 } else if instruction.opcode == Opcode::VFPCLASSSS { instruction.opcode = Opcode::VFPCLASSSD; 8 } else if instruction.opcode == Opcode::VREDUCESS { instruction.opcode = Opcode::VREDUCESD; 8 } else if instruction.opcode == Opcode::VFIXUPIMMSS { instruction.opcode = Opcode::VFIXUPIMMSD; 8 } else if instruction.opcode == Opcode::VGETMANTSS { instruction.opcode = Opcode::VGETMANTSD; 8 } else { 4 } } else { 4 }; if let OperandSpec::RegMMM = mem_oper { instruction.mem_size = 0; } else{ instruction.mem_size = item_size; } if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1 => { ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if let OperandSpec::RegMMM = mem_oper { /* no mem size */ } else{ instruction.mem_size = 8; } if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.imm = read_imm_unsigned(words, 1)?; instruction.operands[3] = OperandSpec::ImmU8; instruction.operand_count = 4; set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::Gm_V_zmm_M_xmm_W0 => { ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); instruction.regs[0].bank = RegisterBank::Z; instruction.regs[3].bank = RegisterBank::Z; let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if let OperandSpec::RegMMM = mem_oper { return Err(DecodeError::InvalidOperand); } else{ instruction.mem_size = 16; } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; } generated::EVEXOperandCode::Gm_V_M_xmm => { check_mask_reg(instruction)?; instruction.mem_size = 16; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } instruction.operands[0] = OperandSpec::RegRRR_maskmerge; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::VMOVSD_10 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; if mem_oper == OperandSpec::RegMMM { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; instruction.mem_size = 0; } else { instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 8; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::VMOVSD_11 => { check_mask_reg(instruction)?; ensure_W(instruction, 1)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper.masked(); if mem_oper == OperandSpec::RegMMM { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; instruction.operand_count = 3; instruction.mem_size = 0; } else { instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; instruction.mem_size = 8; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::VMOVSS_10 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR_maskmerge; if mem_oper == OperandSpec::RegMMM { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; instruction.mem_size = 0; } else { instruction.operands[1] = mem_oper; instruction.operand_count = 2; instruction.mem_size = 4; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::VMOVSS_11 => { check_mask_reg(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper.masked(); if mem_oper == OperandSpec::RegMMM { instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = OperandSpec::RegRRR; instruction.operand_count = 3; instruction.mem_size = 0; } else { instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; instruction.mem_size = 4; } set_reg_sizes(instruction, RegisterBank::X); } generated::EVEXOperandCode::VCVTSI2SS => { check_mask_reg(instruction)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() && mem_oper == OperandSpec::RegMMM { if (!instruction.prefixes.evex_unchecked().vex().w() || !isa_has_qwords()) && instruction.opcode == Opcode::VCVTSI2SD { instruction.operands[0] = OperandSpec::RegRRR; } else { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } } else { instruction.operands[0] = OperandSpec::RegRRR; } instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[1].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[1].bank = RegisterBank::D; } } else { if instruction.prefixes.evex_unchecked().vex().w() { if isa_has_qwords() { instruction.mem_size = 8; } else { if [Opcode::VCVTSI2SS, Opcode::VCVTSI2SD].contains(&instruction.opcode) { instruction.mem_size = 4; } else { instruction.mem_size = 8; } } } else { instruction.mem_size = 4; } } } generated::EVEXOperandCode::VCVTTSS2SI => { check_mask_reg(instruction)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae_noround; } else { instruction.operands[0] = OperandSpec::RegRRR; } if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[0].bank = RegisterBank::D; } if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::VCVTSS2SI => { check_mask_reg(instruction)?; deny_z(instruction)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; if instruction.prefixes.evex_unchecked().broadcast() { instruction.operands[0] = OperandSpec::RegRRR_maskmerge_sae; } else { instruction.operands[0] = OperandSpec::RegRRR; } if instruction.prefixes.evex_unchecked().vex().w() { instruction.regs[0].bank = DEFAULT_EVEX_REGISTER_SIZE; } else { instruction.regs[0].bank = RegisterBank::D; } if mem_oper == OperandSpec::RegMMM { instruction.mem_size = 0; } else { instruction.mem_size = 4; } instruction.operands[1] = mem_oper; instruction.operand_count = 2; } generated::EVEXOperandCode::Operands_12_W0 => { deny_mask_reg(instruction)?; deny_z(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { instruction.opcode = Opcode::VMOVHLPS; instruction.mem_size = 0; } else { instruction.opcode = Opcode::VMOVLPS; instruction.mem_size = 8; } } generated::EVEXOperandCode::Operands_16_W0 => { deny_mask_reg(instruction)?; deny_z(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = OperandSpec::RegRRR; instruction.operands[1] = OperandSpec::RegVex; instruction.operands[2] = mem_oper; instruction.operand_count = 3; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { instruction.opcode = Opcode::VMOVLHPS; instruction.mem_size = 0; } else { instruction.opcode = Opcode::VMOVHPS; instruction.mem_size = 8; } } generated::EVEXOperandCode::Mq_G_W0 => { deny_mask_reg(instruction)?; deny_z(instruction)?; ensure_W(instruction, 0)?; let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegRRR; instruction.operand_count = 2; set_reg_sizes(instruction, RegisterBank::X); if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } else { instruction.mem_size = 8; } } generated::EVEXOperandCode::Mvector_Mask_G_LL => { check_mask_reg(instruction)?; deny_z(instruction)?; // we can't just `deny_vex_reg` because vp is used as bit 5 for the index register if instruction.regs[3].num & 0b1111 != 0 { return Err(DecodeError::InvalidOperand); } let modrm = read_modrm(words)?; set_rrr(instruction, modrm); let mem_oper = read_E_vex(words, instruction, modrm, RegisterBank::X, sink)?; instruction.regs[2].num |= instruction.regs[3].num & 0b10000; instruction.operands[0] = mem_oper; instruction.operands[1] = OperandSpec::RegVex; instruction.regs[3].bank = RegisterBank::K; instruction.regs[3].num = instruction.prefixes.evex_unchecked().mask_reg(); instruction.operands[2] = OperandSpec::RegRRR; instruction.operand_count = 2; if mem_oper == OperandSpec::RegMMM { return Err(DecodeError::InvalidOperand); } if instruction.prefixes.evex_unchecked().lp() { if instruction.prefixes.evex_unchecked().vex().l() { return Err(DecodeError::InvalidOperand); } instruction.regs[0].bank = RegisterBank::Z; instruction.regs[2].bank = RegisterBank::Z; } else if instruction.prefixes.evex_unchecked().vex().l() { instruction.regs[0].bank = RegisterBank::Y; instruction.regs[2].bank = RegisterBank::Y; } else { instruction.regs[0].bank = RegisterBank::X; instruction.regs[2].bank = RegisterBank::X; } if instruction.prefixes.evex_unchecked().vex().w() { if instruction.opcode == Opcode::VPSCATTERDD { instruction.opcode = Opcode::VPSCATTERDQ; } else if instruction.opcode == Opcode::VPSCATTERQD { instruction.opcode = Opcode::VPSCATTERQQ; } instruction.mem_size = 8; } else { instruction.mem_size = 4; } instruction.operand_count = 3; } generated::EVEXOperandCode::Nothing => {} } Ok(()) } yaxpeax-x86-1.2.2/src/shared/generated_evex.in000064400000000000000000003362731046102023000173200ustar 00000000000000#[allow(warnings)] mod generated { use super::Opcode::*; const EVEX_OPCODES: [super::Opcode; 496] = [ V4FMADDPS, V4FMADDSS, V4FNMADDPS, V4FNMADDSS, VADDPD, VADDSD, VADDSS, VAESDEC, VAESDECLAST, VAESENC, VAESENCLAST, VALIGND, VALIGNQ, VANDNPD, VANDPD, VBLENDMPD, VBLENDMPS, VBROADCASTF32X2, VBROADCASTF32X4, VBROADCASTF32X8, VBROADCASTF64X2, VBROADCASTF64X4, VBROADCASTI32X2, VBROADCASTI32X4, VBROADCASTI32X8, VBROADCASTI64X2, VBROADCASTI64X4, VBROADCASTSD, VBROADCASTSS, VCMPPD, VCMPSD, VCMPSS, VCOMISD, VCOMPRESSPD, VCOMPRESSPS, VCVTDQ2PD, VCVTNE2PS2BF16, VCVTNEPS2BF16, VCVTPD2DQ, VCVTPD2PS, VCVTPD2QQ, VCVTPD2UQQ, VCVTPH2PS, VCVTPS2DQ, VCVTPS2PH, VCVTPS2QQ, VCVTPS2UQQ, VCVTQQ2PD, VCVTSD2SI, VCVTSD2SS, VCVTSD2USI, VCVTSI2SD, VCVTSI2SS, VCVTSS2SD, VCVTSS2SI, VCVTSS2USI, VCVTTPD2DQ, VCVTTPD2QQ, VCVTTPD2UQQ, VCVTTPS2DQ, VCVTTPS2QQ, VCVTTPS2UQQ, VCVTTSD2SI, VCVTTSD2USI, VCVTTSS2SI, VCVTTSS2USI, VCVTUDQ2PD, VCVTUDQ2PS, VCVTUQQ2PD, VCVTUQQ2PS, VCVTUSI2SD, VCVTUSI2SS, VDBPSADBW, VDIVPD, VDIVSD, VDIVSS, VDPBF16PS, VEXP2PD, VEXP2PS, VEXPANDPD, VEXPANDPS, VEXTRACTF32X4, VEXTRACTF32X8, VEXTRACTF64X2, VEXTRACTF64X4, VEXTRACTI32X4, VEXTRACTI32X8, VEXTRACTI64X2, VEXTRACTI64X4, VEXTRACTPS, VFIXUPIMMPD, VFIXUPIMMPS, VFIXUPIMMSD, VFIXUPIMMSS, VFMADD132PD, VFMADD132PS, VFMADD132SD, VFMADD132SS, VFMADD213PD, VFMADD213PS, VFMADD213SD, VFMADD213SS, VFMADD231PD, VFMADD231PS, VFMADD231SD, VFMADD231SS, VFMADDSUB132PD, VFMADDSUB132PS, VFMADDSUB213PD, VFMADDSUB213PS, VFMADDSUB231PD, VFMADDSUB231PS, VFMSUB132PD, VFMSUB132PS, VFMSUB132SD, VFMSUB132SS, VFMSUB213PD, VFMSUB213PS, VFMSUB213SD, VFMSUB213SS, VFMSUB231PD, VFMSUB231PS, VFMSUB231SD, VFMSUB231SS, VFMSUBADD132PD, VFMSUBADD132PS, VFMSUBADD213PD, VFMSUBADD213PS, VFMSUBADD231PD, VFMSUBADD231PS, VFNMADD132PD, VFNMADD132PS, VFNMADD132SD, VFNMADD132SS, VFNMADD213PD, VFNMADD213PS, VFNMADD213SD, VFNMADD213SS, VFNMADD231PD, VFNMADD231PS, VFNMADD231SD, VFNMADD231SS, VFNMSUB132PD, VFNMSUB132PS, VFNMSUB132SD, VFNMSUB132SS, VFNMSUB213PD, VFNMSUB213PS, VFNMSUB213SD, VFNMSUB213SS, VFNMSUB231PD, VFNMSUB231PS, VFNMSUB231SD, VFNMSUB231SS, VFPCLASSPD, VFPCLASSPS, VFPCLASSSD, VFPCLASSSS, VGETEXPPD, VGETEXPPS, VGETEXPSD, VGETEXPSS, VGETMANTPD, VGETMANTPS, VGETMANTSD, VGETMANTSS, VGF2P8AFFINEINVQB, VGF2P8AFFINEQB, VGF2P8MULB, VINSERTF32X4, VINSERTF32X8, VINSERTF64X2, VINSERTF64X4, VINSERTI32X4, VINSERTI32X8, VINSERTI64X2, VINSERTI64X4, VINSERTPS, VMAXPD, VMAXSD, VMAXSS, VMINPD, VMINSD, VMINSS, VMOVAPD, VMOVD, VMOVDDUP, VMOVDQA32, VMOVDQA64, VMOVDQU16, VMOVDQU32, VMOVDQU64, VMOVDQU8, VMOVHPD, VMOVLPD, VMOVNTDQ, VMOVNTDQA, VMOVNTPD, VMOVQ, VMOVSD, VMOVSHDUP, VMOVSLDUP, VMOVSS, VMOVUPD, VMULPD, VMULSD, VMULSS, VORPD, VP2INTERSECTD, VP2INTERSECTQ, VP4DPWSSD, VP4DPWSSDS, VPABSB, VPABSD, VPABSQ, VPABSW, VPACKSSDW, VPACKSSWB, VPACKUSDW, VPACKUSWB, VPADDB, VPADDD, VPADDQ, VPADDSB, VPADDSW, VPADDUSB, VPADDUSW, VPADDW, VPALIGNR, VPANDD, VPANDND, VPANDNQ, VPANDQ, VPAVGB, VPAVGW, VPBLENDMB, VPBLENDMD, VPBLENDMQ, VPBLENDMW, VPBROADCASTB, VPBROADCASTD, VPBROADCASTMB2Q, VPBROADCASTMW2D, VPBROADCASTQ, VPBROADCASTW, VPCLMULQDQ, VPCMPB, VPCMPD, VPCMPEQB, VPCMPEQD, VPCMPEQQ, VPCMPEQW, VPCMPGTB, VPCMPGTD, VPCMPGTQ, VPCMPGTW, VPCMPQ, VPCMPUB, VPCMPUD, VPCMPUQ, VPCMPUW, VPCMPW, VPCOMPRESSB, VPCOMPRESSD, VPCOMPRESSQ, VPCOMPRESSW, VPCONFLICTD, VPCONFLICTQ, VPDPBUSD, VPDPBUSDS, VPDPWSSD, VPDPWSSDS, VPERMB, VPERMD, VPERMI2B, VPERMI2D, VPERMI2PD, VPERMI2PS, VPERMI2Q, VPERMI2W, VPERMILPD, VPERMILPS, VPERMPD, VPERMPS, VPERMQ, VPERMT2B, VPERMT2D, VPERMT2PD, VPERMT2PS, VPERMT2Q, VPERMT2W, VPERMW, VPEXPANDB, VPEXPANDD, VPEXPANDQ, VPEXPANDW, VPEXTRB, VPEXTRD, VPEXTRQ, VPEXTRW, VPINSRB, VPINSRD, VPINSRQ, VPINSRW, VPLZCNTD, VPLZCNTQ, VPMADD52HUQ, VPMADD52LUQ, VPMADDUBSW, VPMADDWD, VPMAXSB, VPMAXSD, VPMAXSQ, VPMAXSW, VPMAXUB, VPMAXUD, VPMAXUQ, VPMAXUW, VPMINSB, VPMINSD, VPMINSQ, VPMINSW, VPMINUB, VPMINUD, VPMINUQ, VPMINUW, VPMOVB2M, VPMOVD2M, VPMOVDB, VPMOVDW, VPMOVM2B, VPMOVM2D, VPMOVM2Q, VPMOVM2W, VPMOVQ2M, VPMOVQB, VPMOVQD, VPMOVQW, VPMOVSDB, VPMOVSDW, VPMOVSQB, VPMOVSQD, VPMOVSQW, VPMOVSWB, VPMOVSXBD, VPMOVSXBQ, VPMOVSXBW, VPMOVSXDQ, VPMOVSXWD, VPMOVSXWQ, VPMOVUSDB, VPMOVUSDW, VPMOVUSQB, VPMOVUSQD, VPMOVUSQW, VPMOVUSWB, VPMOVW2M, VPMOVWB, VPMOVZXBD, VPMOVZXBQ, VPMOVZXBW, VPMOVZXDQ, VPMOVZXWD, VPMOVZXWQ, VPMULDQ, VPMULHRSW, VPMULHUW, VPMULHW, VPMULLD, VPMULLQ, VPMULLW, VPMULTISHIFTQB, VPMULUDQ, VPOPCNTB, VPOPCNTD, VPOPCNTQ, VPOPCNTW, VPORD, VPORQ, VPROLD, VPROLQ, VPROLVD, VPROLVQ, VPRORVD, VPRORVQ, VPSADBW, VPSHLDD, VPSHLDQ, VPSHLDVD, VPSHLDVQ, VPSHLDVW, VPSHLDW, VPSHRDD, VPSHRDQ, VPSHRDVD, VPSHRDVQ, VPSHRDVW, VPSHRDW, VPSHUFB, VPSHUFBITQMB, VPSHUFD, VPSHUFHW, VPSHUFLW, VPSLLD, VPSLLQ, VPSLLVD, VPSLLVQ, VPSLLVW, VPSLLW, VPSRAD, VPSRAQ, VPSRAVD, VPSRAVQ, VPSRAVW, VPSRAW, VPSRLD, VPSRLQ, VPSRLVD, VPSRLVQ, VPSRLVW, VPSRLW, VPSUBB, VPSUBD, VPSUBQ, VPSUBSB, VPSUBSW, VPSUBUSB, VPSUBUSW, VPSUBW, VPTERNLOGD, VPTERNLOGQ, VPTESTMB, VPTESTMD, VPTESTMQ, VPTESTMW, VPTESTNMB, VPTESTNMD, VPTESTNMQ, VPTESTNMW, VPUNPCKHBW, VPUNPCKHDQ, VPUNPCKHQDQ, VPUNPCKHWD, VPUNPCKLBW, VPUNPCKLDQ, VPUNPCKLQDQ, VPUNPCKLWD, VPXORD, VPXORQ, VRANGEPD, VRANGEPS, VRANGESD, VRANGESS, VRCP14PD, VRCP14PS, VRCP14SD, VRCP14SS, VRCP28PD, VRCP28PS, VRCP28SD, VRCP28SS, VREDUCEPD, VREDUCEPS, VREDUCESD, VREDUCESS, VRNDSCALEPD, VRNDSCALEPS, VRNDSCALESD, VRNDSCALESS, VRSQRT14PD, VRSQRT14PS, VRSQRT14SD, VRSQRT14SS, VRSQRT28PD, VRSQRT28PS, VRSQRT28SD, VRSQRT28SS, VSCALEFPD, VSCALEFPS, VSCALEFSD, VSCALEFSS, VSHUFF32X4, VSHUFF64X2, VSHUFI32X4, VSHUFI64X2, VSHUFPD, VSQRTPD, VSQRTSD, VSQRTSS, VSUBPD, VSUBSD, VSUBSS, VUCOMISD, VUNPCKHPD, VUNPCKLPD, VXORPD, ]; #[derive(Debug, PartialEq, Eq, Copy, Clone)] pub(crate) enum EVEXOperandCode { Mvector_Mask_G_LL, Gm_U_zmm_imm8_sae_W0, Gm_V_E_LL_sae_W1, Gm_U_zmm_sae_W0, E_G_LL_W0, Ebd_G_xmm_imm8, Edd_G_xmm_imm8, Edm_xmm_G_xmm_W0, Edm_xmm_G_ymm_W0, Em_G_LL, Em_G_LL_W0, Em_G_LL_W1, Em_xmm_G_LL_imm8, Em_xmm_G_ymm_W0, Em_xmm_G_ymm_imm8_sae_W0, Em_xmm_G_zmm_W0, Em_ymm_G_zmm_W0, Em_ymm_G_zmm_imm8, Em_ymm_G_zmm_imm8_sae_W0, Eqm_G_xmm_imm8_sae_W0, Eqm_xmm_G_xmm_W0, Eqm_xmm_G_ymm_W0, Eqm_xmm_G_zmm_W0, Ewd_G_xmm_imm8, Ewm_xmm_G_xmm_W0, G_E_LL_W0, G_Ed_xmm_sae_W0, G_LL_Mask, G_LL_Mask_W0, G_LL_Mask_W1, G_V_E_LL, G_V_E_LL_imm8, G_V_Ed_xmm_imm8_W0, G_V_Mq_xmm_W1, G_V_xmm_Ebd_imm8, G_V_xmm_Edq_imm8, G_V_xmm_Edq_sae, Gd_Ed_xmm_sae, Gm_E_LL, Gm_E_LL_W0, Gm_E_LL_W1, Gm_E_LL_bcast, Gm_E_LL_bcast_W0, Gm_E_LL_bcast_W1, Gm_E_LL_imm8, Gm_E_LL_imm8_bcast_W0, Gm_E_LL_imm8_bcast_W1, Gm_E_LL_imm8_sae, Gm_E_LL_imm8_sae_W0, Gm_E_LL_imm8_sae_W1, Gm_E_LL_sae_bcast, Gm_E_LL_sae_bcast_W0, Gm_E_LL_sae_bcast_W1, Gm_E_zmm_sae_bcast, Gm_Ed_LL_imm8_sae_noround_bcast, Gm_Ed_LL_sae_noround_bcast_W0, Gm_Eq_xmm_sae_W1, Gm_LL_Eb_xmm_W0, Gm_LL_Ed_xmm_W0, Gm_LL_Eq_xmm, Gm_LL_Ew_xmm_W0, Gm_LL_Ud, Gm_LL_Ud_W0, Gm_V_E_LL, Gm_V_E_LL_W0, Gm_V_E_LL_W1, Gm_V_E_LL_bcast, Gm_V_E_LL_bcast_W0, Gm_V_E_LL_bcast_W1, Gm_V_E_LL_imm8, Gm_V_E_LL_imm8_W0, Gm_V_E_LL_imm8_W1, Gm_V_E_LL_imm8_bcast, Gm_V_E_LL_imm8_bcast_W0, Gm_V_E_LL_imm8_bcast_W1, Gm_V_E_LL_imm8_sae_bcast, Gm_V_E_LL_sae_bcast, Gm_V_E_LL_sae_bcast_W0, Gm_V_E_LL_sae_bcast_W1, Gm_V_E_xmm_imm8_sae_W1, Gm_V_E_xmm_sae, Gm_V_E_xmm_sae_W1, Gm_V_Ed_LL_bcast, Gm_V_Ed_LL_bcast_W0, Gm_V_Ed_LL_imm8_bcast, Gm_V_Ed_LL_sae, Gm_V_Ed_xmm, Gm_V_Ed_xmm_imm8_sae, Gm_V_Ed_xmm_sae, Gm_V_Ed_xmm_sae_W0, Gm_V_Ed_xmm_sae_bcast, Gm_V_Ed_xmm_sae_noround_W0, Gm_V_Eq_xmm_sae_W1, Gm_V_LL_E_xmm, Gm_V_LL_E_xmm_W0, Gm_V_LL_E_xmm_W1, Gm_V_LL_E_xmm_imm8, Gm_V_M_xmm, Gm_V_ymm_E_xmm_imm8, Gm_V_zmm_E_xmm_imm8, Gm_V_zmm_E_ymm_imm8, Gm_V_zmm_M_xmm_W0, Gm_xmm_E_xmm_sae_bcast_W1, Gm_xmm_E_ymm_sae_bcast_W1, Gm_xmm_Ed_xmm, Gm_xmm_Ed_xmm_W0, Gm_xmm_Eq_xmm, Gm_xmm_Eq_xmm_W0, Gm_xmm_Ew_xmm, Gm_ymm_E_xmm, Gm_ymm_E_xmm_W0, Gm_ymm_E_zmm_sae_bcast_W1, Gm_ymm_Ed_xmm, Gm_ymm_Ed_xmm_W0, Gm_ymm_Eq_xmm, Gm_ymm_M_xmm, Gm_ymm_U_zmm_sae_W1, Gm_zmm_E_xmm, Gm_zmm_E_ymm, Gm_zmm_E_ymm_W0, Gm_zmm_Ed_xmm, Gm_zmm_Ed_xmm_W0, Gm_zmm_Eq_xmm, Gm_zmm_M_xmm, Gm_zmm_M_ymm, M_G_LL_W0, M_G_LL_W1, Mask_E_LL_imm8_bcast, Mask_Ed_xmm_imm8, Mask_U_LL, Mask_V_E_LL, Mask_V_E_LL_W0, Mask_V_E_LL_bcast, Mask_V_E_LL_bcast_W0, Mask_V_E_LL_bcast_W1, Mask_V_E_LL_imm8, Mask_V_E_LL_imm8_bcast, Mask_V_E_LL_imm8_sae_bcast_W0, Maskm_V_E_LL_imm8_sae_bcast_W1, Maskm_V_Ed_xmm_imm8_sae_W0, Maskm_V_Eq_xmm_imm8_sae_W1, Mq_G_W0, Mq_G_xmm_W1, Nothing, Opcode_72_Gm_E_LL_imm8_bcast, Operands_12_W0, Operands_16_W0, Operands_72_W0, VBROADCASTF32X2_Gm_ymm_Ed_xmm, VCVTDQ2PS, VCVTPH2PS, VCVTSI2SS, VCVTSS2SI, VCVTTPD2DQ, VCVTTPS2UDQ, VCVTTPS2UQQ, VCVTTSS2SI, VCVTUDQ2PD, VCVTUSI2SD, VEXTRACTPS, VMOVD_6e, VMOVD_7e, VMOVQ_7e, VMOVQ_Ed_G_xmm, VMOVQ_G_Ed_xmm, VMOVSD_10, VMOVSD_11, VMOVSS_10, VMOVSS_11, VPEXTRW, VPINSRW, } pub(crate) const TABLES: [&'static [(u8, [(super::Opcode, EVEXOperandCode); 4])]; 12] = [ &EVEX_None_0f, &EVEX_66_0f, &EVEX_f2_0f, &EVEX_f3_0f, &DUMMY, &EVEX_66_0f38, &EVEX_f2_0f38, &EVEX_f3_0f38, &DUMMY, &EVEX_66_0f3a, &DUMMY, &DUMMY, ]; pub(crate) const DUMMY: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 0] = [ ]; const EVEX_None_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 30] = [ (0x10, [(super::Opcode::VMOVUPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVUPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVUPS, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x11, [(super::Opcode::VMOVUPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVUPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVUPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x12, [(super::Opcode::Invalid, EVEXOperandCode::Operands_12_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x13, [(super::Opcode::VMOVLPS, EVEXOperandCode::Mq_G_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x14, [(super::Opcode::VUNPCKLPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKLPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKLPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x15, [(super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VUNPCKHPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x16, [(super::Opcode::Invalid, EVEXOperandCode::Operands_16_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x17, [(super::Opcode::VMOVHPS, EVEXOperandCode::Mq_G_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x28, [(super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Gm_E_LL_sae_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x29, [(super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::VMOVAPS, EVEXOperandCode::Em_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2b, [(super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::VMOVNTPS, EVEXOperandCode::M_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2e, [(super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VUCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]), (0x2f, [(super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0), (super::Opcode::VCOMISS, EVEXOperandCode::G_Ed_xmm_sae_W0)]), (0x51, [(super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VSQRTPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]), (0x54, [(super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x55, [(super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VANDNPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x56, [(super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x57, [(super::Opcode::VXORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VXORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VXORPS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x58, [(super::Opcode::VADDPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VADDPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VADDPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VADDPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x59, [(super::Opcode::VMULPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMULPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMULPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMULPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x5a, [(super::Opcode::VCVTPS2PD, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPS2PD, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPS2PD, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPS2PD, EVEXOperandCode::VCVTPH2PS)]), (0x5b, [(super::Opcode::VCVTDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTDQ2PS, EVEXOperandCode::VCVTDQ2PS)]), (0x5c, [(super::Opcode::VSUBPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VSUBPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VSUBPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VSUBPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x5d, [(super::Opcode::VMINPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMINPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMINPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMINPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x5e, [(super::Opcode::VDIVPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VDIVPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VDIVPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VDIVPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x5f, [(super::Opcode::VMAXPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMAXPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMAXPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0), (super::Opcode::VMAXPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W0)]), (0x78, [(super::Opcode::VCVTTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ), (super::Opcode::VCVTTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ), (super::Opcode::VCVTTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ), (super::Opcode::VCVTTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ)]), (0x79, [(super::Opcode::VCVTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ) // operands=['VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_sae', 'VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512_sae', 'VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512_sae'] , (super::Opcode::VCVTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ) // operands=['VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512_sae', 'VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512_sae', 'VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512_sae'] , (super::Opcode::VCVTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ), (super::Opcode::VCVTPS2UDQ, EVEXOperandCode::VCVTTPS2UDQ)]), (0xc2, [(super::Opcode::VCMPPS, EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0), (super::Opcode::VCMPPS, EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0), (super::Opcode::VCMPPS, EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0), (super::Opcode::VCMPPS, EVEXOperandCode::Mask_V_E_LL_imm8_sae_bcast_W0)]), (0xc6, [(super::Opcode::VSHUFPS, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W0), (super::Opcode::VSHUFPS, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W0), (super::Opcode::VSHUFPS, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), ]; const EVEX_66_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 100] = [ (0x10, [(super::Opcode::VMOVUPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVUPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVUPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x11, [(super::Opcode::VMOVUPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::VMOVUPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::VMOVUPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x12, [(super::Opcode::VMOVLPD, EVEXOperandCode::G_V_Mq_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x13, [(super::Opcode::VMOVLPD, EVEXOperandCode::Mq_G_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x14, [(super::Opcode::VUNPCKLPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VUNPCKLPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VUNPCKLPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x15, [(super::Opcode::VUNPCKHPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VUNPCKHPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VUNPCKHPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x16, [(super::Opcode::VMOVHPD, EVEXOperandCode::G_V_Mq_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x17, [(super::Opcode::VMOVHPD, EVEXOperandCode::Mq_G_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x28, [(super::Opcode::VMOVAPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVAPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVAPD, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x29, [(super::Opcode::VMOVAPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::VMOVAPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::VMOVAPD, EVEXOperandCode::Em_G_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2b, [(super::Opcode::VMOVNTPD, EVEXOperandCode::M_G_LL_W1), (super::Opcode::VMOVNTPD, EVEXOperandCode::M_G_LL_W1), (super::Opcode::VMOVNTPD, EVEXOperandCode::M_G_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2e, [(super::Opcode::VUCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VUCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VUCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VUCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1)]), (0x2f, [(super::Opcode::VCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1), (super::Opcode::VCOMISD, EVEXOperandCode::Gm_Eq_xmm_sae_W1)]), (0x51, [(super::Opcode::VSQRTPD, EVEXOperandCode::Gm_E_LL_sae_bcast_W1), (super::Opcode::VSQRTPD, EVEXOperandCode::Gm_E_LL_sae_bcast_W1), (super::Opcode::VSQRTPD, EVEXOperandCode::Gm_E_LL_sae_bcast_W1), (super::Opcode::VSQRTPD, EVEXOperandCode::Gm_E_LL_sae_bcast_W1)]), (0x54, [(super::Opcode::VANDPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VANDPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VANDPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x55, [(super::Opcode::VANDNPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VANDNPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VANDNPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x56, [(super::Opcode::VORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x57, [(super::Opcode::VXORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VXORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VXORPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x58, [(super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VADDPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x59, [(super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMULPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x5a, [(super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_xmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_xmm_E_ymm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_E_zmm_sae_bcast_W1), (super::Opcode::VCVTPD2PS, EVEXOperandCode::Gm_ymm_U_zmm_sae_W1)]), (0x5b, [(super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VCVTPS2DQ, EVEXOperandCode::Gm_E_LL_sae_bcast)]), (0x5c, [(super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VSUBPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x5d, [(super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMINPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x5e, [(super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VDIVPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x5f, [(super::Opcode::VMAXPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMAXPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMAXPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1), (super::Opcode::VMAXPD, EVEXOperandCode::Gm_V_E_LL_sae_bcast_W1)]), (0x60, [(super::Opcode::VPUNPCKLBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKLBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKLBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x61, [(super::Opcode::VPUNPCKLWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKLWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKLWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x62, [(super::Opcode::VPUNPCKLDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPUNPCKLDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPUNPCKLDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x63, [(super::Opcode::VPACKSSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPACKSSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPACKSSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x64, [(super::Opcode::VPCMPGTB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPGTB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPGTB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x65, [(super::Opcode::VPCMPGTW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPGTW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPGTW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x66, [(super::Opcode::VPCMPGTD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::VPCMPGTD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::VPCMPGTD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x67, [(super::Opcode::VPACKUSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPACKUSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPACKUSWB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x68, [(super::Opcode::VPUNPCKHBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKHBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKHBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x69, [(super::Opcode::VPUNPCKHWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKHWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPUNPCKHWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6a, [(super::Opcode::VPUNPCKHDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPUNPCKHDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPUNPCKHDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6b, [(super::Opcode::VPACKSSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKSSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKSSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6c, [(super::Opcode::VPUNPCKLQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPUNPCKLQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPUNPCKLQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6d, [(super::Opcode::VPUNPCKHQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPUNPCKHQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPUNPCKHQDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6e, [(super::Opcode::VMOVD, EVEXOperandCode::VMOVD_6e), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x6f, [(super::Opcode::VMOVDQA32, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQA32, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQA32, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x70, [(super::Opcode::VPSHUFD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::VPSHUFD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::VPSHUFD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x72, [(super::Opcode::VPROLD, EVEXOperandCode::Opcode_72_Gm_E_LL_imm8_bcast), (super::Opcode::VPROLD, EVEXOperandCode::Opcode_72_Gm_E_LL_imm8_bcast), (super::Opcode::VPROLD, EVEXOperandCode::Opcode_72_Gm_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x74, [(super::Opcode::VPCMPEQB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPEQB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPEQB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x75, [(super::Opcode::VPCMPEQW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPEQW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPCMPEQW, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x76, [(super::Opcode::VPCMPEQD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::VPCMPEQD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::VPCMPEQD, EVEXOperandCode::Mask_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x78, [(super::Opcode::VCVTTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ)]), (0x79, [(super::Opcode::VCVTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2UQQ, EVEXOperandCode::VCVTTPS2UQQ)]), (0x7a, [(super::Opcode::VCVTTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ)]), (0x7b, [(super::Opcode::VCVTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ), (super::Opcode::VCVTPS2QQ, EVEXOperandCode::VCVTTPS2UQQ)]), (0x7e, [(super::Opcode::VMOVD, EVEXOperandCode::VMOVD_7e), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7f, [(super::Opcode::VMOVDQA32, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQA32, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQA32, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc2, [(super::Opcode::VCMPPD, EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1), (super::Opcode::VCMPPD, EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1), (super::Opcode::VCMPPD, EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1), (super::Opcode::VCMPPD, EVEXOperandCode::Maskm_V_E_LL_imm8_sae_bcast_W1)]), (0xc4, [(super::Opcode::VPINSRW, EVEXOperandCode::VPINSRW), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc5, [(super::Opcode::VPEXTRW, EVEXOperandCode::VPEXTRW), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc6, [(super::Opcode::VSHUFPD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VSHUFPD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VSHUFPD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd1, [(super::Opcode::VPSRLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd2, [(super::Opcode::VPSRLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::VPSRLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::VPSRLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd3, [(super::Opcode::VPSRLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::VPSRLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::VPSRLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd4, [(super::Opcode::VPADDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPADDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPADDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd5, [(super::Opcode::VPMULLW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULLW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULLW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd6, [(super::Opcode::VMOVQ, EVEXOperandCode::VMOVQ_Ed_G_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd8, [(super::Opcode::VPSUBUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xd9, [(super::Opcode::VPSUBUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xda, [(super::Opcode::VPMINUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdb, [(super::Opcode::VPANDD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPANDD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPANDD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdc, [(super::Opcode::VPADDUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDUSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdd, [(super::Opcode::VPADDUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDUSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xde, [(super::Opcode::VPMAXUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXUB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdf, [(super::Opcode::VPANDND, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPANDND, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPANDND, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe0, [(super::Opcode::VPAVGB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPAVGB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPAVGB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe1, [(super::Opcode::VPSRAW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRAW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRAW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe2, [(super::Opcode::VPSRAD, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRAD, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSRAD, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe3, [(super::Opcode::VPAVGW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPAVGW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPAVGW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe4, [(super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe5, [(super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe6, [(super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]), (0xe7, [(super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::VMOVNTDQ, EVEXOperandCode::E_G_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe8, [(super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xe9, [(super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xea, [(super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xeb, [(super::Opcode::VPORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xec, [(super::Opcode::VPADDSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xed, [(super::Opcode::VPADDSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xee, [(super::Opcode::VPMAXSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xef, [(super::Opcode::VPXORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPXORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPXORD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf1, [(super::Opcode::VPSLLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSLLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::VPSLLW, EVEXOperandCode::Gm_V_LL_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf2, [(super::Opcode::VPSLLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::VPSLLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::VPSLLD, EVEXOperandCode::Gm_V_LL_E_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf3, [(super::Opcode::VPSLLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::VPSLLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::VPSLLQ, EVEXOperandCode::Gm_V_LL_E_xmm_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf4, [(super::Opcode::VPMULUDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULUDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULUDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf5, [(super::Opcode::VPMADDWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMADDWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMADDWD, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf6, [(super::Opcode::VPSADBW, EVEXOperandCode::G_V_E_LL), (super::Opcode::VPSADBW, EVEXOperandCode::G_V_E_LL), (super::Opcode::VPSADBW, EVEXOperandCode::G_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf8, [(super::Opcode::VPSUBB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xf9, [(super::Opcode::VPSUBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSUBW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xfa, [(super::Opcode::VPSUBD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPSUBD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPSUBD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xfb, [(super::Opcode::VPSUBQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPSUBQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPSUBQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xfc, [(super::Opcode::VPADDB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xfd, [(super::Opcode::VPADDW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPADDW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xfe, [(super::Opcode::VPADDD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPADDD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPADDD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), ]; const EVEX_66_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 143] = [ (0x00, [(super::Opcode::VPSHUFB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSHUFB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPSHUFB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x04, [(super::Opcode::VPMADDUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMADDUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMADDUBSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x0b, [(super::Opcode::VPMULHRSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHRSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMULHRSW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x0c, [(super::Opcode::VPERMILPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VPERMILPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::VPERMILPS, EVEXOperandCode::Gm_V_Ed_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x0d, [(super::Opcode::VPERMILPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPERMILPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPERMILPD, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x10, [(super::Opcode::VPSRLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSRLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSRLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x11, [(super::Opcode::VPSRAVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSRAVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSRAVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x12, [(super::Opcode::VPSLLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSLLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSLLVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x13, [(super::Opcode::VCVTPH2PS, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPH2PS, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPH2PS, EVEXOperandCode::VCVTPH2PS), (super::Opcode::VCVTPH2PS, EVEXOperandCode::VCVTPH2PS)]), (0x14, [(super::Opcode::VPRORVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPRORVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPRORVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x15, [(super::Opcode::VPROLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPROLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPROLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x16, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VPERMPS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VPERMPS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x18, [(super::Opcode::VBROADCASTSS, EVEXOperandCode::Gm_xmm_Ed_xmm_W0), (super::Opcode::VBROADCASTSS, EVEXOperandCode::Gm_ymm_Ed_xmm_W0), (super::Opcode::VBROADCASTSS, EVEXOperandCode::Gm_zmm_Ed_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x19, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VBROADCASTF32X2, EVEXOperandCode::VBROADCASTF32X2_Gm_ymm_Ed_xmm), (super::Opcode::VBROADCASTF32X2, EVEXOperandCode::Gm_zmm_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1a, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VBROADCASTF32X4, EVEXOperandCode::Gm_ymm_M_xmm), (super::Opcode::VBROADCASTF32X4, EVEXOperandCode::Gm_zmm_M_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1b, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VBROADCASTF32X8, EVEXOperandCode::Gm_zmm_M_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1c, [(super::Opcode::VPABSB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPABSB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPABSB, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1d, [(super::Opcode::VPABSW, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPABSW, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPABSW, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1e, [(super::Opcode::VPABSD, EVEXOperandCode::Gm_E_LL_bcast_W0), (super::Opcode::VPABSD, EVEXOperandCode::Gm_E_LL_bcast_W0), (super::Opcode::VPABSD, EVEXOperandCode::Gm_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1f, [(super::Opcode::VPABSQ, EVEXOperandCode::Gm_E_LL_bcast_W1), (super::Opcode::VPABSQ, EVEXOperandCode::Gm_E_LL_bcast_W1), (super::Opcode::VPABSQ, EVEXOperandCode::Gm_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x20, [(super::Opcode::VPMOVSXBW, EVEXOperandCode::Gm_xmm_Eq_xmm), (super::Opcode::VPMOVSXBW, EVEXOperandCode::Gm_ymm_E_xmm), (super::Opcode::VPMOVSXBW, EVEXOperandCode::Gm_zmm_E_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x21, [(super::Opcode::VPMOVSXBD, EVEXOperandCode::Gm_xmm_Ed_xmm), (super::Opcode::VPMOVSXBD, EVEXOperandCode::Gm_ymm_Eq_xmm), (super::Opcode::VPMOVSXBD, EVEXOperandCode::Gm_zmm_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x22, [(super::Opcode::VPMOVSXBQ, EVEXOperandCode::Gm_xmm_Ew_xmm), (super::Opcode::VPMOVSXBQ, EVEXOperandCode::Gm_ymm_Ed_xmm), (super::Opcode::VPMOVSXBQ, EVEXOperandCode::Gm_zmm_Eq_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x23, [(super::Opcode::VPMOVSXWD, EVEXOperandCode::Gm_xmm_Eq_xmm), (super::Opcode::VPMOVSXWD, EVEXOperandCode::Gm_ymm_E_xmm), (super::Opcode::VPMOVSXWD, EVEXOperandCode::Gm_zmm_E_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x24, [(super::Opcode::VPMOVSXWQ, EVEXOperandCode::Gm_xmm_Ed_xmm), (super::Opcode::VPMOVSXWQ, EVEXOperandCode::Gm_ymm_Eq_xmm), (super::Opcode::VPMOVSXWQ, EVEXOperandCode::Gm_zmm_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x25, [(super::Opcode::VPMOVSXDQ, EVEXOperandCode::Gm_xmm_Eq_xmm_W0), (super::Opcode::VPMOVSXDQ, EVEXOperandCode::Gm_ymm_E_xmm_W0), (super::Opcode::VPMOVSXDQ, EVEXOperandCode::Gm_zmm_E_ymm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x26, [(super::Opcode::VPTESTMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPTESTMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPTESTMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x27, [(super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x28, [(super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULDQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x29, [(super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPEQQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2a, [(super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::VMOVNTDQA, EVEXOperandCode::G_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2b, [(super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPACKUSDW, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2c, [(super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VSCALEFPS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x2d, [(super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VSCALEFSS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]), (0x30, [(super::Opcode::VPMOVZXBW, EVEXOperandCode::Gm_xmm_Eq_xmm), (super::Opcode::VPMOVZXBW, EVEXOperandCode::Gm_ymm_E_xmm), (super::Opcode::VPMOVZXBW, EVEXOperandCode::Gm_zmm_E_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x31, [(super::Opcode::VPMOVZXBD, EVEXOperandCode::Gm_xmm_Ed_xmm), (super::Opcode::VPMOVZXBD, EVEXOperandCode::Gm_ymm_Eq_xmm), (super::Opcode::VPMOVZXBD, EVEXOperandCode::Gm_zmm_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x32, [(super::Opcode::VPMOVZXBQ, EVEXOperandCode::Gm_xmm_Ew_xmm), (super::Opcode::VPMOVZXBQ, EVEXOperandCode::Gm_ymm_Ed_xmm), (super::Opcode::VPMOVZXBQ, EVEXOperandCode::Gm_zmm_Eq_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x33, [(super::Opcode::VPMOVZXWD, EVEXOperandCode::Gm_xmm_Eq_xmm), (super::Opcode::VPMOVZXWD, EVEXOperandCode::Gm_ymm_E_xmm), (super::Opcode::VPMOVZXWD, EVEXOperandCode::Gm_zmm_E_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x34, [(super::Opcode::VPMOVZXWQ, EVEXOperandCode::Gm_xmm_Ed_xmm), (super::Opcode::VPMOVZXWQ, EVEXOperandCode::Gm_ymm_Eq_xmm), (super::Opcode::VPMOVZXWQ, EVEXOperandCode::Gm_zmm_E_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x35, [(super::Opcode::VPMOVZXDQ, EVEXOperandCode::Gm_xmm_Eq_xmm_W0), (super::Opcode::VPMOVZXDQ, EVEXOperandCode::Gm_ymm_E_xmm_W0), (super::Opcode::VPMOVZXDQ, EVEXOperandCode::Gm_zmm_E_ymm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x36, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VPERMD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPERMD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x37, [(super::Opcode::VPCMPGTQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPGTQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::VPCMPGTQ, EVEXOperandCode::Mask_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x38, [(super::Opcode::VPMINSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x39, [(super::Opcode::VPMINSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMINSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMINSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3a, [(super::Opcode::VPMINUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMINUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3b, [(super::Opcode::VPMINUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMINUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMINUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3c, [(super::Opcode::VPMAXSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXSB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3d, [(super::Opcode::VPMAXSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXSD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3e, [(super::Opcode::VPMAXUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPMAXUW, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3f, [(super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMAXUD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x40, [(super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPMULLD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x42, [(super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VGETEXPPS, EVEXOperandCode::Gm_E_LL_sae_bcast)]), (0x43, [(super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast), (super::Opcode::VGETEXPSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_bcast)]), (0x44, [(super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPLZCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x45, [(super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x46, [(super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSRAVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x47, [(super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSLLVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x4c, [(super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VRCP14PS, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x4d, [(super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae), (super::Opcode::VRCP14SS, EVEXOperandCode::Gm_V_Ed_xmm_sae)]), (0x4e, [(super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::VRSQRT14PS, EVEXOperandCode::Gm_E_LL_sae_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x4f, [(super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm), (super::Opcode::VRSQRT14SS, EVEXOperandCode::Gm_V_Ed_xmm)]), (0x50, [(super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x51, [(super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPBUSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x52, [(super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSD, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x53, [(super::Opcode::VPDPWSSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VPDPWSSDS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x54, [(super::Opcode::VPOPCNTB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPOPCNTB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPOPCNTB, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x55, [(super::Opcode::VPOPCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPOPCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPOPCNTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x58, [(super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ed_xmm_W0), (super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ed_xmm_W0), (super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ed_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x59, [(super::Opcode::VBROADCASTI32X2, EVEXOperandCode::Gm_LL_Eq_xmm), (super::Opcode::VBROADCASTI32X2, EVEXOperandCode::Gm_LL_Eq_xmm), (super::Opcode::VBROADCASTI32X2, EVEXOperandCode::Gm_LL_Eq_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x5a, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VBROADCASTI32X4, EVEXOperandCode::Gm_ymm_M_xmm), (super::Opcode::VBROADCASTI32X4, EVEXOperandCode::Gm_zmm_M_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x5b, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VBROADCASTI32X8, EVEXOperandCode::Gm_zmm_M_ymm), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x62, [(super::Opcode::VPEXPANDB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPEXPANDB, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPEXPANDB, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x63, [(super::Opcode::VPCOMPRESSB, EVEXOperandCode::Em_G_LL), (super::Opcode::VPCOMPRESSB, EVEXOperandCode::Em_G_LL), (super::Opcode::VPCOMPRESSB, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x64, [(super::Opcode::VPBLENDMD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPBLENDMD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPBLENDMD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x65, [(super::Opcode::VBLENDMPS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VBLENDMPS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VBLENDMPS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x66, [(super::Opcode::VPBLENDMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPBLENDMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPBLENDMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x70, [(super::Opcode::VPSHLDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSHLDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSHLDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x71, [(super::Opcode::VPSHLDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSHLDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSHLDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x72, [(super::Opcode::VPSHRDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSHRDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::VPSHRDVW, EVEXOperandCode::Gm_V_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x73, [(super::Opcode::VPSHRDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSHRDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPSHRDVD, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x75, [(super::Opcode::VPERMI2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMI2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMI2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x76, [(super::Opcode::VPERMI2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPERMI2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPERMI2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x77, [(super::Opcode::VPERMI2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VPERMI2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VPERMI2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x78, [(super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Eb_xmm_W0), (super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Eb_xmm_W0), (super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Eb_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x79, [(super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ew_xmm_W0), (super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ew_xmm_W0), (super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ew_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7a, [(super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::VPBROADCASTB, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7b, [(super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::VPBROADCASTW, EVEXOperandCode::Gm_LL_Ud_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7c, [(super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ud), (super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ud), (super::Opcode::VPBROADCASTD, EVEXOperandCode::Gm_LL_Ud), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7d, [(super::Opcode::VPERMT2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMT2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMT2B, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7e, [(super::Opcode::VPERMT2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPERMT2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::VPERMT2D, EVEXOperandCode::Gm_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7f, [(super::Opcode::VPERMT2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VPERMT2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::VPERMT2PS, EVEXOperandCode::Gm_V_Ed_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x83, [(super::Opcode::VPMULTISHIFTQB, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULTISHIFTQB, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMULTISHIFTQB, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x88, [(super::Opcode::VEXPANDPS, EVEXOperandCode::Gm_E_LL), (super::Opcode::VEXPANDPS, EVEXOperandCode::Gm_E_LL), (super::Opcode::VEXPANDPS, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x89, [(super::Opcode::VPEXPANDD, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPEXPANDD, EVEXOperandCode::Gm_E_LL), (super::Opcode::VPEXPANDD, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x8a, [(super::Opcode::VCOMPRESSPS, EVEXOperandCode::Em_G_LL), (super::Opcode::VCOMPRESSPS, EVEXOperandCode::Em_G_LL), (super::Opcode::VCOMPRESSPS, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x8b, [(super::Opcode::VPCOMPRESSD, EVEXOperandCode::Em_G_LL), (super::Opcode::VPCOMPRESSD, EVEXOperandCode::Em_G_LL), (super::Opcode::VPCOMPRESSD, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x8d, [(super::Opcode::VPERMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::VPERMB, EVEXOperandCode::Gm_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x8f, [(super::Opcode::VPSHUFBITQMB, EVEXOperandCode::Mask_V_E_LL_W0), (super::Opcode::VPSHUFBITQMB, EVEXOperandCode::Mask_V_E_LL_W0), (super::Opcode::VPSHUFBITQMB, EVEXOperandCode::Mask_V_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x96, [(super::Opcode::VFMADDSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x97, [(super::Opcode::VFMSUBADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x98, [(super::Opcode::VFMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x99, [(super::Opcode::VFMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0x9a, [(super::Opcode::VFMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x9b, [(super::Opcode::VFMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0x9c, [(super::Opcode::VFNMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x9d, [(super::Opcode::VFNMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD132SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0x9e, [(super::Opcode::VFNMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB132PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0x9f, [(super::Opcode::VFNMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB132SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xa0, [(super::Opcode::VPSCATTERDD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::VPSCATTERDD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::VPSCATTERDD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xa1, [(super::Opcode::VPSCATTERQD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::VPSCATTERQD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::VPSCATTERQD, EVEXOperandCode::Mvector_Mask_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xa6, [(super::Opcode::VFMADDSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xa7, [(super::Opcode::VFMSUBADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xa8, [(super::Opcode::VFMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xa9, [(super::Opcode::VFMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xaa, [(super::Opcode::VFMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xab, [(super::Opcode::VFMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xac, [(super::Opcode::VFNMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xad, [(super::Opcode::VFNMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD213SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xae, [(super::Opcode::VFNMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB213PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xaf, [(super::Opcode::VFNMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB213SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xb4, [(super::Opcode::VPMADD52LUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMADD52LUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMADD52LUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xb5, [(super::Opcode::VPMADD52HUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMADD52HUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::VPMADD52HUQ, EVEXOperandCode::Gm_V_E_LL_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xb6, [(super::Opcode::VFMADDSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADDSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xb7, [(super::Opcode::VFMSUBADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUBADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xb8, [(super::Opcode::VFMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xb9, [(super::Opcode::VFMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xba, [(super::Opcode::VFMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xbb, [(super::Opcode::VFMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xbc, [(super::Opcode::VFNMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMADD231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xbd, [(super::Opcode::VFNMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMADD231SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xbe, [(super::Opcode::VFNMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast), (super::Opcode::VFNMSUB231PS, EVEXOperandCode::Gm_V_E_LL_sae_bcast)]), (0xbf, [(super::Opcode::VFNMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae), (super::Opcode::VFNMSUB231SS, EVEXOperandCode::Gm_V_Ed_LL_sae)]), (0xc4, [(super::Opcode::VPCONFLICTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPCONFLICTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::VPCONFLICTD, EVEXOperandCode::Gm_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc8, [(super::Opcode::VEXP2PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VEXP2PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VEXP2PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VEXP2PS, EVEXOperandCode::Gm_E_zmm_sae_bcast)]), (0xca, [(super::Opcode::VRCP28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRCP28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRCP28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRCP28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast)]), (0xcb, [(super::Opcode::VRCP28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRCP28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRCP28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRCP28SS, EVEXOperandCode::Gm_V_E_xmm_sae)]), (0xcc, [(super::Opcode::VRSQRT28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRSQRT28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRSQRT28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast), (super::Opcode::VRSQRT28PS, EVEXOperandCode::Gm_E_zmm_sae_bcast)]), (0xcd, [(super::Opcode::VRSQRT28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRSQRT28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRSQRT28SS, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VRSQRT28SS, EVEXOperandCode::Gm_V_E_xmm_sae)]), (0xcf, [(super::Opcode::VGF2P8MULB, EVEXOperandCode::Gm_V_E_LL_W0), (super::Opcode::VGF2P8MULB, EVEXOperandCode::Gm_V_E_LL_W0), (super::Opcode::VGF2P8MULB, EVEXOperandCode::Gm_V_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdc, [(super::Opcode::VAESENC, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESENC, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESENC, EVEXOperandCode::G_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdd, [(super::Opcode::VAESENCLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESENCLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESENCLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xde, [(super::Opcode::VAESDEC, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESDEC, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESDEC, EVEXOperandCode::G_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xdf, [(super::Opcode::VAESDECLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESDECLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::VAESDECLAST, EVEXOperandCode::G_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), ]; const EVEX_66_0f3a: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 51] = [ (0x00, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VPERMQ, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::VPERMQ, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x01, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VPERMPD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::VPERMPD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x03, [(super::Opcode::VALIGND, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VALIGND, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VALIGND, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x04, [(super::Opcode::VPERMILPS, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::VPERMILPS, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::VPERMILPS, EVEXOperandCode::Gm_E_LL_imm8_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x05, [(super::Opcode::VPERMILPD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::VPERMILPD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::VPERMILPD, EVEXOperandCode::Gm_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x08, [(super::Opcode::VRNDSCALEPS, EVEXOperandCode::Gm_E_LL_imm8_sae_W0), (super::Opcode::VRNDSCALEPS, EVEXOperandCode::Gm_E_LL_imm8_sae_W0), (super::Opcode::VRNDSCALEPS, EVEXOperandCode::Gm_E_LL_imm8_sae_W0), (super::Opcode::VRNDSCALEPS, EVEXOperandCode::Gm_E_LL_imm8_sae_W0)]), (0x09, [(super::Opcode::VRNDSCALEPD, EVEXOperandCode::Gm_E_LL_imm8_sae_W1), (super::Opcode::VRNDSCALEPD, EVEXOperandCode::Gm_E_LL_imm8_sae_W1), (super::Opcode::VRNDSCALEPD, EVEXOperandCode::Gm_E_LL_imm8_sae_W1), (super::Opcode::VRNDSCALEPD, EVEXOperandCode::Gm_E_LL_imm8_sae_W1)]), (0x0a, [(super::Opcode::VRNDSCALESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRNDSCALESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRNDSCALESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRNDSCALESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]),// W0 (0x0b, [(super::Opcode::VRNDSCALESD, EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1), (super::Opcode::VRNDSCALESD, EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1), (super::Opcode::VRNDSCALESD, EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1), (super::Opcode::VRNDSCALESD, EVEXOperandCode::Gm_V_E_xmm_imm8_sae_W1)]),// W1 (0x0f, [(super::Opcode::VPALIGNR, EVEXOperandCode::Gm_V_E_LL_imm8), (super::Opcode::VPALIGNR, EVEXOperandCode::Gm_V_E_LL_imm8), (super::Opcode::VPALIGNR, EVEXOperandCode::Gm_V_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x14, [(super::Opcode::VPEXTRB, EVEXOperandCode::Ebd_G_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x15, [(super::Opcode::VPEXTRW, EVEXOperandCode::Ewd_G_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x16, [(super::Opcode::Invalid, EVEXOperandCode::Edd_G_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x17, [(super::Opcode::VEXTRACTPS, EVEXOperandCode::VEXTRACTPS), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x18, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VINSERTF32X4, EVEXOperandCode::Gm_V_LL_E_xmm_imm8), (super::Opcode::VINSERTF32X4, EVEXOperandCode::Gm_V_LL_E_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x19, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VEXTRACTF32X4, EVEXOperandCode::Em_xmm_G_LL_imm8), (super::Opcode::VEXTRACTF32X4, EVEXOperandCode::Em_xmm_G_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1a, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VINSERTF32X8, EVEXOperandCode::Gm_V_zmm_E_ymm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1b, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VEXTRACTF32X8, EVEXOperandCode::Em_ymm_G_zmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1d, [(super::Opcode::VCVTPS2PH, EVEXOperandCode::Eqm_G_xmm_imm8_sae_W0), (super::Opcode::VCVTPS2PH, EVEXOperandCode::Em_xmm_G_ymm_imm8_sae_W0), (super::Opcode::VCVTPS2PH, EVEXOperandCode::Em_ymm_G_zmm_imm8_sae_W0), (super::Opcode::VCVTPS2PH, EVEXOperandCode::Em_ymm_G_zmm_imm8_sae_W0)]), (0x1e, [(super::Opcode::VPCMPUD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::VPCMPUD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::VPCMPUD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x1f, [(super::Opcode::VPCMPD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::VPCMPD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::VPCMPD, EVEXOperandCode::Mask_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x20, [(super::Opcode::VPINSRB, EVEXOperandCode::G_V_xmm_Ebd_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x21, [(super::Opcode::VINSERTPS, EVEXOperandCode::G_V_Ed_xmm_imm8_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x22, [(super::Opcode::VPINSRD, EVEXOperandCode::G_V_xmm_Edq_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x23, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VSHUFF32X4, EVEXOperandCode::Gm_V_Ed_LL_imm8_bcast), (super::Opcode::VSHUFF32X4, EVEXOperandCode::Gm_V_Ed_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x25, [(super::Opcode::VPTERNLOGD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPTERNLOGD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPTERNLOGD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x26, [(super::Opcode::VGETMANTPS, EVEXOperandCode::Gm_Ed_LL_imm8_sae_noround_bcast), (super::Opcode::VGETMANTPS, EVEXOperandCode::Gm_Ed_LL_imm8_sae_noround_bcast), (super::Opcode::VGETMANTPS, EVEXOperandCode::Gm_Ed_LL_imm8_sae_noround_bcast), (super::Opcode::VGETMANTPS, EVEXOperandCode::Gm_Ed_LL_imm8_sae_noround_bcast)]), (0x27, [(super::Opcode::VGETMANTSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VGETMANTSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VGETMANTSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VGETMANTSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]), (0x38, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VINSERTI32X4, EVEXOperandCode::Gm_V_ymm_E_xmm_imm8), (super::Opcode::VINSERTI32X4, EVEXOperandCode::Gm_V_zmm_E_xmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x39, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VEXTRACTI32X4, EVEXOperandCode::Em_xmm_G_LL_imm8), (super::Opcode::VEXTRACTI32X4, EVEXOperandCode::Em_xmm_G_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3a, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VINSERTI32X8, EVEXOperandCode::Gm_V_zmm_E_ymm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3b, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VEXTRACTI32X8, EVEXOperandCode::Em_ymm_G_zmm_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3e, [(super::Opcode::VPCMPUB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::VPCMPUB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::VPCMPUB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3f, [(super::Opcode::VPCMPB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::VPCMPB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::VPCMPB, EVEXOperandCode::Mask_V_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x42, [(super::Opcode::VDBPSADBW, EVEXOperandCode::Gm_V_E_LL_imm8_W0), (super::Opcode::VDBPSADBW, EVEXOperandCode::Gm_V_E_LL_imm8_W0), (super::Opcode::VDBPSADBW, EVEXOperandCode::Gm_V_E_LL_imm8_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x43, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VSHUFI32X4, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VSHUFI32X4, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x44, [(super::Opcode::VPCLMULQDQ, EVEXOperandCode::G_V_E_LL_imm8), (super::Opcode::VPCLMULQDQ, EVEXOperandCode::G_V_E_LL_imm8), (super::Opcode::VPCLMULQDQ, EVEXOperandCode::G_V_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x50, [(super::Opcode::VRANGEPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VRANGEPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VRANGEPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VRANGEPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast)]), (0x51, [(super::Opcode::VRANGESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRANGESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRANGESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VRANGESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]), (0x54, [(super::Opcode::VFIXUPIMMPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VFIXUPIMMPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VFIXUPIMMPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast), (super::Opcode::VFIXUPIMMPS, EVEXOperandCode::Gm_V_E_LL_imm8_sae_bcast)]), (0x55, [(super::Opcode::VFIXUPIMMSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VFIXUPIMMSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VFIXUPIMMSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VFIXUPIMMSS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]), (0x56, [(super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae), (super::Opcode::VREDUCEPS, EVEXOperandCode::Gm_E_LL_imm8_sae)]), (0x57, [(super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae), (super::Opcode::VREDUCESS, EVEXOperandCode::Gm_V_Ed_xmm_imm8_sae)]), (0x66, [(super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::VFPCLASSPS, EVEXOperandCode::Mask_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x67, [(super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8), (super::Opcode::VFPCLASSSS, EVEXOperandCode::Mask_Ed_xmm_imm8)]), (0x70, [(super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHLDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x71, [(super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHLDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x72, [(super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::VPSHRDW, EVEXOperandCode::Gm_V_E_LL_imm8_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x73, [(super::Opcode::VPSHRDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHRDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::VPSHRDD, EVEXOperandCode::Gm_V_E_LL_imm8_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xce, [(super::Opcode::VGF2P8AFFINEQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xcf, [(super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::VGF2P8AFFINEINVQB, EVEXOperandCode::Gm_V_E_LL_imm8_bcast_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), ]; const EVEX_f2_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 26] = [ (0x10, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_10)]),// W0 (0x11, [(super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11), (super::Opcode::VMOVSS, EVEXOperandCode::VMOVSS_11)]),// W0 (0x12, [(super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSLDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x16, [(super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::VMOVSHDUP, EVEXOperandCode::Gm_E_LL_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2a, [(super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SS, EVEXOperandCode::VCVTSI2SS)]), (0x2c, [(super::Opcode::VCVTTSS2SI, EVEXOperandCode::VCVTTSS2SI), (super::Opcode::VCVTTSS2SI, EVEXOperandCode::VCVTTSS2SI), (super::Opcode::VCVTTSS2SI, EVEXOperandCode::VCVTTSS2SI), (super::Opcode::VCVTTSS2SI, EVEXOperandCode::VCVTTSS2SI)]), (0x2d, [(super::Opcode::VCVTSS2SI, EVEXOperandCode::VCVTSS2SI), (super::Opcode::VCVTSS2SI, EVEXOperandCode::VCVTSS2SI), (super::Opcode::VCVTSS2SI, EVEXOperandCode::VCVTSS2SI), (super::Opcode::VCVTSS2SI, EVEXOperandCode::VCVTSS2SI)]), (0x51, [(super::Opcode::VSQRTSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSQRTSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSQRTSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSQRTSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]), (0x58, [(super::Opcode::VADDSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VADDSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VADDSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VADDSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]), (0x59, [(super::Opcode::VMULSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMULSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMULSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMULSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]), (0x5a, [(super::Opcode::VCVTSS2SD, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround_W0), (super::Opcode::VCVTSS2SD, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround_W0), (super::Opcode::VCVTSS2SD, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround_W0), (super::Opcode::VCVTSS2SD, EVEXOperandCode::Gm_V_Ed_xmm_sae_noround_W0)]),// W0 (0x5b, [(super::Opcode::VCVTTPS2DQ, EVEXOperandCode::Gm_Ed_LL_sae_noround_bcast_W0), (super::Opcode::VCVTTPS2DQ, EVEXOperandCode::Gm_Ed_LL_sae_noround_bcast_W0), (super::Opcode::VCVTTPS2DQ, EVEXOperandCode::Gm_Ed_LL_sae_noround_bcast_W0), (super::Opcode::VCVTTPS2DQ, EVEXOperandCode::Gm_Ed_LL_sae_noround_bcast_W0)]), (0x5c, [(super::Opcode::VSUBSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSUBSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSUBSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VSUBSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]), (0x5d, [(super::Opcode::VMINSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMINSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMINSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMINSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]),// W0 (0x5e, [(super::Opcode::VDIVSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VDIVSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VDIVSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VDIVSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]), (0x5f, [(super::Opcode::VMAXSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMAXSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMAXSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0), (super::Opcode::VMAXSS, EVEXOperandCode::Gm_V_Ed_xmm_sae_W0)]),// W0 (0x6f, [(super::Opcode::VMOVDQU32, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU32, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU32, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x70, [(super::Opcode::VPSHUFHW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFHW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFHW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x78, [(super::Opcode::VCVTTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x79, [(super::Opcode::VCVTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSS2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x7a, [(super::Opcode::VCVTUDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTUDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTUDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTUDQ2PD, EVEXOperandCode::VCVTUDQ2PD)]), (0x7b, [(super::Opcode::VCVTUSI2SS, EVEXOperandCode::G_V_xmm_Edq_sae), (super::Opcode::VCVTUSI2SS, EVEXOperandCode::G_V_xmm_Edq_sae), (super::Opcode::VCVTUSI2SS, EVEXOperandCode::G_V_xmm_Edq_sae), (super::Opcode::VCVTUSI2SS, EVEXOperandCode::G_V_xmm_Edq_sae)]), (0x7e, [(super::Opcode::VMOVQ, EVEXOperandCode::VMOVQ_7e), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7f, [(super::Opcode::VMOVDQU32, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU32, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU32, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc2, [(super::Opcode::VCMPSS, EVEXOperandCode::Maskm_V_Ed_xmm_imm8_sae_W0), (super::Opcode::VCMPSS, EVEXOperandCode::Maskm_V_Ed_xmm_imm8_sae_W0), (super::Opcode::VCMPSS, EVEXOperandCode::Maskm_V_Ed_xmm_imm8_sae_W0), (super::Opcode::VCMPSS, EVEXOperandCode::Maskm_V_Ed_xmm_imm8_sae_W0)]), (0xe6, [(super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD), (super::Opcode::VCVTDQ2PD, EVEXOperandCode::VCVTUDQ2PD)]), ]; const EVEX_f2_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 28] = [ (0x10, [(super::Opcode::VPMOVUSWB, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVUSWB, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x11, [(super::Opcode::VPMOVUSDB, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSDB, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x12, [(super::Opcode::VPMOVUSQB, EVEXOperandCode::Ewm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Edm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSQB, EVEXOperandCode::Eqm_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x13, [(super::Opcode::VPMOVUSDW, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSDW, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVUSDW, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x14, [(super::Opcode::VPMOVUSQW, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSQW, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVUSQW, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x15, [(super::Opcode::VPMOVUSQD, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVUSQD, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVUSQD, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x20, [(super::Opcode::VPMOVSWB, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVSWB, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVSWB, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x21, [(super::Opcode::VPMOVSDB, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVSDB, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVSDB, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x22, [(super::Opcode::VPMOVSQB, EVEXOperandCode::Ewm_xmm_G_xmm_W0), (super::Opcode::VPMOVSQB, EVEXOperandCode::Edm_xmm_G_ymm_W0), (super::Opcode::VPMOVSQB, EVEXOperandCode::Eqm_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x23, [(super::Opcode::VPMOVSDW, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVSDW, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVSDW, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x24, [(super::Opcode::VPMOVSQW, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVSQW, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVSQW, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x25, [(super::Opcode::VPMOVSQD, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVSQD, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVSQD, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x26, [(super::Opcode::VPTESTNMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPTESTNMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::VPTESTNMB, EVEXOperandCode::Mask_V_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x27, [(super::Opcode::VPTESTNMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTNMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VPTESTNMD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x28, [(super::Opcode::VPMOVM2B, EVEXOperandCode::G_LL_Mask), (super::Opcode::VPMOVM2B, EVEXOperandCode::G_LL_Mask), (super::Opcode::VPMOVM2B, EVEXOperandCode::G_LL_Mask), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x29, [(super::Opcode::VPMOVB2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::VPMOVB2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::VPMOVB2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2a, [(super::Opcode::VPBROADCASTMB2Q, EVEXOperandCode::G_LL_Mask_W1), (super::Opcode::VPBROADCASTMB2Q, EVEXOperandCode::G_LL_Mask_W1), (super::Opcode::VPBROADCASTMB2Q, EVEXOperandCode::G_LL_Mask_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x30, [(super::Opcode::VPMOVWB, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVWB, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVWB, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x31, [(super::Opcode::VPMOVDB, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVDB, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVDB, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x32, [(super::Opcode::VPMOVQB, EVEXOperandCode::Ewm_xmm_G_xmm_W0), (super::Opcode::VPMOVQB, EVEXOperandCode::Edm_xmm_G_ymm_W0), (super::Opcode::VPMOVQB, EVEXOperandCode::Eqm_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x33, [(super::Opcode::VPMOVDW, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVDW, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVDW, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x34, [(super::Opcode::VPMOVQW, EVEXOperandCode::Edm_xmm_G_xmm_W0), (super::Opcode::VPMOVQW, EVEXOperandCode::Eqm_xmm_G_ymm_W0), (super::Opcode::VPMOVQW, EVEXOperandCode::Em_xmm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x35, [(super::Opcode::VPMOVQD, EVEXOperandCode::Eqm_xmm_G_xmm_W0), (super::Opcode::VPMOVQD, EVEXOperandCode::Em_xmm_G_ymm_W0), (super::Opcode::VPMOVQD, EVEXOperandCode::Em_ymm_G_zmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x38, [(super::Opcode::VPMOVM2D, EVEXOperandCode::G_LL_Mask), (super::Opcode::VPMOVM2D, EVEXOperandCode::G_LL_Mask), (super::Opcode::VPMOVM2D, EVEXOperandCode::G_LL_Mask), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x39, [(super::Opcode::VPMOVD2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::VPMOVD2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::VPMOVD2M, EVEXOperandCode::Mask_U_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x3a, [(super::Opcode::VPBROADCASTMW2D, EVEXOperandCode::G_LL_Mask_W0), (super::Opcode::VPBROADCASTMW2D, EVEXOperandCode::G_LL_Mask_W0), (super::Opcode::VPBROADCASTMW2D, EVEXOperandCode::G_LL_Mask_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x52, [(super::Opcode::VDPBF16PS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VDPBF16PS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VDPBF16PS, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x72, [(super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::VCVTNEPS2BF16, EVEXOperandCode::Operands_72_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), ]; const EVEX_f3_0f: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 24] = [ (0x10, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_10)]),// W1 (0x11, [(super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11), (super::Opcode::VMOVSD, EVEXOperandCode::VMOVSD_11)]),// W1 (0x12, [(super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::VMOVDDUP, EVEXOperandCode::Gm_E_LL_W1), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x2a, [(super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS), (super::Opcode::VCVTSI2SD, EVEXOperandCode::VCVTSI2SS)]), (0x2c, [(super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x2d, [(super::Opcode::VCVTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2SI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x51, [(super::Opcode::VSQRTSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSQRTSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSQRTSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSQRTSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]), (0x58, [(super::Opcode::VADDSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VADDSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VADDSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VADDSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]), (0x59, [(super::Opcode::VMULSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMULSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMULSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMULSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]), (0x5a, [(super::Opcode::VCVTSD2SS, EVEXOperandCode::Gm_V_Eq_xmm_sae_W1), (super::Opcode::VCVTSD2SS, EVEXOperandCode::Gm_V_Eq_xmm_sae_W1), (super::Opcode::VCVTSD2SS, EVEXOperandCode::Gm_V_Eq_xmm_sae_W1), (super::Opcode::VCVTSD2SS, EVEXOperandCode::Gm_V_Eq_xmm_sae_W1)]), (0x5c, [(super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VSUBSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]), (0x5d, [(super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VMINSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]),// W1 (0x5e, [(super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1), (super::Opcode::VDIVSD, EVEXOperandCode::Gm_V_E_xmm_sae_W1)]), (0x5f, [(super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae), (super::Opcode::VMAXSD, EVEXOperandCode::Gm_V_E_xmm_sae)]),// W1 (0x6f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Gm_E_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x70, [(super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::VPSHUFLW, EVEXOperandCode::Gm_E_LL_imm8), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x78, [(super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x79, [(super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae), (super::Opcode::VCVTSD2USI, EVEXOperandCode::Gd_Ed_xmm_sae)]), (0x7a, [(super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS), (super::Opcode::VCVTUDQ2PS, EVEXOperandCode::VCVTDQ2PS)]), (0x7b, [(super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD), (super::Opcode::VCVTUSI2SD, EVEXOperandCode::VCVTUSI2SD)]), (0x7e, [(super::Opcode::VMOVQ, EVEXOperandCode::VMOVQ_G_Ed_xmm), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x7f, [(super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::VMOVDQU8, EVEXOperandCode::Em_G_LL), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xc2, [(super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1), (super::Opcode::VCMPSD, EVEXOperandCode::Maskm_V_Eq_xmm_imm8_sae_W1)]), (0xe6, [(super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ), (super::Opcode::VCVTPD2DQ, EVEXOperandCode::VCVTTPD2DQ)]), ]; const EVEX_f3_0f38: [(u8, [(super::Opcode, EVEXOperandCode); 4]); 8] = [ (0x52, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSD, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x53, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::VP4DPWSSDS, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x68, [(super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::VP2INTERSECTD, EVEXOperandCode::Mask_V_E_LL_bcast), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x72, [(super::Opcode::VCVTNE2PS2BF16, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VCVTNE2PS2BF16, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::VCVTNE2PS2BF16, EVEXOperandCode::Gm_V_E_LL_bcast_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x9a, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::V4FMADDPS, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0x9b, [(super::Opcode::V4FMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FMADDSS, EVEXOperandCode::Gm_V_M_xmm)]),// W0 (0xaa, [(super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::Invalid, EVEXOperandCode::Nothing), (super::Opcode::V4FNMADDPS, EVEXOperandCode::Gm_V_zmm_M_xmm_W0), (super::Opcode::Invalid, EVEXOperandCode::Nothing)]), (0xab, [(super::Opcode::V4FNMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FNMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FNMADDSS, EVEXOperandCode::Gm_V_M_xmm), (super::Opcode::V4FNMADDSS, EVEXOperandCode::Gm_V_M_xmm)]),// W0 ]; } yaxpeax-x86-1.2.2/test/bench.rs000064400000000000000000000102571046102023000143410ustar 00000000000000#![feature(test)] extern crate test; extern crate yaxpeax_x86; extern crate yaxpeax_arch; use yaxpeax_arch::Decoder; #[cfg(feature = "capstone_bench")] use std::ffi::c_void; #[cfg(feature = "capstone_bench")] use std::io::Write; use test::Bencher; /* use yaxpeax_x86::{Instruction, decode_one}; fn decode(bytes: &[u8]) -> Option { let mut instr = Instruction::invalid(); match decode_one(bytes.iter().map(|x| *x), &mut instr) { Some(()) => Some(instr), None => None } } */ #[bench] fn bench_1020000_instrs(b: &mut Bencher) { b.iter(|| { for _i in 0..30000 { test::black_box(do_decode_swathe()); } }) } #[cfg(feature = "capstone_bench")] #[bench] fn bench_102000_intrs_capstone(b: &mut Bencher) { let handle = get_cs_handle(); // panic!("Allocating.."); let mut instr: *mut c_void = unsafe { cs_malloc(handle) }; // panic!("Allocated..."); b.iter(|| { for i in (0..3000) { test::black_box(do_capstone_decode_swathe(handle, instr)); } }) } const DECODE_DATA: [u8; 130] = [ 0x48, 0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00, 0x48, 0x89, 0x44, 0x24, 0x08, 0x48, 0x89, 0x43, 0x18, 0x48, 0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00, 0x49, 0x89, 0x4e, 0x08, 0x48, 0x8b, 0x32, 0x49, 0x89, 0x46, 0x10, 0x4d, 0x0f, 0x43, 0xec, 0x49, 0x0f, 0xb6, 0x06, 0x0f, 0xb7, 0x06, 0x66, 0x41, 0x50, 0x66, 0x41, 0x31, 0xc0, 0x66, 0x41, 0x32, 0xc0, 0x40, 0x32, 0xc5, 0x73, 0x31, 0x72, 0x5a, 0x0f, 0x86, 0x8b, 0x01, 0x00, 0x00, 0x74, 0x47, 0xff, 0x15, 0x7e, 0x72, 0x24, 0x00, 0xc3, 0x48, 0x3d, 0x01, 0xf0, 0xff, 0xff, 0x3d, 0x01, 0xf0, 0xff, 0xff, 0x48, 0x83, 0xf8, 0xff, 0x48, 0x39, 0xc6, 0x48, 0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12, 0x33, 0xc0, 0x48, 0x8d, 0x53, 0x08, 0x31, 0xc9, 0x48, 0x29, 0xc8, 0x48, 0x03, 0x0b, 0x5b, 0x41, 0x5e, 0x48, 0x8d, 0x0c, 0x12, 0xf6, 0xc2, 0x18 ]; fn do_decode_swathe() { // let mut buf = [0u8; 128]; let mut result = yaxpeax_x86::long_mode::Instruction::invalid(); let mut reader = yaxpeax_arch::U8Reader::new(&DECODE_DATA[..]); let decoder = yaxpeax_x86::long_mode::InstDecoder::default(); loop { match decoder.decode_into(&mut result, &mut reader) { Ok(()) => { #[cfg(feature = "capstone_bench")] test::black_box(write!(&mut buf[..], "{}", result)); test::black_box(&result); }, Err(_) => { // println!("done."); break; } } } } #[cfg(feature = "capstone_bench")] extern "C" { pub fn cs_open(arch: u32, mode: u32, handle: *mut usize) -> usize; } #[cfg(feature = "capstone_bench")] extern "C" { pub fn cs_malloc(handle: usize) -> *mut c_void; } #[cfg(feature = "capstone_bench")] extern "C" { pub fn cs_disasm_iter( arch: usize, code: *mut *const u8, size: *mut usize, address: *mut u64, insn: *mut c_void ) -> bool; } #[cfg(feature = "capstone_bench")] fn get_cs_handle() -> usize { let mut handle: usize = 0; let res = unsafe { cs_open(3, 4, &mut handle as *mut usize) }; handle } #[cfg(feature = "capstone_bench")] fn get_instr(handle: usize) -> *mut c_void { unsafe { cs_malloc(handle) as *mut c_void } } #[cfg(feature = "capstone_bench")] fn do_capstone_decode_swathe(cs: usize, instr: *mut c_void) { unsafe { let mut code = &DECODE_DATA as *const u8; let mut len = DECODE_DATA.len(); let mut addr = 0u64; loop { let result = cs_disasm_iter( cs, &mut code as *mut *const u8, &mut len as *mut usize, &mut addr as *mut u64, instr ); //panic!("at least one succeeded"); if result == false { return; } } } } //#[bench] //#[ignore] // VEX prefixes are not supported at the moment, in any form //fn test_avx() { // assert_eq!(&format!("{}", decode( // &[0xc5, 0xf8, 0x10, 0x00] // ).unwrap()), "vmovups xmm0, xmmword [rax]"); //} yaxpeax-x86-1.2.2/test/lib_test.rs000064400000000000000000000002371046102023000150640ustar 00000000000000#[test] fn test_disasm() { let mut instr = Instruction::invalid(); arch::x86_64::instr::decode_one(&[0x33, 0xc0], &mut instr); assert_eq!(1, 1); } yaxpeax-x86-1.2.2/test/long_mode/descriptions.rs000064400000000000000000000334441046102023000177360ustar 00000000000000use std::fmt::Write; use yaxpeax_arch::{AddressBase, LengthedInstruction}; use yaxpeax_arch::annotation::FieldDescription; use yaxpeax_x86::long_mode::Opcode; use yaxpeax_x86::long_mode::RegSpec; use yaxpeax_x86::long_mode::InstDecoder; use yaxpeax_x86::long_mode::Instruction; use yaxpeax_x86::long_mode::InnerDescription; use yaxpeax_arch::annotation::AnnotatingDecoder; fn test_annotations(data: &[u8], expected: &'static str, checks: &[AnnotationCheck]) { test_annotations_under(&InstDecoder::default(), data, expected, checks); } // pair up field descriptions and the check that matched them. we'll use this for // reporting errors if checks don't match up. #[derive(PartialEq, Eq, Copy, Clone)] enum CheckResult { Matched, Failed, Ignored, } impl CheckResult { fn consumed_check(&self) -> bool { *self != CheckResult::Ignored } } struct MatchResult { check: AnnotationCheck, result: CheckResult, } #[derive(Clone)] enum AnnotationCheck { // does not match any description; intended to assert that there should be no extra annotations // after the last check. NoExtra, Exact { // check the reported annotation matches this description desc: InnerDescription, start_bit: u32, end_bit: u32, }, Approximate { check: fn(&InnerDescription) -> bool, start_bit: u32, end_bit: u32, } } impl std::fmt::Display for AnnotationCheck { fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { match self { AnnotationCheck::NoExtra => { write!(f, "no further field descriptions expected") } AnnotationCheck::Exact { desc, start_bit, end_bit } => { write!(f, "bit {}:{}; {}", start_bit, end_bit, desc) } AnnotationCheck::Approximate { start_bit, end_bit, .. } => { write!(f, "bit {}:{}; (fn-based match)", start_bit, end_bit) } } } } impl AnnotationCheck { fn exact(start: u32, end: u32, desc: InnerDescription) -> AnnotationCheck { AnnotationCheck::Exact { desc, start_bit: start, end_bit: end, } } fn approximate(start: u32, end: u32, check: fn(&InnerDescription) -> bool) -> AnnotationCheck { AnnotationCheck::Approximate { check, start_bit: start, end_bit: end, } } fn no_extra() -> AnnotationCheck { AnnotationCheck::NoExtra } fn matches(&self, actual_start: u32, actual_end: u32, actual_desc: InnerDescription) -> CheckResult { match self { AnnotationCheck::NoExtra => { CheckResult::Failed }, AnnotationCheck::Exact { start_bit, end_bit, desc } => { let bits_match = *start_bit == actual_start && *end_bit == actual_end; let desc_match = desc == &actual_desc; let fail_anyway = match (desc, &actual_desc) { // expect that there's only one `Number` field with a given name, so if the // bits are wrong or the value is wrong, that's a guaranteed fail. (InnerDescription::Number(expected_name, _), InnerDescription::Number(actual_name, _)) => { if expected_name == actual_name { true } else { false } } // expect that there's only one opcode field. there won't be a second one that // we might match on later. (InnerDescription::Opcode(_), InnerDescription::Opcode(_)) => { true } (_expected, _actual) => false }; if (!bits_match && !desc_match) && !fail_anyway { return CheckResult::Ignored; } if bits_match && desc_match { CheckResult::Matched } else { CheckResult::Failed } }, AnnotationCheck::Approximate { start_bit, end_bit, check } => { let bits_match = *start_bit == actual_start && *end_bit == actual_end; let desc_match = check(&actual_desc); if !bits_match && !desc_match { return CheckResult::Ignored; } if bits_match && desc_match { CheckResult::Matched } else { CheckResult::Failed } } } } } impl std::fmt::Display for CheckResult { fn fmt(&self, f: &mut std::fmt::Formatter) -> std::fmt::Result { let s = match self { CheckResult::Matched => "\x1b[32mmatched\x1b[0m ", CheckResult::Failed => "\x1b[31mfailed\x1b[0m ", CheckResult::Ignored => "\x1b[33mignored\x1b[0m", }; f.write_str(s) } } fn test_annotations_under(decoder: &InstDecoder, data: &[u8], expected: &'static str, checks: &[AnnotationCheck]) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); let mut sink = yaxpeax_arch::annotation::VecSink::new(); let mut inst = Instruction::default(); match decoder.decode_with_annotation(&mut inst, &mut reader, &mut sink) { Ok(()) => { let text = format!("{}", inst); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, inst, decoder, text, expected ); let mut matches: Vec<((u32, u32, InnerDescription), Option)> = Vec::new(); let mut extra_checks: Vec = Vec::new(); sink.records.sort_by_key(|x| x.2.id()); let mut rec_iter = sink.records.iter(); let mut check_iter = checks.iter(); let mut check = check_iter.next(); let mut failed = false; while let Some((bit_start, bit_end, desc)) = rec_iter.next().cloned() { if let Some(curr_check) = check { if let AnnotationCheck::NoExtra = curr_check { failed = true; } let check_result = curr_check.matches(bit_start, bit_end, desc.desc().clone()); if check_result == CheckResult::Failed { failed = true; } matches.push(((bit_start, bit_end, desc.desc().clone()), Some(MatchResult { check: curr_check.clone(), result: check_result }))); if check_result.consumed_check() { check = check_iter.next(); } } else { // no more checks, so we'll have passed the test at least. continue scooping up // field descriptions into `matches` with no checks. matches.push(((bit_start, bit_end, desc.desc().clone()), None)); } } while let Some(missed_check) = check { check = check_iter.next(); if let AnnotationCheck::NoExtra = missed_check { // "no extra" will be "missed" in that nothing matches it above. in the success // case, it's a leftover check, and should be the only one remaining if the // test is written correctly. so skip it here, and see if we've exhausted the // list of checks.. continue; } extra_checks.push(missed_check.clone()); } if extra_checks.len() > 0 { failed = true; } if failed { eprintln!("[!] annotation check for {}, `{}`, failed:", hex, inst); for ((bit_start, bit_end, desc), check) in matches { let mut desc = format!("bit {}:{}; {}", bit_start, bit_end, desc); while desc.len() < 60 { desc.push(' '); } desc.push(' '); let comment = match check { None => { "\x1b[34mno check\x1b[0m".to_owned() } Some(MatchResult { result, check }) => { if result == CheckResult::Ignored { result.to_string() } else { format!("{}{}", result, check) } } }; eprintln!(" - {}{}", desc, comment); } for check in extra_checks { eprintln!(" ! \x1b[31mextra check\x1b[0m: {}", check); } } assert!(!failed); // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u64.wrapping_offset(inst.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } #[test] fn test_modrm_decode() { test_annotations(&[0xff, 0xc0], "inc eax", &[ AnnotationCheck::exact(11, 13, InnerDescription::Opcode(Opcode::INC)), AnnotationCheck::approximate(0, 7, |desc| { desc.to_string().contains("ModRM_0xff_Ev") }), AnnotationCheck::approximate(14, 15, |desc| { desc.to_string().contains("mmm") && desc.to_string().contains("register number") && desc.to_string().contains("mod bits: 11") }), AnnotationCheck::exact(8, 10, InnerDescription::RegisterNumber("mmm", 0, RegSpec::eax())), AnnotationCheck::no_extra(), ]); test_annotations(&[0xc1, 0xe0, 0x03], "shl eax, 0x3", &[ AnnotationCheck::exact(11, 13, InnerDescription::Opcode(Opcode::SHL)), AnnotationCheck::exact(16, 23, InnerDescription::Number("imm", 3)), AnnotationCheck::approximate(0, 7, |desc| { desc.to_string().contains("ModRM_0xc1_Ev_Ib") }), AnnotationCheck::approximate(14, 15, |desc| { desc.to_string().contains("mmm") && desc.to_string().contains("register number") && desc.to_string().contains("mod bits: 11") }), AnnotationCheck::exact(8, 10, InnerDescription::RegisterNumber("mmm", 0, RegSpec::eax())), AnnotationCheck::no_extra(), ]); test_annotations(&[0x33, 0x08], "xor ecx, dword [rax]", &[ AnnotationCheck::exact(0, 7, InnerDescription::Opcode(Opcode::XOR)), AnnotationCheck::approximate(0, 7, |desc| { desc.to_string() == "operand code `Gv_Ev`" }), AnnotationCheck::approximate(7, 7, |desc| { desc.to_string().contains("operands begin") }), AnnotationCheck::approximate(14, 15, |desc| { desc.to_string().contains("memory operand is [reg]") && desc.to_string().contains("mod bits: 00") }), AnnotationCheck::exact(8, 10, InnerDescription::RegisterNumber("mmm", 0, RegSpec::rax())), AnnotationCheck::exact(11, 13, InnerDescription::RegisterNumber("rrr", 1, RegSpec::ecx())), AnnotationCheck::no_extra(), ]); test_annotations(&[0x66, 0x0f, 0x38, 0x00, 0xc1], "pshufb xmm0, xmm1", &[ AnnotationCheck::exact(0, 7, InnerDescription::Misc("operand size override (to 16 bits)")), AnnotationCheck::approximate(38, 39, |desc| { desc.to_string().contains("mmm") && desc.to_string().contains("register number") && desc.to_string().contains("mod bits: 11") }), AnnotationCheck::exact(32, 34, InnerDescription::RegisterNumber("mmm", 1, RegSpec::ecx())), AnnotationCheck::exact(35, 37, InnerDescription::RegisterNumber("rrr", 0, RegSpec::eax())), AnnotationCheck::no_extra(), ]); // modrm + rex.w test_annotations(&[0x48, 0x33, 0x08], "xor rcx, qword [rax]", &[]); test_annotations(&[0x48, 0x33, 0x20], "xor rsp, qword [rax]", &[]); test_annotations(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor rax, qword [rip + 0x12345678]", &[]); // specifically sib with base == 0b101 // mod bits 00 test_annotations(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]", &[]); test_annotations(&[0x43, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]", &[]); // mod bits 01 test_annotations(&[0x42, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [rbp + r12 * 1 + 0x20]", &[]); test_annotations(&[0x43, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [r13 + r12 * 1 + 0x20]", &[]); // mod bits 10 test_annotations(&[0x42, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [rbp + r12 * 1 + 0x50403020]", &[]); test_annotations(&[0x43, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r13 + r12 * 1 + 0x50403020]", &[]); } yaxpeax-x86-1.2.2/test/long_mode/display.rs000064400000000000000000000227041046102023000166720ustar 00000000000000use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, LengthedInstruction}; use yaxpeax_x86::long_mode::{DisplayStyle, InstDecoder}; fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), DisplayStyle::Intel, data, expected); } fn test_c_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), DisplayStyle::C, data, expected); } fn test_display_under(decoder: &InstDecoder, style: DisplayStyle, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { let text = format!("{}", instr.display_with(style)); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u64.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } } } // decided i do not like at&t syntax much at all. not going to write a formatter for it. some test // cases will live on in case someone else feels like adding one, or i get mad enough to do it. #[allow(unreachable_code)] #[ignore] #[test] fn test_instructions_atnt() { // `ignore` is now used to avoid running (slow!) exhaustive tests in a default `cargo test`. // running exhaustive tests now runs these tests, which fail. so instead, return early. return; // just modrm test_display(&[0x33, 0x08], "xor (%rax), %ecx"); test_display(&[0x33, 0x20], "xor (%rax), %esp"); test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor 0x12345678(%rip), %eax"); test_display(&[0x33, 0x41, 0x23], "xor 0x23(%rcx), %eax"); test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor %0x43650123, %eax"); test_display(&[0x33, 0xc1], "xor %ecx, %eax"); // modrm + rex.w test_display(&[0x48, 0x33, 0x08], "xor (%rax), %rcx"); test_display(&[0x48, 0x33, 0x20], "xor (%rax), %rsp"); test_display(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor 0x12345678(%rip), %rax"); test_display(&[0x48, 0x33, 0x41, 0x23], "xor 0x23(%rcx), %rax"); test_display(&[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor 0x43650123(%rcx), %rax"); test_display(&[0x48, 0x33, 0xc1], "xor %rcx, %rax"); // modrm + rex.r test_display(&[0x44, 0x33, 0x08], "xor (%rax), %r9d"); test_display(&[0x44, 0x33, 0x20], "xor (%rax), %r12d"); test_display(&[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor 0x12345678(%rip), %r8d"); test_display(&[0x44, 0x33, 0x41, 0x23], "xor 0x23(%rcx), %r8d"); test_display(&[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor 0x43650123(%rcx), %r8d"); test_display(&[0x44, 0x33, 0xc1], "xor %ecx, %r8d"); // modrm + rex.rb test_display(&[0x45, 0x33, 0x08], "xor (%r8), %r9d"); test_display(&[0x45, 0x33, 0x20], "xor (%r8), %r12d"); test_display(&[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor 0x12345678(%rip), %r8d"); test_display(&[0x45, 0x33, 0x41, 0x23], "xor 0x23(%r9), %r8d"); test_display(&[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor 0x43650123(%r9), %r8d"); test_display(&[0x45, 0x33, 0xc1], "xor %r9d, %r8d"); // sib test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor (0x44332211), %eax"); test_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor (0x44332211), %eax"); test_display(&[0x41, 0x33, 0x44, 0x65, 0x11], "xor 0x11(%r13), %eax"); test_display(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor 0x50403020(,%r12,1), %esi"); test_display(&[0x4f, 0x0f, 0xe7, 0x03], "movntq %mm0, (%r11)"); test_display(&[0x0f, 0xe7, 0x03], "movntq %mm0, (%rbx)"); test_display(&[0x4f, 0x0f, 0x7f, 0x0f], "movq %mm1, (%r15)"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw $0x14, %eax, %mm0"); test_display(&[0x4f, 0x0f, 0xd1, 0x00], "psrlw (%r8), %mm0"); test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw 0x77ccbbaa(%rip), %mm7"); } #[test] fn test_instructions_c() { // just modrm test_c_display(&[0x33, 0x08], "ecx ^= [rax]"); test_c_display(&[0x33, 0x20], "esp ^= [rax]"); test_c_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "eax ^= [rip + 0x12345678]"); test_c_display(&[0x33, 0x41, 0x23], "eax ^= [rcx + 0x23]"); test_c_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "eax ^= [rcx + 0x43650123]"); test_c_display(&[0x33, 0xc1], "eax ^= ecx"); // modrm + rex.w test_c_display(&[0x48, 0x33, 0x08], "rcx ^= [rax]"); test_c_display(&[0x48, 0x33, 0x20], "rsp ^= [rax]"); test_c_display(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "rax ^= [rip + 0x12345678]"); test_c_display(&[0x48, 0x33, 0x41, 0x23], "rax ^= [rcx + 0x23]"); test_c_display(&[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "rax ^= [rcx + 0x43650123]"); test_c_display(&[0x48, 0x33, 0xc1], "rax ^= rcx"); // modrm + rex.r test_c_display(&[0x44, 0x33, 0x08], "r9d ^= [rax]"); test_c_display(&[0x44, 0x33, 0x20], "r12d ^= [rax]"); test_c_display(&[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "r8d ^= [rip + 0x12345678]"); test_c_display(&[0x44, 0x33, 0x41, 0x23], "r8d ^= [rcx + 0x23]"); test_c_display(&[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "r8d ^= [rcx + 0x43650123]"); test_c_display(&[0x44, 0x33, 0xc1], "r8d ^= ecx"); // modrm + rex.rb test_c_display(&[0x45, 0x33, 0x08], "r9d ^= [r8]"); test_c_display(&[0x45, 0x33, 0x20], "r12d ^= [r8]"); test_c_display(&[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "r8d ^= [rip + 0x12345678]"); test_c_display(&[0x45, 0x33, 0x41, 0x23], "r8d ^= [r9 + 0x23]"); test_c_display(&[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "r8d ^= [r9 + 0x43650123]"); test_c_display(&[0x45, 0x33, 0xc1], "r8d ^= r9d"); // sib test_c_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "eax ^= [0x44332211]"); test_c_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "eax ^= [0x44332211]"); test_c_display(&[0x41, 0x33, 0x44, 0x65, 0x11], "eax ^= [r13 + 0x11]"); test_c_display(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "esi ^= [r12 * 1 + 0x50403020]"); test_c_display(&[0x4f, 0x0f, 0xe7, 0x03], "[r11] = movntq(mm0)"); test_c_display(&[0x0f, 0xe7, 0x03], "[rbx] = movntq(mm0)"); test_c_display(&[0x4f, 0x0f, 0x7f, 0x0f], "[r15] = movq(mm1)"); test_c_display(&[0x0f, 0xc4, 0xc0, 0x14], "mm0 = pinsrw(mm0, eax, 0x14)"); test_c_display(&[0x4f, 0x0f, 0xd1, 0x00], "mm0 = psrlw(mm0, [r8])"); test_c_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "mm7 = pmulhw(mm7, [rip + 0x77ccbbaa])"); test_c_display(&[0xf3, 0x48, 0xa5], "rep qword { es:[rdi++] = ds:[rsi++] }"); test_c_display(&[0xf3, 0xa5], "rep dword { es:[rdi++] = ds:[rsi++] }"); test_c_display(&[0xf3, 0x66, 0xa5], "rep word { es:[rdi++] = ds:[rsi++] }"); test_c_display(&[0xf3, 0xa4], "rep byte { es:[rdi++] = ds:[rsi++] }"); test_c_display(&[0xf6, 0xc2, 0x18], "rflags = flags(dl & 0x18)"); test_c_display(&[0xf6, 0xc2, 0x18], "rflags = flags(dl & 0x18)"); test_c_display(&[0x84, 0xc0], "rflags = flags(al & al)"); test_c_display(&[0x85, 0xc0], "rflags = flags(eax & eax)"); test_c_display(&[0x3a, 0xc0], "rflags = flags(al - al)"); test_c_display(&[0x3b, 0xc0], "rflags = flags(eax - eax)"); test_c_display(&[0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(r11d) (x86 bsf)"); test_c_display(&[0xf3, 0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(r11d)"); // test_c_display(&[0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(r11d) (x86 bsf"); // for non-bm1 test_c_display(&[0x41, 0x0f, 0xbd, 0xd3], "edx = msb(r11d)"); // test_c_display(&[0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(r11d) (x86 bsr"); // for non-bm1 test_c_display(&[0xd2, 0xc0], "al = al rol cl"); test_c_display(&[0xd2, 0xc8], "al = al ror cl"); test_c_display(&[0xd2, 0xd0], "al = al rcl cl"); test_c_display(&[0xd2, 0xd8], "al = al rcr cl"); test_c_display(&[0xd2, 0xe0], "al = al << cl"); test_c_display(&[0xd2, 0xe8], "al = al >> cl"); test_c_display(&[0xd2, 0xf0], "al = al <<< cl"); test_c_display(&[0xd2, 0xf8], "al = al >>> cl"); test_c_display(&[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], "eax = [r9] ror 0x5 (x86 rorx)"); test_c_display(&[0xc4, 0xc2, 0xe3, 0xf7, 0x01], "rax = [r9] >> rbx (x86 shrx)"); test_c_display(&[0xc4, 0xc2, 0xe1, 0xf7, 0x01], "rax = [r9] << rbx (x86 shlx)"); test_c_display(&[0xd2, 0xe0], "al = al << cl"); test_c_display(&[0x66, 0x0f, 0xac, 0xcf, 0x11], "di = shrd(di, cx, 0x11)"); test_c_display(&[0x0f, 0xa5, 0xc9], "ecx = shld(ecx, ecx, cl)"); test_c_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "eax += [rcx] + rflags.cf"); test_c_display(&[0xf3, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "r8 += [r9] + rflags.of"); test_c_display(&[0xfe, 0x00], "byte [rax]++"); test_c_display(&[0x66, 0xff, 0x08], "word [rax]--"); test_c_display(&[0xff, 0x00], "dword [rax]++"); test_c_display(&[0x48, 0xff, 0x00], "qword [rax]++"); test_c_display(&[0xff, 0xe0], "jmp rax"); } yaxpeax-x86-1.2.2/test/long_mode/evex_generated.rs000064400000000000000000067453651046102023000202370ustar 00000000000000use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, U8Reader, LengthedInstruction}; use yaxpeax_x86::long_mode::InstDecoder; #[allow(dead_code)] fn test_invalid(data: &[u8]) { test_invalid_under(&InstDecoder::default(), data); } fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) { let mut reader = U8Reader::new(data); if let Ok(inst) = decoder.decode(&mut reader) { // realistically, the chances an error only shows up under non-fmt builds seems unlikely, // but try to report *something* in such cases. cfg_if::cfg_if! { if #[cfg(feature="fmt")] { panic!("decoded {:?} from {:02x?} under decoder {}", inst.opcode(), data, decoder); } else { // don't warn about the unused inst here let _ = inst; panic!("decoded instruction from {:02x?} under decoder ", data); } } } else { // this is fine } } #[allow(dead_code)] fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), data, expected); } fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { let text = format!("{}", instr); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); } else { eprintln!("non-fmt build cannot compare text equality") } } // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u64.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } fn test_avx_full(bytes: &[u8], text: &'static str) { // test with a hypothetical CPU that supports all of AVX512. at time of writing, no such CPU // exists. test_display_under(&InstDecoder::minimal().with_avx512(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } #[allow(non_snake_case)] #[test] fn tests_None_0f() { test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0xca], "vmovups ymm1{k5}{z}, ymm2"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0x0a], "vmovups ymm1{k5}{z}, ymmword [rdx]"); // VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0xca], "vmovups ymm1, ymm2"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0xca], "vmovups ymm1{k5}, ymm2"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0x0a], "vmovups ymm1, ymmword [rdx]"); // VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0x0a], "vmovups ymm1{k5}, ymmword [rdx]"); // VMOVUPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0xca], "vmovups zmm1{k5}{z}, zmm2"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0x0a], "vmovups zmm1{k5}{z}, zmmword [rdx]"); // VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0xca], "vmovups zmm1, zmm2"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0xca], "vmovups zmm1{k5}, zmm2"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0x0a], "vmovups zmm1, zmmword [rdx]"); // VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0x0a], "vmovups zmm1{k5}, zmmword [rdx]"); // VMOVUPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0xca], "vmovups xmm1{k5}{z}, xmm2"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0x0a], "vmovups xmm1{k5}{z}, xmmword [rdx]"); // VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0xca], "vmovups xmm1, xmm2"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0xca], "vmovups xmm1{k5}, xmm2"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0x0a], "vmovups xmm1, xmmword [rdx]"); // VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0x0a], "vmovups xmm1{k5}, xmmword [rdx]"); // VMOVUPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x11, 0xca], "vmovups ymm2{k5}{z}, ymm1"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0xca], "vmovups ymm2, ymm1"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0xca], "vmovups ymm2{k5}, ymm1"); // VMOVUPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0x0a], "vmovups ymmword [rdx], ymm1"); // VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0x0a], "vmovups ymmword [rdx]{k5}, ymm1"); // VMOVUPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x11, 0xca], "vmovups zmm2{k5}{z}, zmm1"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0xca], "vmovups zmm2, zmm1"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0xca], "vmovups zmm2{k5}, zmm1"); // VMOVUPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0x0a], "vmovups zmmword [rdx], zmm1"); // VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0x0a], "vmovups zmmword [rdx]{k5}, zmm1"); // VMOVUPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0xca], "vmovups xmm2{k5}{z}, xmm1"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0xca], "vmovups xmm2, xmm1"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0xca], "vmovups xmm2{k5}, xmm1"); // VMOVUPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x0a], "vmovups xmmword [rdx], xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [rdx]{k5}, xmm1"); // VMOVUPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); // VMOVHLPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [rdx]"); // VMOVLPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [rdx], xmm1"); // VMOVLPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x14, 0x0a], "vunpcklps ymm1, ymm0, dword [rdx]{1to8}"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0xca], "vunpcklps ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0xca], "vunpcklps ymm1, ymm0, ymm2"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0xca], "vunpcklps ymm1{k5}, ymm0, ymm2"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0x0a], "vunpcklps ymm1, ymm0, ymmword [rdx]"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, ymmword [rdx]"); // VUNPCKLPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x14, 0x0a], "vunpcklps zmm1, zmm0, dword [rdx]{1to16}"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x14, 0x0a], "vunpcklps xmm1, xmm0, dword [rdx]{1to4}"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0xca], "vunpcklps zmm1{k5}{z}, zmm0, zmm2"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0xca], "vunpcklps zmm1, zmm0, zmm2"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0xca], "vunpcklps zmm1{k5}, zmm0, zmm2"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0x0a], "vunpcklps zmm1, zmm0, zmmword [rdx]"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, zmmword [rdx]"); // VUNPCKLPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0xca], "vunpcklps xmm1{k5}{z}, xmm0, xmm2"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0xca], "vunpcklps xmm1, xmm0, xmm2"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0xca], "vunpcklps xmm1{k5}, xmm0, xmm2"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0x0a], "vunpcklps xmm1, xmm0, xmmword [rdx]"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKLPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x15, 0x0a], "vunpckhps ymm1, ymm0, dword [rdx]{1to8}"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0xca], "vunpckhps ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0xca], "vunpckhps ymm1, ymm0, ymm2"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0xca], "vunpckhps ymm1{k5}, ymm0, ymm2"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0x0a], "vunpckhps ymm1, ymm0, ymmword [rdx]"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, ymmword [rdx]"); // VUNPCKHPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x15, 0x0a], "vunpckhps zmm1, zmm0, dword [rdx]{1to16}"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x15, 0x0a], "vunpckhps xmm1, xmm0, dword [rdx]{1to4}"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0xca], "vunpckhps zmm1{k5}{z}, zmm0, zmm2"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0xca], "vunpckhps zmm1, zmm0, zmm2"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0xca], "vunpckhps zmm1{k5}, zmm0, zmm2"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0x0a], "vunpckhps zmm1, zmm0, zmmword [rdx]"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, zmmword [rdx]"); // VUNPCKHPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0xca], "vunpckhps xmm1{k5}{z}, xmm0, xmm2"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0xca], "vunpckhps xmm1, xmm0, xmm2"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0xca], "vunpckhps xmm1{k5}, xmm0, xmm2"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKHPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2"); // VMOVLHPS_XMMf32_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [rdx]"); // VMOVHPS_XMMf32_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [rdx], xmm1"); // VMOVHPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x0a], "vmovaps ymm1, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0x0a], "vmovaps ymm1{k5}, ymmword [rdx]"); // VMOVAPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0xca], "vmovaps zmm1{k5}{z}, zmm2"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0x0a], "vmovaps zmm1{k5}{z}, zmmword [rdx]"); // VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0xca], "vmovaps zmm1, zmm2"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0xca], "vmovaps zmm1{k5}, zmm2"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0x0a], "vmovaps zmm1, zmmword [rdx]"); // VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x0a], "vmovaps zmm1{k5}, zmmword [rdx]"); // VMOVAPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0xca], "vmovaps xmm1{k5}{z}, xmm2"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x0a], "vmovaps xmm1{k5}{z}, xmmword [rdx]"); // VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0xca], "vmovaps xmm1, xmm2"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0xca], "vmovaps xmm1{k5}, xmm2"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0x0a], "vmovaps xmm1, xmmword [rdx]"); // VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0x0a], "vmovaps xmm1{k5}, xmmword [rdx]"); // VMOVAPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x29, 0xca], "vmovaps ymm2{k5}{z}, ymm1"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0xca], "vmovaps ymm2, ymm1"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0xca], "vmovaps ymm2{k5}, ymm1"); // VMOVAPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0x0a], "vmovaps ymmword [rdx], ymm1"); // VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0x0a], "vmovaps ymmword [rdx]{k5}, ymm1"); // VMOVAPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x29, 0xca], "vmovaps zmm2{k5}{z}, zmm1"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0xca], "vmovaps zmm2, zmm1"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0xca], "vmovaps zmm2{k5}, zmm1"); // VMOVAPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x0a], "vmovaps zmmword [rdx], zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x0a], "vmovaps zmmword [rdx]{k5}, zmm1"); // VMOVAPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x29, 0xca], "vmovaps xmm2{k5}{z}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0xca], "vmovaps xmm2, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0xca], "vmovaps xmm2{k5}, xmm1"); // VMOVAPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x0a], "vmovaps xmmword [rdx], xmm1"); // VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0x0a], "vmovaps xmmword [rdx]{k5}, xmm1"); // VMOVAPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x0a], "vmovntps ymmword [rdx], ymm1"); // VMOVNTPS_MEMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x0a], "vmovntps zmmword [rdx], zmm1"); // VMOVNTPS_MEMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [rdx], xmm1"); // VMOVNTPS_MEMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2"); // VUCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [rdx]"); // VUCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); // VCOMISS_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [rdx]"); // VCOMISS_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, dword [rdx]{1to8}"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0xca], "vsqrtps zmm1{rd-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0xca], "vsqrtps zmm1{k5}{rd-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0x0a], "vsqrtps ymm1, dword [rdx]{1to8}"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0x0a], "vsqrtps ymm1{k5}, dword [rdx]{1to8}"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0xca], "vsqrtps ymm1{k5}{z}, ymm2"); // VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, ymmword [rdx]"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0xca], "vsqrtps ymm1, ymm2"); // VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0xca], "vsqrtps ymm1{k5}, ymm2"); // VSQRTPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0x0a], "vsqrtps ymm1, ymmword [rdx]"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0x0a], "vsqrtps ymm1{k5}, ymmword [rdx]"); // VSQRTPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{ru-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, dword [rdx]{1to16}"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0xca], "vsqrtps zmm1{ru-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0xca], "vsqrtps zmm1{k5}{ru-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0x0a], "vsqrtps zmm1, dword [rdx]{1to16}"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0x0a], "vsqrtps zmm1{k5}, dword [rdx]{1to16}"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rne-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, dword [rdx]{1to4}"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0xca], "vsqrtps zmm1{rne-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0xca], "vsqrtps zmm1{k5}{rne-sae}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0x0a], "vsqrtps xmm1, dword [rdx]{1to4}"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0x0a], "vsqrtps xmm1{k5}, dword [rdx]{1to4}"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, zmmword [rdx]"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0xca], "vsqrtps zmm1, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0xca], "vsqrtps zmm1{k5}, zmm2"); // VSQRTPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0x0a], "vsqrtps zmm1, zmmword [rdx]"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0x0a], "vsqrtps zmm1{k5}, zmmword [rdx]"); // VSQRTPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0xca], "vsqrtps xmm1{k5}{z}, xmm2"); // VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, xmmword [rdx]"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0xca], "vsqrtps xmm1, xmm2"); // VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0xca], "vsqrtps xmm1{k5}, xmm2"); // VSQRTPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0x0a], "vsqrtps xmm1, xmmword [rdx]"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0x0a], "vsqrtps xmm1{k5}, xmmword [rdx]"); // VSQRTPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x54, 0x0a], "vandps ymm1, ymm0, dword [rdx]{1to8}"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0xca], "vandps ymm1{k5}{z}, ymm0, ymm2"); // VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0xca], "vandps ymm1, ymm0, ymm2"); // VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0xca], "vandps ymm1{k5}, ymm0, ymm2"); // VANDPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0x0a], "vandps ymm1, ymm0, ymmword [rdx]"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, ymmword [rdx]"); // VANDPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x54, 0x0a], "vandps zmm1, zmm0, dword [rdx]{1to16}"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x54, 0x0a], "vandps xmm1, xmm0, dword [rdx]{1to4}"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0xca], "vandps zmm1{k5}{z}, zmm0, zmm2"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0xca], "vandps zmm1, zmm0, zmm2"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0xca], "vandps zmm1{k5}, zmm0, zmm2"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0x0a], "vandps zmm1, zmm0, zmmword [rdx]"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, zmmword [rdx]"); // VANDPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0xca], "vandps xmm1{k5}{z}, xmm0, xmm2"); // VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0xca], "vandps xmm1, xmm0, xmm2"); // VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0xca], "vandps xmm1{k5}, xmm0, xmm2"); // VANDPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0x0a], "vandps xmm1, xmm0, xmmword [rdx]"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, xmmword [rdx]"); // VANDPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x55, 0x0a], "vandnps ymm1, ymm0, dword [rdx]{1to8}"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0xca], "vandnps ymm1{k5}{z}, ymm0, ymm2"); // VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0xca], "vandnps ymm1, ymm0, ymm2"); // VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0xca], "vandnps ymm1{k5}, ymm0, ymm2"); // VANDNPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0x0a], "vandnps ymm1, ymm0, ymmword [rdx]"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, ymmword [rdx]"); // VANDNPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x55, 0x0a], "vandnps zmm1, zmm0, dword [rdx]{1to16}"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x55, 0x0a], "vandnps xmm1, xmm0, dword [rdx]{1to4}"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0xca], "vandnps zmm1{k5}{z}, zmm0, zmm2"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0xca], "vandnps zmm1, zmm0, zmm2"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0xca], "vandnps zmm1{k5}, zmm0, zmm2"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0x0a], "vandnps zmm1, zmm0, zmmword [rdx]"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, zmmword [rdx]"); // VANDNPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0xca], "vandnps xmm1{k5}{z}, xmm0, xmm2"); // VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0xca], "vandnps xmm1, xmm0, xmm2"); // VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0xca], "vandnps xmm1{k5}, xmm0, xmm2"); // VANDNPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0x0a], "vandnps xmm1, xmm0, xmmword [rdx]"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, xmmword [rdx]"); // VANDNPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x56, 0x0a], "vorps ymm1, ymm0, dword [rdx]{1to8}"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0xca], "vorps ymm1{k5}{z}, ymm0, ymm2"); // VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0xca], "vorps ymm1, ymm0, ymm2"); // VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0xca], "vorps ymm1{k5}, ymm0, ymm2"); // VORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0x0a], "vorps ymm1, ymm0, ymmword [rdx]"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, ymmword [rdx]"); // VORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x56, 0x0a], "vorps zmm1, zmm0, dword [rdx]{1to16}"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x56, 0x0a], "vorps xmm1, xmm0, dword [rdx]{1to4}"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0xca], "vorps zmm1{k5}{z}, zmm0, zmm2"); // VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0xca], "vorps zmm1, zmm0, zmm2"); // VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0xca], "vorps zmm1{k5}, zmm0, zmm2"); // VORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0x0a], "vorps zmm1, zmm0, zmmword [rdx]"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, zmmword [rdx]"); // VORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0xca], "vorps xmm1{k5}{z}, xmm0, xmm2"); // VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0xca], "vorps xmm1, xmm0, xmm2"); // VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0xca], "vorps xmm1{k5}, xmm0, xmm2"); // VORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0x0a], "vorps xmm1, xmm0, xmmword [rdx]"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, xmmword [rdx]"); // VORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x57, 0x0a], "vxorps ymm1, ymm0, dword [rdx]{1to8}"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0xca], "vxorps ymm1{k5}{z}, ymm0, ymm2"); // VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0xca], "vxorps ymm1, ymm0, ymm2"); // VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0xca], "vxorps ymm1{k5}, ymm0, ymm2"); // VXORPS_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0x0a], "vxorps ymm1, ymm0, ymmword [rdx]"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, ymmword [rdx]"); // VXORPS_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x57, 0x0a], "vxorps zmm1, zmm0, dword [rdx]{1to16}"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x57, 0x0a], "vxorps xmm1, xmm0, dword [rdx]{1to4}"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0xca], "vxorps zmm1{k5}{z}, zmm0, zmm2"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0xca], "vxorps zmm1, zmm0, zmm2"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0xca], "vxorps zmm1{k5}, zmm0, zmm2"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0x0a], "vxorps zmm1, zmm0, zmmword [rdx]"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, zmmword [rdx]"); // VXORPS_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0xca], "vxorps xmm1{k5}{z}, xmm0, xmm2"); // VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0xca], "vxorps xmm1, xmm0, xmm2"); // VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0xca], "vxorps xmm1{k5}, xmm0, xmm2"); // VXORPS_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0x0a], "vxorps xmm1, xmm0, xmmword [rdx]"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, xmmword [rdx]"); // VXORPS_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x58, 0xca], "vaddps zmm1{rz-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x58, 0xca], "vaddps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0xca], "vaddps zmm1{rd-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0xca], "vaddps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0x0a], "vaddps ymm1, ymm0, dword [rdx]{1to8}"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0xca], "vaddps ymm1{k5}{z}, ymm0, ymm2"); // VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0xca], "vaddps ymm1, ymm0, ymm2"); // VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0xca], "vaddps ymm1{k5}, ymm0, ymm2"); // VADDPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0x0a], "vaddps ymm1, ymm0, ymmword [rdx]"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, ymmword [rdx]"); // VADDPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0xca], "vaddps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0xca], "vaddps zmm1{ru-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0xca], "vaddps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0x0a], "vaddps zmm1, zmm0, dword [rdx]{1to16}"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0xca], "vaddps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0xca], "vaddps zmm1{rne-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0xca], "vaddps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0x0a], "vaddps xmm1, xmm0, dword [rdx]{1to4}"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0xca], "vaddps zmm1{k5}{z}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0xca], "vaddps zmm1, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0xca], "vaddps zmm1{k5}, zmm0, zmm2"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0x0a], "vaddps zmm1, zmm0, zmmword [rdx]"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, zmmword [rdx]"); // VADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0xca], "vaddps xmm1{k5}{z}, xmm0, xmm2"); // VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0xca], "vaddps xmm1, xmm0, xmm2"); // VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0xca], "vaddps xmm1{k5}, xmm0, xmm2"); // VADDPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0x0a], "vaddps xmm1, xmm0, xmmword [rdx]"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, xmmword [rdx]"); // VADDPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x59, 0xca], "vmulps zmm1{rz-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x59, 0xca], "vmulps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0xca], "vmulps zmm1{rd-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0xca], "vmulps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0x0a], "vmulps ymm1, ymm0, dword [rdx]{1to8}"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0xca], "vmulps ymm1{k5}{z}, ymm0, ymm2"); // VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0xca], "vmulps ymm1, ymm0, ymm2"); // VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0xca], "vmulps ymm1{k5}, ymm0, ymm2"); // VMULPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0x0a], "vmulps ymm1, ymm0, ymmword [rdx]"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, ymmword [rdx]"); // VMULPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0xca], "vmulps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0xca], "vmulps zmm1{ru-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0xca], "vmulps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0x0a], "vmulps zmm1, zmm0, dword [rdx]{1to16}"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0xca], "vmulps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0xca], "vmulps zmm1{rne-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0xca], "vmulps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0x0a], "vmulps xmm1, xmm0, dword [rdx]{1to4}"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0xca], "vmulps zmm1{k5}{z}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0xca], "vmulps zmm1, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0xca], "vmulps zmm1{k5}, zmm0, zmm2"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0x0a], "vmulps zmm1, zmm0, zmmword [rdx]"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, zmmword [rdx]"); // VMULPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0xca], "vmulps xmm1{k5}{z}, xmm0, xmm2"); // VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0xca], "vmulps xmm1, xmm0, xmm2"); // VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0xca], "vmulps xmm1{k5}, xmm0, xmm2"); // VMULPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0x0a], "vmulps xmm1, xmm0, xmmword [rdx]"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, xmmword [rdx]"); // VMULPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x0a], "vcvtps2pd ymm1, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, dword [rdx]{1to4}"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0xca], "vcvtps2pd ymm1{k5}{z}, xmm2"); // VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, xmmword [rdx]"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0xca], "vcvtps2pd ymm1, xmm2"); // VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0xca], "vcvtps2pd ymm1{k5}, xmm2"); // VCVTPS2PD_YMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0x0a], "vcvtps2pd ymm1, xmmword [rdx]"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, xmmword [rdx]"); // VCVTPS2PD_YMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5a, 0x0a], "vcvtps2pd zmm1, dword [rdx]{1to8}"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, dword [rdx]{1to8}"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5a, 0x0a], "vcvtps2pd xmm1, dword [rdx]{1to2}"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, dword [rdx]{1to2}"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, ymmword [rdx]"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0xca], "vcvtps2pd zmm1, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}, ymm2"); // VCVTPS2PD_ZMMf64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0x0a], "vcvtps2pd zmm1, ymmword [rdx]"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, ymmword [rdx]"); // VCVTPS2PD_ZMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}{z}, xmm2"); // VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, qword [rdx]"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0xca], "vcvtps2pd xmm1, xmm2"); // VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}, xmm2"); // VCVTPS2PD_XMMf64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0x0a], "vcvtps2pd xmm1, qword [rdx]"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, qword [rdx]"); // VCVTPS2PD_XMMf64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x5b, 0xca], "vcvtqq2ps ymm1{rz-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rz-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0xca], "vcvtqq2ps ymm1{rd-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rd-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [rdx]{1to4}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [rdx]{1to4}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, ymm2"); // VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, ymmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0xca], "vcvtqq2ps xmm1, ymm2"); // VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, ymm2"); // VCVTQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0x0a], "vcvtqq2ps xmm1, ymmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, ymmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5b, 0xca], "vcvtdq2ps zmm1{rz-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rz-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0xca], "vcvtdq2ps zmm1{rd-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rd-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0x0a], "vcvtdq2ps ymm1, dword [rdx]{1to8}"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, dword [rdx]{1to8}"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}{z}, ymm2"); // VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, ymmword [rdx]"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0xca], "vcvtdq2ps ymm1, ymm2"); // VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}, ymm2"); // VCVTDQ2PS_YMMf32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0x0a], "vcvtdq2ps ymm1, ymmword [rdx]"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, ymmword [rdx]"); // VCVTDQ2PS_YMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0xca], "vcvtqq2ps ymm1{ru-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{ru-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0x0a], "vcvtqq2ps ymm1, qword [rdx]{1to8}"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, qword [rdx]{1to8}"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0xca], "vcvtqq2ps ymm1{rne-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rne-sae}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [rdx]{1to2}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [rdx]{1to2}"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, zmmword [rdx]"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0xca], "vcvtqq2ps ymm1, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}, zmm2"); // VCVTQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0x0a], "vcvtqq2ps ymm1, zmmword [rdx]"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, zmmword [rdx]"); // VCVTQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, xmm2"); // VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, xmmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0xca], "vcvtqq2ps xmm1, xmm2"); // VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, xmm2"); // VCVTQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0x0a], "vcvtqq2ps xmm1, xmmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, xmmword [rdx]"); // VCVTQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0xca], "vcvtdq2ps zmm1{ru-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{ru-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0x0a], "vcvtdq2ps zmm1, dword [rdx]{1to16}"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, dword [rdx]{1to16}"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0xca], "vcvtdq2ps zmm1{rne-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rne-sae}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0x0a], "vcvtdq2ps xmm1, dword [rdx]{1to4}"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, dword [rdx]{1to4}"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, zmmword [rdx]"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0xca], "vcvtdq2ps zmm1, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}, zmm2"); // VCVTDQ2PS_ZMMf32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0x0a], "vcvtdq2ps zmm1, zmmword [rdx]"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, zmmword [rdx]"); // VCVTDQ2PS_ZMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}{z}, xmm2"); // VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, xmmword [rdx]"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0xca], "vcvtdq2ps xmm1, xmm2"); // VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}, xmm2"); // VCVTDQ2PS_XMMf32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0x0a], "vcvtdq2ps xmm1, xmmword [rdx]"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, xmmword [rdx]"); // VCVTDQ2PS_XMMf32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5c, 0xca], "vsubps zmm1{rz-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5c, 0xca], "vsubps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0xca], "vsubps zmm1{rd-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0xca], "vsubps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0x0a], "vsubps ymm1, ymm0, dword [rdx]{1to8}"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0xca], "vsubps ymm1{k5}{z}, ymm0, ymm2"); // VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0xca], "vsubps ymm1, ymm0, ymm2"); // VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0xca], "vsubps ymm1{k5}, ymm0, ymm2"); // VSUBPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0x0a], "vsubps ymm1, ymm0, ymmword [rdx]"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, ymmword [rdx]"); // VSUBPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0xca], "vsubps zmm1{ru-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0xca], "vsubps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0x0a], "vsubps zmm1, zmm0, dword [rdx]{1to16}"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0xca], "vsubps zmm1{rne-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0xca], "vsubps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0x0a], "vsubps xmm1, xmm0, dword [rdx]{1to4}"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0xca], "vsubps zmm1{k5}{z}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0xca], "vsubps zmm1, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0xca], "vsubps zmm1{k5}, zmm0, zmm2"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0x0a], "vsubps zmm1, zmm0, zmmword [rdx]"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, zmmword [rdx]"); // VSUBPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0xca], "vsubps xmm1{k5}{z}, xmm0, xmm2"); // VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0xca], "vsubps xmm1, xmm0, xmm2"); // VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0xca], "vsubps xmm1{k5}, xmm0, xmm2"); // VSUBPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0x0a], "vsubps xmm1, xmm0, xmmword [rdx]"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, xmmword [rdx]"); // VSUBPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5d, 0xca], "vminps zmm1{k5}{z}{sae}, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5d, 0xca], "vminps zmm1{sae}, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5d, 0xca], "vminps zmm1{k5}{sae}, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5d, 0x0a], "vminps ymm1, ymm0, dword [rdx]{1to8}"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0xca], "vminps ymm1{k5}{z}, ymm0, ymm2"); // VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0xca], "vminps ymm1, ymm0, ymm2"); // VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0xca], "vminps ymm1{k5}, ymm0, ymm2"); // VMINPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0x0a], "vminps ymm1, ymm0, ymmword [rdx]"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, ymmword [rdx]"); // VMINPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5d, 0x0a], "vminps zmm1, zmm0, dword [rdx]{1to16}"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5d, 0x0a], "vminps xmm1, xmm0, dword [rdx]{1to4}"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0xca], "vminps zmm1{k5}{z}, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0xca], "vminps zmm1, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0xca], "vminps zmm1{k5}, zmm0, zmm2"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0x0a], "vminps zmm1, zmm0, zmmword [rdx]"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, zmmword [rdx]"); // VMINPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0xca], "vminps xmm1{k5}{z}, xmm0, xmm2"); // VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0xca], "vminps xmm1, xmm0, xmm2"); // VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0xca], "vminps xmm1{k5}, xmm0, xmm2"); // VMINPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0x0a], "vminps xmm1, xmm0, xmmword [rdx]"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, xmmword [rdx]"); // VMINPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5e, 0xca], "vdivps zmm1{rz-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5e, 0xca], "vdivps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0xca], "vdivps zmm1{rd-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0xca], "vdivps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0x0a], "vdivps ymm1, ymm0, dword [rdx]{1to8}"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0xca], "vdivps ymm1{k5}{z}, ymm0, ymm2"); // VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0xca], "vdivps ymm1, ymm0, ymm2"); // VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0xca], "vdivps ymm1{k5}, ymm0, ymm2"); // VDIVPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0x0a], "vdivps ymm1, ymm0, ymmword [rdx]"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, ymmword [rdx]"); // VDIVPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0xca], "vdivps zmm1{ru-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0xca], "vdivps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0x0a], "vdivps zmm1, zmm0, dword [rdx]{1to16}"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0xca], "vdivps zmm1{rne-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0xca], "vdivps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0x0a], "vdivps xmm1, xmm0, dword [rdx]{1to4}"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0xca], "vdivps zmm1{k5}{z}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0xca], "vdivps zmm1, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0xca], "vdivps zmm1{k5}, zmm0, zmm2"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0x0a], "vdivps zmm1, zmm0, zmmword [rdx]"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, zmmword [rdx]"); // VDIVPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0xca], "vdivps xmm1{k5}{z}, xmm0, xmm2"); // VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0xca], "vdivps xmm1, xmm0, xmm2"); // VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0xca], "vdivps xmm1{k5}, xmm0, xmm2"); // VDIVPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0x0a], "vdivps xmm1, xmm0, xmmword [rdx]"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, xmmword [rdx]"); // VDIVPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}{sae}, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5f, 0xca], "vmaxps zmm1{sae}, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5f, 0xca], "vmaxps zmm1{k5}{sae}, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5f, 0x0a], "vmaxps ymm1, ymm0, dword [rdx]{1to8}"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0xca], "vmaxps ymm1{k5}{z}, ymm0, ymm2"); // VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0xca], "vmaxps ymm1, ymm0, ymm2"); // VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0xca], "vmaxps ymm1{k5}, ymm0, ymm2"); // VMAXPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0x0a], "vmaxps ymm1, ymm0, ymmword [rdx]"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, ymmword [rdx]"); // VMAXPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5f, 0x0a], "vmaxps zmm1, zmm0, dword [rdx]{1to16}"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5f, 0x0a], "vmaxps xmm1, xmm0, dword [rdx]{1to4}"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0xca], "vmaxps zmm1, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0xca], "vmaxps zmm1{k5}, zmm0, zmm2"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0x0a], "vmaxps zmm1, zmm0, zmmword [rdx]"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, zmmword [rdx]"); // VMAXPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0xca], "vmaxps xmm1{k5}{z}, xmm0, xmm2"); // VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0xca], "vmaxps xmm1, xmm0, xmm2"); // VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0xca], "vmaxps xmm1{k5}, xmm0, xmm2"); // VMAXPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0x0a], "vmaxps xmm1, xmm0, xmmword [rdx]"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, xmmword [rdx]"); // VMAXPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}{sae}, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x78, 0xca], "vcvttpd2udq ymm1{sae}, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{sae}, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [rdx]{1to4}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [rdx]{1to4}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, ymm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, ymmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0xca], "vcvttpd2udq xmm1, ymm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, ymm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0x0a], "vcvttpd2udq xmm1, ymmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, ymmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}{sae}, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x78, 0xca], "vcvttps2udq zmm1{sae}, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x78, 0xca], "vcvttps2udq zmm1{k5}{sae}, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x78, 0x0a], "vcvttps2udq ymm1, dword [rdx]{1to8}"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, dword [rdx]{1to8}"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0xca], "vcvttps2udq ymm1{k5}{z}, ymm2"); // VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, ymmword [rdx]"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0xca], "vcvttps2udq ymm1, ymm2"); // VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0xca], "vcvttps2udq ymm1{k5}, ymm2"); // VCVTTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0x0a], "vcvttps2udq ymm1, ymmword [rdx]"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, ymmword [rdx]"); // VCVTTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x78, 0x0a], "vcvttpd2udq ymm1, qword [rdx]{1to8}"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, qword [rdx]{1to8}"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [rdx]{1to2}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [rdx]{1to2}"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, zmmword [rdx]"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0xca], "vcvttpd2udq ymm1, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}, zmm2"); // VCVTTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0x0a], "vcvttpd2udq ymm1, zmmword [rdx]"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, zmmword [rdx]"); // VCVTTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, xmm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0xca], "vcvttpd2udq xmm1, xmm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, xmm2"); // VCVTTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0x0a], "vcvttpd2udq xmm1, xmmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, xmmword [rdx]"); // VCVTTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x78, 0x0a], "vcvttps2udq zmm1, dword [rdx]{1to16}"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, dword [rdx]{1to16}"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x78, 0x0a], "vcvttps2udq xmm1, dword [rdx]{1to4}"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, dword [rdx]{1to4}"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, zmmword [rdx]"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0xca], "vcvttps2udq zmm1, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0xca], "vcvttps2udq zmm1{k5}, zmm2"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0x0a], "vcvttps2udq zmm1, zmmword [rdx]"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, zmmword [rdx]"); // VCVTTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0xca], "vcvttps2udq xmm1{k5}{z}, xmm2"); // VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0xca], "vcvttps2udq xmm1, xmm2"); // VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0xca], "vcvttps2udq xmm1{k5}, xmm2"); // VCVTTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0x0a], "vcvttps2udq xmm1, xmmword [rdx]"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, xmmword [rdx]"); // VCVTTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x79, 0xca], "vcvtpd2udq ymm1{rz-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rz-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rd-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0xca], "vcvtpd2udq ymm1{rd-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rd-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [rdx]{1to4}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [rdx]{1to4}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, ymm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, ymmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0xca], "vcvtpd2udq xmm1, ymm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, ymm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0x0a], "vcvtpd2udq xmm1, ymmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, ymmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x79, 0xca], "vcvtps2udq zmm1{rz-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rz-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0xca], "vcvtps2udq zmm1{rd-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rd-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0x0a], "vcvtps2udq ymm1, dword [rdx]{1to8}"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, dword [rdx]{1to8}"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0xca], "vcvtps2udq ymm1{k5}{z}, ymm2"); // VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0xca], "vcvtps2udq ymm1, ymm2"); // VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0xca], "vcvtps2udq ymm1{k5}, ymm2"); // VCVTPS2UDQ_YMMu32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0x0a], "vcvtps2udq ymm1, ymmword [rdx]"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, ymmword [rdx]"); // VCVTPS2UDQ_YMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{ru-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0xca], "vcvtpd2udq ymm1{ru-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{ru-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0x0a], "vcvtpd2udq ymm1, qword [rdx]{1to8}"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, qword [rdx]{1to8}"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rne-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0xca], "vcvtpd2udq ymm1{rne-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rne-sae}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [rdx]{1to2}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [rdx]{1to2}"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, zmmword [rdx]"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0xca], "vcvtpd2udq ymm1, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}, zmm2"); // VCVTPD2UDQ_YMMu32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0x0a], "vcvtpd2udq ymm1, zmmword [rdx]"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, zmmword [rdx]"); // VCVTPD2UDQ_YMMu32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, xmm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0xca], "vcvtpd2udq xmm1, xmm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, xmm2"); // VCVTPD2UDQ_XMMu32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0x0a], "vcvtpd2udq xmm1, xmmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, xmmword [rdx]"); // VCVTPD2UDQ_XMMu32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0xca], "vcvtps2udq zmm1{ru-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{ru-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0x0a], "vcvtps2udq zmm1, dword [rdx]{1to16}"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, dword [rdx]{1to16}"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0xca], "vcvtps2udq zmm1{rne-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rne-sae}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0x0a], "vcvtps2udq xmm1, dword [rdx]{1to4}"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, dword [rdx]{1to4}"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, zmmword [rdx]"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0xca], "vcvtps2udq zmm1, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0xca], "vcvtps2udq zmm1{k5}, zmm2"); // VCVTPS2UDQ_ZMMu32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0x0a], "vcvtps2udq zmm1, zmmword [rdx]"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, zmmword [rdx]"); // VCVTPS2UDQ_ZMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0xca], "vcvtps2udq xmm1{k5}{z}, xmm2"); // VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0xca], "vcvtps2udq xmm1, xmm2"); // VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0xca], "vcvtps2udq xmm1{k5}, xmm2"); // VCVTPS2UDQ_XMMu32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0x0a], "vcvtps2udq xmm1, xmmword [rdx]"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, xmmword [rdx]"); // VCVTPS2UDQ_XMMu32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0xca, 0xcc], "vcmpps k1, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, ymmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, dword [rdx]{1to16}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, dword [rdx]{1to4}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0xca, 0xcc], "vcmpps k1, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, zmm0, zmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, zmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0xca, 0xcc], "vcmpps k1, xmm0, xmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, xmm0, xmm2, 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, xmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VCMPPS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0xca, 0xcc], "vshufps ymm1, ymm0, ymm2, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0xca, 0xcc], "vshufps zmm1, zmm0, zmm2, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0xca, 0xcc], "vshufps xmm1, xmm0, xmm2, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}, xmm0, xmm2, 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, xmmword [rdx], 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VSHUFPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX } #[test] fn tests_66_0f() { test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0xca], "vmovupd ymm1{k5}{z}, ymm2"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0x0a], "vmovupd ymm1{k5}{z}, ymmword [rdx]"); // VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0xca], "vmovupd ymm1, ymm2"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0xca], "vmovupd ymm1{k5}, ymm2"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0x0a], "vmovupd ymm1, ymmword [rdx]"); // VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x0a], "vmovupd ymm1{k5}, ymmword [rdx]"); // VMOVUPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0xca], "vmovupd zmm1{k5}{z}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x0a], "vmovupd zmm1{k5}{z}, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0xca], "vmovupd zmm1, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0xca], "vmovupd zmm1{k5}, zmm2"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x0a], "vmovupd zmm1, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0x0a], "vmovupd zmm1{k5}, zmmword [rdx]"); // VMOVUPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0xca], "vmovupd xmm1{k5}{z}, xmm2"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0x0a], "vmovupd xmm1{k5}{z}, xmmword [rdx]"); // VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0xca], "vmovupd xmm1, xmm2"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0xca], "vmovupd xmm1{k5}, xmm2"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0x0a], "vmovupd xmm1, xmmword [rdx]"); // VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0x0a], "vmovupd xmm1{k5}, xmmword [rdx]"); // VMOVUPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x11, 0xca], "vmovupd ymm2{k5}{z}, ymm1"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0xca], "vmovupd ymm2, ymm1"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0xca], "vmovupd ymm2{k5}, ymm1"); // VMOVUPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0x0a], "vmovupd ymmword [rdx], ymm1"); // VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0x0a], "vmovupd ymmword [rdx]{k5}, ymm1"); // VMOVUPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x11, 0xca], "vmovupd zmm2{k5}{z}, zmm1"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0xca], "vmovupd zmm2, zmm1"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0xca], "vmovupd zmm2{k5}, zmm1"); // VMOVUPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0x0a], "vmovupd zmmword [rdx], zmm1"); // VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0x0a], "vmovupd zmmword [rdx]{k5}, zmm1"); // VMOVUPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x11, 0xca], "vmovupd xmm2{k5}{z}, xmm1"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0xca], "vmovupd xmm2, xmm1"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0xca], "vmovupd xmm2{k5}, xmm1"); // VMOVUPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0x0a], "vmovupd xmmword [rdx], xmm1"); // VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0x0a], "vmovupd xmmword [rdx]{k5}, xmm1"); // VMOVUPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x12, 0x0a], "vmovlpd xmm1, xmm0, qword [rdx]"); // VMOVLPD_XMMf64_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x13, 0x0a], "vmovlpd qword [rdx], xmm1"); // VMOVLPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0xca], "vunpcklpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0xca], "vunpcklpd ymm1, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0xca], "vunpcklpd ymm1{k5}, ymm0, ymm2"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, ymmword [rdx]"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, ymmword [rdx]"); // VUNPCKLPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, qword [rdx]{1to8}"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, qword [rdx]{1to2}"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0xca], "vunpcklpd zmm1{k5}{z}, zmm0, zmm2"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0xca], "vunpcklpd zmm1, zmm0, zmm2"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0xca], "vunpcklpd zmm1{k5}, zmm0, zmm2"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, zmmword [rdx]"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, zmmword [rdx]"); // VUNPCKLPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0xca], "vunpcklpd xmm1{k5}{z}, xmm0, xmm2"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0xca], "vunpcklpd xmm1, xmm0, xmm2"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0xca], "vunpcklpd xmm1{k5}, xmm0, xmm2"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, xmmword [rdx]"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKLPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0xca], "vunpckhpd ymm1{k5}{z}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0xca], "vunpckhpd ymm1, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0xca], "vunpckhpd ymm1{k5}, ymm0, ymm2"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, ymmword [rdx]"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, ymmword [rdx]"); // VUNPCKHPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, qword [rdx]{1to8}"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, qword [rdx]{1to2}"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0xca], "vunpckhpd zmm1{k5}{z}, zmm0, zmm2"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0xca], "vunpckhpd zmm1, zmm0, zmm2"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0xca], "vunpckhpd zmm1{k5}, zmm0, zmm2"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, zmmword [rdx]"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, zmmword [rdx]"); // VUNPCKHPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0xca], "vunpckhpd xmm1{k5}{z}, xmm0, xmm2"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0xca], "vunpckhpd xmm1, xmm0, xmm2"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0xca], "vunpckhpd xmm1{k5}, xmm0, xmm2"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, xmmword [rdx]"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, xmmword [rdx]"); // VUNPCKHPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x16, 0x0a], "vmovhpd xmm1, xmm0, qword [rdx]"); // VMOVHPD_XMMf64_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x17, 0x0a], "vmovhpd qword [rdx], xmm1"); // VMOVHPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0xca], "vmovapd ymm1{k5}{z}, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0x0a], "vmovapd ymm1{k5}{z}, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0xca], "vmovapd ymm1, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0xca], "vmovapd ymm1{k5}, ymm2"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x0a], "vmovapd ymm1, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x0a], "vmovapd ymm1{k5}, ymmword [rdx]"); // VMOVAPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0xca], "vmovapd zmm1{k5}{z}, zmm2"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x0a], "vmovapd zmm1{k5}{z}, zmmword [rdx]"); // VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0xca], "vmovapd zmm1, zmm2"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0xca], "vmovapd zmm1{k5}, zmm2"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0x0a], "vmovapd zmm1, zmmword [rdx]"); // VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0x0a], "vmovapd zmm1{k5}, zmmword [rdx]"); // VMOVAPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0xca], "vmovapd xmm1{k5}{z}, xmm2"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0x0a], "vmovapd xmm1{k5}{z}, xmmword [rdx]"); // VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0xca], "vmovapd xmm1, xmm2"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0xca], "vmovapd xmm1{k5}, xmm2"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0x0a], "vmovapd xmm1, xmmword [rdx]"); // VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0x0a], "vmovapd xmm1{k5}, xmmword [rdx]"); // VMOVAPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x29, 0xca], "vmovapd ymm2{k5}{z}, ymm1"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0xca], "vmovapd ymm2, ymm1"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0xca], "vmovapd ymm2{k5}, ymm1"); // VMOVAPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0x0a], "vmovapd ymmword [rdx], ymm1"); // VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0x0a], "vmovapd ymmword [rdx]{k5}, ymm1"); // VMOVAPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x29, 0xca], "vmovapd zmm2{k5}{z}, zmm1"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0xca], "vmovapd zmm2, zmm1"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0xca], "vmovapd zmm2{k5}, zmm1"); // VMOVAPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0x0a], "vmovapd zmmword [rdx], zmm1"); // VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0x0a], "vmovapd zmmword [rdx]{k5}, zmm1"); // VMOVAPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x29, 0xca], "vmovapd xmm2{k5}{z}, xmm1"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0xca], "vmovapd xmm2, xmm1"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0xca], "vmovapd xmm2{k5}, xmm1"); // VMOVAPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0x0a], "vmovapd xmmword [rdx], xmm1"); // VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0x0a], "vmovapd xmmword [rdx]{k5}, xmm1"); // VMOVAPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x0a], "vmovntpd ymmword [rdx], ymm1"); // VMOVNTPD_MEMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [rdx], zmm1"); // VMOVNTPD_MEMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [rdx], xmm1"); // VMOVNTPD_MEMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); // VUCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [rdx]"); // VUCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0xca], "vcomisd xmm1, xmm2"); // VCOMISD_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x0a], "vcomisd xmm1, qword [rdx]"); // VCOMISD_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rz-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x51, 0xca], "vsqrtpd zmm1{rz-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rz-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rd-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, qword [rdx]{1to4}"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0xca], "vsqrtpd zmm1{rd-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rd-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0x0a], "vsqrtpd ymm1, qword [rdx]{1to4}"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, qword [rdx]{1to4}"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0xca], "vsqrtpd ymm1{k5}{z}, ymm2"); // VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, ymmword [rdx]"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0xca], "vsqrtpd ymm1, ymm2"); // VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0xca], "vsqrtpd ymm1{k5}, ymm2"); // VSQRTPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0x0a], "vsqrtpd ymm1, ymmword [rdx]"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, ymmword [rdx]"); // VSQRTPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{ru-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, qword [rdx]{1to8}"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0xca], "vsqrtpd zmm1{ru-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0xca], "vsqrtpd zmm1{k5}{ru-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0x0a], "vsqrtpd zmm1, qword [rdx]{1to8}"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, qword [rdx]{1to8}"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rne-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, qword [rdx]{1to2}"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0xca], "vsqrtpd zmm1{rne-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rne-sae}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0x0a], "vsqrtpd xmm1, qword [rdx]{1to2}"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, qword [rdx]{1to2}"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, zmmword [rdx]"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0xca], "vsqrtpd zmm1, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0xca], "vsqrtpd zmm1{k5}, zmm2"); // VSQRTPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0x0a], "vsqrtpd zmm1, zmmword [rdx]"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, zmmword [rdx]"); // VSQRTPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0xca], "vsqrtpd xmm1{k5}{z}, xmm2"); // VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, xmmword [rdx]"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0xca], "vsqrtpd xmm1, xmm2"); // VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0xca], "vsqrtpd xmm1{k5}, xmm2"); // VSQRTPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0x0a], "vsqrtpd xmm1, xmmword [rdx]"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, xmmword [rdx]"); // VSQRTPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x54, 0x0a], "vandpd ymm1, ymm0, qword [rdx]{1to4}"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0xca], "vandpd ymm1{k5}{z}, ymm0, ymm2"); // VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0xca], "vandpd ymm1, ymm0, ymm2"); // VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0xca], "vandpd ymm1{k5}, ymm0, ymm2"); // VANDPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0x0a], "vandpd ymm1, ymm0, ymmword [rdx]"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, ymmword [rdx]"); // VANDPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x54, 0x0a], "vandpd zmm1, zmm0, qword [rdx]{1to8}"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x54, 0x0a], "vandpd xmm1, xmm0, qword [rdx]{1to2}"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0xca], "vandpd zmm1{k5}{z}, zmm0, zmm2"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0xca], "vandpd zmm1, zmm0, zmm2"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0xca], "vandpd zmm1{k5}, zmm0, zmm2"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0x0a], "vandpd zmm1, zmm0, zmmword [rdx]"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, zmmword [rdx]"); // VANDPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0xca], "vandpd xmm1{k5}{z}, xmm0, xmm2"); // VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0xca], "vandpd xmm1, xmm0, xmm2"); // VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0xca], "vandpd xmm1{k5}, xmm0, xmm2"); // VANDPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0x0a], "vandpd xmm1, xmm0, xmmword [rdx]"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, xmmword [rdx]"); // VANDPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x55, 0x0a], "vandnpd ymm1, ymm0, qword [rdx]{1to4}"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0xca], "vandnpd ymm1{k5}{z}, ymm0, ymm2"); // VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0xca], "vandnpd ymm1, ymm0, ymm2"); // VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0xca], "vandnpd ymm1{k5}, ymm0, ymm2"); // VANDNPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0x0a], "vandnpd ymm1, ymm0, ymmword [rdx]"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, ymmword [rdx]"); // VANDNPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x55, 0x0a], "vandnpd zmm1, zmm0, qword [rdx]{1to8}"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x55, 0x0a], "vandnpd xmm1, xmm0, qword [rdx]{1to2}"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0xca], "vandnpd zmm1{k5}{z}, zmm0, zmm2"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0xca], "vandnpd zmm1, zmm0, zmm2"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0xca], "vandnpd zmm1{k5}, zmm0, zmm2"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0x0a], "vandnpd zmm1, zmm0, zmmword [rdx]"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, zmmword [rdx]"); // VANDNPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0xca], "vandnpd xmm1{k5}{z}, xmm0, xmm2"); // VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0xca], "vandnpd xmm1, xmm0, xmm2"); // VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0xca], "vandnpd xmm1{k5}, xmm0, xmm2"); // VANDNPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0x0a], "vandnpd xmm1, xmm0, xmmword [rdx]"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, xmmword [rdx]"); // VANDNPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x56, 0x0a], "vorpd ymm1, ymm0, qword [rdx]{1to4}"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0xca], "vorpd ymm1{k5}{z}, ymm0, ymm2"); // VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0xca], "vorpd ymm1, ymm0, ymm2"); // VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0xca], "vorpd ymm1{k5}, ymm0, ymm2"); // VORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0x0a], "vorpd ymm1, ymm0, ymmword [rdx]"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, ymmword [rdx]"); // VORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x56, 0x0a], "vorpd zmm1, zmm0, qword [rdx]{1to8}"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x56, 0x0a], "vorpd xmm1, xmm0, qword [rdx]{1to2}"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0xca], "vorpd zmm1{k5}{z}, zmm0, zmm2"); // VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0xca], "vorpd zmm1, zmm0, zmm2"); // VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0xca], "vorpd zmm1{k5}, zmm0, zmm2"); // VORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0x0a], "vorpd zmm1, zmm0, zmmword [rdx]"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, zmmword [rdx]"); // VORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0xca], "vorpd xmm1{k5}{z}, xmm0, xmm2"); // VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0xca], "vorpd xmm1, xmm0, xmm2"); // VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0xca], "vorpd xmm1{k5}, xmm0, xmm2"); // VORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0x0a], "vorpd xmm1, xmm0, xmmword [rdx]"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, xmmword [rdx]"); // VORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x57, 0x0a], "vxorpd ymm1, ymm0, qword [rdx]{1to4}"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0xca], "vxorpd ymm1{k5}{z}, ymm0, ymm2"); // VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0xca], "vxorpd ymm1, ymm0, ymm2"); // VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0xca], "vxorpd ymm1{k5}, ymm0, ymm2"); // VXORPD_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0x0a], "vxorpd ymm1, ymm0, ymmword [rdx]"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, ymmword [rdx]"); // VXORPD_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x57, 0x0a], "vxorpd zmm1, zmm0, qword [rdx]{1to8}"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x57, 0x0a], "vxorpd xmm1, xmm0, qword [rdx]{1to2}"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0xca], "vxorpd zmm1{k5}{z}, zmm0, zmm2"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0xca], "vxorpd zmm1, zmm0, zmm2"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0xca], "vxorpd zmm1{k5}, zmm0, zmm2"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0x0a], "vxorpd zmm1, zmm0, zmmword [rdx]"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, zmmword [rdx]"); // VXORPD_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0xca], "vxorpd xmm1{k5}{z}, xmm0, xmm2"); // VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0xca], "vxorpd xmm1, xmm0, xmm2"); // VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0xca], "vxorpd xmm1{k5}, xmm0, xmm2"); // VXORPD_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0x0a], "vxorpd xmm1, xmm0, xmmword [rdx]"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, xmmword [rdx]"); // VXORPD_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x58, 0xca], "vaddpd zmm1{rz-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x58, 0xca], "vaddpd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0xca], "vaddpd zmm1{rd-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0xca], "vaddpd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0x0a], "vaddpd ymm1, ymm0, qword [rdx]{1to4}"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0xca], "vaddpd ymm1{k5}{z}, ymm0, ymm2"); // VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0xca], "vaddpd ymm1, ymm0, ymm2"); // VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0xca], "vaddpd ymm1{k5}, ymm0, ymm2"); // VADDPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0x0a], "vaddpd ymm1, ymm0, ymmword [rdx]"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, ymmword [rdx]"); // VADDPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0xca], "vaddpd zmm1{ru-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0xca], "vaddpd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0x0a], "vaddpd zmm1, zmm0, qword [rdx]{1to8}"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0xca], "vaddpd zmm1{rne-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0xca], "vaddpd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0x0a], "vaddpd xmm1, xmm0, qword [rdx]{1to2}"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0xca], "vaddpd zmm1{k5}{z}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0xca], "vaddpd zmm1, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0xca], "vaddpd zmm1{k5}, zmm0, zmm2"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0x0a], "vaddpd zmm1, zmm0, zmmword [rdx]"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, zmmword [rdx]"); // VADDPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0xca], "vaddpd xmm1{k5}{z}, xmm0, xmm2"); // VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0xca], "vaddpd xmm1, xmm0, xmm2"); // VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0xca], "vaddpd xmm1{k5}, xmm0, xmm2"); // VADDPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0x0a], "vaddpd xmm1, xmm0, xmmword [rdx]"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, xmmword [rdx]"); // VADDPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x59, 0xca], "vmulpd zmm1{rz-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x59, 0xca], "vmulpd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0xca], "vmulpd zmm1{rd-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0xca], "vmulpd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0x0a], "vmulpd ymm1, ymm0, qword [rdx]{1to4}"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0xca], "vmulpd ymm1{k5}{z}, ymm0, ymm2"); // VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0xca], "vmulpd ymm1, ymm0, ymm2"); // VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0xca], "vmulpd ymm1{k5}, ymm0, ymm2"); // VMULPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0x0a], "vmulpd ymm1, ymm0, ymmword [rdx]"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, ymmword [rdx]"); // VMULPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0xca], "vmulpd zmm1{ru-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0xca], "vmulpd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0x0a], "vmulpd zmm1, zmm0, qword [rdx]{1to8}"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0xca], "vmulpd zmm1{rne-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0xca], "vmulpd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0x0a], "vmulpd xmm1, xmm0, qword [rdx]{1to2}"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0xca], "vmulpd zmm1{k5}{z}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0xca], "vmulpd zmm1, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0xca], "vmulpd zmm1{k5}, zmm0, zmm2"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0x0a], "vmulpd zmm1, zmm0, zmmword [rdx]"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, zmmword [rdx]"); // VMULPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0xca], "vmulpd xmm1{k5}{z}, xmm0, xmm2"); // VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0xca], "vmulpd xmm1, xmm0, xmm2"); // VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0xca], "vmulpd xmm1{k5}, xmm0, xmm2"); // VMULPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0x0a], "vmulpd xmm1, xmm0, xmmword [rdx]"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, xmmword [rdx]"); // VMULPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5a, 0xca], "vcvtpd2ps ymm1{rz-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rz-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rd-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0xca], "vcvtpd2ps ymm1{rd-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rd-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [rdx]{1to4}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [rdx]{1to4}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, ymm2"); // VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, ymmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0xca], "vcvtpd2ps xmm1, ymm2"); // VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, ymm2"); // VCVTPD2PS_XMMf32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0x0a], "vcvtpd2ps xmm1, ymmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, ymmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{ru-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0xca], "vcvtpd2ps ymm1{ru-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{ru-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0x0a], "vcvtpd2ps ymm1, qword [rdx]{1to8}"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, qword [rdx]{1to8}"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rne-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0xca], "vcvtpd2ps ymm1{rne-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rne-sae}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [rdx]{1to2}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [rdx]{1to2}"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, zmmword [rdx]"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0xca], "vcvtpd2ps ymm1, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}, zmm2"); // VCVTPD2PS_YMMf32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0x0a], "vcvtpd2ps ymm1, zmmword [rdx]"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, zmmword [rdx]"); // VCVTPD2PS_YMMf32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, xmm2"); // VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, xmmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0xca], "vcvtpd2ps xmm1, xmm2"); // VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, xmm2"); // VCVTPD2PS_XMMf32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0x0a], "vcvtpd2ps xmm1, xmmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, xmmword [rdx]"); // VCVTPD2PS_XMMf32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x5b, 0xca], "vcvtps2dq zmm1{rz-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rz-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0xca], "vcvtps2dq zmm1{rd-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rd-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0x0a], "vcvtps2dq ymm1, dword [rdx]{1to8}"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, dword [rdx]{1to8}"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0xca], "vcvtps2dq ymm1{k5}{z}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0xca], "vcvtps2dq ymm1{k5}, ymm2"); // VCVTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x0a], "vcvtps2dq ymm1, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, ymmword [rdx]"); // VCVTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0xca], "vcvtps2dq zmm1{ru-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{ru-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0x0a], "vcvtps2dq zmm1, dword [rdx]{1to16}"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, dword [rdx]{1to16}"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0xca], "vcvtps2dq zmm1{rne-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rne-sae}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0x0a], "vcvtps2dq xmm1, dword [rdx]{1to4}"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, dword [rdx]{1to4}"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, zmmword [rdx]"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0xca], "vcvtps2dq zmm1, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}, zmm2"); // VCVTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0x0a], "vcvtps2dq zmm1, zmmword [rdx]"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, zmmword [rdx]"); // VCVTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}{z}, xmm2"); // VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0xca], "vcvtps2dq xmm1, xmm2"); // VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}, xmm2"); // VCVTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0x0a], "vcvtps2dq xmm1, xmmword [rdx]"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, xmmword [rdx]"); // VCVTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5c, 0xca], "vsubpd zmm1{rz-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5c, 0xca], "vsubpd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0xca], "vsubpd zmm1{rd-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0xca], "vsubpd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0x0a], "vsubpd ymm1, ymm0, qword [rdx]{1to4}"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0xca], "vsubpd ymm1{k5}{z}, ymm0, ymm2"); // VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0xca], "vsubpd ymm1, ymm0, ymm2"); // VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0xca], "vsubpd ymm1{k5}, ymm0, ymm2"); // VSUBPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0x0a], "vsubpd ymm1, ymm0, ymmword [rdx]"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, ymmword [rdx]"); // VSUBPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0xca], "vsubpd zmm1{ru-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0xca], "vsubpd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0x0a], "vsubpd zmm1, zmm0, qword [rdx]{1to8}"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0xca], "vsubpd zmm1{rne-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0xca], "vsubpd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0x0a], "vsubpd xmm1, xmm0, qword [rdx]{1to2}"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0xca], "vsubpd zmm1, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0xca], "vsubpd zmm1{k5}, zmm0, zmm2"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0x0a], "vsubpd zmm1, zmm0, zmmword [rdx]"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, zmmword [rdx]"); // VSUBPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0xca], "vsubpd xmm1{k5}{z}, xmm0, xmm2"); // VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0xca], "vsubpd xmm1, xmm0, xmm2"); // VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0xca], "vsubpd xmm1{k5}, xmm0, xmm2"); // VSUBPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0x0a], "vsubpd xmm1, xmm0, xmmword [rdx]"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, xmmword [rdx]"); // VSUBPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5d, 0xca], "vminpd zmm1{k5}{z}{sae}, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5d, 0xca], "vminpd zmm1{sae}, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5d, 0xca], "vminpd zmm1{k5}{sae}, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5d, 0x0a], "vminpd ymm1, ymm0, qword [rdx]{1to4}"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0xca], "vminpd ymm1{k5}{z}, ymm0, ymm2"); // VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0xca], "vminpd ymm1, ymm0, ymm2"); // VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0xca], "vminpd ymm1{k5}, ymm0, ymm2"); // VMINPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0x0a], "vminpd ymm1, ymm0, ymmword [rdx]"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, ymmword [rdx]"); // VMINPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5d, 0x0a], "vminpd zmm1, zmm0, qword [rdx]{1to8}"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5d, 0x0a], "vminpd xmm1, xmm0, qword [rdx]{1to2}"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0xca], "vminpd zmm1{k5}{z}, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0xca], "vminpd zmm1, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0xca], "vminpd zmm1{k5}, zmm0, zmm2"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0x0a], "vminpd zmm1, zmm0, zmmword [rdx]"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, zmmword [rdx]"); // VMINPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0xca], "vminpd xmm1{k5}{z}, xmm0, xmm2"); // VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0xca], "vminpd xmm1, xmm0, xmm2"); // VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0xca], "vminpd xmm1{k5}, xmm0, xmm2"); // VMINPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0x0a], "vminpd xmm1, xmm0, xmmword [rdx]"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, xmmword [rdx]"); // VMINPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5e, 0xca], "vdivpd zmm1{rz-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5e, 0xca], "vdivpd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0xca], "vdivpd zmm1{rd-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0xca], "vdivpd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0x0a], "vdivpd ymm1, ymm0, qword [rdx]{1to4}"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0xca], "vdivpd ymm1{k5}{z}, ymm0, ymm2"); // VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0xca], "vdivpd ymm1, ymm0, ymm2"); // VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0xca], "vdivpd ymm1{k5}, ymm0, ymm2"); // VDIVPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0x0a], "vdivpd ymm1, ymm0, ymmword [rdx]"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, ymmword [rdx]"); // VDIVPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0xca], "vdivpd zmm1{ru-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0xca], "vdivpd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0x0a], "vdivpd zmm1, zmm0, qword [rdx]{1to8}"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0xca], "vdivpd zmm1{rne-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0xca], "vdivpd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0x0a], "vdivpd xmm1, xmm0, qword [rdx]{1to2}"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0xca], "vdivpd zmm1, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0xca], "vdivpd zmm1{k5}, zmm0, zmm2"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0x0a], "vdivpd zmm1, zmm0, zmmword [rdx]"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, zmmword [rdx]"); // VDIVPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0xca], "vdivpd xmm1{k5}{z}, xmm0, xmm2"); // VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0xca], "vdivpd xmm1, xmm0, xmm2"); // VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0xca], "vdivpd xmm1{k5}, xmm0, xmm2"); // VDIVPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0x0a], "vdivpd xmm1, xmm0, xmmword [rdx]"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, xmmword [rdx]"); // VDIVPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}{sae}, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5f, 0xca], "vmaxpd zmm1{sae}, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5f, 0xca], "vmaxpd zmm1{k5}{sae}, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, qword [rdx]{1to4}"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0xca], "vmaxpd ymm1{k5}{z}, ymm0, ymm2"); // VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0xca], "vmaxpd ymm1, ymm0, ymm2"); // VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0xca], "vmaxpd ymm1{k5}, ymm0, ymm2"); // VMAXPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, ymmword [rdx]"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, ymmword [rdx]"); // VMAXPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, qword [rdx]{1to8}"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, qword [rdx]{1to2}"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0xca], "vmaxpd zmm1, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0xca], "vmaxpd zmm1{k5}, zmm0, zmm2"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, zmmword [rdx]"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, zmmword [rdx]"); // VMAXPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0xca], "vmaxpd xmm1{k5}{z}, xmm0, xmm2"); // VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0xca], "vmaxpd xmm1, xmm0, xmm2"); // VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0xca], "vmaxpd xmm1{k5}, xmm0, xmm2"); // VMAXPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, xmmword [rdx]"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, xmmword [rdx]"); // VMAXPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0xca], "vpunpcklbw ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0x0a], "vpunpcklbw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0xca], "vpunpcklbw ymm1, ymm0, ymm2"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0xca], "vpunpcklbw ymm1{k5}, ymm0, ymm2"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0x0a], "vpunpcklbw ymm1, ymm0, ymmword [rdx]"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0x0a], "vpunpcklbw ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKLBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0xca], "vpunpcklbw zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0x0a], "vpunpcklbw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0xca], "vpunpcklbw zmm1, zmm0, zmm2"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0xca], "vpunpcklbw zmm1{k5}, zmm0, zmm2"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0x0a], "vpunpcklbw zmm1, zmm0, zmmword [rdx]"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0x0a], "vpunpcklbw zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKLBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0xca], "vpunpcklbw xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0xca], "vpunpcklbw xmm1, xmm0, xmm2"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0xca], "vpunpcklbw xmm1{k5}, xmm0, xmm2"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0x0a], "vpunpcklbw xmm1, xmm0, xmmword [rdx]"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKLBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0xca], "vpunpcklwd ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0x0a], "vpunpcklwd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0xca], "vpunpcklwd ymm1, ymm0, ymm2"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0xca], "vpunpcklwd ymm1{k5}, ymm0, ymm2"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0x0a], "vpunpcklwd ymm1, ymm0, ymmword [rdx]"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0x0a], "vpunpcklwd ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKLWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0xca], "vpunpcklwd zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0x0a], "vpunpcklwd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0xca], "vpunpcklwd zmm1, zmm0, zmm2"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0xca], "vpunpcklwd zmm1{k5}, zmm0, zmm2"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0x0a], "vpunpcklwd zmm1, zmm0, zmmword [rdx]"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0x0a], "vpunpcklwd zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKLWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0xca], "vpunpcklwd xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0xca], "vpunpcklwd xmm1, xmm0, xmm2"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0xca], "vpunpcklwd xmm1{k5}, xmm0, xmm2"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0x0a], "vpunpcklwd xmm1, xmm0, xmmword [rdx]"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKLWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, dword [rdx]{1to8}"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0xca], "vpunpckldq ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0xca], "vpunpckldq ymm1, ymm0, ymm2"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0xca], "vpunpckldq ymm1{k5}, ymm0, ymm2"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, ymmword [rdx]"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKLDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, dword [rdx]{1to16}"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, dword [rdx]{1to4}"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0xca], "vpunpckldq zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0xca], "vpunpckldq zmm1, zmm0, zmm2"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0xca], "vpunpckldq zmm1{k5}, zmm0, zmm2"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, zmmword [rdx]"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKLDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0xca], "vpunpckldq xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0xca], "vpunpckldq xmm1, xmm0, xmm2"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0xca], "vpunpckldq xmm1{k5}, xmm0, xmm2"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKLDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0xca], "vpacksswb ymm1{k5}{z}, ymm0, ymm2"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0x0a], "vpacksswb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0xca], "vpacksswb ymm1, ymm0, ymm2"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0xca], "vpacksswb ymm1{k5}, ymm0, ymm2"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0x0a], "vpacksswb ymm1, ymm0, ymmword [rdx]"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0x0a], "vpacksswb ymm1{k5}, ymm0, ymmword [rdx]"); // VPACKSSWB_YMMi8_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0xca], "vpacksswb zmm1{k5}{z}, zmm0, zmm2"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0x0a], "vpacksswb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0xca], "vpacksswb zmm1, zmm0, zmm2"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0xca], "vpacksswb zmm1{k5}, zmm0, zmm2"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0x0a], "vpacksswb zmm1, zmm0, zmmword [rdx]"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0x0a], "vpacksswb zmm1{k5}, zmm0, zmmword [rdx]"); // VPACKSSWB_ZMMi8_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0xca], "vpacksswb xmm1{k5}{z}, xmm0, xmm2"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0x0a], "vpacksswb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0xca], "vpacksswb xmm1, xmm0, xmm2"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0xca], "vpacksswb xmm1{k5}, xmm0, xmm2"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0x0a], "vpacksswb xmm1, xmm0, xmmword [rdx]"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0x0a], "vpacksswb xmm1{k5}, xmm0, xmmword [rdx]"); // VPACKSSWB_XMMi8_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0xca], "vpcmpgtb k1, ymm0, ymm2"); // VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0xca], "vpcmpgtb k1{k5}, ymm0, ymm2"); // VPCMPGTB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0x0a], "vpcmpgtb k1, ymm0, ymmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0x0a], "vpcmpgtb k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0xca], "vpcmpgtb k1, zmm0, zmm2"); // VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0xca], "vpcmpgtb k1{k5}, zmm0, zmm2"); // VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0x0a], "vpcmpgtb k1, zmm0, zmmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0x0a], "vpcmpgtb k1{k5}, zmm0, zmmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0xca], "vpcmpgtb k1, xmm0, xmm2"); // VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0xca], "vpcmpgtb k1{k5}, xmm0, xmm2"); // VPCMPGTB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0x0a], "vpcmpgtb k1, xmm0, xmmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0x0a], "vpcmpgtb k1{k5}, xmm0, xmmword [rdx]"); // VPCMPGTB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0xca], "vpcmpgtw k1, ymm0, ymm2"); // VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0xca], "vpcmpgtw k1{k5}, ymm0, ymm2"); // VPCMPGTW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0x0a], "vpcmpgtw k1, ymm0, ymmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0x0a], "vpcmpgtw k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0xca], "vpcmpgtw k1, zmm0, zmm2"); // VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0xca], "vpcmpgtw k1{k5}, zmm0, zmm2"); // VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0x0a], "vpcmpgtw k1, zmm0, zmmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0x0a], "vpcmpgtw k1{k5}, zmm0, zmmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0xca], "vpcmpgtw k1, xmm0, xmm2"); // VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0xca], "vpcmpgtw k1{k5}, xmm0, xmm2"); // VPCMPGTW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0x0a], "vpcmpgtw k1, xmm0, xmmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0x0a], "vpcmpgtw k1{k5}, xmm0, xmmword [rdx]"); // VPCMPGTW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x66, 0x0a], "vpcmpgtd k1, ymm0, dword [rdx]{1to8}"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0xca], "vpcmpgtd k1, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0xca], "vpcmpgtd k1{k5}, ymm0, ymm2"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x0a], "vpcmpgtd k1, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x0a], "vpcmpgtd k1, zmm0, dword [rdx]{1to16}"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, dword [rdx]{1to16}"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x66, 0x0a], "vpcmpgtd k1, xmm0, dword [rdx]{1to4}"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, dword [rdx]{1to4}"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0xca], "vpcmpgtd k1, zmm0, zmm2"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0xca], "vpcmpgtd k1{k5}, zmm0, zmm2"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0x0a], "vpcmpgtd k1, zmm0, zmmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, zmmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0xca], "vpcmpgtd k1, xmm0, xmm2"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0xca], "vpcmpgtd k1{k5}, xmm0, xmm2"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0x0a], "vpcmpgtd k1, xmm0, xmmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, xmmword [rdx]"); // VPCMPGTD_MASKmskw_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0xca], "vpackuswb ymm1{k5}{z}, ymm0, ymm2"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0x0a], "vpackuswb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0xca], "vpackuswb ymm1, ymm0, ymm2"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0xca], "vpackuswb ymm1{k5}, ymm0, ymm2"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0x0a], "vpackuswb ymm1, ymm0, ymmword [rdx]"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0x0a], "vpackuswb ymm1{k5}, ymm0, ymmword [rdx]"); // VPACKUSWB_YMMu8_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0xca], "vpackuswb zmm1{k5}{z}, zmm0, zmm2"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0x0a], "vpackuswb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0xca], "vpackuswb zmm1, zmm0, zmm2"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0xca], "vpackuswb zmm1{k5}, zmm0, zmm2"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0x0a], "vpackuswb zmm1, zmm0, zmmword [rdx]"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0x0a], "vpackuswb zmm1{k5}, zmm0, zmmword [rdx]"); // VPACKUSWB_ZMMu8_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0xca], "vpackuswb xmm1{k5}{z}, xmm0, xmm2"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0x0a], "vpackuswb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0xca], "vpackuswb xmm1, xmm0, xmm2"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0xca], "vpackuswb xmm1{k5}, xmm0, xmm2"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0x0a], "vpackuswb xmm1, xmm0, xmmword [rdx]"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0x0a], "vpackuswb xmm1{k5}, xmm0, xmmword [rdx]"); // VPACKUSWB_XMMu8_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0xca], "vpunpckhbw ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0x0a], "vpunpckhbw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0xca], "vpunpckhbw ymm1, ymm0, ymm2"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0xca], "vpunpckhbw ymm1{k5}, ymm0, ymm2"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0x0a], "vpunpckhbw ymm1, ymm0, ymmword [rdx]"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0x0a], "vpunpckhbw ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKHBW_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0xca], "vpunpckhbw zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0x0a], "vpunpckhbw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0xca], "vpunpckhbw zmm1, zmm0, zmm2"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0xca], "vpunpckhbw zmm1{k5}, zmm0, zmm2"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0x0a], "vpunpckhbw zmm1, zmm0, zmmword [rdx]"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0x0a], "vpunpckhbw zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKHBW_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0xca], "vpunpckhbw xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0xca], "vpunpckhbw xmm1, xmm0, xmm2"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0xca], "vpunpckhbw xmm1{k5}, xmm0, xmm2"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0x0a], "vpunpckhbw xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHBW_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0xca], "vpunpckhwd ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0x0a], "vpunpckhwd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0xca], "vpunpckhwd ymm1, ymm0, ymm2"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0xca], "vpunpckhwd ymm1{k5}, ymm0, ymm2"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0x0a], "vpunpckhwd ymm1, ymm0, ymmword [rdx]"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0x0a], "vpunpckhwd ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKHWD_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0xca], "vpunpckhwd zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0x0a], "vpunpckhwd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0xca], "vpunpckhwd zmm1, zmm0, zmm2"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0xca], "vpunpckhwd zmm1{k5}, zmm0, zmm2"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0x0a], "vpunpckhwd zmm1, zmm0, zmmword [rdx]"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0x0a], "vpunpckhwd zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKHWD_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0xca], "vpunpckhwd xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0xca], "vpunpckhwd xmm1, xmm0, xmm2"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0xca], "vpunpckhwd xmm1{k5}, xmm0, xmm2"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0x0a], "vpunpckhwd xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHWD_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, dword [rdx]{1to8}"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0xca], "vpunpckhdq ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0xca], "vpunpckhdq ymm1, ymm0, ymm2"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0xca], "vpunpckhdq ymm1{k5}, ymm0, ymm2"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, ymmword [rdx]"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKHDQ_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, dword [rdx]{1to16}"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, dword [rdx]{1to4}"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0xca], "vpunpckhdq zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0xca], "vpunpckhdq zmm1, zmm0, zmm2"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0xca], "vpunpckhdq zmm1{k5}, zmm0, zmm2"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, zmmword [rdx]"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKHDQ_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0xca], "vpunpckhdq xmm1, xmm0, xmm2"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}, xmm0, xmm2"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHDQ_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, dword [rdx]{1to8}"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0xca], "vpackssdw ymm1{k5}{z}, ymm0, ymm2"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0xca], "vpackssdw ymm1, ymm0, ymm2"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0xca], "vpackssdw ymm1{k5}, ymm0, ymm2"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, ymmword [rdx]"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, ymmword [rdx]"); // VPACKSSDW_YMMi16_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, dword [rdx]{1to16}"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, dword [rdx]{1to4}"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0xca], "vpackssdw zmm1{k5}{z}, zmm0, zmm2"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0xca], "vpackssdw zmm1, zmm0, zmm2"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0xca], "vpackssdw zmm1{k5}, zmm0, zmm2"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, zmmword [rdx]"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, zmmword [rdx]"); // VPACKSSDW_ZMMi16_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0xca], "vpackssdw xmm1{k5}{z}, xmm0, xmm2"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0xca], "vpackssdw xmm1, xmm0, xmm2"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0xca], "vpackssdw xmm1{k5}, xmm0, xmm2"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, xmmword [rdx]"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, xmmword [rdx]"); // VPACKSSDW_XMMi16_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, qword [rdx]{1to4}"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0xca], "vpunpcklqdq ymm1, ymm0, ymm2"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}, ymm0, ymm2"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, ymmword [rdx]"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKLQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, qword [rdx]{1to8}"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, qword [rdx]{1to2}"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0xca], "vpunpcklqdq zmm1, zmm0, zmm2"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}, zmm0, zmm2"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, zmmword [rdx]"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKLQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0xca], "vpunpcklqdq xmm1, xmm0, xmm2"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}, xmm0, xmm2"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKLQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, qword [rdx]{1to4}"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymm2"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0xca], "vpunpckhqdq ymm1, ymm0, ymm2"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}, ymm0, ymm2"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, ymmword [rdx]"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, ymmword [rdx]"); // VPUNPCKHQDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, qword [rdx]{1to8}"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, qword [rdx]{1to2}"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmm2"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0xca], "vpunpckhqdq zmm1, zmm0, zmm2"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}, zmm0, zmm2"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, zmmword [rdx]"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, zmmword [rdx]"); // VPUNPCKHQDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmm2"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0xca], "vpunpckhqdq xmm1, xmm0, xmm2"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}, xmm0, xmm2"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [rdx]"); // VPUNPCKHQDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0xca], "vmovq xmm1, rdx"); // VMOVQ_XMMu64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0xca], "vmovd xmm1, edx"); // VMOVD_XMMu32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6e, 0x0a], "vmovd xmm1, dword [rdx]"); // VMOVD_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0xca], "vmovdqa64 ymm1{k5}{z}, ymm2"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0xca], "vmovdqa64 ymm1, ymm2"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0xca], "vmovdqa64 ymm1{k5}, ymm2"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0x0a], "vmovdqa64 ymm1, ymmword [rdx]"); // VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}, ymmword [rdx]"); // VMOVDQA64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0xca], "vmovdqa32 ymm1{k5}{z}, ymm2"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0xca], "vmovdqa32 ymm1, ymm2"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0xca], "vmovdqa32 ymm1{k5}, ymm2"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0x0a], "vmovdqa32 ymm1, ymmword [rdx]"); // VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}, ymmword [rdx]"); // VMOVDQA32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0xca], "vmovdqa64 zmm1{k5}{z}, zmm2"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0xca], "vmovdqa64 zmm1, zmm2"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0xca], "vmovdqa64 zmm1{k5}, zmm2"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0x0a], "vmovdqa64 zmm1, zmmword [rdx]"); // VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}, zmmword [rdx]"); // VMOVDQA64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}{z}, xmm2"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0xca], "vmovdqa64 xmm1, xmm2"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}, xmm2"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0x0a], "vmovdqa64 xmm1, xmmword [rdx]"); // VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}, xmmword [rdx]"); // VMOVDQA64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0xca], "vmovdqa32 zmm1{k5}{z}, zmm2"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0xca], "vmovdqa32 zmm1, zmm2"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0xca], "vmovdqa32 zmm1{k5}, zmm2"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0x0a], "vmovdqa32 zmm1, zmmword [rdx]"); // VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}, zmmword [rdx]"); // VMOVDQA32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}{z}, xmm2"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0xca], "vmovdqa32 xmm1, xmm2"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}, xmm2"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0x0a], "vmovdqa32 xmm1, xmmword [rdx]"); // VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}, xmmword [rdx]"); // VMOVDQA32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x70, 0x0a, 0xcc], "vpshufd ymm1, dword [rdx]{1to8}, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}{z}, ymm2, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0xca, 0xcc], "vpshufd ymm1, ymm2, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}, ymm2, 0xcc"); // VPSHUFD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0x0a, 0xcc], "vpshufd ymm1, ymmword [rdx], 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, ymmword [rdx], 0xcc"); // VPSHUFD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x70, 0x0a, 0xcc], "vpshufd zmm1, dword [rdx]{1to16}, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, dword [rdx]{1to16}, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x70, 0x0a, 0xcc], "vpshufd xmm1, dword [rdx]{1to4}, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, dword [rdx]{1to4}, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}{z}, zmm2, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0xca, 0xcc], "vpshufd zmm1, zmm2, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}, zmm2, 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0x0a, 0xcc], "vpshufd zmm1, zmmword [rdx], 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, zmmword [rdx], 0xcc"); // VPSHUFD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}{z}, xmm2, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0xca, 0xcc], "vpshufd xmm1, xmm2, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}, xmm2, 0xcc"); // VPSHUFD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0x0a, 0xcc], "vpshufd xmm1, xmmword [rdx], 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, xmmword [rdx], 0xcc"); // VPSHUFD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX // TODO: 72 (and 71) are selected by /r. these need more exhaustive (hmmm) testing. test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x72, 0x0a, 0xcc], "vprolq ymm0, qword [rdx]{1to4}, 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, qword [rdx]{1to4}, 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}{z}, ymm2, 0xcc"); // VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, ymmword [rdx], 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vprolq ymm0, ymm2, 0xcc"); // VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}, ymm2, 0xcc"); // VPROLQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vprolq ymm0, ymmword [rdx], 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, ymmword [rdx], 0xcc"); // VPROLQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x72, 0x0a, 0xcc], "vprold ymm0, dword [rdx]{1to8}, 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, dword [rdx]{1to8}, 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0xca, 0xcc], "vprold ymm0{k5}{z}, ymm2, 0xcc"); // VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, ymmword [rdx], 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0xca, 0xcc], "vprold ymm0, ymm2, 0xcc"); // VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0xca, 0xcc], "vprold ymm0{k5}, ymm2, 0xcc"); // VPROLD_YMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0x0a, 0xcc], "vprold ymm0, ymmword [rdx], 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, ymmword [rdx], 0xcc"); // VPROLD_YMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x72, 0x0a, 0xcc], "vprolq zmm0, qword [rdx]{1to8}, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, qword [rdx]{1to8}, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, qword [rdx]{1to2}, 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x72, 0x0a, 0xcc], "vprolq xmm0, qword [rdx]{1to2}, 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, qword [rdx]{1to2}, 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}{z}, zmm2, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, zmmword [rdx], 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vprolq zmm0, zmm2, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}, zmm2, 0xcc"); // VPROLQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vprolq zmm0, zmmword [rdx], 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, zmmword [rdx], 0xcc"); // VPROLQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}{z}, xmm2, 0xcc"); // VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, xmmword [rdx], 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vprolq xmm0, xmm2, 0xcc"); // VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}, xmm2, 0xcc"); // VPROLQ_XMMu64_MASKmskw_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vprolq xmm0, xmmword [rdx], 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, xmmword [rdx], 0xcc"); // VPROLQ_XMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x72, 0x0a, 0xcc], "vprold zmm0, dword [rdx]{1to16}, 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, dword [rdx]{1to16}, 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x72, 0x0a, 0xcc], "vprold xmm0, dword [rdx]{1to4}, 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, dword [rdx]{1to4}, 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0xca, 0xcc], "vprold zmm0{k5}{z}, zmm2, 0xcc"); // VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, zmmword [rdx], 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0xca, 0xcc], "vprold zmm0, zmm2, 0xcc"); // VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0xca, 0xcc], "vprold zmm0{k5}, zmm2, 0xcc"); // VPROLD_ZMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0x0a, 0xcc], "vprold zmm0, zmmword [rdx], 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, zmmword [rdx], 0xcc"); // VPROLD_ZMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}{z}, xmm2, 0xcc"); // VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, xmmword [rdx], 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0xca, 0xcc], "vprold xmm0, xmm2, 0xcc"); // VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}, xmm2, 0xcc"); // VPROLD_XMMu32_MASKmskw_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0x0a, 0xcc], "vprold xmm0, xmmword [rdx], 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, xmmword [rdx], 0xcc"); // VPROLD_XMMu32_MASKmskw_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0xca], "vpcmpeqb k1, ymm0, ymm2"); // VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0xca], "vpcmpeqb k1{k5}, ymm0, ymm2"); // VPCMPEQB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0x0a], "vpcmpeqb k1, ymm0, ymmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0x0a], "vpcmpeqb k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0xca], "vpcmpeqb k1, zmm0, zmm2"); // VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0xca], "vpcmpeqb k1{k5}, zmm0, zmm2"); // VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0x0a], "vpcmpeqb k1, zmm0, zmmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0x0a], "vpcmpeqb k1{k5}, zmm0, zmmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0xca], "vpcmpeqb k1, xmm0, xmm2"); // VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0xca], "vpcmpeqb k1{k5}, xmm0, xmm2"); // VPCMPEQB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0x0a], "vpcmpeqb k1, xmm0, xmmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0x0a], "vpcmpeqb k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0xca], "vpcmpeqw k1, ymm0, ymm2"); // VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0xca], "vpcmpeqw k1{k5}, ymm0, ymm2"); // VPCMPEQW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0x0a], "vpcmpeqw k1, ymm0, ymmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0x0a], "vpcmpeqw k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0xca], "vpcmpeqw k1, zmm0, zmm2"); // VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0xca], "vpcmpeqw k1{k5}, zmm0, zmm2"); // VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0x0a], "vpcmpeqw k1, zmm0, zmmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0x0a], "vpcmpeqw k1{k5}, zmm0, zmmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0xca], "vpcmpeqw k1, xmm0, xmm2"); // VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0xca], "vpcmpeqw k1{k5}, xmm0, xmm2"); // VPCMPEQW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0x0a], "vpcmpeqw k1, xmm0, xmmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0x0a], "vpcmpeqw k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x76, 0x0a], "vpcmpeqd k1, ymm0, dword [rdx]{1to8}"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0xca], "vpcmpeqd k1, ymm0, ymm2"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0xca], "vpcmpeqd k1{k5}, ymm0, ymm2"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0x0a], "vpcmpeqd k1, ymm0, ymmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x76, 0x0a], "vpcmpeqd k1, zmm0, dword [rdx]{1to16}"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, dword [rdx]{1to16}"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x76, 0x0a], "vpcmpeqd k1, xmm0, dword [rdx]{1to4}"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, dword [rdx]{1to4}"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0xca], "vpcmpeqd k1, zmm0, zmm2"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0xca], "vpcmpeqd k1{k5}, zmm0, zmm2"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0x0a], "vpcmpeqd k1, zmm0, zmmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, zmmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0xca], "vpcmpeqd k1, xmm0, xmm2"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0xca], "vpcmpeqd k1{k5}, xmm0, xmm2"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0x0a], "vpcmpeqd k1, xmm0, xmmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}{sae}, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x78, 0xca], "vcvttpd2uqq zmm1{sae}, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{sae}, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x78, 0x0a], "vcvttpd2uqq ymm1, qword [rdx]{1to4}"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, qword [rdx]{1to4}"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}{z}, ymm2"); // VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, ymmword [rdx]"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0xca], "vcvttpd2uqq ymm1, ymm2"); // VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}, ymm2"); // VCVTTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0x0a], "vcvttpd2uqq ymm1, ymmword [rdx]"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, ymmword [rdx]"); // VCVTTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}{sae}, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x78, 0xca], "vcvttps2uqq zmm1{sae}, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{sae}, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x78, 0x0a], "vcvttps2uqq ymm1, dword [rdx]{1to4}"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, dword [rdx]{1to4}"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0xca], "vcvttps2uqq ymm1{k5}{z}, xmm2"); // VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, xmmword [rdx]"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0xca], "vcvttps2uqq ymm1, xmm2"); // VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0xca], "vcvttps2uqq ymm1{k5}, xmm2"); // VCVTTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0x0a], "vcvttps2uqq ymm1, xmmword [rdx]"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, xmmword [rdx]"); // VCVTTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x78, 0x0a], "vcvttpd2uqq zmm1, qword [rdx]{1to8}"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, qword [rdx]{1to8}"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x78, 0x0a], "vcvttpd2uqq xmm1, qword [rdx]{1to2}"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, qword [rdx]{1to2}"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, zmmword [rdx]"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0xca], "vcvttpd2uqq zmm1, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}, zmm2"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0x0a], "vcvttpd2uqq zmm1, zmmword [rdx]"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, zmmword [rdx]"); // VCVTTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}{z}, xmm2"); // VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0xca], "vcvttpd2uqq xmm1, xmm2"); // VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}, xmm2"); // VCVTTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0x0a], "vcvttpd2uqq xmm1, xmmword [rdx]"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, xmmword [rdx]"); // VCVTTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x78, 0x0a], "vcvttps2uqq zmm1, dword [rdx]{1to8}"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, dword [rdx]{1to8}"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x78, 0x0a], "vcvttps2uqq xmm1, dword [rdx]{1to2}"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, dword [rdx]{1to2}"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, ymmword [rdx]"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0xca], "vcvttps2uqq zmm1, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}, ymm2"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0x0a], "vcvttps2uqq zmm1, ymmword [rdx]"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, ymmword [rdx]"); // VCVTTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}{z}, xmm2"); // VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, qword [rdx]"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0xca], "vcvttps2uqq xmm1, xmm2"); // VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}, xmm2"); // VCVTTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0x0a], "vcvttps2uqq xmm1, qword [rdx]"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, qword [rdx]"); // VCVTTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x79, 0xca], "vcvtpd2uqq zmm1{rz-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rz-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0xca], "vcvtpd2uqq zmm1{rd-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rd-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0x0a], "vcvtpd2uqq ymm1, qword [rdx]{1to4}"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, qword [rdx]{1to4}"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}{z}, ymm2"); // VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0xca], "vcvtpd2uqq ymm1, ymm2"); // VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}, ymm2"); // VCVTPD2UQQ_YMMu64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0x0a], "vcvtpd2uqq ymm1, ymmword [rdx]"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, ymmword [rdx]"); // VCVTPD2UQQ_YMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rz-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x79, 0xca], "vcvtps2uqq zmm1{rz-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rz-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rd-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0xca], "vcvtps2uqq zmm1{rd-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rd-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0x0a], "vcvtps2uqq ymm1, dword [rdx]{1to4}"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, dword [rdx]{1to4}"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0xca], "vcvtps2uqq ymm1{k5}{z}, xmm2"); // VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, xmmword [rdx]"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0xca], "vcvtps2uqq ymm1, xmm2"); // VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0xca], "vcvtps2uqq ymm1{k5}, xmm2"); // VCVTPS2UQQ_YMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0x0a], "vcvtps2uqq ymm1, xmmword [rdx]"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, xmmword [rdx]"); // VCVTPS2UQQ_YMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0xca], "vcvtpd2uqq zmm1{ru-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{ru-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0x0a], "vcvtpd2uqq zmm1, qword [rdx]{1to8}"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, qword [rdx]{1to8}"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0xca], "vcvtpd2uqq zmm1{rne-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rne-sae}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0x0a], "vcvtpd2uqq xmm1, qword [rdx]{1to2}"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, qword [rdx]{1to2}"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, zmmword [rdx]"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0xca], "vcvtpd2uqq zmm1, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}, zmm2"); // VCVTPD2UQQ_ZMMu64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0x0a], "vcvtpd2uqq zmm1, zmmword [rdx]"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, zmmword [rdx]"); // VCVTPD2UQQ_ZMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}{z}, xmm2"); // VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0xca], "vcvtpd2uqq xmm1, xmm2"); // VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}, xmm2"); // VCVTPD2UQQ_XMMu64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0x0a], "vcvtpd2uqq xmm1, xmmword [rdx]"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, xmmword [rdx]"); // VCVTPD2UQQ_XMMu64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{ru-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0xca], "vcvtps2uqq zmm1{ru-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{ru-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0x0a], "vcvtps2uqq zmm1, dword [rdx]{1to8}"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, dword [rdx]{1to8}"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rne-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0xca], "vcvtps2uqq zmm1{rne-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rne-sae}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0x0a], "vcvtps2uqq xmm1, dword [rdx]{1to2}"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, dword [rdx]{1to2}"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, ymmword [rdx]"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0xca], "vcvtps2uqq zmm1, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}, ymm2"); // VCVTPS2UQQ_ZMMu64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0x0a], "vcvtps2uqq zmm1, ymmword [rdx]"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, ymmword [rdx]"); // VCVTPS2UQQ_ZMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}{z}, xmm2"); // VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, qword [rdx]"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0xca], "vcvtps2uqq xmm1, xmm2"); // VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}, xmm2"); // VCVTPS2UQQ_XMMu64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0x0a], "vcvtps2uqq xmm1, qword [rdx]"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, qword [rdx]"); // VCVTPS2UQQ_XMMu64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}{sae}, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x7a, 0xca], "vcvttpd2qq zmm1{sae}, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{sae}, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7a, 0x0a], "vcvttpd2qq ymm1, qword [rdx]{1to4}"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, qword [rdx]{1to4}"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}{z}, ymm2"); // VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, ymmword [rdx]"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0xca], "vcvttpd2qq ymm1, ymm2"); // VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}, ymm2"); // VCVTTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0x0a], "vcvttpd2qq ymm1, ymmword [rdx]"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, ymmword [rdx]"); // VCVTTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}{sae}, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x7a, 0xca], "vcvttps2qq zmm1{sae}, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{sae}, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7a, 0x0a], "vcvttps2qq ymm1, dword [rdx]{1to4}"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, dword [rdx]{1to4}"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0xca], "vcvttps2qq ymm1{k5}{z}, xmm2"); // VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, xmmword [rdx]"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0xca], "vcvttps2qq ymm1, xmm2"); // VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0xca], "vcvttps2qq ymm1{k5}, xmm2"); // VCVTTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0x0a], "vcvttps2qq ymm1, xmmword [rdx]"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, xmmword [rdx]"); // VCVTTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7a, 0x0a], "vcvttpd2qq zmm1, qword [rdx]{1to8}"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, qword [rdx]{1to8}"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7a, 0x0a], "vcvttpd2qq xmm1, qword [rdx]{1to2}"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, qword [rdx]{1to2}"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, zmmword [rdx]"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0xca], "vcvttpd2qq zmm1, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}, zmm2"); // VCVTTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0x0a], "vcvttpd2qq zmm1, zmmword [rdx]"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, zmmword [rdx]"); // VCVTTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}{z}, xmm2"); // VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0xca], "vcvttpd2qq xmm1, xmm2"); // VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}, xmm2"); // VCVTTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0x0a], "vcvttpd2qq xmm1, xmmword [rdx]"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, xmmword [rdx]"); // VCVTTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7a, 0x0a], "vcvttps2qq zmm1, dword [rdx]{1to8}"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, dword [rdx]{1to8}"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7a, 0x0a], "vcvttps2qq xmm1, dword [rdx]{1to2}"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, dword [rdx]{1to2}"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, ymmword [rdx]"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0xca], "vcvttps2qq zmm1, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}, ymm2"); // VCVTTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0x0a], "vcvttps2qq zmm1, ymmword [rdx]"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, ymmword [rdx]"); // VCVTTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}{z}, xmm2"); // VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, qword [rdx]"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0xca], "vcvttps2qq xmm1, xmm2"); // VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}, xmm2"); // VCVTTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0x0a], "vcvttps2qq xmm1, qword [rdx]"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, qword [rdx]"); // VCVTTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x7b, 0xca], "vcvtpd2qq zmm1{rz-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rz-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0xca], "vcvtpd2qq zmm1{rd-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rd-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0x0a], "vcvtpd2qq ymm1, qword [rdx]{1to4}"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, qword [rdx]{1to4}"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}{z}, ymm2"); // VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, ymmword [rdx]"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0xca], "vcvtpd2qq ymm1, ymm2"); // VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}, ymm2"); // VCVTPD2QQ_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0x0a], "vcvtpd2qq ymm1, ymmword [rdx]"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, ymmword [rdx]"); // VCVTPD2QQ_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rz-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x7b, 0xca], "vcvtps2qq zmm1{rz-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rz-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rd-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0xca], "vcvtps2qq zmm1{rd-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rd-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0x0a], "vcvtps2qq ymm1, dword [rdx]{1to4}"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, dword [rdx]{1to4}"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0xca], "vcvtps2qq ymm1{k5}{z}, xmm2"); // VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, xmmword [rdx]"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0xca], "vcvtps2qq ymm1, xmm2"); // VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0xca], "vcvtps2qq ymm1{k5}, xmm2"); // VCVTPS2QQ_YMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0x0a], "vcvtps2qq ymm1, xmmword [rdx]"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, xmmword [rdx]"); // VCVTPS2QQ_YMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0xca], "vcvtpd2qq zmm1{ru-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{ru-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0x0a], "vcvtpd2qq zmm1, qword [rdx]{1to8}"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, qword [rdx]{1to8}"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0xca], "vcvtpd2qq zmm1{rne-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rne-sae}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0x0a], "vcvtpd2qq xmm1, qword [rdx]{1to2}"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, qword [rdx]{1to2}"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, zmmword [rdx]"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0xca], "vcvtpd2qq zmm1, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}, zmm2"); // VCVTPD2QQ_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0x0a], "vcvtpd2qq zmm1, zmmword [rdx]"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, zmmword [rdx]"); // VCVTPD2QQ_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}{z}, xmm2"); // VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0xca], "vcvtpd2qq xmm1, xmm2"); // VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}, xmm2"); // VCVTPD2QQ_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0x0a], "vcvtpd2qq xmm1, xmmword [rdx]"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, xmmword [rdx]"); // VCVTPD2QQ_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{ru-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0xca], "vcvtps2qq zmm1{ru-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{ru-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0x0a], "vcvtps2qq zmm1, dword [rdx]{1to8}"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, dword [rdx]{1to8}"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rne-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0xca], "vcvtps2qq zmm1{rne-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rne-sae}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0x0a], "vcvtps2qq xmm1, dword [rdx]{1to2}"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, dword [rdx]{1to2}"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, ymmword [rdx]"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0xca], "vcvtps2qq zmm1, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}, ymm2"); // VCVTPS2QQ_ZMMi64_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0x0a], "vcvtps2qq zmm1, ymmword [rdx]"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, ymmword [rdx]"); // VCVTPS2QQ_ZMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}{z}, xmm2"); // VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, qword [rdx]"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0xca], "vcvtps2qq xmm1, xmm2"); // VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}, xmm2"); // VCVTPS2QQ_XMMi64_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0x0a], "vcvtps2qq xmm1, qword [rdx]"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, qword [rdx]"); // VCVTPS2QQ_XMMi64_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0xca], "vmovq rdx, xmm1"); // VMOVQ_GPR64u64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x0a], "vmovq qword [rdx], xmm1"); // VMOVQ_MEMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0xca], "vmovd edx, xmm1"); // VMOVD_GPR32u32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7e, 0x0a], "vmovd dword [rdx], xmm1"); // VMOVD_MEMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7f, 0xca], "vmovdqa64 ymm2{k5}{z}, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0xca], "vmovdqa64 ymm2, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0xca], "vmovdqa64 ymm2{k5}, ymm1"); // VMOVDQA64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0x0a], "vmovdqa64 ymmword [rdx], ymm1"); // VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0x0a], "vmovdqa64 ymmword [rdx]{k5}, ymm1"); // VMOVDQA64_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7f, 0xca], "vmovdqa32 ymm2{k5}{z}, ymm1"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0xca], "vmovdqa32 ymm2, ymm1"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0xca], "vmovdqa32 ymm2{k5}, ymm1"); // VMOVDQA32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0x0a], "vmovdqa32 ymmword [rdx], ymm1"); // VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0x0a], "vmovdqa32 ymmword [rdx]{k5}, ymm1"); // VMOVDQA32_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7f, 0xca], "vmovdqa64 zmm2{k5}{z}, zmm1"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0xca], "vmovdqa64 zmm2, zmm1"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0xca], "vmovdqa64 zmm2{k5}, zmm1"); // VMOVDQA64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0x0a], "vmovdqa64 zmmword [rdx], zmm1"); // VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0x0a], "vmovdqa64 zmmword [rdx]{k5}, zmm1"); // VMOVDQA64_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}{z}, xmm1"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0xca], "vmovdqa64 xmm2, xmm1"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}, xmm1"); // VMOVDQA64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0x0a], "vmovdqa64 xmmword [rdx], xmm1"); // VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0x0a], "vmovdqa64 xmmword [rdx]{k5}, xmm1"); // VMOVDQA64_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7f, 0xca], "vmovdqa32 zmm2{k5}{z}, zmm1"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0xca], "vmovdqa32 zmm2, zmm1"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0xca], "vmovdqa32 zmm2{k5}, zmm1"); // VMOVDQA32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0x0a], "vmovdqa32 zmmword [rdx], zmm1"); // VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0x0a], "vmovdqa32 zmmword [rdx]{k5}, zmm1"); // VMOVDQA32_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}{z}, xmm1"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0xca], "vmovdqa32 xmm2, xmm1"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}, xmm1"); // VMOVDQA32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x0a], "vmovdqa32 xmmword [rdx], xmm1"); // VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0x0a], "vmovdqa32 xmmword [rdx]{k5}, xmm1"); // VMOVDQA32_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xc2, 0xca, 0xcc], "vcmppd k1{sae}, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}{sae}, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0xca, 0xcc], "vcmppd k1, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, ymm0, ymm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, ymmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, qword [rdx]{1to8}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, qword [rdx]{1to2}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0xca, 0xcc], "vcmppd k1, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, zmm0, zmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, zmmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0xca, 0xcc], "vcmppd k1, xmm0, xmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, xmm0, xmm2, 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, xmmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VCMPPD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0xca, 0xcc], "vpinsrw xmm1, xmm0, edx, 0xcc"); // VPINSRW_XMMu16_XMMu16_GPR32u16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0x0a, 0xcc], "vpinsrw xmm1, xmm0, word [rdx], 0xcc"); // VPINSRW_XMMu16_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc5, 0xca, 0xcc], "vpextrw ecx, xmm2, 0xcc"); // VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512_C5, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0xca, 0xcc], "vshufpd ymm1, ymm0, ymm2, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0xca, 0xcc], "vshufpd zmm1, zmm0, zmm2, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0xca, 0xcc], "vshufpd xmm1, xmm0, xmm2, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}, xmm0, xmm2, 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, xmmword [rdx], 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VSHUFPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0xca], "vpsrlw ymm1{k5}{z}, ymm0, xmm2"); // VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0x0a], "vpsrlw ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0xca], "vpsrlw ymm1, ymm0, xmm2"); // VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0xca], "vpsrlw ymm1{k5}, ymm0, xmm2"); // VPSRLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0x0a], "vpsrlw ymm1, ymm0, xmmword [rdx]"); // VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0x0a], "vpsrlw ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0xca], "vpsrlw zmm1{k5}{z}, zmm0, xmm2"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0x0a], "vpsrlw zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0xca], "vpsrlw zmm1, zmm0, xmm2"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0xca], "vpsrlw zmm1{k5}, zmm0, xmm2"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0x0a], "vpsrlw zmm1, zmm0, xmmword [rdx]"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0x0a], "vpsrlw zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0xca], "vpsrlw xmm1{k5}{z}, xmm0, xmm2"); // VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0x0a], "vpsrlw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0xca], "vpsrlw xmm1, xmm0, xmm2"); // VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0xca], "vpsrlw xmm1{k5}, xmm0, xmm2"); // VPSRLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0x0a], "vpsrlw xmm1, xmm0, xmmword [rdx]"); // VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0x0a], "vpsrlw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0xca], "vpsrld ymm1{k5}{z}, ymm0, xmm2"); // VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0x0a], "vpsrld ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0xca], "vpsrld ymm1, ymm0, xmm2"); // VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0xca], "vpsrld ymm1{k5}, ymm0, xmm2"); // VPSRLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0x0a], "vpsrld ymm1, ymm0, xmmword [rdx]"); // VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0x0a], "vpsrld ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0xca], "vpsrld zmm1{k5}{z}, zmm0, xmm2"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0x0a], "vpsrld zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0xca], "vpsrld zmm1, zmm0, xmm2"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0xca], "vpsrld zmm1{k5}, zmm0, xmm2"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0x0a], "vpsrld zmm1, zmm0, xmmword [rdx]"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0x0a], "vpsrld zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0xca], "vpsrld xmm1{k5}{z}, xmm0, xmm2"); // VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0x0a], "vpsrld xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0xca], "vpsrld xmm1, xmm0, xmm2"); // VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0xca], "vpsrld xmm1{k5}, xmm0, xmm2"); // VPSRLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0x0a], "vpsrld xmm1, xmm0, xmmword [rdx]"); // VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0x0a], "vpsrld xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0xca], "vpsrlq ymm1{k5}{z}, ymm0, xmm2"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0x0a], "vpsrlq ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0xca], "vpsrlq ymm1, ymm0, xmm2"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0xca], "vpsrlq ymm1{k5}, ymm0, xmm2"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0x0a], "vpsrlq ymm1, ymm0, xmmword [rdx]"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0x0a], "vpsrlq ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0xca], "vpsrlq zmm1{k5}{z}, zmm0, xmm2"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0x0a], "vpsrlq zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0xca], "vpsrlq zmm1, zmm0, xmm2"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0xca], "vpsrlq zmm1{k5}, zmm0, xmm2"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0x0a], "vpsrlq zmm1, zmm0, xmmword [rdx]"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0x0a], "vpsrlq zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0xca], "vpsrlq xmm1{k5}{z}, xmm0, xmm2"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0x0a], "vpsrlq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0xca], "vpsrlq xmm1, xmm0, xmm2"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0xca], "vpsrlq xmm1{k5}, xmm0, xmm2"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0x0a], "vpsrlq xmm1, xmm0, xmmword [rdx]"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0x0a], "vpsrlq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xd4, 0x0a], "vpaddq ymm1, ymm0, qword [rdx]{1to4}"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0xca], "vpaddq ymm1{k5}{z}, ymm0, ymm2"); // VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0xca], "vpaddq ymm1, ymm0, ymm2"); // VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0xca], "vpaddq ymm1{k5}, ymm0, ymm2"); // VPADDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0x0a], "vpaddq ymm1, ymm0, ymmword [rdx]"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xd4, 0x0a], "vpaddq zmm1, zmm0, qword [rdx]{1to8}"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xd4, 0x0a], "vpaddq xmm1, xmm0, qword [rdx]{1to2}"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0xca], "vpaddq zmm1{k5}{z}, zmm0, zmm2"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0xca], "vpaddq zmm1, zmm0, zmm2"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0xca], "vpaddq zmm1{k5}, zmm0, zmm2"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0x0a], "vpaddq zmm1, zmm0, zmmword [rdx]"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0xca], "vpaddq xmm1{k5}{z}, xmm0, xmm2"); // VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0xca], "vpaddq xmm1, xmm0, xmm2"); // VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0xca], "vpaddq xmm1{k5}, xmm0, xmm2"); // VPADDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0x0a], "vpaddq xmm1, xmm0, xmmword [rdx]"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0xca], "vpmullw ymm1{k5}{z}, ymm0, ymm2"); // VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0x0a], "vpmullw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0xca], "vpmullw ymm1, ymm0, ymm2"); // VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0xca], "vpmullw ymm1{k5}, ymm0, ymm2"); // VPMULLW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0x0a], "vpmullw ymm1, ymm0, ymmword [rdx]"); // VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0x0a], "vpmullw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0xca], "vpmullw zmm1{k5}{z}, zmm0, zmm2"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0x0a], "vpmullw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0xca], "vpmullw zmm1, zmm0, zmm2"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0xca], "vpmullw zmm1{k5}, zmm0, zmm2"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0x0a], "vpmullw zmm1, zmm0, zmmword [rdx]"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0x0a], "vpmullw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0xca], "vpmullw xmm1{k5}{z}, xmm0, xmm2"); // VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0x0a], "vpmullw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0xca], "vpmullw xmm1, xmm0, xmm2"); // VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0xca], "vpmullw xmm1{k5}, xmm0, xmm2"); // VPMULLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0x0a], "vpmullw xmm1, xmm0, xmmword [rdx]"); // VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0x0a], "vpmullw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0xca], "vmovq xmm2, xmm1"); // VMOVQ_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0x0a], "vmovq qword [rdx], xmm1"); // VMOVQ_MEMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0xca], "vpsubusb ymm1{k5}{z}, ymm0, ymm2"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0x0a], "vpsubusb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0xca], "vpsubusb ymm1, ymm0, ymm2"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0xca], "vpsubusb ymm1{k5}, ymm0, ymm2"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0x0a], "vpsubusb ymm1, ymm0, ymmword [rdx]"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0x0a], "vpsubusb ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0xca], "vpsubusb zmm1{k5}{z}, zmm0, zmm2"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0x0a], "vpsubusb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0xca], "vpsubusb zmm1, zmm0, zmm2"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0xca], "vpsubusb zmm1{k5}, zmm0, zmm2"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0x0a], "vpsubusb zmm1, zmm0, zmmword [rdx]"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0x0a], "vpsubusb zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0xca], "vpsubusb xmm1{k5}{z}, xmm0, xmm2"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0x0a], "vpsubusb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0xca], "vpsubusb xmm1, xmm0, xmm2"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0xca], "vpsubusb xmm1{k5}, xmm0, xmm2"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0x0a], "vpsubusb xmm1, xmm0, xmmword [rdx]"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0x0a], "vpsubusb xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0xca], "vpsubusw ymm1{k5}{z}, ymm0, ymm2"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0x0a], "vpsubusw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0xca], "vpsubusw ymm1, ymm0, ymm2"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0xca], "vpsubusw ymm1{k5}, ymm0, ymm2"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0x0a], "vpsubusw ymm1, ymm0, ymmword [rdx]"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0x0a], "vpsubusw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0xca], "vpsubusw zmm1{k5}{z}, zmm0, zmm2"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0x0a], "vpsubusw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0xca], "vpsubusw zmm1, zmm0, zmm2"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0xca], "vpsubusw zmm1{k5}, zmm0, zmm2"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0x0a], "vpsubusw zmm1, zmm0, zmmword [rdx]"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0x0a], "vpsubusw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0xca], "vpsubusw xmm1{k5}{z}, xmm0, xmm2"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0x0a], "vpsubusw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0xca], "vpsubusw xmm1, xmm0, xmm2"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0xca], "vpsubusw xmm1{k5}, xmm0, xmm2"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0x0a], "vpsubusw xmm1, xmm0, xmmword [rdx]"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0x0a], "vpsubusw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0xca], "vpminub ymm1{k5}{z}, ymm0, ymm2"); // VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0x0a], "vpminub ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0xca], "vpminub ymm1, ymm0, ymm2"); // VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0xca], "vpminub ymm1{k5}, ymm0, ymm2"); // VPMINUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0x0a], "vpminub ymm1, ymm0, ymmword [rdx]"); // VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0x0a], "vpminub ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0xca], "vpminub zmm1{k5}{z}, zmm0, zmm2"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0x0a], "vpminub zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0xca], "vpminub zmm1, zmm0, zmm2"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0xca], "vpminub zmm1{k5}, zmm0, zmm2"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0x0a], "vpminub zmm1, zmm0, zmmword [rdx]"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0x0a], "vpminub zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0xca], "vpminub xmm1{k5}{z}, xmm0, xmm2"); // VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0x0a], "vpminub xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0xca], "vpminub xmm1, xmm0, xmm2"); // VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0xca], "vpminub xmm1{k5}, xmm0, xmm2"); // VPMINUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0x0a], "vpminub xmm1, xmm0, xmmword [rdx]"); // VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0x0a], "vpminub xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdb, 0x0a], "vpandq ymm1, ymm0, qword [rdx]{1to4}"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0xca], "vpandq ymm1{k5}{z}, ymm0, ymm2"); // VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0xca], "vpandq ymm1, ymm0, ymm2"); // VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0xca], "vpandq ymm1{k5}, ymm0, ymm2"); // VPANDQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0x0a], "vpandq ymm1, ymm0, ymmword [rdx]"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, ymmword [rdx]"); // VPANDQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdb, 0x0a], "vpandd ymm1, ymm0, dword [rdx]{1to8}"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0xca], "vpandd ymm1{k5}{z}, ymm0, ymm2"); // VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0xca], "vpandd ymm1, ymm0, ymm2"); // VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0xca], "vpandd ymm1{k5}, ymm0, ymm2"); // VPANDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0x0a], "vpandd ymm1, ymm0, ymmword [rdx]"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, ymmword [rdx]"); // VPANDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdb, 0x0a], "vpandq zmm1, zmm0, qword [rdx]{1to8}"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdb, 0x0a], "vpandq xmm1, xmm0, qword [rdx]{1to2}"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0xca], "vpandq zmm1{k5}{z}, zmm0, zmm2"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0xca], "vpandq zmm1, zmm0, zmm2"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0xca], "vpandq zmm1{k5}, zmm0, zmm2"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0x0a], "vpandq zmm1, zmm0, zmmword [rdx]"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, zmmword [rdx]"); // VPANDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0xca], "vpandq xmm1{k5}{z}, xmm0, xmm2"); // VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0xca], "vpandq xmm1, xmm0, xmm2"); // VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0xca], "vpandq xmm1{k5}, xmm0, xmm2"); // VPANDQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0x0a], "vpandq xmm1, xmm0, xmmword [rdx]"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, xmmword [rdx]"); // VPANDQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdb, 0x0a], "vpandd zmm1, zmm0, dword [rdx]{1to16}"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdb, 0x0a], "vpandd xmm1, xmm0, dword [rdx]{1to4}"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0xca], "vpandd zmm1{k5}{z}, zmm0, zmm2"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0xca], "vpandd zmm1, zmm0, zmm2"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0xca], "vpandd zmm1{k5}, zmm0, zmm2"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0x0a], "vpandd zmm1, zmm0, zmmword [rdx]"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, zmmword [rdx]"); // VPANDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0xca], "vpandd xmm1{k5}{z}, xmm0, xmm2"); // VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0xca], "vpandd xmm1, xmm0, xmm2"); // VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0xca], "vpandd xmm1{k5}, xmm0, xmm2"); // VPANDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0x0a], "vpandd xmm1, xmm0, xmmword [rdx]"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, xmmword [rdx]"); // VPANDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0xca], "vpaddusb ymm1{k5}{z}, ymm0, ymm2"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0x0a], "vpaddusb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0xca], "vpaddusb ymm1, ymm0, ymm2"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0xca], "vpaddusb ymm1{k5}, ymm0, ymm2"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0x0a], "vpaddusb ymm1, ymm0, ymmword [rdx]"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0x0a], "vpaddusb ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDUSB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0xca], "vpaddusb zmm1{k5}{z}, zmm0, zmm2"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0x0a], "vpaddusb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0xca], "vpaddusb zmm1, zmm0, zmm2"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0xca], "vpaddusb zmm1{k5}, zmm0, zmm2"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0x0a], "vpaddusb zmm1, zmm0, zmmword [rdx]"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0x0a], "vpaddusb zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDUSB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0xca], "vpaddusb xmm1{k5}{z}, xmm0, xmm2"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0x0a], "vpaddusb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0xca], "vpaddusb xmm1, xmm0, xmm2"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0xca], "vpaddusb xmm1{k5}, xmm0, xmm2"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0x0a], "vpaddusb xmm1, xmm0, xmmword [rdx]"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0x0a], "vpaddusb xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDUSB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0xca], "vpaddusw ymm1{k5}{z}, ymm0, ymm2"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0x0a], "vpaddusw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0xca], "vpaddusw ymm1, ymm0, ymm2"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0xca], "vpaddusw ymm1{k5}, ymm0, ymm2"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0x0a], "vpaddusw ymm1, ymm0, ymmword [rdx]"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0x0a], "vpaddusw ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDUSW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0xca], "vpaddusw zmm1{k5}{z}, zmm0, zmm2"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0x0a], "vpaddusw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0xca], "vpaddusw zmm1, zmm0, zmm2"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0xca], "vpaddusw zmm1{k5}, zmm0, zmm2"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0x0a], "vpaddusw zmm1, zmm0, zmmword [rdx]"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0x0a], "vpaddusw zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDUSW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0xca], "vpaddusw xmm1{k5}{z}, xmm0, xmm2"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0x0a], "vpaddusw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0xca], "vpaddusw xmm1, xmm0, xmm2"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0xca], "vpaddusw xmm1{k5}, xmm0, xmm2"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0x0a], "vpaddusw xmm1, xmm0, xmmword [rdx]"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0x0a], "vpaddusw xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDUSW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0xca], "vpmaxub ymm1{k5}{z}, ymm0, ymm2"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0x0a], "vpmaxub ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0xca], "vpmaxub ymm1, ymm0, ymm2"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0xca], "vpmaxub ymm1{k5}, ymm0, ymm2"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0x0a], "vpmaxub ymm1, ymm0, ymmword [rdx]"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0x0a], "vpmaxub ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXUB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0xca], "vpmaxub zmm1{k5}{z}, zmm0, zmm2"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0x0a], "vpmaxub zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0xca], "vpmaxub zmm1, zmm0, zmm2"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0xca], "vpmaxub zmm1{k5}, zmm0, zmm2"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0x0a], "vpmaxub zmm1, zmm0, zmmword [rdx]"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0x0a], "vpmaxub zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXUB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0xca], "vpmaxub xmm1{k5}{z}, xmm0, xmm2"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0x0a], "vpmaxub xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0xca], "vpmaxub xmm1, xmm0, xmm2"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0xca], "vpmaxub xmm1{k5}, xmm0, xmm2"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0x0a], "vpmaxub xmm1, xmm0, xmmword [rdx]"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0x0a], "vpmaxub xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXUB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdf, 0x0a], "vpandnq ymm1, ymm0, qword [rdx]{1to4}"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0xca], "vpandnq ymm1{k5}{z}, ymm0, ymm2"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0xca], "vpandnq ymm1, ymm0, ymm2"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0xca], "vpandnq ymm1{k5}, ymm0, ymm2"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0x0a], "vpandnq ymm1, ymm0, ymmword [rdx]"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, ymmword [rdx]"); // VPANDNQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdf, 0x0a], "vpandnd ymm1, ymm0, dword [rdx]{1to8}"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0xca], "vpandnd ymm1{k5}{z}, ymm0, ymm2"); // VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0xca], "vpandnd ymm1, ymm0, ymm2"); // VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0xca], "vpandnd ymm1{k5}, ymm0, ymm2"); // VPANDND_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0x0a], "vpandnd ymm1, ymm0, ymmword [rdx]"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, ymmword [rdx]"); // VPANDND_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdf, 0x0a], "vpandnq zmm1, zmm0, qword [rdx]{1to8}"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdf, 0x0a], "vpandnq xmm1, xmm0, qword [rdx]{1to2}"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0xca], "vpandnq zmm1{k5}{z}, zmm0, zmm2"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0xca], "vpandnq zmm1, zmm0, zmm2"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0xca], "vpandnq zmm1{k5}, zmm0, zmm2"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0x0a], "vpandnq zmm1, zmm0, zmmword [rdx]"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, zmmword [rdx]"); // VPANDNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0xca], "vpandnq xmm1{k5}{z}, xmm0, xmm2"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0xca], "vpandnq xmm1, xmm0, xmm2"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0xca], "vpandnq xmm1{k5}, xmm0, xmm2"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0x0a], "vpandnq xmm1, xmm0, xmmword [rdx]"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, xmmword [rdx]"); // VPANDNQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdf, 0x0a], "vpandnd zmm1, zmm0, dword [rdx]{1to16}"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdf, 0x0a], "vpandnd xmm1, xmm0, dword [rdx]{1to4}"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0xca], "vpandnd zmm1{k5}{z}, zmm0, zmm2"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0xca], "vpandnd zmm1, zmm0, zmm2"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0xca], "vpandnd zmm1{k5}, zmm0, zmm2"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0x0a], "vpandnd zmm1, zmm0, zmmword [rdx]"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, zmmword [rdx]"); // VPANDND_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0xca], "vpandnd xmm1{k5}{z}, xmm0, xmm2"); // VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0xca], "vpandnd xmm1, xmm0, xmm2"); // VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0xca], "vpandnd xmm1{k5}, xmm0, xmm2"); // VPANDND_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0x0a], "vpandnd xmm1, xmm0, xmmword [rdx]"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, xmmword [rdx]"); // VPANDND_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0xca], "vpavgb ymm1{k5}{z}, ymm0, ymm2"); // VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0x0a], "vpavgb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0xca], "vpavgb ymm1, ymm0, ymm2"); // VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0xca], "vpavgb ymm1{k5}, ymm0, ymm2"); // VPAVGB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0x0a], "vpavgb ymm1, ymm0, ymmword [rdx]"); // VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0x0a], "vpavgb ymm1{k5}, ymm0, ymmword [rdx]"); // VPAVGB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0xca], "vpavgb zmm1{k5}{z}, zmm0, zmm2"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0x0a], "vpavgb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0xca], "vpavgb zmm1, zmm0, zmm2"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0xca], "vpavgb zmm1{k5}, zmm0, zmm2"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0x0a], "vpavgb zmm1, zmm0, zmmword [rdx]"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0x0a], "vpavgb zmm1{k5}, zmm0, zmmword [rdx]"); // VPAVGB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0xca], "vpavgb xmm1{k5}{z}, xmm0, xmm2"); // VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0x0a], "vpavgb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0xca], "vpavgb xmm1, xmm0, xmm2"); // VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0xca], "vpavgb xmm1{k5}, xmm0, xmm2"); // VPAVGB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0x0a], "vpavgb xmm1, xmm0, xmmword [rdx]"); // VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0x0a], "vpavgb xmm1{k5}, xmm0, xmmword [rdx]"); // VPAVGB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0xca], "vpsraw ymm1{k5}{z}, ymm0, xmm2"); // VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0x0a], "vpsraw ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0xca], "vpsraw ymm1, ymm0, xmm2"); // VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0xca], "vpsraw ymm1{k5}, ymm0, xmm2"); // VPSRAW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0x0a], "vpsraw ymm1, ymm0, xmmword [rdx]"); // VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0x0a], "vpsraw ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRAW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0xca], "vpsraw zmm1{k5}{z}, zmm0, xmm2"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0x0a], "vpsraw zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0xca], "vpsraw zmm1, zmm0, xmm2"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0xca], "vpsraw zmm1{k5}, zmm0, xmm2"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0x0a], "vpsraw zmm1, zmm0, xmmword [rdx]"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0x0a], "vpsraw zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRAW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0xca], "vpsraw xmm1{k5}{z}, xmm0, xmm2"); // VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0x0a], "vpsraw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0xca], "vpsraw xmm1, xmm0, xmm2"); // VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0xca], "vpsraw xmm1{k5}, xmm0, xmm2"); // VPSRAW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0x0a], "vpsraw xmm1, xmm0, xmmword [rdx]"); // VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0x0a], "vpsraw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0xca], "vpsraq ymm1{k5}{z}, ymm0, xmm2"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0x0a], "vpsraq ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0xca], "vpsraq ymm1, ymm0, xmm2"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0xca], "vpsraq ymm1{k5}, ymm0, xmm2"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0x0a], "vpsraq ymm1, ymm0, xmmword [rdx]"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0x0a], "vpsraq ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRAQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0xca], "vpsrad ymm1{k5}{z}, ymm0, xmm2"); // VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0x0a], "vpsrad ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0xca], "vpsrad ymm1, ymm0, xmm2"); // VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0xca], "vpsrad ymm1{k5}, ymm0, xmm2"); // VPSRAD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0x0a], "vpsrad ymm1, ymm0, xmmword [rdx]"); // VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0x0a], "vpsrad ymm1{k5}, ymm0, xmmword [rdx]"); // VPSRAD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0xca], "vpsraq zmm1{k5}{z}, zmm0, xmm2"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0x0a], "vpsraq zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0xca], "vpsraq zmm1, zmm0, xmm2"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0xca], "vpsraq zmm1{k5}, zmm0, xmm2"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0x0a], "vpsraq zmm1, zmm0, xmmword [rdx]"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0x0a], "vpsraq zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRAQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0xca], "vpsraq xmm1{k5}{z}, xmm0, xmm2"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0x0a], "vpsraq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0xca], "vpsraq xmm1, xmm0, xmm2"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0xca], "vpsraq xmm1{k5}, xmm0, xmm2"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0x0a], "vpsraq xmm1, xmm0, xmmword [rdx]"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0x0a], "vpsraq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0xca], "vpsrad zmm1{k5}{z}, zmm0, xmm2"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0x0a], "vpsrad zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0xca], "vpsrad zmm1, zmm0, xmm2"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0xca], "vpsrad zmm1{k5}, zmm0, xmm2"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0x0a], "vpsrad zmm1, zmm0, xmmword [rdx]"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0x0a], "vpsrad zmm1{k5}, zmm0, xmmword [rdx]"); // VPSRAD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0xca], "vpsrad xmm1{k5}{z}, xmm0, xmm2"); // VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0x0a], "vpsrad xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0xca], "vpsrad xmm1, xmm0, xmm2"); // VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0xca], "vpsrad xmm1{k5}, xmm0, xmm2"); // VPSRAD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0x0a], "vpsrad xmm1, xmm0, xmmword [rdx]"); // VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0x0a], "vpsrad xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0xca], "vpavgw ymm1{k5}{z}, ymm0, ymm2"); // VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0x0a], "vpavgw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0xca], "vpavgw ymm1, ymm0, ymm2"); // VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0xca], "vpavgw ymm1{k5}, ymm0, ymm2"); // VPAVGW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0x0a], "vpavgw ymm1, ymm0, ymmword [rdx]"); // VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0x0a], "vpavgw ymm1{k5}, ymm0, ymmword [rdx]"); // VPAVGW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0xca], "vpavgw zmm1{k5}{z}, zmm0, zmm2"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0x0a], "vpavgw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0xca], "vpavgw zmm1, zmm0, zmm2"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0xca], "vpavgw zmm1{k5}, zmm0, zmm2"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0x0a], "vpavgw zmm1, zmm0, zmmword [rdx]"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0x0a], "vpavgw zmm1{k5}, zmm0, zmmword [rdx]"); // VPAVGW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0xca], "vpavgw xmm1{k5}{z}, xmm0, xmm2"); // VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0x0a], "vpavgw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0xca], "vpavgw xmm1, xmm0, xmm2"); // VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0xca], "vpavgw xmm1{k5}, xmm0, xmm2"); // VPAVGW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0x0a], "vpavgw xmm1, xmm0, xmmword [rdx]"); // VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0x0a], "vpavgw xmm1{k5}, xmm0, xmmword [rdx]"); // VPAVGW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0xca], "vpmulhuw ymm1{k5}{z}, ymm0, ymm2"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0x0a], "vpmulhuw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0xca], "vpmulhuw ymm1, ymm0, ymm2"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0xca], "vpmulhuw ymm1{k5}, ymm0, ymm2"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0x0a], "vpmulhuw ymm1, ymm0, ymmword [rdx]"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0x0a], "vpmulhuw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULHUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0xca], "vpmulhuw zmm1{k5}{z}, zmm0, zmm2"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0x0a], "vpmulhuw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0xca], "vpmulhuw zmm1, zmm0, zmm2"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0xca], "vpmulhuw zmm1{k5}, zmm0, zmm2"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0x0a], "vpmulhuw zmm1, zmm0, zmmword [rdx]"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0x0a], "vpmulhuw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULHUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0xca], "vpmulhuw xmm1{k5}{z}, xmm0, xmm2"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0xca], "vpmulhuw xmm1, xmm0, xmm2"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0xca], "vpmulhuw xmm1{k5}, xmm0, xmm2"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0x0a], "vpmulhuw xmm1, xmm0, xmmword [rdx]"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULHUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0xca], "vpmulhw ymm1{k5}{z}, ymm0, ymm2"); // VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0x0a], "vpmulhw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0xca], "vpmulhw ymm1, ymm0, ymm2"); // VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0xca], "vpmulhw ymm1{k5}, ymm0, ymm2"); // VPMULHW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0x0a], "vpmulhw ymm1, ymm0, ymmword [rdx]"); // VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0x0a], "vpmulhw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULHW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0xca], "vpmulhw zmm1{k5}{z}, zmm0, zmm2"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0x0a], "vpmulhw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0xca], "vpmulhw zmm1, zmm0, zmm2"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0xca], "vpmulhw zmm1{k5}, zmm0, zmm2"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0x0a], "vpmulhw zmm1, zmm0, zmmword [rdx]"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0x0a], "vpmulhw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULHW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0xca], "vpmulhw xmm1{k5}{z}, xmm0, xmm2"); // VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0x0a], "vpmulhw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0xca], "vpmulhw xmm1, xmm0, xmm2"); // VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0xca], "vpmulhw xmm1{k5}, xmm0, xmm2"); // VPMULHW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0x0a], "vpmulhw xmm1, xmm0, xmmword [rdx]"); // VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x0a], "vpmulhw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULHW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xe6, 0xca], "vcvttpd2dq ymm1{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{sae}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [rdx]{1to4}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, ymm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, ymmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0xca], "vcvttpd2dq xmm1, ymm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, ymm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0x0a], "vcvttpd2dq xmm1, ymmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, ymmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xe6, 0x0a], "vcvttpd2dq ymm1, qword [rdx]{1to8}"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, qword [rdx]{1to8}"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [rdx]{1to2}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [rdx]{1to2}"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, zmmword [rdx]"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0xca], "vcvttpd2dq ymm1, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}, zmm2"); // VCVTTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0x0a], "vcvttpd2dq ymm1, zmmword [rdx]"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, zmmword [rdx]"); // VCVTTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, xmm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0xca], "vcvttpd2dq xmm1, xmm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, xmm2"); // VCVTTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0x0a], "vcvttpd2dq xmm1, xmmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, xmmword [rdx]"); // VCVTTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x0a], "vmovntdq ymmword [rdx], ymm1"); // VMOVNTDQ_MEMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x0a], "vmovntdq zmmword [rdx], zmm1"); // VMOVNTDQ_MEMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x0a], "vmovntdq xmmword [rdx], xmm1"); // VMOVNTDQ_MEMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0xca], "vpsubsb ymm1{k5}{z}, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x0a], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0xca], "vpsubsb ymm1{k5}, ymm0, ymm2"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0x0a], "vpsubsb ymm1, ymm0, ymmword [rdx]"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0x0a], "vpsubsb ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0xca], "vpsubsb zmm1{k5}{z}, zmm0, zmm2"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0x0a], "vpsubsb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0xca], "vpsubsb zmm1, zmm0, zmm2"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0xca], "vpsubsb zmm1{k5}, zmm0, zmm2"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0x0a], "vpsubsb zmm1, zmm0, zmmword [rdx]"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0x0a], "vpsubsb zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0xca], "vpsubsb xmm1{k5}{z}, xmm0, xmm2"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0x0a], "vpsubsb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0xca], "vpsubsb xmm1, xmm0, xmm2"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0xca], "vpsubsb xmm1{k5}, xmm0, xmm2"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0x0a], "vpsubsb xmm1, xmm0, xmmword [rdx]"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0x0a], "vpsubsb xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0xca], "vpsubsw ymm1{k5}{z}, ymm0, ymm2"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0x0a], "vpsubsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0xca], "vpsubsw ymm1, ymm0, ymm2"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0xca], "vpsubsw ymm1{k5}, ymm0, ymm2"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0x0a], "vpsubsw ymm1, ymm0, ymmword [rdx]"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0x0a], "vpsubsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0xca], "vpsubsw zmm1{k5}{z}, zmm0, zmm2"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0x0a], "vpsubsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0xca], "vpsubsw zmm1, zmm0, zmm2"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0xca], "vpsubsw zmm1{k5}, zmm0, zmm2"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0x0a], "vpsubsw zmm1, zmm0, zmmword [rdx]"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0x0a], "vpsubsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0xca], "vpsubsw xmm1{k5}{z}, xmm0, xmm2"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0x0a], "vpsubsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0xca], "vpsubsw xmm1, xmm0, xmm2"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0xca], "vpsubsw xmm1{k5}, xmm0, xmm2"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0x0a], "vpsubsw xmm1, xmm0, xmmword [rdx]"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0x0a], "vpsubsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0xca], "vpminsw ymm1{k5}{z}, ymm0, ymm2"); // VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0x0a], "vpminsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0xca], "vpminsw ymm1, ymm0, ymm2"); // VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0xca], "vpminsw ymm1{k5}, ymm0, ymm2"); // VPMINSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0x0a], "vpminsw ymm1, ymm0, ymmword [rdx]"); // VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0x0a], "vpminsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0xca], "vpminsw zmm1{k5}{z}, zmm0, zmm2"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0x0a], "vpminsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0xca], "vpminsw zmm1, zmm0, zmm2"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0xca], "vpminsw zmm1{k5}, zmm0, zmm2"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0x0a], "vpminsw zmm1, zmm0, zmmword [rdx]"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0x0a], "vpminsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0xca], "vpminsw xmm1{k5}{z}, xmm0, xmm2"); // VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0x0a], "vpminsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0xca], "vpminsw xmm1, xmm0, xmm2"); // VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0xca], "vpminsw xmm1{k5}, xmm0, xmm2"); // VPMINSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0x0a], "vpminsw xmm1, xmm0, xmmword [rdx]"); // VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0x0a], "vpminsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xeb, 0x0a], "vporq ymm1, ymm0, qword [rdx]{1to4}"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0xca], "vporq ymm1{k5}{z}, ymm0, ymm2"); // VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0xca], "vporq ymm1, ymm0, ymm2"); // VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0xca], "vporq ymm1{k5}, ymm0, ymm2"); // VPORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0x0a], "vporq ymm1, ymm0, ymmword [rdx]"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, ymmword [rdx]"); // VPORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xeb, 0x0a], "vpord ymm1, ymm0, dword [rdx]{1to8}"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0xca], "vpord ymm1{k5}{z}, ymm0, ymm2"); // VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0xca], "vpord ymm1, ymm0, ymm2"); // VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0xca], "vpord ymm1{k5}, ymm0, ymm2"); // VPORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0x0a], "vpord ymm1, ymm0, ymmword [rdx]"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, ymmword [rdx]"); // VPORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xeb, 0x0a], "vporq zmm1, zmm0, qword [rdx]{1to8}"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xeb, 0x0a], "vporq xmm1, xmm0, qword [rdx]{1to2}"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0xca], "vporq zmm1{k5}{z}, zmm0, zmm2"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0xca], "vporq zmm1, zmm0, zmm2"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0xca], "vporq zmm1{k5}, zmm0, zmm2"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0x0a], "vporq zmm1, zmm0, zmmword [rdx]"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, zmmword [rdx]"); // VPORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0xca], "vporq xmm1{k5}{z}, xmm0, xmm2"); // VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0xca], "vporq xmm1, xmm0, xmm2"); // VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0xca], "vporq xmm1{k5}, xmm0, xmm2"); // VPORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0x0a], "vporq xmm1, xmm0, xmmword [rdx]"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, xmmword [rdx]"); // VPORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xeb, 0x0a], "vpord zmm1, zmm0, dword [rdx]{1to16}"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xeb, 0x0a], "vpord xmm1, xmm0, dword [rdx]{1to4}"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0xca], "vpord zmm1{k5}{z}, zmm0, zmm2"); // VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0xca], "vpord zmm1, zmm0, zmm2"); // VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0xca], "vpord zmm1{k5}, zmm0, zmm2"); // VPORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0x0a], "vpord zmm1, zmm0, zmmword [rdx]"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, zmmword [rdx]"); // VPORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0xca], "vpord xmm1{k5}{z}, xmm0, xmm2"); // VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0xca], "vpord xmm1, xmm0, xmm2"); // VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0xca], "vpord xmm1{k5}, xmm0, xmm2"); // VPORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0x0a], "vpord xmm1, xmm0, xmmword [rdx]"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, xmmword [rdx]"); // VPORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0xca], "vpaddsb ymm1{k5}{z}, ymm0, ymm2"); // VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0x0a], "vpaddsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0xca], "vpaddsb ymm1, ymm0, ymm2"); // VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0xca], "vpaddsb ymm1{k5}, ymm0, ymm2"); // VPADDSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0x0a], "vpaddsb ymm1, ymm0, ymmword [rdx]"); // VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0x0a], "vpaddsb ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0xca], "vpaddsb zmm1{k5}{z}, zmm0, zmm2"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0x0a], "vpaddsb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0xca], "vpaddsb zmm1, zmm0, zmm2"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0xca], "vpaddsb zmm1{k5}, zmm0, zmm2"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0x0a], "vpaddsb zmm1, zmm0, zmmword [rdx]"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0x0a], "vpaddsb zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0xca], "vpaddsb xmm1{k5}{z}, xmm0, xmm2"); // VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0x0a], "vpaddsb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0xca], "vpaddsb xmm1, xmm0, xmm2"); // VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0xca], "vpaddsb xmm1{k5}, xmm0, xmm2"); // VPADDSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0x0a], "vpaddsb xmm1, xmm0, xmmword [rdx]"); // VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0x0a], "vpaddsb xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0xca], "vpaddsw ymm1{k5}{z}, ymm0, ymm2"); // VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0x0a], "vpaddsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0xca], "vpaddsw ymm1, ymm0, ymm2"); // VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0xca], "vpaddsw ymm1{k5}, ymm0, ymm2"); // VPADDSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0x0a], "vpaddsw ymm1, ymm0, ymmword [rdx]"); // VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0x0a], "vpaddsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0xca], "vpaddsw zmm1{k5}{z}, zmm0, zmm2"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0x0a], "vpaddsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0xca], "vpaddsw zmm1, zmm0, zmm2"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0xca], "vpaddsw zmm1{k5}, zmm0, zmm2"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0x0a], "vpaddsw zmm1, zmm0, zmmword [rdx]"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0x0a], "vpaddsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0xca], "vpaddsw xmm1{k5}{z}, xmm0, xmm2"); // VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0x0a], "vpaddsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0xca], "vpaddsw xmm1, xmm0, xmm2"); // VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0xca], "vpaddsw xmm1{k5}, xmm0, xmm2"); // VPADDSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0x0a], "vpaddsw xmm1, xmm0, xmmword [rdx]"); // VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0x0a], "vpaddsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0xca], "vpmaxsw ymm1{k5}{z}, ymm0, ymm2"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0x0a], "vpmaxsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0xca], "vpmaxsw ymm1, ymm0, ymm2"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0xca], "vpmaxsw ymm1{k5}, ymm0, ymm2"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0x0a], "vpmaxsw ymm1, ymm0, ymmword [rdx]"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0x0a], "vpmaxsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0xca], "vpmaxsw zmm1{k5}{z}, zmm0, zmm2"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0x0a], "vpmaxsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0xca], "vpmaxsw zmm1, zmm0, zmm2"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0xca], "vpmaxsw zmm1{k5}, zmm0, zmm2"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0x0a], "vpmaxsw zmm1, zmm0, zmmword [rdx]"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0x0a], "vpmaxsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0xca], "vpmaxsw xmm1{k5}{z}, xmm0, xmm2"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0x0a], "vpmaxsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0xca], "vpmaxsw xmm1, xmm0, xmm2"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0xca], "vpmaxsw xmm1{k5}, xmm0, xmm2"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0x0a], "vpmaxsw xmm1, xmm0, xmmword [rdx]"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0x0a], "vpmaxsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xef, 0x0a], "vpxorq ymm1, ymm0, qword [rdx]{1to4}"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0xca], "vpxorq ymm1{k5}{z}, ymm0, ymm2"); // VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0xca], "vpxorq ymm1, ymm0, ymm2"); // VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0xca], "vpxorq ymm1{k5}, ymm0, ymm2"); // VPXORQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0x0a], "vpxorq ymm1, ymm0, ymmword [rdx]"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, ymmword [rdx]"); // VPXORQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xef, 0x0a], "vpxord ymm1, ymm0, dword [rdx]{1to8}"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0xca], "vpxord ymm1{k5}{z}, ymm0, ymm2"); // VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0xca], "vpxord ymm1, ymm0, ymm2"); // VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0xca], "vpxord ymm1{k5}, ymm0, ymm2"); // VPXORD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0x0a], "vpxord ymm1, ymm0, ymmword [rdx]"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, ymmword [rdx]"); // VPXORD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xef, 0x0a], "vpxorq zmm1, zmm0, qword [rdx]{1to8}"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xef, 0x0a], "vpxorq xmm1, xmm0, qword [rdx]{1to2}"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0xca], "vpxorq zmm1{k5}{z}, zmm0, zmm2"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0xca], "vpxorq zmm1, zmm0, zmm2"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0xca], "vpxorq zmm1{k5}, zmm0, zmm2"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0x0a], "vpxorq zmm1, zmm0, zmmword [rdx]"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, zmmword [rdx]"); // VPXORQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0xca], "vpxorq xmm1{k5}{z}, xmm0, xmm2"); // VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0xca], "vpxorq xmm1, xmm0, xmm2"); // VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0xca], "vpxorq xmm1{k5}, xmm0, xmm2"); // VPXORQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0x0a], "vpxorq xmm1, xmm0, xmmword [rdx]"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, xmmword [rdx]"); // VPXORQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xef, 0x0a], "vpxord zmm1, zmm0, dword [rdx]{1to16}"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xef, 0x0a], "vpxord xmm1, xmm0, dword [rdx]{1to4}"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0xca], "vpxord zmm1{k5}{z}, zmm0, zmm2"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0xca], "vpxord zmm1, zmm0, zmm2"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0xca], "vpxord zmm1{k5}, zmm0, zmm2"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0x0a], "vpxord zmm1, zmm0, zmmword [rdx]"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, zmmword [rdx]"); // VPXORD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0xca], "vpxord xmm1{k5}{z}, xmm0, xmm2"); // VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0xca], "vpxord xmm1, xmm0, xmm2"); // VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0xca], "vpxord xmm1{k5}, xmm0, xmm2"); // VPXORD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0x0a], "vpxord xmm1, xmm0, xmmword [rdx]"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, xmmword [rdx]"); // VPXORD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0xca], "vpsllw ymm1{k5}{z}, ymm0, xmm2"); // VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0x0a], "vpsllw ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0xca], "vpsllw ymm1, ymm0, xmm2"); // VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0xca], "vpsllw ymm1{k5}, ymm0, xmm2"); // VPSLLW_YMMu16_MASKmskw_YMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0x0a], "vpsllw ymm1, ymm0, xmmword [rdx]"); // VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0x0a], "vpsllw ymm1{k5}, ymm0, xmmword [rdx]"); // VPSLLW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0xca], "vpsllw zmm1{k5}{z}, zmm0, xmm2"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0x0a], "vpsllw zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0xca], "vpsllw zmm1, zmm0, xmm2"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0xca], "vpsllw zmm1{k5}, zmm0, xmm2"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0x0a], "vpsllw zmm1, zmm0, xmmword [rdx]"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0x0a], "vpsllw zmm1{k5}, zmm0, xmmword [rdx]"); // VPSLLW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0xca], "vpsllw xmm1{k5}{z}, xmm0, xmm2"); // VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0x0a], "vpsllw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0xca], "vpsllw xmm1, xmm0, xmm2"); // VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0xca], "vpsllw xmm1{k5}, xmm0, xmm2"); // VPSLLW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0x0a], "vpsllw xmm1, xmm0, xmmword [rdx]"); // VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0x0a], "vpsllw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0xca], "vpslld ymm1{k5}{z}, ymm0, xmm2"); // VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0x0a], "vpslld ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0xca], "vpslld ymm1, ymm0, xmm2"); // VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0xca], "vpslld ymm1{k5}, ymm0, xmm2"); // VPSLLD_YMMu32_MASKmskw_YMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0x0a], "vpslld ymm1, ymm0, xmmword [rdx]"); // VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0x0a], "vpslld ymm1{k5}, ymm0, xmmword [rdx]"); // VPSLLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0xca], "vpslld zmm1{k5}{z}, zmm0, xmm2"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0x0a], "vpslld zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0xca], "vpslld zmm1, zmm0, xmm2"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0xca], "vpslld zmm1{k5}, zmm0, xmm2"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0x0a], "vpslld zmm1, zmm0, xmmword [rdx]"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0x0a], "vpslld zmm1{k5}, zmm0, xmmword [rdx]"); // VPSLLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0xca], "vpslld xmm1{k5}{z}, xmm0, xmm2"); // VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0x0a], "vpslld xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0xca], "vpslld xmm1, xmm0, xmm2"); // VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0xca], "vpslld xmm1{k5}, xmm0, xmm2"); // VPSLLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0x0a], "vpslld xmm1, xmm0, xmmword [rdx]"); // VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0x0a], "vpslld xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0xca], "vpsllq ymm1{k5}{z}, ymm0, xmm2"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0x0a], "vpsllq ymm1{k5}{z}, ymm0, xmmword [rdx]"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0xca], "vpsllq ymm1, ymm0, xmm2"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0xca], "vpsllq ymm1{k5}, ymm0, xmm2"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0x0a], "vpsllq ymm1, ymm0, xmmword [rdx]"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0x0a], "vpsllq ymm1{k5}, ymm0, xmmword [rdx]"); // VPSLLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0xca], "vpsllq zmm1{k5}{z}, zmm0, xmm2"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0x0a], "vpsllq zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0xca], "vpsllq zmm1, zmm0, xmm2"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0xca], "vpsllq zmm1{k5}, zmm0, xmm2"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0x0a], "vpsllq zmm1, zmm0, xmmword [rdx]"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0x0a], "vpsllq zmm1{k5}, zmm0, xmmword [rdx]"); // VPSLLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0xca], "vpsllq xmm1{k5}{z}, xmm0, xmm2"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0x0a], "vpsllq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0xca], "vpsllq xmm1, xmm0, xmm2"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0xca], "vpsllq xmm1{k5}, xmm0, xmm2"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0x0a], "vpsllq xmm1, xmm0, xmmword [rdx]"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0x0a], "vpsllq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, qword [rdx]{1to4}"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0xca], "vpmuludq ymm1{k5}{z}, ymm0, ymm2"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0xca], "vpmuludq ymm1, ymm0, ymm2"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0xca], "vpmuludq ymm1{k5}, ymm0, ymm2"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, ymmword [rdx]"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULUDQ_YMMu64_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, qword [rdx]{1to8}"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, qword [rdx]{1to2}"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0xca], "vpmuludq zmm1{k5}{z}, zmm0, zmm2"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0xca], "vpmuludq zmm1, zmm0, zmm2"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0xca], "vpmuludq zmm1{k5}, zmm0, zmm2"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, zmmword [rdx]"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULUDQ_ZMMu64_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0xca], "vpmuludq xmm1{k5}{z}, xmm0, xmm2"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0xca], "vpmuludq xmm1, xmm0, xmm2"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0xca], "vpmuludq xmm1{k5}, xmm0, xmm2"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, xmmword [rdx]"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULUDQ_XMMu64_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0xca], "vpmaddwd ymm1{k5}{z}, ymm0, ymm2"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0x0a], "vpmaddwd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0xca], "vpmaddwd ymm1, ymm0, ymm2"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0xca], "vpmaddwd ymm1{k5}, ymm0, ymm2"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0x0a], "vpmaddwd ymm1, ymm0, ymmword [rdx]"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0x0a], "vpmaddwd ymm1{k5}, ymm0, ymmword [rdx]"); // VPMADDWD_YMMi32_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0xca], "vpmaddwd zmm1{k5}{z}, zmm0, zmm2"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0x0a], "vpmaddwd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0xca], "vpmaddwd zmm1, zmm0, zmm2"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0xca], "vpmaddwd zmm1{k5}, zmm0, zmm2"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0x0a], "vpmaddwd zmm1, zmm0, zmmword [rdx]"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0x0a], "vpmaddwd zmm1{k5}, zmm0, zmmword [rdx]"); // VPMADDWD_ZMMi32_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0xca], "vpmaddwd xmm1{k5}{z}, xmm0, xmm2"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0xca], "vpmaddwd xmm1, xmm0, xmm2"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0xca], "vpmaddwd xmm1{k5}, xmm0, xmm2"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0x0a], "vpmaddwd xmm1, xmm0, xmmword [rdx]"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADDWD_XMMi32_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); // VPSADBW_YMMu16_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x0a], "vpsadbw ymm1, ymm0, ymmword [rdx]"); // VPSADBW_YMMu16_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0xca], "vpsadbw zmm1, zmm0, zmm2"); // VPSADBW_ZMMu16_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x0a], "vpsadbw zmm1, zmm0, zmmword [rdx]"); // VPSADBW_ZMMu16_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); // VPSADBW_XMMu16_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0x0a], "vpsadbw xmm1, xmm0, xmmword [rdx]"); // VPSADBW_XMMu16_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0xca], "vpsubb ymm1{k5}{z}, ymm0, ymm2"); // VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0x0a], "vpsubb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0xca], "vpsubb ymm1, ymm0, ymm2"); // VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0xca], "vpsubb ymm1{k5}, ymm0, ymm2"); // VPSUBB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0x0a], "vpsubb ymm1, ymm0, ymmword [rdx]"); // VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0x0a], "vpsubb ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0xca], "vpsubb zmm1{k5}{z}, zmm0, zmm2"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0x0a], "vpsubb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0xca], "vpsubb zmm1, zmm0, zmm2"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0xca], "vpsubb zmm1{k5}, zmm0, zmm2"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0x0a], "vpsubb zmm1, zmm0, zmmword [rdx]"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0x0a], "vpsubb zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0xca], "vpsubb xmm1{k5}{z}, xmm0, xmm2"); // VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0x0a], "vpsubb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0xca], "vpsubb xmm1, xmm0, xmm2"); // VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0xca], "vpsubb xmm1{k5}, xmm0, xmm2"); // VPSUBB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0x0a], "vpsubb xmm1, xmm0, xmmword [rdx]"); // VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0x0a], "vpsubb xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0xca], "vpsubw ymm1{k5}{z}, ymm0, ymm2"); // VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0x0a], "vpsubw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0xca], "vpsubw ymm1, ymm0, ymm2"); // VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0xca], "vpsubw ymm1{k5}, ymm0, ymm2"); // VPSUBW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0x0a], "vpsubw ymm1, ymm0, ymmword [rdx]"); // VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0x0a], "vpsubw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0xca], "vpsubw zmm1{k5}{z}, zmm0, zmm2"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0x0a], "vpsubw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0xca], "vpsubw zmm1, zmm0, zmm2"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0xca], "vpsubw zmm1{k5}, zmm0, zmm2"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0x0a], "vpsubw zmm1, zmm0, zmmword [rdx]"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0x0a], "vpsubw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0xca], "vpsubw xmm1{k5}{z}, xmm0, xmm2"); // VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0x0a], "vpsubw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0xca], "vpsubw xmm1, xmm0, xmm2"); // VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0xca], "vpsubw xmm1{k5}, xmm0, xmm2"); // VPSUBW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0x0a], "vpsubw xmm1, xmm0, xmmword [rdx]"); // VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0x0a], "vpsubw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfa, 0x0a], "vpsubd ymm1, ymm0, dword [rdx]{1to8}"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0xca], "vpsubd ymm1{k5}{z}, ymm0, ymm2"); // VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0xca], "vpsubd ymm1, ymm0, ymm2"); // VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0xca], "vpsubd ymm1{k5}, ymm0, ymm2"); // VPSUBD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0x0a], "vpsubd ymm1, ymm0, ymmword [rdx]"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfa, 0x0a], "vpsubd zmm1, zmm0, dword [rdx]{1to16}"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfa, 0x0a], "vpsubd xmm1, xmm0, dword [rdx]{1to4}"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0xca], "vpsubd zmm1{k5}{z}, zmm0, zmm2"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0xca], "vpsubd zmm1, zmm0, zmm2"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0xca], "vpsubd zmm1{k5}, zmm0, zmm2"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0x0a], "vpsubd zmm1, zmm0, zmmword [rdx]"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0xca], "vpsubd xmm1{k5}{z}, xmm0, xmm2"); // VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0xca], "vpsubd xmm1, xmm0, xmm2"); // VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0xca], "vpsubd xmm1{k5}, xmm0, xmm2"); // VPSUBD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0x0a], "vpsubd xmm1, xmm0, xmmword [rdx]"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xfb, 0x0a], "vpsubq ymm1, ymm0, qword [rdx]{1to4}"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0xca], "vpsubq ymm1{k5}{z}, ymm0, ymm2"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0xca], "vpsubq ymm1, ymm0, ymm2"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0xca], "vpsubq ymm1{k5}, ymm0, ymm2"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0x0a], "vpsubq ymm1, ymm0, ymmword [rdx]"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSUBQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xfb, 0x0a], "vpsubq zmm1, zmm0, qword [rdx]{1to8}"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xfb, 0x0a], "vpsubq xmm1, xmm0, qword [rdx]{1to2}"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0xca], "vpsubq zmm1{k5}{z}, zmm0, zmm2"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0xca], "vpsubq zmm1, zmm0, zmm2"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0xca], "vpsubq zmm1{k5}, zmm0, zmm2"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0x0a], "vpsubq zmm1, zmm0, zmmword [rdx]"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSUBQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0xca], "vpsubq xmm1{k5}{z}, xmm0, xmm2"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0xca], "vpsubq xmm1, xmm0, xmm2"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0xca], "vpsubq xmm1{k5}, xmm0, xmm2"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0x0a], "vpsubq xmm1, xmm0, xmmword [rdx]"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSUBQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0xca], "vpaddb ymm1{k5}{z}, ymm0, ymm2"); // VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0x0a], "vpaddb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0xca], "vpaddb ymm1, ymm0, ymm2"); // VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0xca], "vpaddb ymm1{k5}, ymm0, ymm2"); // VPADDB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0x0a], "vpaddb ymm1, ymm0, ymmword [rdx]"); // VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0x0a], "vpaddb ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0xca], "vpaddb zmm1{k5}{z}, zmm0, zmm2"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0x0a], "vpaddb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0xca], "vpaddb zmm1, zmm0, zmm2"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0xca], "vpaddb zmm1{k5}, zmm0, zmm2"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0x0a], "vpaddb zmm1, zmm0, zmmword [rdx]"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0x0a], "vpaddb zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0xca], "vpaddb xmm1{k5}{z}, xmm0, xmm2"); // VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0x0a], "vpaddb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0xca], "vpaddb xmm1, xmm0, xmm2"); // VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0xca], "vpaddb xmm1{k5}, xmm0, xmm2"); // VPADDB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0x0a], "vpaddb xmm1, xmm0, xmmword [rdx]"); // VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0x0a], "vpaddb xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0xca], "vpaddw ymm1{k5}{z}, ymm0, ymm2"); // VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0x0a], "vpaddw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0xca], "vpaddw ymm1, ymm0, ymm2"); // VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0xca], "vpaddw ymm1{k5}, ymm0, ymm2"); // VPADDW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0x0a], "vpaddw ymm1, ymm0, ymmword [rdx]"); // VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0x0a], "vpaddw ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0xca], "vpaddw zmm1{k5}{z}, zmm0, zmm2"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0x0a], "vpaddw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0xca], "vpaddw zmm1, zmm0, zmm2"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0xca], "vpaddw zmm1{k5}, zmm0, zmm2"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0x0a], "vpaddw zmm1, zmm0, zmmword [rdx]"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0x0a], "vpaddw zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0xca], "vpaddw xmm1{k5}{z}, xmm0, xmm2"); // VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0x0a], "vpaddw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0xca], "vpaddw xmm1, xmm0, xmm2"); // VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0xca], "vpaddw xmm1{k5}, xmm0, xmm2"); // VPADDW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0x0a], "vpaddw xmm1, xmm0, xmmword [rdx]"); // VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0x0a], "vpaddw xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfe, 0x0a], "vpaddd ymm1, ymm0, dword [rdx]{1to8}"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0xca], "vpaddd ymm1{k5}{z}, ymm0, ymm2"); // VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0xca], "vpaddd ymm1, ymm0, ymm2"); // VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0xca], "vpaddd ymm1{k5}, ymm0, ymm2"); // VPADDD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0x0a], "vpaddd ymm1, ymm0, ymmword [rdx]"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, ymmword [rdx]"); // VPADDD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfe, 0x0a], "vpaddd zmm1, zmm0, dword [rdx]{1to16}"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfe, 0x0a], "vpaddd xmm1, xmm0, dword [rdx]{1to4}"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0xca], "vpaddd zmm1{k5}{z}, zmm0, zmm2"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0xca], "vpaddd zmm1, zmm0, zmm2"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0xca], "vpaddd zmm1{k5}, zmm0, zmm2"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x0a], "vpaddd zmm1, zmm0, zmmword [rdx]"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, zmmword [rdx]"); // VPADDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0xca], "vpaddd xmm1{k5}{z}, xmm0, xmm2"); // VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0xca], "vpaddd xmm1, xmm0, xmm2"); // VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0xca], "vpaddd xmm1{k5}, xmm0, xmm2"); // VPADDD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0x0a], "vpaddd xmm1, xmm0, xmmword [rdx]"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, xmmword [rdx]"); // VPADDD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX } #[test] fn tests_f2_0f() { test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0xca], "vmovss xmm1{k5}{z}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x0a], "vmovss xmm1{k5}{z}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0xca], "vmovss xmm1, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0xca], "vmovss xmm1{k5}, xmm0, xmm2"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x0a], "vmovss xmm1, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x0a], "vmovss xmm1{k5}, dword [rdx]"); // VMOVSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0xca], "vmovss xmm2{k5}{z}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0xca], "vmovss xmm2, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0xca], "vmovss xmm2{k5}, xmm0, xmm1"); // VMOVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x0a], "vmovss dword [rdx], xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x0a], "vmovss dword [rdx]{k5}, xmm1"); // VMOVSS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0xca], "vmovsldup ymm1{k5}{z}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x0a], "vmovsldup ymm1{k5}{z}, ymmword [rdx]"); // VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0xca], "vmovsldup ymm1, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0xca], "vmovsldup ymm1{k5}, ymm2"); // VMOVSLDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0x0a], "vmovsldup ymm1, ymmword [rdx]"); // VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0x0a], "vmovsldup ymm1{k5}, ymmword [rdx]"); // VMOVSLDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0xca], "vmovsldup zmm1{k5}{z}, zmm2"); // VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0x0a], "vmovsldup zmm1{k5}{z}, zmmword [rdx]"); // VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0xca], "vmovsldup zmm1, zmm2"); // VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0xca], "vmovsldup zmm1{k5}, zmm2"); // VMOVSLDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0x0a], "vmovsldup zmm1, zmmword [rdx]"); // VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0x0a], "vmovsldup zmm1{k5}, zmmword [rdx]"); // VMOVSLDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0xca], "vmovsldup xmm1{k5}{z}, xmm2"); // VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0x0a], "vmovsldup xmm1{k5}{z}, xmmword [rdx]"); // VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0xca], "vmovsldup xmm1, xmm2"); // VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0xca], "vmovsldup xmm1{k5}, xmm2"); // VMOVSLDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0x0a], "vmovsldup xmm1, xmmword [rdx]"); // VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0x0a], "vmovsldup xmm1{k5}, xmmword [rdx]"); // VMOVSLDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0xca], "vmovshdup ymm1{k5}{z}, ymm2"); // VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0x0a], "vmovshdup ymm1{k5}{z}, ymmword [rdx]"); // VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0xca], "vmovshdup ymm1, ymm2"); // VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0xca], "vmovshdup ymm1{k5}, ymm2"); // VMOVSHDUP_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0x0a], "vmovshdup ymm1, ymmword [rdx]"); // VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0x0a], "vmovshdup ymm1{k5}, ymmword [rdx]"); // VMOVSHDUP_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0xca], "vmovshdup zmm1{k5}{z}, zmm2"); // VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0x0a], "vmovshdup zmm1{k5}{z}, zmmword [rdx]"); // VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0xca], "vmovshdup zmm1, zmm2"); // VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0xca], "vmovshdup zmm1{k5}, zmm2"); // VMOVSHDUP_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0x0a], "vmovshdup zmm1, zmmword [rdx]"); // VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0x0a], "vmovshdup zmm1{k5}, zmmword [rdx]"); // VMOVSHDUP_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0xca], "vmovshdup xmm1{k5}{z}, xmm2"); // VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0x0a], "vmovshdup xmm1{k5}{z}, xmmword [rdx]"); // VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0xca], "vmovshdup xmm1, xmm2"); // VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0xca], "vmovshdup xmm1{k5}, xmm2"); // VMOVSHDUP_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0x0a], "vmovshdup xmm1, xmmword [rdx]"); // VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0x0a], "vmovshdup xmm1{k5}, xmmword [rdx]"); // VMOVSHDUP_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, qword [rdx]"); // VCVTSI2SS_XMMf32_XMMf32_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, dword [rdx]"); // VCVTSI2SS_XMMf32_XMMf32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x2a, 0xca], "vcvtsi2ss xmm1{ru-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, rdx"); // VCVTSI2SS_XMMf32_XMMf32_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x2a, 0xca], "vcvtsi2ss xmm1{ru-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTSI2SS_XMMf32_XMMf32_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2c, 0xca], "vcvttss2si rcx{sae}, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si rcx, xmm2"); // VCVTTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si rcx, dword [rdx]"); // VCVTTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); // VCVTTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2c, 0x0a], "vcvttss2si ecx, dword [rdx]"); // VCVTTSS2SI_GPR32i32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2d, 0xca], "vcvtss2si rcx{rz-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0xca], "vcvtss2si rcx{rd-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si rcx, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si rcx, dword [rdx]"); // VCVTSS2SI_GPR64i64_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x2d, 0x0a], "vcvtss2si ecx, dword [rdx]"); // VCVTSS2SI_GPR32i32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x2d, 0xca], "vcvtss2si rcx{ru-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x2d, 0xca], "vcvtss2si rcx{rne-sae}, xmm2"); // VCVTSS2SI_GPR64i64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x2d, 0xca], "vcvtss2si ecx{ru-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x2d, 0xca], "vcvtss2si ecx{rne-sae}, xmm2"); // VCVTSS2SI_GPR32i32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x51, 0xca], "vsqrtss xmm1{rz-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x51, 0xca], "vsqrtss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x51, 0xca], "vsqrtss xmm1{rd-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x51, 0xca], "vsqrtss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0xca], "vsqrtss xmm1{k5}{z}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0x0a], "vsqrtss xmm1{k5}{z}, xmm0, dword [rdx]"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0xca], "vsqrtss xmm1, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0xca], "vsqrtss xmm1{k5}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0x0a], "vsqrtss xmm1, xmm0, dword [rdx]"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0x0a], "vsqrtss xmm1{k5}, xmm0, dword [rdx]"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x51, 0xca], "vsqrtss xmm1{ru-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x51, 0xca], "vsqrtss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x51, 0xca], "vsqrtss xmm1{rne-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x51, 0xca], "vsqrtss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSQRTSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x58, 0xca], "vaddss xmm1{rz-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x58, 0xca], "vaddss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x58, 0xca], "vaddss xmm1{rd-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x58, 0xca], "vaddss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0xca], "vaddss xmm1{k5}{z}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0x0a], "vaddss xmm1{k5}{z}, xmm0, dword [rdx]"); // VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0xca], "vaddss xmm1, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0xca], "vaddss xmm1{k5}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0x0a], "vaddss xmm1, xmm0, dword [rdx]"); // VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0x0a], "vaddss xmm1{k5}, xmm0, dword [rdx]"); // VADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x58, 0xca], "vaddss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x58, 0xca], "vaddss xmm1{ru-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x58, 0xca], "vaddss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x58, 0xca], "vaddss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x58, 0xca], "vaddss xmm1{rne-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x58, 0xca], "vaddss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VADDSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x59, 0xca], "vmulss xmm1{rz-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x59, 0xca], "vmulss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x59, 0xca], "vmulss xmm1{rd-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x59, 0xca], "vmulss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0xca], "vmulss xmm1{k5}{z}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0x0a], "vmulss xmm1{k5}{z}, xmm0, dword [rdx]"); // VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0xca], "vmulss xmm1, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0xca], "vmulss xmm1{k5}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0x0a], "vmulss xmm1, xmm0, dword [rdx]"); // VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0x0a], "vmulss xmm1{k5}, xmm0, dword [rdx]"); // VMULSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x59, 0xca], "vmulss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x59, 0xca], "vmulss xmm1{ru-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x59, 0xca], "vmulss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x59, 0xca], "vmulss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x59, 0xca], "vmulss xmm1{rne-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x59, 0xca], "vmulss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VMULSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0xca], "vcvtss2sd xmm1{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{sae}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [rdx]"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0xca], "vcvtss2sd xmm1, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}, xmm0, xmm2"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0x0a], "vcvtss2sd xmm1, xmm0, dword [rdx]"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}, xmm0, dword [rdx]"); // VCVTSS2SD_XMMf64_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}{sae}, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5b, 0xca], "vcvttps2dq zmm1{sae}, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{sae}, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5b, 0x0a], "vcvttps2dq ymm1, dword [rdx]{1to8}"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, dword [rdx]{1to8}"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0xca], "vcvttps2dq ymm1{k5}{z}, ymm2"); // VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, ymmword [rdx]"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0xca], "vcvttps2dq ymm1, ymm2"); // VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0xca], "vcvttps2dq ymm1{k5}, ymm2"); // VCVTTPS2DQ_YMMi32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0x0a], "vcvttps2dq ymm1, ymmword [rdx]"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, ymmword [rdx]"); // VCVTTPS2DQ_YMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5b, 0x0a], "vcvttps2dq zmm1, dword [rdx]{1to16}"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, dword [rdx]{1to16}"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5b, 0x0a], "vcvttps2dq xmm1, dword [rdx]{1to4}"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, dword [rdx]{1to4}"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, zmmword [rdx]"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0xca], "vcvttps2dq zmm1, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}, zmm2"); // VCVTTPS2DQ_ZMMi32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0x0a], "vcvttps2dq zmm1, zmmword [rdx]"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, zmmword [rdx]"); // VCVTTPS2DQ_ZMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}{z}, xmm2"); // VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, xmmword [rdx]"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0xca], "vcvttps2dq xmm1, xmm2"); // VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}, xmm2"); // VCVTTPS2DQ_XMMi32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0x0a], "vcvttps2dq xmm1, xmmword [rdx]"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, xmmword [rdx]"); // VCVTTPS2DQ_XMMi32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5c, 0xca], "vsubss xmm1{rz-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5c, 0xca], "vsubss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5c, 0xca], "vsubss xmm1{rd-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5c, 0xca], "vsubss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0xca], "vsubss xmm1{k5}{z}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0x0a], "vsubss xmm1{k5}{z}, xmm0, dword [rdx]"); // VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0xca], "vsubss xmm1, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0xca], "vsubss xmm1{k5}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0x0a], "vsubss xmm1, xmm0, dword [rdx]"); // VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0x0a], "vsubss xmm1{k5}, xmm0, dword [rdx]"); // VSUBSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5c, 0xca], "vsubss xmm1{ru-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5c, 0xca], "vsubss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5c, 0xca], "vsubss xmm1{rne-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5c, 0xca], "vsubss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSUBSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5d, 0xca], "vminss xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5d, 0xca], "vminss xmm1{sae}, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5d, 0xca], "vminss xmm1{k5}{sae}, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0xca], "vminss xmm1{k5}{z}, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0x0a], "vminss xmm1{k5}{z}, xmm0, dword [rdx]"); // VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0xca], "vminss xmm1, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0xca], "vminss xmm1{k5}, xmm0, xmm2"); // VMINSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0x0a], "vminss xmm1, xmm0, dword [rdx]"); // VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0x0a], "vminss xmm1{k5}, xmm0, dword [rdx]"); // VMINSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5e, 0xca], "vdivss xmm1{rz-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5e, 0xca], "vdivss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5e, 0xca], "vdivss xmm1{rd-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5e, 0xca], "vdivss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0xca], "vdivss xmm1{k5}{z}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0x0a], "vdivss xmm1{k5}{z}, xmm0, dword [rdx]"); // VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0xca], "vdivss xmm1, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0xca], "vdivss xmm1{k5}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0x0a], "vdivss xmm1, xmm0, dword [rdx]"); // VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0x0a], "vdivss xmm1{k5}, xmm0, dword [rdx]"); // VDIVSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5e, 0xca], "vdivss xmm1{ru-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5e, 0xca], "vdivss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5e, 0xca], "vdivss xmm1{rne-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5e, 0xca], "vdivss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VDIVSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5f, 0xca], "vmaxss xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5f, 0xca], "vmaxss xmm1{sae}, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5f, 0xca], "vmaxss xmm1{k5}{sae}, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0xca], "vmaxss xmm1{k5}{z}, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0x0a], "vmaxss xmm1{k5}{z}, xmm0, dword [rdx]"); // VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0xca], "vmaxss xmm1, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0xca], "vmaxss xmm1{k5}, xmm0, xmm2"); // VMAXSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0x0a], "vmaxss xmm1, xmm0, dword [rdx]"); // VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0x0a], "vmaxss xmm1{k5}, xmm0, dword [rdx]"); // VMAXSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0xca], "vmovdqu64 ymm1{k5}{z}, ymm2"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0xca], "vmovdqu64 ymm1, ymm2"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0xca], "vmovdqu64 ymm1{k5}, ymm2"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0x0a], "vmovdqu64 ymm1, ymmword [rdx]"); // VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}, ymmword [rdx]"); // VMOVDQU64_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0xca], "vmovdqu32 ymm1{k5}{z}, ymm2"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0xca], "vmovdqu32 ymm1, ymm2"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0xca], "vmovdqu32 ymm1{k5}, ymm2"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0x0a], "vmovdqu32 ymm1, ymmword [rdx]"); // VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}, ymmword [rdx]"); // VMOVDQU32_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0xca], "vmovdqu64 zmm1{k5}{z}, zmm2"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0xca], "vmovdqu64 zmm1, zmm2"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0xca], "vmovdqu64 zmm1{k5}, zmm2"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0x0a], "vmovdqu64 zmm1, zmmword [rdx]"); // VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}, zmmword [rdx]"); // VMOVDQU64_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}{z}, xmm2"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0xca], "vmovdqu64 xmm1, xmm2"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}, xmm2"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0x0a], "vmovdqu64 xmm1, xmmword [rdx]"); // VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}, xmmword [rdx]"); // VMOVDQU64_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0xca], "vmovdqu32 zmm1{k5}{z}, zmm2"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0xca], "vmovdqu32 zmm1, zmm2"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0xca], "vmovdqu32 zmm1{k5}, zmm2"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x0a], "vmovdqu32 zmm1, zmmword [rdx]"); // VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}, zmmword [rdx]"); // VMOVDQU32_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}{z}, xmm2"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0xca], "vmovdqu32 xmm1, xmm2"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}, xmm2"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0x0a], "vmovdqu32 xmm1, xmmword [rdx]"); // VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}, xmmword [rdx]"); // VMOVDQU32_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}{z}, ymm2, 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0xca, 0xcc], "vpshufhw ymm1, ymm2, 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}, ymm2, 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0x0a, 0xcc], "vpshufhw ymm1, ymmword [rdx], 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}, ymmword [rdx], 0xcc"); // VPSHUFHW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}{z}, zmm2, 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0xca, 0xcc], "vpshufhw zmm1, zmm2, 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}, zmm2, 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0x0a, 0xcc], "vpshufhw zmm1, zmmword [rdx], 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}, zmmword [rdx], 0xcc"); // VPSHUFHW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}{z}, xmm2, 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0xca, 0xcc], "vpshufhw xmm1, xmm2, 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}, xmm2, 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0x0a, 0xcc], "vpshufhw xmm1, xmmword [rdx], 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}, xmmword [rdx], 0xcc"); // VPSHUFHW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x78, 0xca], "vcvttss2usi rcx{sae}, xmm2"); // VCVTTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0xca], "vcvttss2usi rcx, xmm2"); // VCVTTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0x0a], "vcvttss2usi rcx, dword [rdx]"); // VCVTTSS2USI_GPR64u64_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x78, 0xca], "vcvttss2usi ecx{sae}, xmm2"); // VCVTTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x78, 0xca], "vcvttss2usi ecx, xmm2"); // VCVTTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x78, 0x0a], "vcvttss2usi ecx, dword [rdx]"); // VCVTTSS2USI_GPR32u32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x79, 0xca], "vcvtss2usi rcx{rz-sae}, xmm2"); // VCVTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x79, 0xca], "vcvtss2usi rcx{rd-sae}, xmm2"); // VCVTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0xca], "vcvtss2usi rcx, xmm2"); // VCVTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0x0a], "vcvtss2usi rcx, dword [rdx]"); // VCVTSS2USI_GPR64u64_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x79, 0xca], "vcvtss2usi ecx{rz-sae}, xmm2"); // VCVTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x79, 0xca], "vcvtss2usi ecx{rd-sae}, xmm2"); // VCVTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x79, 0xca], "vcvtss2usi ecx, xmm2"); // VCVTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x79, 0x0a], "vcvtss2usi ecx, dword [rdx]"); // VCVTSS2USI_GPR32u32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x79, 0xca], "vcvtss2usi rcx{ru-sae}, xmm2"); // VCVTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x79, 0xca], "vcvtss2usi rcx{rne-sae}, xmm2"); // VCVTSS2USI_GPR64u64_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x79, 0xca], "vcvtss2usi ecx{ru-sae}, xmm2"); // VCVTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x79, 0xca], "vcvtss2usi ecx{rne-sae}, xmm2"); // VCVTSS2USI_GPR32u32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x7a, 0xca], "vcvtuqq2pd zmm1{rz-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x7d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rz-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0xca], "vcvtuqq2pd zmm1{rd-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rd-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0x0a], "vcvtuqq2pd ymm1, qword [rdx]{1to4}"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, qword [rdx]{1to4}"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}{z}, ymm2"); // VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, ymmword [rdx]"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0xca], "vcvtuqq2pd ymm1, ymm2"); // VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}, ymm2"); // VCVTUQQ2PD_YMMf64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0x0a], "vcvtuqq2pd ymm1, ymmword [rdx]"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, ymmword [rdx]"); // VCVTUQQ2PD_YMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7a, 0x0a], "vcvtudq2pd ymm1, dword [rdx]{1to4}"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, dword [rdx]{1to4}"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}{z}, xmm2"); // VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, xmmword [rdx]"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0xca], "vcvtudq2pd ymm1, xmm2"); // VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}, xmm2"); // VCVTUDQ2PD_YMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0x0a], "vcvtudq2pd ymm1, xmmword [rdx]"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, xmmword [rdx]"); // VCVTUDQ2PD_YMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0xca], "vcvtuqq2pd zmm1{ru-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{ru-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0x0a], "vcvtuqq2pd zmm1, qword [rdx]{1to8}"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, qword [rdx]{1to8}"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0xca], "vcvtuqq2pd zmm1{rne-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rne-sae}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0x0a], "vcvtuqq2pd xmm1, qword [rdx]{1to2}"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, qword [rdx]{1to2}"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, zmmword [rdx]"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0xca], "vcvtuqq2pd zmm1, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}, zmm2"); // VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0x0a], "vcvtuqq2pd zmm1, zmmword [rdx]"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, zmmword [rdx]"); // VCVTUQQ2PD_ZMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}{z}, xmm2"); // VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, xmmword [rdx]"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0xca], "vcvtuqq2pd xmm1, xmm2"); // VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}, xmm2"); // VCVTUQQ2PD_XMMf64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0x0a], "vcvtuqq2pd xmm1, xmmword [rdx]"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, xmmword [rdx]"); // VCVTUQQ2PD_XMMf64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7a, 0x0a], "vcvtudq2pd zmm1, dword [rdx]{1to8}"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, dword [rdx]{1to8}"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7a, 0x0a], "vcvtudq2pd xmm1, dword [rdx]{1to2}"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, dword [rdx]{1to2}"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}{z}, ymm2"); // VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, ymmword [rdx]"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0xca], "vcvtudq2pd zmm1, ymm2"); // VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}, ymm2"); // VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0x0a], "vcvtudq2pd zmm1, ymmword [rdx]"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, ymmword [rdx]"); // VCVTUDQ2PD_ZMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}{z}, xmm2"); // VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, qword [rdx]"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0xca], "vcvtudq2pd xmm1, xmm2"); // VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}, xmm2"); // VCVTUDQ2PD_XMMf64_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0x0a], "vcvtudq2pd xmm1, qword [rdx]"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, qword [rdx]"); // VCVTUDQ2PD_XMMf64_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, qword [rdx]"); // VCVTUSI2SS_XMMf32_XMMf32_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, dword [rdx]"); // VCVTUSI2SS_XMMf32_XMMf32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, rdx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, edx"); // VCVTUSI2SS_XMMf32_XMMf32_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xca], "vmovq xmm1, xmm2"); // VMOVQ_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x0a], "vmovq xmm1, qword [rdx]"); // VMOVQ_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7f, 0xca], "vmovdqu64 ymm2{k5}{z}, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0xca], "vmovdqu64 ymm2, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0xca], "vmovdqu64 ymm2{k5}, ymm1"); // VMOVDQU64_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0x0a], "vmovdqu64 ymmword [rdx], ymm1"); // VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0x0a], "vmovdqu64 ymmword [rdx]{k5}, ymm1"); // VMOVDQU64_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7f, 0xca], "vmovdqu32 ymm2{k5}{z}, ymm1"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0xca], "vmovdqu32 ymm2, ymm1"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0xca], "vmovdqu32 ymm2{k5}, ymm1"); // VMOVDQU32_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0x0a], "vmovdqu32 ymmword [rdx], ymm1"); // VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0x0a], "vmovdqu32 ymmword [rdx]{k5}, ymm1"); // VMOVDQU32_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7f, 0xca], "vmovdqu64 zmm2{k5}{z}, zmm1"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0xca], "vmovdqu64 zmm2, zmm1"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0xca], "vmovdqu64 zmm2{k5}, zmm1"); // VMOVDQU64_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0x0a], "vmovdqu64 zmmword [rdx], zmm1"); // VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0x0a], "vmovdqu64 zmmword [rdx]{k5}, zmm1"); // VMOVDQU64_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}{z}, xmm1"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0xca], "vmovdqu64 xmm2, xmm1"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}, xmm1"); // VMOVDQU64_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0x0a], "vmovdqu64 xmmword [rdx], xmm1"); // VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0x0a], "vmovdqu64 xmmword [rdx]{k5}, xmm1"); // VMOVDQU64_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7f, 0xca], "vmovdqu32 zmm2{k5}{z}, zmm1"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0xca], "vmovdqu32 zmm2, zmm1"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0xca], "vmovdqu32 zmm2{k5}, zmm1"); // VMOVDQU32_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0x0a], "vmovdqu32 zmmword [rdx], zmm1"); // VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0x0a], "vmovdqu32 zmmword [rdx]{k5}, zmm1"); // VMOVDQU32_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}{z}, xmm1"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0xca], "vmovdqu32 xmm2, xmm1"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}, xmm1"); // VMOVDQU32_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0x0a], "vmovdqu32 xmmword [rdx], xmm1"); // VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0x0a], "vmovdqu32 xmmword [rdx]{k5}, xmm1"); // VMOVDQU32_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0xc2, 0xca, 0xcc], "vcmpss k1{sae}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}{sae}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0xca, 0xcc], "vcmpss k1, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x0a, 0xcc], "vcmpss k1, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpss k1{k5}, xmm0, dword [rdx], 0xcc"); // VCMPSS_MASKmskw_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0xe6, 0xca], "vcvtqq2pd zmm1{rz-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x7d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rz-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0xca], "vcvtqq2pd zmm1{rd-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rd-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0x0a], "vcvtqq2pd ymm1, qword [rdx]{1to4}"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, qword [rdx]{1to4}"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}{z}, ymm2"); // VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, ymmword [rdx]"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0xca], "vcvtqq2pd ymm1, ymm2"); // VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}, ymm2"); // VCVTQQ2PD_YMMi64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0x0a], "vcvtqq2pd ymm1, ymmword [rdx]"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, ymmword [rdx]"); // VCVTQQ2PD_YMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, dword [rdx]{1to4}"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0xe6, 0x0a], "vcvtdq2pd ymm1, dword [rdx]{1to4}"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, dword [rdx]{1to4}"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}{z}, xmm2"); // VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, xmmword [rdx]"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0xca], "vcvtdq2pd ymm1, xmm2"); // VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}, xmm2"); // VCVTDQ2PD_YMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0x0a], "vcvtdq2pd ymm1, xmmword [rdx]"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, xmmword [rdx]"); // VCVTDQ2PD_YMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0xca], "vcvtqq2pd zmm1{ru-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{ru-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0x0a], "vcvtqq2pd zmm1, qword [rdx]{1to8}"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, qword [rdx]{1to8}"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0xca], "vcvtqq2pd zmm1{rne-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rne-sae}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0x0a], "vcvtqq2pd xmm1, qword [rdx]{1to2}"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, qword [rdx]{1to2}"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, zmmword [rdx]"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0xca], "vcvtqq2pd zmm1, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}, zmm2"); // VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0x0a], "vcvtqq2pd zmm1, zmmword [rdx]"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, zmmword [rdx]"); // VCVTQQ2PD_ZMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}{z}, xmm2"); // VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, xmmword [rdx]"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0xca], "vcvtqq2pd xmm1, xmm2"); // VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}, xmm2"); // VCVTQQ2PD_XMMi64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0x0a], "vcvtqq2pd xmm1, xmmword [rdx]"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, xmmword [rdx]"); // VCVTQQ2PD_XMMi64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0xe6, 0x0a], "vcvtdq2pd zmm1, dword [rdx]{1to8}"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, dword [rdx]{1to8}"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, dword [rdx]{1to2}"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0xe6, 0x0a], "vcvtdq2pd xmm1, dword [rdx]{1to2}"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, dword [rdx]{1to2}"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}{z}, ymm2"); // VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, ymmword [rdx]"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0xca], "vcvtdq2pd zmm1, ymm2"); // VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}, ymm2"); // VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0x0a], "vcvtdq2pd zmm1, ymmword [rdx]"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, ymmword [rdx]"); // VCVTDQ2PD_ZMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}{z}, xmm2"); // VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, qword [rdx]"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0xca], "vcvtdq2pd xmm1, xmm2"); // VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}, xmm2"); // VCVTDQ2PD_XMMf64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0x0a], "vcvtdq2pd xmm1, qword [rdx]"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, qword [rdx]"); // VCVTDQ2PD_XMMf64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX } #[test] fn tests_f3_0f() { test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0xca], "vmovsd xmm1{k5}{z}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x0a], "vmovsd xmm1{k5}{z}, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0xca], "vmovsd xmm1, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0xca], "vmovsd xmm1{k5}, xmm0, xmm2"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x0a], "vmovsd xmm1, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0x0a], "vmovsd xmm1{k5}, qword [rdx]"); // VMOVSD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0xca], "vmovsd xmm2{k5}{z}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0xca], "vmovsd xmm2{k5}, xmm0, xmm1"); // VMOVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x0a], "vmovsd qword [rdx], xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x0a], "vmovsd qword [rdx]{k5}, xmm1"); // VMOVSD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0xca], "vmovddup ymm1{k5}{z}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x0a], "vmovddup ymm1{k5}{z}, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0xca], "vmovddup ymm1, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0xca], "vmovddup ymm1{k5}, ymm2"); // VMOVDDUP_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x0a], "vmovddup ymm1, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0x0a], "vmovddup ymm1{k5}, ymmword [rdx]"); // VMOVDDUP_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0xca], "vmovddup zmm1{k5}{z}, zmm2"); // VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0x0a], "vmovddup zmm1{k5}{z}, zmmword [rdx]"); // VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0xca], "vmovddup zmm1, zmm2"); // VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0xca], "vmovddup zmm1{k5}, zmm2"); // VMOVDDUP_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0x0a], "vmovddup zmm1, zmmword [rdx]"); // VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0x0a], "vmovddup zmm1{k5}, zmmword [rdx]"); // VMOVDDUP_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0xca], "vmovddup xmm1{k5}{z}, xmm2"); // VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0x0a], "vmovddup xmm1{k5}{z}, qword [rdx]"); // VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0xca], "vmovddup xmm1, xmm2"); // VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0xca], "vmovddup xmm1{k5}, xmm2"); // VMOVDDUP_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0x0a], "vmovddup xmm1, qword [rdx]"); // VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0x0a], "vmovddup xmm1{k5}, qword [rdx]"); // VMOVDDUP_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2a, 0xca], "vcvtsi2sd xmm1{rz-sae}, xmm0, rdx"); // VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x2a, 0xca], "vcvtsi2sd xmm1{rd-sae}, xmm0, rdx"); // VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, rdx"); // VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, qword [rdx]"); // VCVTSI2SD_XMMf64_XMMf64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); // VCVTSI2SD_XMMf64_XMMf64_GPR32i32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, dword [rdx]"); // VCVTSI2SD_XMMf64_XMMf64_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x2a, 0xca], "vcvtsi2sd xmm1{ru-sae}, xmm0, rdx"); // VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x2a, 0xca], "vcvtsi2sd xmm1{rne-sae}, xmm0, rdx"); // VCVTSI2SD_XMMf64_XMMf64_GPR64i64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2c, 0xca], "vcvttsd2si rcx{sae}, xmm2"); // VCVTTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0xca], "vcvttsd2si rcx, xmm2"); // VCVTTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0x0a], "vcvttsd2si rcx, qword [rdx]"); // VCVTTSD2SI_GPR64i64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x2c, 0xca], "vcvttsd2si ecx{sae}, xmm2"); // VCVTTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); // VCVTTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x2c, 0x0a], "vcvttsd2si ecx, qword [rdx]"); // VCVTTSD2SI_GPR32i32_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2d, 0xca], "vcvtsd2si rcx{rz-sae}, xmm2"); // VCVTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x2d, 0xca], "vcvtsd2si rcx{rd-sae}, xmm2"); // VCVTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0xca], "vcvtsd2si rcx, xmm2"); // VCVTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0x0a], "vcvtsd2si rcx, qword [rdx]"); // VCVTSD2SI_GPR64i64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x2d, 0xca], "vcvtsd2si ecx{rz-sae}, xmm2"); // VCVTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x2d, 0xca], "vcvtsd2si ecx{rd-sae}, xmm2"); // VCVTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); // VCVTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x2d, 0x0a], "vcvtsd2si ecx, qword [rdx]"); // VCVTSD2SI_GPR32i32_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x2d, 0xca], "vcvtsd2si rcx{ru-sae}, xmm2"); // VCVTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x2d, 0xca], "vcvtsd2si rcx{rne-sae}, xmm2"); // VCVTSD2SI_GPR64i64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x2d, 0xca], "vcvtsd2si ecx{ru-sae}, xmm2"); // VCVTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x2d, 0xca], "vcvtsd2si ecx{rne-sae}, xmm2"); // VCVTSD2SI_GPR32i32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x51, 0xca], "vsqrtsd xmm1{rz-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0xca], "vsqrtsd xmm1{rd-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0x0a], "vsqrtsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0xca], "vsqrtsd xmm1, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0xca], "vsqrtsd xmm1{k5}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x0a], "vsqrtsd xmm1{k5}, xmm0, qword [rdx]"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x51, 0xca], "vsqrtsd xmm1{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x51, 0xca], "vsqrtsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x51, 0xca], "vsqrtsd xmm1{rne-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSQRTSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x58, 0xca], "vaddsd xmm1{rz-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x58, 0xca], "vaddsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x58, 0xca], "vaddsd xmm1{rd-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x58, 0xca], "vaddsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0xca], "vaddsd xmm1{k5}{z}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0x0a], "vaddsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0xca], "vaddsd xmm1, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0xca], "vaddsd xmm1{k5}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0x0a], "vaddsd xmm1, xmm0, qword [rdx]"); // VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0x0a], "vaddsd xmm1{k5}, xmm0, qword [rdx]"); // VADDSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x58, 0xca], "vaddsd xmm1{ru-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x58, 0xca], "vaddsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x58, 0xca], "vaddsd xmm1{rne-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x58, 0xca], "vaddsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VADDSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x59, 0xca], "vmulsd xmm1{rz-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x59, 0xca], "vmulsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x59, 0xca], "vmulsd xmm1{rd-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x59, 0xca], "vmulsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0xca], "vmulsd xmm1{k5}{z}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0x0a], "vmulsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0xca], "vmulsd xmm1, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0xca], "vmulsd xmm1{k5}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0x0a], "vmulsd xmm1, xmm0, qword [rdx]"); // VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0x0a], "vmulsd xmm1{k5}, xmm0, qword [rdx]"); // VMULSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x59, 0xca], "vmulsd xmm1{ru-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x59, 0xca], "vmulsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x59, 0xca], "vmulsd xmm1{rne-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x59, 0xca], "vmulsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VMULSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5a, 0xca], "vcvtsd2ss xmm1{rz-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5a, 0xca], "vcvtsd2ss xmm1{rd-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}, xmm0, qword [rdx]"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5a, 0xca], "vcvtsd2ss xmm1{ru-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5a, 0xca], "vcvtsd2ss xmm1{rne-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VCVTSD2SS_XMMf32_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5c, 0xca], "vsubsd xmm1{rz-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5c, 0xca], "vsubsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5c, 0xca], "vsubsd xmm1{rd-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5c, 0xca], "vsubsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0xca], "vsubsd xmm1{k5}{z}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0x0a], "vsubsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0xca], "vsubsd xmm1, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0xca], "vsubsd xmm1{k5}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0x0a], "vsubsd xmm1, xmm0, qword [rdx]"); // VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0x0a], "vsubsd xmm1{k5}, xmm0, qword [rdx]"); // VSUBSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5c, 0xca], "vsubsd xmm1{ru-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5c, 0xca], "vsubsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5c, 0xca], "vsubsd xmm1{rne-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5c, 0xca], "vsubsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSUBSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5d, 0xca], "vminsd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5d, 0xca], "vminsd xmm1{sae}, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5d, 0xca], "vminsd xmm1{k5}{sae}, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0xca], "vminsd xmm1{k5}{z}, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0x0a], "vminsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0xca], "vminsd xmm1, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0xca], "vminsd xmm1{k5}, xmm0, xmm2"); // VMINSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0x0a], "vminsd xmm1, xmm0, qword [rdx]"); // VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0x0a], "vminsd xmm1{k5}, xmm0, qword [rdx]"); // VMINSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5e, 0xca], "vdivsd xmm1{rz-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5e, 0xca], "vdivsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5e, 0xca], "vdivsd xmm1{rd-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5e, 0xca], "vdivsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0xca], "vdivsd xmm1{k5}{z}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0x0a], "vdivsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0xca], "vdivsd xmm1, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0xca], "vdivsd xmm1{k5}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0x0a], "vdivsd xmm1, xmm0, qword [rdx]"); // VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0x0a], "vdivsd xmm1{k5}, xmm0, qword [rdx]"); // VDIVSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5e, 0xca], "vdivsd xmm1{ru-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5e, 0xca], "vdivsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5e, 0xca], "vdivsd xmm1{rne-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5e, 0xca], "vdivsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VDIVSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5f, 0xca], "vmaxsd xmm1{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5f, 0xca], "vmaxsd xmm1{k5}{sae}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x0a], "vmaxsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0xca], "vmaxsd xmm1, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0xca], "vmaxsd xmm1{k5}, xmm0, xmm2"); // VMAXSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0x0a], "vmaxsd xmm1, xmm0, qword [rdx]"); // VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0x0a], "vmaxsd xmm1{k5}, xmm0, qword [rdx]"); // VMAXSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0xca], "vmovdqu16 ymm1{k5}{z}, ymm2"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0xca], "vmovdqu16 ymm1, ymm2"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0xca], "vmovdqu16 ymm1{k5}, ymm2"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0x0a], "vmovdqu16 ymm1, ymmword [rdx]"); // VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}, ymmword [rdx]"); // VMOVDQU16_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0xca], "vmovdqu8 ymm1{k5}{z}, ymm2"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}{z}, ymmword [rdx]"); // VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0xca], "vmovdqu8 ymm1, ymm2"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0xca], "vmovdqu8 ymm1{k5}, ymm2"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0x0a], "vmovdqu8 ymm1, ymmword [rdx]"); // VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}, ymmword [rdx]"); // VMOVDQU8_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0xca], "vmovdqu16 zmm1{k5}{z}, zmm2"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0xca], "vmovdqu16 zmm1, zmm2"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0xca], "vmovdqu16 zmm1{k5}, zmm2"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0x0a], "vmovdqu16 zmm1, zmmword [rdx]"); // VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}, zmmword [rdx]"); // VMOVDQU16_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}{z}, xmm2"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0xca], "vmovdqu16 xmm1, xmm2"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}, xmm2"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0x0a], "vmovdqu16 xmm1, xmmword [rdx]"); // VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}, xmmword [rdx]"); // VMOVDQU16_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0xca], "vmovdqu8 zmm1{k5}{z}, zmm2"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}{z}, zmmword [rdx]"); // VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0xca], "vmovdqu8 zmm1, zmm2"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0xca], "vmovdqu8 zmm1{k5}, zmm2"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0x0a], "vmovdqu8 zmm1, zmmword [rdx]"); // VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}, zmmword [rdx]"); // VMOVDQU8_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}{z}, xmm2"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}{z}, xmmword [rdx]"); // VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0xca], "vmovdqu8 xmm1, xmm2"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}, xmm2"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0x0a], "vmovdqu8 xmm1, xmmword [rdx]"); // VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}, xmmword [rdx]"); // VMOVDQU8_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}{z}, ymm2, 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0xca, 0xcc], "vpshuflw ymm1, ymm2, 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}, ymm2, 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0x0a, 0xcc], "vpshuflw ymm1, ymmword [rdx], 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}, ymmword [rdx], 0xcc"); // VPSHUFLW_YMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}{z}, zmm2, 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0xca, 0xcc], "vpshuflw zmm1, zmm2, 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}, zmm2, 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0x0a, 0xcc], "vpshuflw zmm1, zmmword [rdx], 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}, zmmword [rdx], 0xcc"); // VPSHUFLW_ZMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}{z}, xmm2, 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0xca, 0xcc], "vpshuflw xmm1, xmm2, 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}, xmm2, 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0x0a, 0xcc], "vpshuflw xmm1, xmmword [rdx], 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}, xmmword [rdx], 0xcc"); // VPSHUFLW_XMMu16_MASKmskw_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x78, 0xca], "vcvttsd2usi rcx{sae}, xmm2"); // VCVTTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0xca], "vcvttsd2usi rcx, xmm2"); // VCVTTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0x0a], "vcvttsd2usi rcx, qword [rdx]"); // VCVTTSD2USI_GPR64u64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x78, 0xca], "vcvttsd2usi ecx{sae}, xmm2"); // VCVTTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x78, 0xca], "vcvttsd2usi ecx, xmm2"); // VCVTTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x78, 0x0a], "vcvttsd2usi ecx, qword [rdx]"); // VCVTTSD2USI_GPR32u32_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x79, 0xca], "vcvtsd2usi rcx{rz-sae}, xmm2"); // VCVTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x79, 0xca], "vcvtsd2usi rcx{rd-sae}, xmm2"); // VCVTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0xca], "vcvtsd2usi rcx, xmm2"); // VCVTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0x0a], "vcvtsd2usi rcx, qword [rdx]"); // VCVTSD2USI_GPR64u64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x79, 0xca], "vcvtsd2usi ecx{rz-sae}, xmm2"); // VCVTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x79, 0xca], "vcvtsd2usi ecx{rd-sae}, xmm2"); // VCVTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x79, 0xca], "vcvtsd2usi ecx, xmm2"); // VCVTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x79, 0x0a], "vcvtsd2usi ecx, qword [rdx]"); // VCVTSD2USI_GPR32u32_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x79, 0xca], "vcvtsd2usi rcx{ru-sae}, xmm2"); // VCVTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x79, 0xca], "vcvtsd2usi rcx{rne-sae}, xmm2"); // VCVTSD2USI_GPR64u64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x79, 0xca], "vcvtsd2usi ecx{ru-sae}, xmm2"); // VCVTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x79, 0xca], "vcvtsd2usi ecx{rne-sae}, xmm2"); // VCVTSD2USI_GPR32u32_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x7a, 0xca], "vcvtuqq2ps ymm1{rz-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rz-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0xca], "vcvtuqq2ps ymm1{rd-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rd-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [rdx]{1to4}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [rdx]{1to4}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, ymm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, ymmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0xca], "vcvtuqq2ps xmm1, ymm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, ymm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_YMMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0x0a], "vcvtuqq2ps xmm1, ymmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, ymmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xfd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rz-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x7a, 0xca], "vcvtudq2ps zmm1{rz-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x7d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rz-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rd-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, dword [rdx]{1to8}"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0xca], "vcvtudq2ps zmm1{rd-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rd-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0x0a], "vcvtudq2ps ymm1, dword [rdx]{1to8}"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, dword [rdx]{1to8}"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}{z}, ymm2"); // VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, ymmword [rdx]"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0xca], "vcvtudq2ps ymm1, ymm2"); // VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}, ymm2"); // VCVTUDQ2PS_YMMf32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0x0a], "vcvtudq2ps ymm1, ymmword [rdx]"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, ymmword [rdx]"); // VCVTUDQ2PS_YMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0xca], "vcvtuqq2ps ymm1{ru-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{ru-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0x0a], "vcvtuqq2ps ymm1, qword [rdx]{1to8}"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, qword [rdx]{1to8}"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0xca], "vcvtuqq2ps ymm1{rne-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rne-sae}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [rdx]{1to2}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [rdx]{1to2}"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, zmmword [rdx]"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0xca], "vcvtuqq2ps ymm1, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}, zmm2"); // VCVTUQQ2PS_YMMf32_MASKmskw_ZMMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0x0a], "vcvtuqq2ps ymm1, zmmword [rdx]"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, zmmword [rdx]"); // VCVTUQQ2PS_YMMf32_MASKmskw_MEMu64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, xmm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, xmmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0xca], "vcvtuqq2ps xmm1, xmm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, xmm2"); // VCVTUQQ2PS_XMMf32_MASKmskw_XMMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0x0a], "vcvtuqq2ps xmm1, xmmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, xmmword [rdx]"); // VCVTUQQ2PS_XMMf32_MASKmskw_MEMu64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{ru-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0xca], "vcvtudq2ps zmm1{ru-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{ru-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0x0a], "vcvtudq2ps zmm1, dword [rdx]{1to16}"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, dword [rdx]{1to16}"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rne-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0xca], "vcvtudq2ps zmm1{rne-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rne-sae}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0x0a], "vcvtudq2ps xmm1, dword [rdx]{1to4}"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, dword [rdx]{1to4}"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, zmmword [rdx]"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0xca], "vcvtudq2ps zmm1, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}, zmm2"); // VCVTUDQ2PS_ZMMf32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0x0a], "vcvtudq2ps zmm1, zmmword [rdx]"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, zmmword [rdx]"); // VCVTUDQ2PS_ZMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}{z}, xmm2"); // VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, xmmword [rdx]"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0xca], "vcvtudq2ps xmm1, xmm2"); // VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}, xmm2"); // VCVTUDQ2PS_XMMf32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0x0a], "vcvtudq2ps xmm1, xmmword [rdx]"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, xmmword [rdx]"); // VCVTUDQ2PS_XMMf32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1{rz-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7b, 0xca], "vcvtusi2sd xmm1{rd-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, qword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, edx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, dword [rdx]"); // VCVTUSI2SD_XMMf64_XMMf64_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7b, 0xca], "vcvtusi2sd xmm1{ru-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7b, 0xca], "vcvtusi2sd xmm1{rne-sae}, xmm0, rdx"); // VCVTUSI2SD_XMMf64_XMMf64_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7f, 0xca], "vmovdqu16 ymm2{k5}{z}, ymm1"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0xca], "vmovdqu16 ymm2, ymm1"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0xca], "vmovdqu16 ymm2{k5}, ymm1"); // VMOVDQU16_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0x0a], "vmovdqu16 ymmword [rdx], ymm1"); // VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0x0a], "vmovdqu16 ymmword [rdx]{k5}, ymm1"); // VMOVDQU16_MEMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7f, 0xca], "vmovdqu8 ymm2{k5}{z}, ymm1"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0xca], "vmovdqu8 ymm2, ymm1"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0xca], "vmovdqu8 ymm2{k5}, ymm1"); // VMOVDQU8_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0x0a], "vmovdqu8 ymmword [rdx], ymm1"); // VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0x0a], "vmovdqu8 ymmword [rdx]{k5}, ymm1"); // VMOVDQU8_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7f, 0xca], "vmovdqu16 zmm2{k5}{z}, zmm1"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0xca], "vmovdqu16 zmm2, zmm1"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0xca], "vmovdqu16 zmm2{k5}, zmm1"); // VMOVDQU16_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0x0a], "vmovdqu16 zmmword [rdx], zmm1"); // VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0x0a], "vmovdqu16 zmmword [rdx]{k5}, zmm1"); // VMOVDQU16_MEMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}{z}, xmm1"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0xca], "vmovdqu16 xmm2, xmm1"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}, xmm1"); // VMOVDQU16_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0x0a], "vmovdqu16 xmmword [rdx], xmm1"); // VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0x0a], "vmovdqu16 xmmword [rdx]{k5}, xmm1"); // VMOVDQU16_MEMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7f, 0xca], "vmovdqu8 zmm2{k5}{z}, zmm1"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0xca], "vmovdqu8 zmm2, zmm1"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0xca], "vmovdqu8 zmm2{k5}, zmm1"); // VMOVDQU8_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0x0a], "vmovdqu8 zmmword [rdx], zmm1"); // VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0x0a], "vmovdqu8 zmmword [rdx]{k5}, zmm1"); // VMOVDQU8_MEMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}{z}, xmm1"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0xca], "vmovdqu8 xmm2, xmm1"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}, xmm1"); // VMOVDQU8_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0x0a], "vmovdqu8 xmmword [rdx], xmm1"); // VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0x0a], "vmovdqu8 xmmword [rdx]{k5}, xmm1"); // VMOVDQU8_MEMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xc2, 0xca, 0xcc], "vcmpsd k1{sae}, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}{sae}, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0xca, 0xcc], "vcmpsd k1, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}, xmm0, xmm2, 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x0a, 0xcc], "vcmpsd k1, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpsd k1{k5}, xmm0, qword [rdx], 0xcc"); // VCMPSD_MASKmskw_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xe6, 0xca], "vcvtpd2dq ymm1{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rz-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rd-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [rdx]{1to4}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0xca], "vcvtpd2dq ymm1{rd-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rd-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [rdx]{1to4}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [rdx]{1to4}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, ymm2"); // VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, ymmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0xca], "vcvtpd2dq xmm1, ymm2"); // VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, ymm2"); // VCVTPD2DQ_XMMi32_MASKmskw_YMMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0x0a], "vcvtpd2dq xmm1, ymmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, ymmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{ru-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, qword [rdx]{1to8}"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0xca], "vcvtpd2dq ymm1{ru-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{ru-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0x0a], "vcvtpd2dq ymm1, qword [rdx]{1to8}"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, qword [rdx]{1to8}"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rne-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [rdx]{1to2}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0xca], "vcvtpd2dq ymm1{rne-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rne-sae}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [rdx]{1to2}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [rdx]{1to2}"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, zmmword [rdx]"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0xca], "vcvtpd2dq ymm1, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}, zmm2"); // VCVTPD2DQ_YMMi32_MASKmskw_ZMMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0x0a], "vcvtpd2dq ymm1, zmmword [rdx]"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, zmmword [rdx]"); // VCVTPD2DQ_YMMi32_MASKmskw_MEMf64_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, xmm2"); // VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, xmmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0xca], "vcvtpd2dq xmm1, xmm2"); // VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, xmm2"); // VCVTPD2DQ_XMMi32_MASKmskw_XMMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0x0a], "vcvtpd2dq xmm1, xmmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, xmmword [rdx]"); // VCVTPD2DQ_XMMi32_MASKmskw_MEMf64_AVX512_VL128, extension: AVX512EVEX } #[test] fn tests_66_0f38() { test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0xca], "vpshufb ymm1{k5}{z}, ymm0, ymm2"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0x0a], "vpshufb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0xca], "vpshufb ymm1, ymm0, ymm2"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0xca], "vpshufb ymm1{k5}, ymm0, ymm2"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0x0a], "vpshufb ymm1, ymm0, ymmword [rdx]"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0x0a], "vpshufb ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHUFB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0xca], "vpshufb zmm1{k5}{z}, zmm0, zmm2"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0x0a], "vpshufb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0xca], "vpshufb zmm1, zmm0, zmm2"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0xca], "vpshufb zmm1{k5}, zmm0, zmm2"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0x0a], "vpshufb zmm1, zmm0, zmmword [rdx]"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0x0a], "vpshufb zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHUFB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0xca], "vpshufb xmm1{k5}{z}, xmm0, xmm2"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0x0a], "vpshufb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0xca], "vpshufb xmm1, xmm0, xmm2"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0xca], "vpshufb xmm1{k5}, xmm0, xmm2"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0x0a], "vpshufb xmm1, xmm0, xmmword [rdx]"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0x0a], "vpshufb xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHUFB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0xca], "vpmaddubsw ymm1{k5}{z}, ymm0, ymm2"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0x0a], "vpmaddubsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0xca], "vpmaddubsw ymm1, ymm0, ymm2"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0xca], "vpmaddubsw ymm1{k5}, ymm0, ymm2"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0x0a], "vpmaddubsw ymm1, ymm0, ymmword [rdx]"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0x0a], "vpmaddubsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMADDUBSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0xca], "vpmaddubsw zmm1{k5}{z}, zmm0, zmm2"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0x0a], "vpmaddubsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0xca], "vpmaddubsw zmm1, zmm0, zmm2"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0xca], "vpmaddubsw zmm1{k5}, zmm0, zmm2"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0x0a], "vpmaddubsw zmm1, zmm0, zmmword [rdx]"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0x0a], "vpmaddubsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMADDUBSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0xca], "vpmaddubsw xmm1{k5}{z}, xmm0, xmm2"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0xca], "vpmaddubsw xmm1, xmm0, xmm2"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0xca], "vpmaddubsw xmm1{k5}, xmm0, xmm2"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0x0a], "vpmaddubsw xmm1, xmm0, xmmword [rdx]"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADDUBSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0xca], "vpmulhrsw ymm1{k5}{z}, ymm0, ymm2"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0xca], "vpmulhrsw ymm1, ymm0, ymm2"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0xca], "vpmulhrsw ymm1{k5}, ymm0, ymm2"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0x0a], "vpmulhrsw ymm1, ymm0, ymmword [rdx]"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULHRSW_YMMi16_MASKmskw_YMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0xca], "vpmulhrsw zmm1{k5}{z}, zmm0, zmm2"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0xca], "vpmulhrsw zmm1, zmm0, zmm2"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0xca], "vpmulhrsw zmm1{k5}, zmm0, zmm2"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0x0a], "vpmulhrsw zmm1, zmm0, zmmword [rdx]"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULHRSW_ZMMi16_MASKmskw_ZMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}{z}, xmm0, xmm2"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0xca], "vpmulhrsw xmm1, xmm0, xmm2"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}, xmm0, xmm2"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0x0a], "vpmulhrsw xmm1, xmm0, xmmword [rdx]"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULHRSW_XMMi16_MASKmskw_XMMi16_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x0c, 0x0a], "vpermilps ymm1, ymm0, dword [rdx]{1to8}"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0xca], "vpermilps ymm1{k5}{z}, ymm0, ymm2"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0xca], "vpermilps ymm1, ymm0, ymm2"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0xca], "vpermilps ymm1{k5}, ymm0, ymm2"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0x0a], "vpermilps ymm1, ymm0, ymmword [rdx]"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x0c, 0x0a], "vpermilps zmm1, zmm0, dword [rdx]{1to16}"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x0c, 0x0a], "vpermilps xmm1, xmm0, dword [rdx]{1to4}"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0xca], "vpermilps zmm1{k5}{z}, zmm0, zmm2"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0xca], "vpermilps zmm1, zmm0, zmm2"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0xca], "vpermilps zmm1{k5}, zmm0, zmm2"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0x0a], "vpermilps zmm1, zmm0, zmmword [rdx]"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0xca], "vpermilps xmm1{k5}{z}, xmm0, xmm2"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0xca], "vpermilps xmm1, xmm0, xmm2"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0xca], "vpermilps xmm1{k5}, xmm0, xmm2"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0x0a], "vpermilps xmm1, xmm0, xmmword [rdx]"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, qword [rdx]{1to4}"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0xca], "vpermilpd ymm1{k5}{z}, ymm0, ymm2"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0xca], "vpermilpd ymm1, ymm0, ymm2"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0xca], "vpermilpd ymm1{k5}, ymm0, ymm2"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, ymmword [rdx]"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, qword [rdx]{1to8}"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, qword [rdx]{1to2}"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0xca], "vpermilpd zmm1{k5}{z}, zmm0, zmm2"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0xca], "vpermilpd zmm1, zmm0, zmm2"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0xca], "vpermilpd zmm1{k5}, zmm0, zmm2"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, zmmword [rdx]"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0xca], "vpermilpd xmm1{k5}{z}, xmm0, xmm2"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0xca], "vpermilpd xmm1, xmm0, xmm2"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0xca], "vpermilpd xmm1{k5}, xmm0, xmm2"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, xmmword [rdx]"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0xca], "vpsrlvw ymm1{k5}{z}, ymm0, ymm2"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0x0a], "vpsrlvw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0xca], "vpsrlvw ymm1, ymm0, ymm2"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0xca], "vpsrlvw ymm1{k5}, ymm0, ymm2"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0x0a], "vpsrlvw ymm1, ymm0, ymmword [rdx]"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0x0a], "vpsrlvw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0xca], "vpsrlvw zmm1{k5}{z}, zmm0, zmm2"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0x0a], "vpsrlvw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0xca], "vpsrlvw zmm1, zmm0, zmm2"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0xca], "vpsrlvw zmm1{k5}, zmm0, zmm2"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0x0a], "vpsrlvw zmm1, zmm0, zmmword [rdx]"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0x0a], "vpsrlvw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0xca], "vpsrlvw xmm1{k5}{z}, xmm0, xmm2"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0x0a], "vpsrlvw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0xca], "vpsrlvw xmm1, xmm0, xmm2"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0xca], "vpsrlvw xmm1{k5}, xmm0, xmm2"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0x0a], "vpsrlvw xmm1, xmm0, xmmword [rdx]"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0x0a], "vpsrlvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0xca], "vpsravw ymm1{k5}{z}, ymm0, ymm2"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0x0a], "vpsravw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0xca], "vpsravw ymm1, ymm0, ymm2"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0xca], "vpsravw ymm1{k5}, ymm0, ymm2"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0x0a], "vpsravw ymm1, ymm0, ymmword [rdx]"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0x0a], "vpsravw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRAVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0xca], "vpsravw zmm1{k5}{z}, zmm0, zmm2"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0x0a], "vpsravw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0xca], "vpsravw zmm1, zmm0, zmm2"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0xca], "vpsravw zmm1{k5}, zmm0, zmm2"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0x0a], "vpsravw zmm1, zmm0, zmmword [rdx]"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0x0a], "vpsravw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRAVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0xca], "vpsravw xmm1{k5}{z}, xmm0, xmm2"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0x0a], "vpsravw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0xca], "vpsravw xmm1, xmm0, xmm2"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0xca], "vpsravw xmm1{k5}, xmm0, xmm2"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0x0a], "vpsravw xmm1, xmm0, xmmword [rdx]"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0x0a], "vpsravw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0xca], "vpsllvw ymm1{k5}{z}, ymm0, ymm2"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0x0a], "vpsllvw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0xca], "vpsllvw ymm1, ymm0, ymm2"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0xca], "vpsllvw ymm1{k5}, ymm0, ymm2"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0x0a], "vpsllvw ymm1, ymm0, ymmword [rdx]"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0x0a], "vpsllvw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSLLVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0xca], "vpsllvw zmm1{k5}{z}, zmm0, zmm2"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0x0a], "vpsllvw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0xca], "vpsllvw zmm1, zmm0, zmm2"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0xca], "vpsllvw zmm1{k5}, zmm0, zmm2"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0x0a], "vpsllvw zmm1, zmm0, zmmword [rdx]"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0x0a], "vpsllvw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSLLVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0xca], "vpsllvw xmm1{k5}{z}, xmm0, xmm2"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0x0a], "vpsllvw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0xca], "vpsllvw xmm1, xmm0, xmm2"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0xca], "vpsllvw xmm1{k5}, xmm0, xmm2"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0x0a], "vpsllvw xmm1, xmm0, xmmword [rdx]"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x0a], "vpsllvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x13, 0xca], "vcvtph2ps zmm1{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x13, 0xca], "vcvtph2ps zmm1{k5}{sae}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0xca], "vcvtph2ps ymm1{k5}{z}, xmm2"); // VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x0a], "vcvtph2ps ymm1{k5}{z}, xmmword [rdx]"); // VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0xca], "vcvtph2ps ymm1, xmm2"); // VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0xca], "vcvtph2ps ymm1{k5}, xmm2"); // VCVTPH2PS_YMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0x0a], "vcvtph2ps ymm1, xmmword [rdx]"); // VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0x0a], "vcvtph2ps ymm1{k5}, xmmword [rdx]"); // VCVTPH2PS_YMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0x0a], "vcvtph2ps zmm1{k5}{z}, ymmword [rdx]"); // VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0xca], "vcvtph2ps zmm1, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0xca], "vcvtph2ps zmm1{k5}, ymm2"); // VCVTPH2PS_ZMMf32_MASKmskw_YMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0x0a], "vcvtph2ps zmm1, ymmword [rdx]"); // VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0x0a], "vcvtph2ps zmm1{k5}, ymmword [rdx]"); // VCVTPH2PS_ZMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0xca], "vcvtph2ps xmm1{k5}{z}, xmm2"); // VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}{z}, qword [rdx]"); // VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0xca], "vcvtph2ps xmm1, xmm2"); // VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0xca], "vcvtph2ps xmm1{k5}, xmm2"); // VCVTPH2PS_XMMf32_MASKmskw_XMMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0x0a], "vcvtph2ps xmm1, qword [rdx]"); // VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}, qword [rdx]"); // VCVTPH2PS_XMMf32_MASKmskw_MEMf16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x14, 0x0a], "vprorvq ymm1, ymm0, qword [rdx]{1to4}"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0xca], "vprorvq ymm1{k5}{z}, ymm0, ymm2"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0xca], "vprorvq ymm1, ymm0, ymm2"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0xca], "vprorvq ymm1{k5}, ymm0, ymm2"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0x0a], "vprorvq ymm1, ymm0, ymmword [rdx]"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPRORVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x0a], "vprorvd ymm1, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0xca], "vprorvd ymm1{k5}{z}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0xca], "vprorvd ymm1, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0xca], "vprorvd ymm1{k5}, ymm0, ymm2"); // VPRORVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0x0a], "vprorvd ymm1, ymm0, ymmword [rdx]"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPRORVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x14, 0x0a], "vprorvq zmm1, zmm0, qword [rdx]{1to8}"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x14, 0x0a], "vprorvq xmm1, xmm0, qword [rdx]{1to2}"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0xca], "vprorvq zmm1{k5}{z}, zmm0, zmm2"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0xca], "vprorvq zmm1, zmm0, zmm2"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0xca], "vprorvq zmm1{k5}, zmm0, zmm2"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0x0a], "vprorvq zmm1, zmm0, zmmword [rdx]"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPRORVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0xca], "vprorvq xmm1{k5}{z}, xmm0, xmm2"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0xca], "vprorvq xmm1, xmm0, xmm2"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0xca], "vprorvq xmm1{k5}, xmm0, xmm2"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0x0a], "vprorvq xmm1, xmm0, xmmword [rdx]"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPRORVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x14, 0x0a], "vprorvd zmm1, zmm0, dword [rdx]{1to16}"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x14, 0x0a], "vprorvd xmm1, xmm0, dword [rdx]{1to4}"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0xca], "vprorvd zmm1{k5}{z}, zmm0, zmm2"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0xca], "vprorvd zmm1, zmm0, zmm2"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0xca], "vprorvd zmm1{k5}, zmm0, zmm2"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0x0a], "vprorvd zmm1, zmm0, zmmword [rdx]"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPRORVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0xca], "vprorvd xmm1{k5}{z}, xmm0, xmm2"); // VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0xca], "vprorvd xmm1, xmm0, xmm2"); // VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0xca], "vprorvd xmm1{k5}, xmm0, xmm2"); // VPRORVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0x0a], "vprorvd xmm1, xmm0, xmmword [rdx]"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPRORVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x15, 0x0a], "vprolvq ymm1, ymm0, qword [rdx]{1to4}"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0xca], "vprolvq ymm1{k5}{z}, ymm0, ymm2"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0xca], "vprolvq ymm1, ymm0, ymm2"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0xca], "vprolvq ymm1{k5}, ymm0, ymm2"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0x0a], "vprolvq ymm1, ymm0, ymmword [rdx]"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPROLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x15, 0x0a], "vprolvd ymm1, ymm0, dword [rdx]{1to8}"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0xca], "vprolvd ymm1{k5}{z}, ymm0, ymm2"); // VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0xca], "vprolvd ymm1, ymm0, ymm2"); // VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0xca], "vprolvd ymm1{k5}, ymm0, ymm2"); // VPROLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0x0a], "vprolvd ymm1, ymm0, ymmword [rdx]"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPROLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x15, 0x0a], "vprolvq zmm1, zmm0, qword [rdx]{1to8}"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x15, 0x0a], "vprolvq xmm1, xmm0, qword [rdx]{1to2}"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0xca], "vprolvq zmm1{k5}{z}, zmm0, zmm2"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0xca], "vprolvq zmm1, zmm0, zmm2"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0xca], "vprolvq zmm1{k5}, zmm0, zmm2"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0x0a], "vprolvq zmm1, zmm0, zmmword [rdx]"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPROLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0xca], "vprolvq xmm1{k5}{z}, xmm0, xmm2"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0xca], "vprolvq xmm1, xmm0, xmm2"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0xca], "vprolvq xmm1{k5}, xmm0, xmm2"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0x0a], "vprolvq xmm1, xmm0, xmmword [rdx]"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPROLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x15, 0x0a], "vprolvd zmm1, zmm0, dword [rdx]{1to16}"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x15, 0x0a], "vprolvd xmm1, xmm0, dword [rdx]{1to4}"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0xca], "vprolvd zmm1{k5}{z}, zmm0, zmm2"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0xca], "vprolvd zmm1, zmm0, zmm2"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0xca], "vprolvd zmm1{k5}, zmm0, zmm2"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0x0a], "vprolvd zmm1, zmm0, zmmword [rdx]"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPROLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0xca], "vprolvd xmm1{k5}{z}, xmm0, xmm2"); // VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0xca], "vprolvd xmm1, xmm0, xmm2"); // VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0xca], "vprolvd xmm1{k5}, xmm0, xmm2"); // VPROLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0x0a], "vprolvd xmm1, xmm0, xmmword [rdx]"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPROLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x16, 0x0a], "vpermpd ymm1, ymm0, qword [rdx]{1to4}"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0xca], "vpermpd ymm1{k5}{z}, ymm0, ymm2"); // VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0xca], "vpermpd ymm1, ymm0, ymm2"); // VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0xca], "vpermpd ymm1{k5}, ymm0, ymm2"); // VPERMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0x0a], "vpermpd ymm1, ymm0, ymmword [rdx]"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x16, 0x0a], "vpermps ymm1, ymm0, dword [rdx]{1to8}"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0xca], "vpermps ymm1{k5}{z}, ymm0, ymm2"); // VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0xca], "vpermps ymm1, ymm0, ymm2"); // VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0xca], "vpermps ymm1{k5}, ymm0, ymm2"); // VPERMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0x0a], "vpermps ymm1, ymm0, ymmword [rdx]"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x16, 0x0a], "vpermpd zmm1, zmm0, qword [rdx]{1to8}"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0xca], "vpermpd zmm1{k5}{z}, zmm0, zmm2"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0xca], "vpermpd zmm1, zmm0, zmm2"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0xca], "vpermpd zmm1{k5}, zmm0, zmm2"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0x0a], "vpermpd zmm1, zmm0, zmmword [rdx]"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x16, 0x0a], "vpermps zmm1, zmm0, dword [rdx]{1to16}"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0xca], "vpermps zmm1{k5}{z}, zmm0, zmm2"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0xca], "vpermps zmm1, zmm0, zmm2"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0xca], "vpermps zmm1{k5}, zmm0, zmm2"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0x0a], "vpermps zmm1, zmm0, zmmword [rdx]"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0xca], "vbroadcastss ymm1{k5}{z}, xmm2"); // VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0x0a], "vbroadcastss ymm1{k5}{z}, dword [rdx]"); // VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0xca], "vbroadcastss ymm1, xmm2"); // VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0xca], "vbroadcastss ymm1{k5}, xmm2"); // VBROADCASTSS_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0x0a], "vbroadcastss ymm1, dword [rdx]"); // VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0x0a], "vbroadcastss ymm1{k5}, dword [rdx]"); // VBROADCASTSS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0xca], "vbroadcastss zmm1{k5}{z}, xmm2"); // VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0x0a], "vbroadcastss zmm1{k5}{z}, dword [rdx]"); // VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0xca], "vbroadcastss zmm1, xmm2"); // VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0xca], "vbroadcastss zmm1{k5}, xmm2"); // VBROADCASTSS_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0x0a], "vbroadcastss zmm1, dword [rdx]"); // VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0x0a], "vbroadcastss zmm1{k5}, dword [rdx]"); // VBROADCASTSS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0xca], "vbroadcastss xmm1{k5}{z}, xmm2"); // VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0x0a], "vbroadcastss xmm1{k5}{z}, dword [rdx]"); // VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0xca], "vbroadcastss xmm1, xmm2"); // VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0xca], "vbroadcastss xmm1{k5}, xmm2"); // VBROADCASTSS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0x0a], "vbroadcastss xmm1, dword [rdx]"); // VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0x0a], "vbroadcastss xmm1{k5}, dword [rdx]"); // VBROADCASTSS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0xca], "vbroadcastsd ymm1{k5}{z}, xmm2"); // VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0x0a], "vbroadcastsd ymm1{k5}{z}, qword [rdx]"); // VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0xca], "vbroadcastsd ymm1, xmm2"); // VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0xca], "vbroadcastsd ymm1{k5}, xmm2"); // VBROADCASTSD_YMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0x0a], "vbroadcastsd ymm1, qword [rdx]"); // VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0x0a], "vbroadcastsd ymm1{k5}, qword [rdx]"); // VBROADCASTSD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}{z}, xmm2"); // VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}{z}, qword [rdx]"); // VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0xca], "vbroadcastf32x2 ymm1, xmm2"); // VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}, xmm2"); // VBROADCASTF32X2_YMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0x0a], "vbroadcastf32x2 ymm1, qword [rdx]"); // VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}, qword [rdx]"); // VBROADCASTF32X2_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0xca], "vbroadcastsd zmm1{k5}{z}, xmm2"); // VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0x0a], "vbroadcastsd zmm1{k5}{z}, qword [rdx]"); // VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0xca], "vbroadcastsd zmm1, xmm2"); // VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0xca], "vbroadcastsd zmm1{k5}, xmm2"); // VBROADCASTSD_ZMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0x0a], "vbroadcastsd zmm1, qword [rdx]"); // VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0x0a], "vbroadcastsd zmm1{k5}, qword [rdx]"); // VBROADCASTSD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}{z}, xmm2"); // VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}{z}, qword [rdx]"); // VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0xca], "vbroadcastf32x2 zmm1, xmm2"); // VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}, xmm2"); // VBROADCASTF32X2_ZMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0x0a], "vbroadcastf32x2 zmm1, qword [rdx]"); // VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}, qword [rdx]"); // VBROADCASTF32X2_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}{z}, xmmword [rdx]"); // VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1a, 0x0a], "vbroadcastf64x2 ymm1, xmmword [rdx]"); // VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}, xmmword [rdx]"); // VBROADCASTF64X2_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}{z}, xmmword [rdx]"); // VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1a, 0x0a], "vbroadcastf32x4 ymm1, xmmword [rdx]"); // VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}, xmmword [rdx]"); // VBROADCASTF32X4_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}{z}, xmmword [rdx]"); // VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x0a], "vbroadcastf64x2 zmm1, xmmword [rdx]"); // VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}, xmmword [rdx]"); // VBROADCASTF64X2_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}{z}, xmmword [rdx]"); // VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x0a], "vbroadcastf32x4 zmm1, xmmword [rdx]"); // VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}, xmmword [rdx]"); // VBROADCASTF32X4_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}{z}, ymmword [rdx]"); // VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x0a], "vbroadcastf64x4 zmm1, ymmword [rdx]"); // VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}, ymmword [rdx]"); // VBROADCASTF64X4_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}{z}, ymmword [rdx]"); // VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x0a], "vbroadcastf32x8 zmm1, ymmword [rdx]"); // VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}, ymmword [rdx]"); // VBROADCASTF32X8_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0xca], "vpabsb ymm1{k5}{z}, ymm2"); // VPABSB_YMMi8_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0x0a], "vpabsb ymm1{k5}{z}, ymmword [rdx]"); // VPABSB_YMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0xca], "vpabsb ymm1, ymm2"); // VPABSB_YMMi8_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0xca], "vpabsb ymm1{k5}, ymm2"); // VPABSB_YMMi8_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0x0a], "vpabsb ymm1, ymmword [rdx]"); // VPABSB_YMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0x0a], "vpabsb ymm1{k5}, ymmword [rdx]"); // VPABSB_YMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0xca], "vpabsb zmm1{k5}{z}, zmm2"); // VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0x0a], "vpabsb zmm1{k5}{z}, zmmword [rdx]"); // VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0xca], "vpabsb zmm1, zmm2"); // VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0xca], "vpabsb zmm1{k5}, zmm2"); // VPABSB_ZMMi8_MASKmskw_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0x0a], "vpabsb zmm1, zmmword [rdx]"); // VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0x0a], "vpabsb zmm1{k5}, zmmword [rdx]"); // VPABSB_ZMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0xca], "vpabsb xmm1{k5}{z}, xmm2"); // VPABSB_XMMi8_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0x0a], "vpabsb xmm1{k5}{z}, xmmword [rdx]"); // VPABSB_XMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0xca], "vpabsb xmm1, xmm2"); // VPABSB_XMMi8_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0xca], "vpabsb xmm1{k5}, xmm2"); // VPABSB_XMMi8_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0x0a], "vpabsb xmm1, xmmword [rdx]"); // VPABSB_XMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0x0a], "vpabsb xmm1{k5}, xmmword [rdx]"); // VPABSB_XMMi8_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0xca], "vpabsw ymm1{k5}{z}, ymm2"); // VPABSW_YMMi16_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0x0a], "vpabsw ymm1{k5}{z}, ymmword [rdx]"); // VPABSW_YMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0xca], "vpabsw ymm1, ymm2"); // VPABSW_YMMi16_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0xca], "vpabsw ymm1{k5}, ymm2"); // VPABSW_YMMi16_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0x0a], "vpabsw ymm1, ymmword [rdx]"); // VPABSW_YMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0x0a], "vpabsw ymm1{k5}, ymmword [rdx]"); // VPABSW_YMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0xca], "vpabsw zmm1{k5}{z}, zmm2"); // VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0x0a], "vpabsw zmm1{k5}{z}, zmmword [rdx]"); // VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0xca], "vpabsw zmm1, zmm2"); // VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0xca], "vpabsw zmm1{k5}, zmm2"); // VPABSW_ZMMi16_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0x0a], "vpabsw zmm1, zmmword [rdx]"); // VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0x0a], "vpabsw zmm1{k5}, zmmword [rdx]"); // VPABSW_ZMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0xca], "vpabsw xmm1{k5}{z}, xmm2"); // VPABSW_XMMi16_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0x0a], "vpabsw xmm1{k5}{z}, xmmword [rdx]"); // VPABSW_XMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0xca], "vpabsw xmm1, xmm2"); // VPABSW_XMMi16_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0xca], "vpabsw xmm1{k5}, xmm2"); // VPABSW_XMMi16_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0x0a], "vpabsw xmm1, xmmword [rdx]"); // VPABSW_XMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0x0a], "vpabsw xmm1{k5}, xmmword [rdx]"); // VPABSW_XMMi16_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, dword [rdx]{1to8}"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x1e, 0x0a], "vpabsd ymm1, dword [rdx]{1to8}"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x1e, 0x0a], "vpabsd ymm1{k5}, dword [rdx]{1to8}"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0xca], "vpabsd ymm1{k5}{z}, ymm2"); // VPABSD_YMMi32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, ymmword [rdx]"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0xca], "vpabsd ymm1, ymm2"); // VPABSD_YMMi32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0xca], "vpabsd ymm1{k5}, ymm2"); // VPABSD_YMMi32_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0x0a], "vpabsd ymm1, ymmword [rdx]"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0x0a], "vpabsd ymm1{k5}, ymmword [rdx]"); // VPABSD_YMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, dword [rdx]{1to16}"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x1e, 0x0a], "vpabsd zmm1, dword [rdx]{1to16}"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x1e, 0x0a], "vpabsd zmm1{k5}, dword [rdx]{1to16}"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, dword [rdx]{1to4}"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x1e, 0x0a], "vpabsd xmm1, dword [rdx]{1to4}"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x1e, 0x0a], "vpabsd xmm1{k5}, dword [rdx]{1to4}"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0xca], "vpabsd zmm1{k5}{z}, zmm2"); // VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, zmmword [rdx]"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0xca], "vpabsd zmm1, zmm2"); // VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0xca], "vpabsd zmm1{k5}, zmm2"); // VPABSD_ZMMi32_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0x0a], "vpabsd zmm1, zmmword [rdx]"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0x0a], "vpabsd zmm1{k5}, zmmword [rdx]"); // VPABSD_ZMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0xca], "vpabsd xmm1{k5}{z}, xmm2"); // VPABSD_XMMi32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, xmmword [rdx]"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0xca], "vpabsd xmm1, xmm2"); // VPABSD_XMMi32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0xca], "vpabsd xmm1{k5}, xmm2"); // VPABSD_XMMi32_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0x0a], "vpabsd xmm1, xmmword [rdx]"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0x0a], "vpabsd xmm1{k5}, xmmword [rdx]"); // VPABSD_XMMi32_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, qword [rdx]{1to4}"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x1f, 0x0a], "vpabsq ymm1, qword [rdx]{1to4}"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x1f, 0x0a], "vpabsq ymm1{k5}, qword [rdx]{1to4}"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0xca], "vpabsq ymm1{k5}{z}, ymm2"); // VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, ymmword [rdx]"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0xca], "vpabsq ymm1, ymm2"); // VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0xca], "vpabsq ymm1{k5}, ymm2"); // VPABSQ_YMMi64_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0x0a], "vpabsq ymm1, ymmword [rdx]"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0x0a], "vpabsq ymm1{k5}, ymmword [rdx]"); // VPABSQ_YMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, qword [rdx]{1to8}"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x1f, 0x0a], "vpabsq zmm1, qword [rdx]{1to8}"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x1f, 0x0a], "vpabsq zmm1{k5}, qword [rdx]{1to8}"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, qword [rdx]{1to2}"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x1f, 0x0a], "vpabsq xmm1, qword [rdx]{1to2}"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x1f, 0x0a], "vpabsq xmm1{k5}, qword [rdx]{1to2}"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0xca], "vpabsq zmm1{k5}{z}, zmm2"); // VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, zmmword [rdx]"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0xca], "vpabsq zmm1, zmm2"); // VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0xca], "vpabsq zmm1{k5}, zmm2"); // VPABSQ_ZMMi64_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0x0a], "vpabsq zmm1, zmmword [rdx]"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0x0a], "vpabsq zmm1{k5}, zmmword [rdx]"); // VPABSQ_ZMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0xca], "vpabsq xmm1{k5}{z}, xmm2"); // VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, xmmword [rdx]"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0xca], "vpabsq xmm1, xmm2"); // VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0xca], "vpabsq xmm1{k5}, xmm2"); // VPABSQ_XMMi64_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0x0a], "vpabsq xmm1, xmmword [rdx]"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0x0a], "vpabsq xmm1{k5}, xmmword [rdx]"); // VPABSQ_XMMi64_MASKmskw_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0xca], "vpmovsxbw ymm1{k5}{z}, xmm2"); // VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0x0a], "vpmovsxbw ymm1{k5}{z}, xmmword [rdx]"); // VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0xca], "vpmovsxbw ymm1, xmm2"); // VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0xca], "vpmovsxbw ymm1{k5}, xmm2"); // VPMOVSXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0x0a], "vpmovsxbw ymm1, xmmword [rdx]"); // VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0x0a], "vpmovsxbw ymm1{k5}, xmmword [rdx]"); // VPMOVSXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0xca], "vpmovsxbw zmm1{k5}{z}, ymm2"); // VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0x0a], "vpmovsxbw zmm1{k5}{z}, ymmword [rdx]"); // VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0xca], "vpmovsxbw zmm1, ymm2"); // VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0xca], "vpmovsxbw zmm1{k5}, ymm2"); // VPMOVSXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0x0a], "vpmovsxbw zmm1, ymmword [rdx]"); // VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0x0a], "vpmovsxbw zmm1{k5}, ymmword [rdx]"); // VPMOVSXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0xca], "vpmovsxbw xmm1{k5}{z}, xmm2"); // VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}{z}, qword [rdx]"); // VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0xca], "vpmovsxbw xmm1, xmm2"); // VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0xca], "vpmovsxbw xmm1{k5}, xmm2"); // VPMOVSXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0x0a], "vpmovsxbw xmm1, qword [rdx]"); // VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}, qword [rdx]"); // VPMOVSXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0xca], "vpmovsxbd ymm1{k5}{z}, xmm2"); // VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0x0a], "vpmovsxbd ymm1{k5}{z}, qword [rdx]"); // VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0xca], "vpmovsxbd ymm1, xmm2"); // VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0xca], "vpmovsxbd ymm1{k5}, xmm2"); // VPMOVSXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0x0a], "vpmovsxbd ymm1, qword [rdx]"); // VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0x0a], "vpmovsxbd ymm1{k5}, qword [rdx]"); // VPMOVSXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0xca], "vpmovsxbd zmm1{k5}{z}, xmm2"); // VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0x0a], "vpmovsxbd zmm1{k5}{z}, xmmword [rdx]"); // VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0xca], "vpmovsxbd zmm1, xmm2"); // VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0xca], "vpmovsxbd zmm1{k5}, xmm2"); // VPMOVSXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0x0a], "vpmovsxbd zmm1, xmmword [rdx]"); // VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0x0a], "vpmovsxbd zmm1{k5}, xmmword [rdx]"); // VPMOVSXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0xca], "vpmovsxbd xmm1{k5}{z}, xmm2"); // VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}{z}, dword [rdx]"); // VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0xca], "vpmovsxbd xmm1, xmm2"); // VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0xca], "vpmovsxbd xmm1{k5}, xmm2"); // VPMOVSXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0x0a], "vpmovsxbd xmm1, dword [rdx]"); // VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}, dword [rdx]"); // VPMOVSXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0xca], "vpmovsxbq ymm1{k5}{z}, xmm2"); // VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0x0a], "vpmovsxbq ymm1{k5}{z}, dword [rdx]"); // VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0xca], "vpmovsxbq ymm1, xmm2"); // VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0xca], "vpmovsxbq ymm1{k5}, xmm2"); // VPMOVSXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0x0a], "vpmovsxbq ymm1, dword [rdx]"); // VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0x0a], "vpmovsxbq ymm1{k5}, dword [rdx]"); // VPMOVSXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0xca], "vpmovsxbq zmm1{k5}{z}, xmm2"); // VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0x0a], "vpmovsxbq zmm1{k5}{z}, qword [rdx]"); // VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0xca], "vpmovsxbq zmm1, xmm2"); // VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0xca], "vpmovsxbq zmm1{k5}, xmm2"); // VPMOVSXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0x0a], "vpmovsxbq zmm1, qword [rdx]"); // VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0x0a], "vpmovsxbq zmm1{k5}, qword [rdx]"); // VPMOVSXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0xca], "vpmovsxbq xmm1{k5}{z}, xmm2"); // VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}{z}, word [rdx]"); // VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0xca], "vpmovsxbq xmm1, xmm2"); // VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0xca], "vpmovsxbq xmm1{k5}, xmm2"); // VPMOVSXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0x0a], "vpmovsxbq xmm1, word [rdx]"); // VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}, word [rdx]"); // VPMOVSXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0xca], "vpmovsxwd ymm1{k5}{z}, xmm2"); // VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0x0a], "vpmovsxwd ymm1{k5}{z}, xmmword [rdx]"); // VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0xca], "vpmovsxwd ymm1, xmm2"); // VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0xca], "vpmovsxwd ymm1{k5}, xmm2"); // VPMOVSXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0x0a], "vpmovsxwd ymm1, xmmword [rdx]"); // VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0x0a], "vpmovsxwd ymm1{k5}, xmmword [rdx]"); // VPMOVSXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0xca], "vpmovsxwd zmm1{k5}{z}, ymm2"); // VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0x0a], "vpmovsxwd zmm1{k5}{z}, ymmword [rdx]"); // VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0xca], "vpmovsxwd zmm1, ymm2"); // VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0xca], "vpmovsxwd zmm1{k5}, ymm2"); // VPMOVSXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0x0a], "vpmovsxwd zmm1, ymmword [rdx]"); // VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0x0a], "vpmovsxwd zmm1{k5}, ymmword [rdx]"); // VPMOVSXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0xca], "vpmovsxwd xmm1{k5}{z}, xmm2"); // VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}{z}, qword [rdx]"); // VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0xca], "vpmovsxwd xmm1, xmm2"); // VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0xca], "vpmovsxwd xmm1{k5}, xmm2"); // VPMOVSXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0x0a], "vpmovsxwd xmm1, qword [rdx]"); // VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}, qword [rdx]"); // VPMOVSXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0xca], "vpmovsxwq ymm1{k5}{z}, xmm2"); // VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0x0a], "vpmovsxwq ymm1{k5}{z}, qword [rdx]"); // VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0xca], "vpmovsxwq ymm1, xmm2"); // VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0xca], "vpmovsxwq ymm1{k5}, xmm2"); // VPMOVSXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0x0a], "vpmovsxwq ymm1, qword [rdx]"); // VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0x0a], "vpmovsxwq ymm1{k5}, qword [rdx]"); // VPMOVSXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0xca], "vpmovsxwq zmm1{k5}{z}, xmm2"); // VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0x0a], "vpmovsxwq zmm1{k5}{z}, xmmword [rdx]"); // VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0xca], "vpmovsxwq zmm1, xmm2"); // VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0xca], "vpmovsxwq zmm1{k5}, xmm2"); // VPMOVSXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0x0a], "vpmovsxwq zmm1, xmmword [rdx]"); // VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0x0a], "vpmovsxwq zmm1{k5}, xmmword [rdx]"); // VPMOVSXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0xca], "vpmovsxwq xmm1{k5}{z}, xmm2"); // VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}{z}, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0xca], "vpmovsxwq xmm1, xmm2"); // VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0xca], "vpmovsxwq xmm1{k5}, xmm2"); // VPMOVSXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x0a], "vpmovsxwq xmm1, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}, dword [rdx]"); // VPMOVSXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0xca], "vpmovsxdq ymm1{k5}{z}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x0a], "vpmovsxdq ymm1{k5}{z}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0xca], "vpmovsxdq ymm1{k5}, xmm2"); // VPMOVSXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x0a], "vpmovsxdq ymm1, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x0a], "vpmovsxdq ymm1{k5}, xmmword [rdx]"); // VPMOVSXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0xca], "vpmovsxdq zmm1{k5}{z}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x0a], "vpmovsxdq zmm1{k5}{z}, ymmword [rdx]"); // VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0xca], "vpmovsxdq zmm1, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0xca], "vpmovsxdq zmm1{k5}, ymm2"); // VPMOVSXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0x0a], "vpmovsxdq zmm1, ymmword [rdx]"); // VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0x0a], "vpmovsxdq zmm1{k5}, ymmword [rdx]"); // VPMOVSXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0xca], "vpmovsxdq xmm1{k5}{z}, xmm2"); // VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}{z}, qword [rdx]"); // VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0xca], "vpmovsxdq xmm1, xmm2"); // VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0xca], "vpmovsxdq xmm1{k5}, xmm2"); // VPMOVSXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0x0a], "vpmovsxdq xmm1, qword [rdx]"); // VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}, qword [rdx]"); // VPMOVSXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0xca], "vptestmw k1, ymm0, ymm2"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0xca], "vptestmw k1{k5}, ymm0, ymm2"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x0a], "vptestmw k1, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x0a], "vptestmw k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0xca], "vptestmb k1, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0xca], "vptestmb k1{k5}, ymm0, ymm2"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x0a], "vptestmb k1, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x0a], "vptestmb k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0xca], "vptestmw k1, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0xca], "vptestmw k1{k5}, zmm0, zmm2"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x0a], "vptestmw k1, zmm0, zmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0x0a], "vptestmw k1{k5}, zmm0, zmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0xca], "vptestmw k1, xmm0, xmm2"); // VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0xca], "vptestmw k1{k5}, xmm0, xmm2"); // VPTESTMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0x0a], "vptestmw k1, xmm0, xmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0x0a], "vptestmw k1{k5}, xmm0, xmmword [rdx]"); // VPTESTMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0xca], "vptestmb k1, zmm0, zmm2"); // VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0xca], "vptestmb k1{k5}, zmm0, zmm2"); // VPTESTMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0x0a], "vptestmb k1, zmm0, zmmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0x0a], "vptestmb k1{k5}, zmm0, zmmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0xca], "vptestmb k1, xmm0, xmm2"); // VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0xca], "vptestmb k1{k5}, xmm0, xmm2"); // VPTESTMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0x0a], "vptestmb k1, xmm0, xmmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0x0a], "vptestmb k1{k5}, xmm0, xmmword [rdx]"); // VPTESTMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x27, 0x0a], "vptestmq k1, ymm0, qword [rdx]{1to4}"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0xca], "vptestmq k1, ymm0, ymm2"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0xca], "vptestmq k1{k5}, ymm0, ymm2"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0x0a], "vptestmq k1, ymm0, ymmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x0a], "vptestmd k1, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0xca], "vptestmd k1, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0xca], "vptestmd k1{k5}, ymm0, ymm2"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x0a], "vptestmd k1, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, ymmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x0a], "vptestmq k1, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x0a], "vptestmq k1, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0xca], "vptestmq k1, zmm0, zmm2"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0xca], "vptestmq k1{k5}, zmm0, zmm2"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0x0a], "vptestmq k1, zmm0, zmmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, zmmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0xca], "vptestmq k1, xmm0, xmm2"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0xca], "vptestmq k1{k5}, xmm0, xmm2"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0x0a], "vptestmq k1, xmm0, xmmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, xmmword [rdx]"); // VPTESTMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x27, 0x0a], "vptestmd k1, zmm0, dword [rdx]{1to16}"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, dword [rdx]{1to16}"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x27, 0x0a], "vptestmd k1, xmm0, dword [rdx]{1to4}"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, dword [rdx]{1to4}"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0xca], "vptestmd k1, zmm0, zmm2"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0xca], "vptestmd k1{k5}, zmm0, zmm2"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0x0a], "vptestmd k1, zmm0, zmmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, zmmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0xca], "vptestmd k1, xmm0, xmm2"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0xca], "vptestmd k1{k5}, xmm0, xmm2"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0x0a], "vptestmd k1, xmm0, xmmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, xmmword [rdx]"); // VPTESTMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x0a], "vpmuldq ymm1, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0xca], "vpmuldq ymm1{k5}{z}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0xca], "vpmuldq ymm1{k5}, ymm0, ymm2"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0x0a], "vpmuldq ymm1, ymm0, ymmword [rdx]"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULDQ_YMMi64_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x28, 0x0a], "vpmuldq zmm1, zmm0, qword [rdx]{1to8}"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x28, 0x0a], "vpmuldq xmm1, xmm0, qword [rdx]{1to2}"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0xca], "vpmuldq zmm1{k5}{z}, zmm0, zmm2"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0xca], "vpmuldq zmm1, zmm0, zmm2"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0xca], "vpmuldq zmm1{k5}, zmm0, zmm2"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0x0a], "vpmuldq zmm1, zmm0, zmmword [rdx]"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULDQ_ZMMi64_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0xca], "vpmuldq xmm1{k5}{z}, xmm0, xmm2"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0xca], "vpmuldq xmm1, xmm0, xmm2"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0xca], "vpmuldq xmm1{k5}, xmm0, xmm2"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0x0a], "vpmuldq xmm1, xmm0, xmmword [rdx]"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULDQ_XMMi64_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x29, 0x0a], "vpcmpeqq k1, ymm0, qword [rdx]{1to4}"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0xca], "vpcmpeqq k1, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0xca], "vpcmpeqq k1{k5}, ymm0, ymm2"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x0a], "vpcmpeqq k1, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, ymmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x0a], "vpcmpeqq k1, zmm0, qword [rdx]{1to8}"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x29, 0x0a], "vpcmpeqq k1, xmm0, qword [rdx]{1to2}"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0xca], "vpcmpeqq k1, zmm0, zmm2"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0xca], "vpcmpeqq k1{k5}, zmm0, zmm2"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0x0a], "vpcmpeqq k1, zmm0, zmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, zmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0xca], "vpcmpeqq k1, xmm0, xmm2"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0xca], "vpcmpeqq k1{k5}, xmm0, xmm2"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x0a], "vpcmpeqq k1, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, xmmword [rdx]"); // VPCMPEQQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [rdx]"); // VMOVNTDQA_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x0a], "vmovntdqa zmm1, zmmword [rdx]"); // VMOVNTDQA_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [rdx]"); // VMOVNTDQA_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, dword [rdx]{1to8}"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0xca], "vpackusdw ymm1{k5}{z}, ymm0, ymm2"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0xca], "vpackusdw ymm1, ymm0, ymm2"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0xca], "vpackusdw ymm1{k5}, ymm0, ymm2"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, ymmword [rdx]"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, ymmword [rdx]"); // VPACKUSDW_YMMu16_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, dword [rdx]{1to16}"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, dword [rdx]{1to4}"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0xca], "vpackusdw zmm1{k5}{z}, zmm0, zmm2"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0xca], "vpackusdw zmm1, zmm0, zmm2"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0xca], "vpackusdw zmm1{k5}, zmm0, zmm2"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, zmmword [rdx]"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, zmmword [rdx]"); // VPACKUSDW_ZMMu16_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0xca], "vpackusdw xmm1{k5}{z}, xmm0, xmm2"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0xca], "vpackusdw xmm1, xmm0, xmm2"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0xca], "vpackusdw xmm1{k5}, xmm0, xmm2"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, xmmword [rdx]"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, xmmword [rdx]"); // VPACKUSDW_XMMu16_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x2c, 0xca], "vscalefpd zmm1{rz-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0xca], "vscalefpd zmm1{rd-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, qword [rdx]{1to4}"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0xca], "vscalefpd ymm1{k5}{z}, ymm0, ymm2"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0xca], "vscalefpd ymm1, ymm0, ymm2"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0xca], "vscalefpd ymm1{k5}, ymm0, ymm2"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, ymmword [rdx]"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, ymmword [rdx]"); // VSCALEFPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2c, 0xca], "vscalefps zmm1{rz-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2c, 0xca], "vscalefps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0xca], "vscalefps zmm1{rd-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0xca], "vscalefps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0x0a], "vscalefps ymm1, ymm0, dword [rdx]{1to8}"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0xca], "vscalefps ymm1{k5}{z}, ymm0, ymm2"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0xca], "vscalefps ymm1, ymm0, ymm2"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0xca], "vscalefps ymm1{k5}, ymm0, ymm2"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0x0a], "vscalefps ymm1, ymm0, ymmword [rdx]"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, ymmword [rdx]"); // VSCALEFPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0xca], "vscalefpd zmm1{ru-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0xca], "vscalefpd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, qword [rdx]{1to8}"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0xca], "vscalefpd zmm1{rne-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, qword [rdx]{1to2}"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0xca], "vscalefpd zmm1, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0xca], "vscalefpd zmm1{k5}, zmm0, zmm2"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, zmmword [rdx]"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, zmmword [rdx]"); // VSCALEFPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0xca], "vscalefpd xmm1{k5}{z}, xmm0, xmm2"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0xca], "vscalefpd xmm1, xmm0, xmm2"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0xca], "vscalefpd xmm1{k5}, xmm0, xmm2"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, xmmword [rdx]"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, xmmword [rdx]"); // VSCALEFPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0xca], "vscalefps zmm1{ru-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0xca], "vscalefps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0x0a], "vscalefps zmm1, zmm0, dword [rdx]{1to16}"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0xca], "vscalefps zmm1{rne-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0xca], "vscalefps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0x0a], "vscalefps xmm1, xmm0, dword [rdx]{1to4}"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0xca], "vscalefps zmm1, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0xca], "vscalefps zmm1{k5}, zmm0, zmm2"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0x0a], "vscalefps zmm1, zmm0, zmmword [rdx]"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, zmmword [rdx]"); // VSCALEFPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0xca], "vscalefps xmm1{k5}{z}, xmm0, xmm2"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0xca], "vscalefps xmm1, xmm0, xmm2"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0xca], "vscalefps xmm1{k5}, xmm0, xmm2"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0x0a], "vscalefps xmm1, xmm0, xmmword [rdx]"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, xmmword [rdx]"); // VSCALEFPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x2d, 0xca], "vscalefsd xmm1{rz-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2d, 0xca], "vscalefsd xmm1{rd-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0x0a], "vscalefsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0xca], "vscalefsd xmm1, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0xca], "vscalefsd xmm1{k5}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x0a], "vscalefsd xmm1, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x0a], "vscalefsd xmm1{k5}, xmm0, qword [rdx]"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2d, 0xca], "vscalefss xmm1{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2d, 0xca], "vscalefss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2d, 0xca], "vscalefss xmm1{rd-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2d, 0xca], "vscalefss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0xca], "vscalefss xmm1{k5}{z}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0x0a], "vscalefss xmm1{k5}{z}, xmm0, dword [rdx]"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0xca], "vscalefss xmm1, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0xca], "vscalefss xmm1{k5}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0x0a], "vscalefss xmm1, xmm0, dword [rdx]"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0x0a], "vscalefss xmm1{k5}, xmm0, dword [rdx]"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2d, 0xca], "vscalefsd xmm1{ru-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2d, 0xca], "vscalefsd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2d, 0xca], "vscalefsd xmm1{rne-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSCALEFSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2d, 0xca], "vscalefss xmm1{ru-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2d, 0xca], "vscalefss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2d, 0xca], "vscalefss xmm1{rne-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2d, 0xca], "vscalefss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VSCALEFSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0xca], "vpmovzxbw ymm1{k5}{z}, xmm2"); // VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0x0a], "vpmovzxbw ymm1{k5}{z}, xmmword [rdx]"); // VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0xca], "vpmovzxbw ymm1, xmm2"); // VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0xca], "vpmovzxbw ymm1{k5}, xmm2"); // VPMOVZXBW_YMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0x0a], "vpmovzxbw ymm1, xmmword [rdx]"); // VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0x0a], "vpmovzxbw ymm1{k5}, xmmword [rdx]"); // VPMOVZXBW_YMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0xca], "vpmovzxbw zmm1{k5}{z}, ymm2"); // VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0x0a], "vpmovzxbw zmm1{k5}{z}, ymmword [rdx]"); // VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0xca], "vpmovzxbw zmm1, ymm2"); // VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0xca], "vpmovzxbw zmm1{k5}, ymm2"); // VPMOVZXBW_ZMMi16_MASKmskw_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0x0a], "vpmovzxbw zmm1, ymmword [rdx]"); // VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0x0a], "vpmovzxbw zmm1{k5}, ymmword [rdx]"); // VPMOVZXBW_ZMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0xca], "vpmovzxbw xmm1{k5}{z}, xmm2"); // VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}{z}, qword [rdx]"); // VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0xca], "vpmovzxbw xmm1, xmm2"); // VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0xca], "vpmovzxbw xmm1{k5}, xmm2"); // VPMOVZXBW_XMMi16_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0x0a], "vpmovzxbw xmm1, qword [rdx]"); // VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}, qword [rdx]"); // VPMOVZXBW_XMMi16_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0xca], "vpmovzxbd ymm1{k5}{z}, xmm2"); // VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0x0a], "vpmovzxbd ymm1{k5}{z}, qword [rdx]"); // VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0xca], "vpmovzxbd ymm1, xmm2"); // VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0xca], "vpmovzxbd ymm1{k5}, xmm2"); // VPMOVZXBD_YMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0x0a], "vpmovzxbd ymm1, qword [rdx]"); // VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0x0a], "vpmovzxbd ymm1{k5}, qword [rdx]"); // VPMOVZXBD_YMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0xca], "vpmovzxbd zmm1{k5}{z}, xmm2"); // VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0x0a], "vpmovzxbd zmm1{k5}{z}, xmmword [rdx]"); // VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0xca], "vpmovzxbd zmm1, xmm2"); // VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0xca], "vpmovzxbd zmm1{k5}, xmm2"); // VPMOVZXBD_ZMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0x0a], "vpmovzxbd zmm1, xmmword [rdx]"); // VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0x0a], "vpmovzxbd zmm1{k5}, xmmword [rdx]"); // VPMOVZXBD_ZMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0xca], "vpmovzxbd xmm1{k5}{z}, xmm2"); // VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}{z}, dword [rdx]"); // VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0xca], "vpmovzxbd xmm1, xmm2"); // VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0xca], "vpmovzxbd xmm1{k5}, xmm2"); // VPMOVZXBD_XMMi32_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0x0a], "vpmovzxbd xmm1, dword [rdx]"); // VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}, dword [rdx]"); // VPMOVZXBD_XMMi32_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0xca], "vpmovzxbq ymm1{k5}{z}, xmm2"); // VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0x0a], "vpmovzxbq ymm1{k5}{z}, dword [rdx]"); // VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0xca], "vpmovzxbq ymm1, xmm2"); // VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0xca], "vpmovzxbq ymm1{k5}, xmm2"); // VPMOVZXBQ_YMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0x0a], "vpmovzxbq ymm1, dword [rdx]"); // VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0x0a], "vpmovzxbq ymm1{k5}, dword [rdx]"); // VPMOVZXBQ_YMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0xca], "vpmovzxbq zmm1{k5}{z}, xmm2"); // VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0x0a], "vpmovzxbq zmm1{k5}{z}, qword [rdx]"); // VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0xca], "vpmovzxbq zmm1, xmm2"); // VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0xca], "vpmovzxbq zmm1{k5}, xmm2"); // VPMOVZXBQ_ZMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0x0a], "vpmovzxbq zmm1, qword [rdx]"); // VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0x0a], "vpmovzxbq zmm1{k5}, qword [rdx]"); // VPMOVZXBQ_ZMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0xca], "vpmovzxbq xmm1{k5}{z}, xmm2"); // VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}{z}, word [rdx]"); // VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0xca], "vpmovzxbq xmm1, xmm2"); // VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0xca], "vpmovzxbq xmm1{k5}, xmm2"); // VPMOVZXBQ_XMMi64_MASKmskw_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0x0a], "vpmovzxbq xmm1, word [rdx]"); // VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}, word [rdx]"); // VPMOVZXBQ_XMMi64_MASKmskw_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0xca], "vpmovzxwd ymm1{k5}{z}, xmm2"); // VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0x0a], "vpmovzxwd ymm1{k5}{z}, xmmword [rdx]"); // VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0xca], "vpmovzxwd ymm1, xmm2"); // VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0xca], "vpmovzxwd ymm1{k5}, xmm2"); // VPMOVZXWD_YMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0x0a], "vpmovzxwd ymm1, xmmword [rdx]"); // VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0x0a], "vpmovzxwd ymm1{k5}, xmmword [rdx]"); // VPMOVZXWD_YMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0xca], "vpmovzxwd zmm1{k5}{z}, ymm2"); // VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0x0a], "vpmovzxwd zmm1{k5}{z}, ymmword [rdx]"); // VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0xca], "vpmovzxwd zmm1, ymm2"); // VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0xca], "vpmovzxwd zmm1{k5}, ymm2"); // VPMOVZXWD_ZMMi32_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0x0a], "vpmovzxwd zmm1, ymmword [rdx]"); // VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0x0a], "vpmovzxwd zmm1{k5}, ymmword [rdx]"); // VPMOVZXWD_ZMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0xca], "vpmovzxwd xmm1{k5}{z}, xmm2"); // VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}{z}, qword [rdx]"); // VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0xca], "vpmovzxwd xmm1, xmm2"); // VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0xca], "vpmovzxwd xmm1{k5}, xmm2"); // VPMOVZXWD_XMMi32_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0x0a], "vpmovzxwd xmm1, qword [rdx]"); // VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}, qword [rdx]"); // VPMOVZXWD_XMMi32_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0xca], "vpmovzxwq ymm1{k5}{z}, xmm2"); // VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0x0a], "vpmovzxwq ymm1{k5}{z}, qword [rdx]"); // VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0xca], "vpmovzxwq ymm1, xmm2"); // VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0xca], "vpmovzxwq ymm1{k5}, xmm2"); // VPMOVZXWQ_YMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0x0a], "vpmovzxwq ymm1, qword [rdx]"); // VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0x0a], "vpmovzxwq ymm1{k5}, qword [rdx]"); // VPMOVZXWQ_YMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0xca], "vpmovzxwq zmm1{k5}{z}, xmm2"); // VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0x0a], "vpmovzxwq zmm1{k5}{z}, xmmword [rdx]"); // VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0xca], "vpmovzxwq zmm1, xmm2"); // VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0xca], "vpmovzxwq zmm1{k5}, xmm2"); // VPMOVZXWQ_ZMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0x0a], "vpmovzxwq zmm1, xmmword [rdx]"); // VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0x0a], "vpmovzxwq zmm1{k5}, xmmword [rdx]"); // VPMOVZXWQ_ZMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0xca], "vpmovzxwq xmm1{k5}{z}, xmm2"); // VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}{z}, dword [rdx]"); // VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0xca], "vpmovzxwq xmm1, xmm2"); // VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0xca], "vpmovzxwq xmm1{k5}, xmm2"); // VPMOVZXWQ_XMMi64_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0x0a], "vpmovzxwq xmm1, dword [rdx]"); // VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}, dword [rdx]"); // VPMOVZXWQ_XMMi64_MASKmskw_MEMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0xca], "vpmovzxdq ymm1{k5}{z}, xmm2"); // VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0x0a], "vpmovzxdq ymm1{k5}{z}, xmmword [rdx]"); // VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0xca], "vpmovzxdq ymm1, xmm2"); // VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0xca], "vpmovzxdq ymm1{k5}, xmm2"); // VPMOVZXDQ_YMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0x0a], "vpmovzxdq ymm1, xmmword [rdx]"); // VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0x0a], "vpmovzxdq ymm1{k5}, xmmword [rdx]"); // VPMOVZXDQ_YMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0xca], "vpmovzxdq zmm1{k5}{z}, ymm2"); // VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0x0a], "vpmovzxdq zmm1{k5}{z}, ymmword [rdx]"); // VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0xca], "vpmovzxdq zmm1, ymm2"); // VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0xca], "vpmovzxdq zmm1{k5}, ymm2"); // VPMOVZXDQ_ZMMi64_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0x0a], "vpmovzxdq zmm1, ymmword [rdx]"); // VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0x0a], "vpmovzxdq zmm1{k5}, ymmword [rdx]"); // VPMOVZXDQ_ZMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0xca], "vpmovzxdq xmm1{k5}{z}, xmm2"); // VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}{z}, qword [rdx]"); // VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0xca], "vpmovzxdq xmm1, xmm2"); // VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0xca], "vpmovzxdq xmm1{k5}, xmm2"); // VPMOVZXDQ_XMMi64_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0x0a], "vpmovzxdq xmm1, qword [rdx]"); // VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}, qword [rdx]"); // VPMOVZXDQ_XMMi64_MASKmskw_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x36, 0x0a], "vpermq ymm1, ymm0, qword [rdx]{1to4}"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0xca], "vpermq ymm1{k5}{z}, ymm0, ymm2"); // VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0xca], "vpermq ymm1, ymm0, ymm2"); // VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0xca], "vpermq ymm1{k5}, ymm0, ymm2"); // VPERMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0x0a], "vpermq ymm1, ymm0, ymmword [rdx]"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x36, 0x0a], "vpermd ymm1, ymm0, dword [rdx]{1to8}"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0xca], "vpermd ymm1{k5}{z}, ymm0, ymm2"); // VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0xca], "vpermd ymm1, ymm0, ymm2"); // VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0xca], "vpermd ymm1{k5}, ymm0, ymm2"); // VPERMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0x0a], "vpermd ymm1, ymm0, ymmword [rdx]"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x36, 0x0a], "vpermq zmm1, zmm0, qword [rdx]{1to8}"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0xca], "vpermq zmm1{k5}{z}, zmm0, zmm2"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0xca], "vpermq zmm1, zmm0, zmm2"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0xca], "vpermq zmm1{k5}, zmm0, zmm2"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0x0a], "vpermq zmm1, zmm0, zmmword [rdx]"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x36, 0x0a], "vpermd zmm1, zmm0, dword [rdx]{1to16}"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0xca], "vpermd zmm1{k5}{z}, zmm0, zmm2"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0xca], "vpermd zmm1, zmm0, zmm2"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0xca], "vpermd zmm1{k5}, zmm0, zmm2"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0x0a], "vpermd zmm1, zmm0, zmmword [rdx]"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x37, 0x0a], "vpcmpgtq k1, ymm0, qword [rdx]{1to4}"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0xca], "vpcmpgtq k1, ymm0, ymm2"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0xca], "vpcmpgtq k1{k5}, ymm0, ymm2"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0x0a], "vpcmpgtq k1, ymm0, ymmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, ymmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x37, 0x0a], "vpcmpgtq k1, zmm0, qword [rdx]{1to8}"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x37, 0x0a], "vpcmpgtq k1, xmm0, qword [rdx]{1to2}"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0xca], "vpcmpgtq k1, zmm0, zmm2"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0xca], "vpcmpgtq k1{k5}, zmm0, zmm2"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0x0a], "vpcmpgtq k1, zmm0, zmmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, zmmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0xca], "vpcmpgtq k1, xmm0, xmm2"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0xca], "vpcmpgtq k1{k5}, xmm0, xmm2"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0x0a], "vpcmpgtq k1, xmm0, xmmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, xmmword [rdx]"); // VPCMPGTQ_MASKmskw_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0xca], "vpminsb ymm1{k5}{z}, ymm0, ymm2"); // VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0x0a], "vpminsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0xca], "vpminsb ymm1, ymm0, ymm2"); // VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0xca], "vpminsb ymm1{k5}, ymm0, ymm2"); // VPMINSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0x0a], "vpminsb ymm1, ymm0, ymmword [rdx]"); // VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0x0a], "vpminsb ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0xca], "vpminsb zmm1{k5}{z}, zmm0, zmm2"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0x0a], "vpminsb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0xca], "vpminsb zmm1, zmm0, zmm2"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0xca], "vpminsb zmm1{k5}, zmm0, zmm2"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0x0a], "vpminsb zmm1, zmm0, zmmword [rdx]"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0x0a], "vpminsb zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0xca], "vpminsb xmm1{k5}{z}, xmm0, xmm2"); // VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0x0a], "vpminsb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0xca], "vpminsb xmm1, xmm0, xmm2"); // VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0xca], "vpminsb xmm1{k5}, xmm0, xmm2"); // VPMINSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0x0a], "vpminsb xmm1, xmm0, xmmword [rdx]"); // VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0x0a], "vpminsb xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x39, 0x0a], "vpminsq ymm1, ymm0, qword [rdx]{1to4}"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0xca], "vpminsq ymm1{k5}{z}, ymm0, ymm2"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0xca], "vpminsq ymm1, ymm0, ymm2"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0xca], "vpminsq ymm1{k5}, ymm0, ymm2"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0x0a], "vpminsq ymm1, ymm0, ymmword [rdx]"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x39, 0x0a], "vpminsd ymm1, ymm0, dword [rdx]{1to8}"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0xca], "vpminsd ymm1{k5}{z}, ymm0, ymm2"); // VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0xca], "vpminsd ymm1, ymm0, ymm2"); // VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0xca], "vpminsd ymm1{k5}, ymm0, ymm2"); // VPMINSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0x0a], "vpminsd ymm1, ymm0, ymmword [rdx]"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x39, 0x0a], "vpminsq zmm1, zmm0, qword [rdx]{1to8}"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x39, 0x0a], "vpminsq xmm1, xmm0, qword [rdx]{1to2}"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0xca], "vpminsq zmm1{k5}{z}, zmm0, zmm2"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0xca], "vpminsq zmm1, zmm0, zmm2"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0xca], "vpminsq zmm1{k5}, zmm0, zmm2"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0x0a], "vpminsq zmm1, zmm0, zmmword [rdx]"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0xca], "vpminsq xmm1{k5}{z}, xmm0, xmm2"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0xca], "vpminsq xmm1, xmm0, xmm2"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0xca], "vpminsq xmm1{k5}, xmm0, xmm2"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0x0a], "vpminsq xmm1, xmm0, xmmword [rdx]"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x39, 0x0a], "vpminsd zmm1, zmm0, dword [rdx]{1to16}"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x39, 0x0a], "vpminsd xmm1, xmm0, dword [rdx]{1to4}"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0xca], "vpminsd zmm1{k5}{z}, zmm0, zmm2"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0xca], "vpminsd zmm1, zmm0, zmm2"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0xca], "vpminsd zmm1{k5}, zmm0, zmm2"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0x0a], "vpminsd zmm1, zmm0, zmmword [rdx]"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0xca], "vpminsd xmm1{k5}{z}, xmm0, xmm2"); // VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0xca], "vpminsd xmm1, xmm0, xmm2"); // VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0xca], "vpminsd xmm1{k5}, xmm0, xmm2"); // VPMINSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0x0a], "vpminsd xmm1, xmm0, xmmword [rdx]"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0xca], "vpminuw ymm1{k5}{z}, ymm0, ymm2"); // VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0x0a], "vpminuw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0xca], "vpminuw ymm1, ymm0, ymm2"); // VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0xca], "vpminuw ymm1{k5}, ymm0, ymm2"); // VPMINUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0x0a], "vpminuw ymm1, ymm0, ymmword [rdx]"); // VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0x0a], "vpminuw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0xca], "vpminuw zmm1{k5}{z}, zmm0, zmm2"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0x0a], "vpminuw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0xca], "vpminuw zmm1, zmm0, zmm2"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0xca], "vpminuw zmm1{k5}, zmm0, zmm2"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0x0a], "vpminuw zmm1, zmm0, zmmword [rdx]"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0x0a], "vpminuw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0xca], "vpminuw xmm1{k5}{z}, xmm0, xmm2"); // VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0x0a], "vpminuw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0xca], "vpminuw xmm1, xmm0, xmm2"); // VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0xca], "vpminuw xmm1{k5}, xmm0, xmm2"); // VPMINUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0x0a], "vpminuw xmm1, xmm0, xmmword [rdx]"); // VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0x0a], "vpminuw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3b, 0x0a], "vpminuq ymm1, ymm0, qword [rdx]{1to4}"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0xca], "vpminuq ymm1{k5}{z}, ymm0, ymm2"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0xca], "vpminuq ymm1, ymm0, ymm2"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0xca], "vpminuq ymm1{k5}, ymm0, ymm2"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0x0a], "vpminuq ymm1, ymm0, ymmword [rdx]"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3b, 0x0a], "vpminud ymm1, ymm0, dword [rdx]{1to8}"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0xca], "vpminud ymm1{k5}{z}, ymm0, ymm2"); // VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0xca], "vpminud ymm1, ymm0, ymm2"); // VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0xca], "vpminud ymm1{k5}, ymm0, ymm2"); // VPMINUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0x0a], "vpminud ymm1, ymm0, ymmword [rdx]"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, ymmword [rdx]"); // VPMINUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3b, 0x0a], "vpminuq zmm1, zmm0, qword [rdx]{1to8}"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3b, 0x0a], "vpminuq xmm1, xmm0, qword [rdx]{1to2}"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0xca], "vpminuq zmm1{k5}{z}, zmm0, zmm2"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0xca], "vpminuq zmm1, zmm0, zmm2"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0xca], "vpminuq zmm1{k5}, zmm0, zmm2"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0x0a], "vpminuq zmm1, zmm0, zmmword [rdx]"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0xca], "vpminuq xmm1{k5}{z}, xmm0, xmm2"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0xca], "vpminuq xmm1, xmm0, xmm2"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0xca], "vpminuq xmm1{k5}, xmm0, xmm2"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0x0a], "vpminuq xmm1, xmm0, xmmword [rdx]"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3b, 0x0a], "vpminud zmm1, zmm0, dword [rdx]{1to16}"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3b, 0x0a], "vpminud xmm1, xmm0, dword [rdx]{1to4}"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0xca], "vpminud zmm1{k5}{z}, zmm0, zmm2"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0xca], "vpminud zmm1, zmm0, zmm2"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0xca], "vpminud zmm1{k5}, zmm0, zmm2"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0x0a], "vpminud zmm1, zmm0, zmmword [rdx]"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, zmmword [rdx]"); // VPMINUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0xca], "vpminud xmm1{k5}{z}, xmm0, xmm2"); // VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0xca], "vpminud xmm1, xmm0, xmm2"); // VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0xca], "vpminud xmm1{k5}, xmm0, xmm2"); // VPMINUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0x0a], "vpminud xmm1, xmm0, xmmword [rdx]"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, xmmword [rdx]"); // VPMINUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0xca], "vpmaxsb ymm1{k5}{z}, ymm0, ymm2"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0x0a], "vpmaxsb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0xca], "vpmaxsb ymm1, ymm0, ymm2"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0xca], "vpmaxsb ymm1{k5}, ymm0, ymm2"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_YMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0x0a], "vpmaxsb ymm1, ymm0, ymmword [rdx]"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0x0a], "vpmaxsb ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXSB_YMMi8_MASKmskw_YMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0xca], "vpmaxsb zmm1{k5}{z}, zmm0, zmm2"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0x0a], "vpmaxsb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0xca], "vpmaxsb zmm1, zmm0, zmm2"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0xca], "vpmaxsb zmm1{k5}, zmm0, zmm2"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_ZMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0x0a], "vpmaxsb zmm1, zmm0, zmmword [rdx]"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0x0a], "vpmaxsb zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXSB_ZMMi8_MASKmskw_ZMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0xca], "vpmaxsb xmm1{k5}{z}, xmm0, xmm2"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0xca], "vpmaxsb xmm1, xmm0, xmm2"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0xca], "vpmaxsb xmm1{k5}, xmm0, xmm2"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_XMMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0x0a], "vpmaxsb xmm1, xmm0, xmmword [rdx]"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXSB_XMMi8_MASKmskw_XMMi8_MEMi8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, qword [rdx]{1to4}"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0xca], "vpmaxsq ymm1{k5}{z}, ymm0, ymm2"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0xca], "vpmaxsq ymm1, ymm0, ymm2"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0xca], "vpmaxsq ymm1{k5}, ymm0, ymm2"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, ymmword [rdx]"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXSQ_YMMi64_MASKmskw_YMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, dword [rdx]{1to8}"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0xca], "vpmaxsd ymm1{k5}{z}, ymm0, ymm2"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0xca], "vpmaxsd ymm1, ymm0, ymm2"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0xca], "vpmaxsd ymm1{k5}, ymm0, ymm2"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, ymmword [rdx]"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXSD_YMMi32_MASKmskw_YMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, qword [rdx]{1to8}"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, qword [rdx]{1to2}"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0xca], "vpmaxsq zmm1{k5}{z}, zmm0, zmm2"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0xca], "vpmaxsq zmm1, zmm0, zmm2"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0xca], "vpmaxsq zmm1{k5}, zmm0, zmm2"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, zmmword [rdx]"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXSQ_ZMMi64_MASKmskw_ZMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0xca], "vpmaxsq xmm1{k5}{z}, xmm0, xmm2"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0xca], "vpmaxsq xmm1, xmm0, xmm2"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0xca], "vpmaxsq xmm1{k5}, xmm0, xmm2"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, xmmword [rdx]"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXSQ_XMMi64_MASKmskw_XMMi64_MEMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, dword [rdx]{1to16}"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, dword [rdx]{1to4}"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0xca], "vpmaxsd zmm1{k5}{z}, zmm0, zmm2"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0xca], "vpmaxsd zmm1, zmm0, zmm2"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0xca], "vpmaxsd zmm1{k5}, zmm0, zmm2"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, zmmword [rdx]"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXSD_ZMMi32_MASKmskw_ZMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0xca], "vpmaxsd xmm1{k5}{z}, xmm0, xmm2"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0xca], "vpmaxsd xmm1, xmm0, xmm2"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0xca], "vpmaxsd xmm1{k5}, xmm0, xmm2"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, xmmword [rdx]"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXSD_XMMi32_MASKmskw_XMMi32_MEMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0xca], "vpmaxuw ymm1{k5}{z}, ymm0, ymm2"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0x0a], "vpmaxuw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0xca], "vpmaxuw ymm1, ymm0, ymm2"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0xca], "vpmaxuw ymm1{k5}, ymm0, ymm2"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0x0a], "vpmaxuw ymm1, ymm0, ymmword [rdx]"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0x0a], "vpmaxuw ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXUW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0xca], "vpmaxuw zmm1{k5}{z}, zmm0, zmm2"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0x0a], "vpmaxuw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0xca], "vpmaxuw zmm1, zmm0, zmm2"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0xca], "vpmaxuw zmm1{k5}, zmm0, zmm2"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0x0a], "vpmaxuw zmm1, zmm0, zmmword [rdx]"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0x0a], "vpmaxuw zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXUW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0xca], "vpmaxuw xmm1{k5}{z}, xmm0, xmm2"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0xca], "vpmaxuw xmm1, xmm0, xmm2"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0xca], "vpmaxuw xmm1{k5}, xmm0, xmm2"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0x0a], "vpmaxuw xmm1, xmm0, xmmword [rdx]"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXUW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, qword [rdx]{1to4}"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0xca], "vpmaxuq ymm1{k5}{z}, ymm0, ymm2"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0xca], "vpmaxuq ymm1, ymm0, ymm2"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0xca], "vpmaxuq ymm1{k5}, ymm0, ymm2"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, ymmword [rdx]"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, dword [rdx]{1to8}"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0xca], "vpmaxud ymm1{k5}{z}, ymm0, ymm2"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0xca], "vpmaxud ymm1, ymm0, ymm2"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0xca], "vpmaxud ymm1{k5}, ymm0, ymm2"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, ymmword [rdx]"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, ymmword [rdx]"); // VPMAXUD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, qword [rdx]{1to8}"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, qword [rdx]{1to2}"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0xca], "vpmaxuq zmm1{k5}{z}, zmm0, zmm2"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0xca], "vpmaxuq zmm1, zmm0, zmm2"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0xca], "vpmaxuq zmm1{k5}, zmm0, zmm2"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, zmmword [rdx]"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0xca], "vpmaxuq xmm1{k5}{z}, xmm0, xmm2"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0xca], "vpmaxuq xmm1, xmm0, xmm2"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0xca], "vpmaxuq xmm1{k5}, xmm0, xmm2"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, xmmword [rdx]"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, dword [rdx]{1to16}"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, dword [rdx]{1to4}"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0xca], "vpmaxud zmm1{k5}{z}, zmm0, zmm2"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0xca], "vpmaxud zmm1, zmm0, zmm2"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0xca], "vpmaxud zmm1{k5}, zmm0, zmm2"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, zmmword [rdx]"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, zmmword [rdx]"); // VPMAXUD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0xca], "vpmaxud xmm1{k5}{z}, xmm0, xmm2"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0xca], "vpmaxud xmm1, xmm0, xmm2"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0xca], "vpmaxud xmm1{k5}, xmm0, xmm2"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, xmmword [rdx]"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, xmmword [rdx]"); // VPMAXUD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x40, 0x0a], "vpmullq ymm1, ymm0, qword [rdx]{1to4}"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0xca], "vpmullq ymm1{k5}{z}, ymm0, ymm2"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0xca], "vpmullq ymm1, ymm0, ymm2"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0xca], "vpmullq ymm1{k5}, ymm0, ymm2"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0x0a], "vpmullq ymm1, ymm0, ymmword [rdx]"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULLQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x40, 0x0a], "vpmulld ymm1, ymm0, dword [rdx]{1to8}"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0xca], "vpmulld ymm1{k5}{z}, ymm0, ymm2"); // VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0xca], "vpmulld ymm1, ymm0, ymm2"); // VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0xca], "vpmulld ymm1{k5}, ymm0, ymm2"); // VPMULLD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0x0a], "vpmulld ymm1, ymm0, ymmword [rdx]"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULLD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x40, 0x0a], "vpmullq zmm1, zmm0, qword [rdx]{1to8}"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x40, 0x0a], "vpmullq xmm1, xmm0, qword [rdx]{1to2}"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0xca], "vpmullq zmm1{k5}{z}, zmm0, zmm2"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0xca], "vpmullq zmm1, zmm0, zmm2"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0xca], "vpmullq zmm1{k5}, zmm0, zmm2"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0x0a], "vpmullq zmm1, zmm0, zmmword [rdx]"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULLQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0xca], "vpmullq xmm1{k5}{z}, xmm0, xmm2"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0xca], "vpmullq xmm1, xmm0, xmm2"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0xca], "vpmullq xmm1{k5}, xmm0, xmm2"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0x0a], "vpmullq xmm1, xmm0, xmmword [rdx]"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULLQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x40, 0x0a], "vpmulld zmm1, zmm0, dword [rdx]{1to16}"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x40, 0x0a], "vpmulld xmm1, xmm0, dword [rdx]{1to4}"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0xca], "vpmulld zmm1{k5}{z}, zmm0, zmm2"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0xca], "vpmulld zmm1, zmm0, zmm2"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0xca], "vpmulld zmm1{k5}, zmm0, zmm2"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0x0a], "vpmulld zmm1, zmm0, zmmword [rdx]"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULLD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0xca], "vpmulld xmm1{k5}{z}, xmm0, xmm2"); // VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0xca], "vpmulld xmm1, xmm0, xmm2"); // VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0xca], "vpmulld xmm1{k5}, xmm0, xmm2"); // VPMULLD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0x0a], "vpmulld xmm1, xmm0, xmmword [rdx]"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULLD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}{sae}, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x42, 0xca], "vgetexppd zmm1{sae}, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x42, 0xca], "vgetexppd zmm1{k5}{sae}, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, qword [rdx]{1to4}"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x42, 0x0a], "vgetexppd ymm1, qword [rdx]{1to4}"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x42, 0x0a], "vgetexppd ymm1{k5}, qword [rdx]{1to4}"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0xca], "vgetexppd ymm1{k5}{z}, ymm2"); // VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, ymmword [rdx]"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0xca], "vgetexppd ymm1, ymm2"); // VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0xca], "vgetexppd ymm1{k5}, ymm2"); // VGETEXPPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0x0a], "vgetexppd ymm1, ymmword [rdx]"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0x0a], "vgetexppd ymm1{k5}, ymmword [rdx]"); // VGETEXPPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}{sae}, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x42, 0xca], "vgetexpps zmm1{sae}, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x42, 0xca], "vgetexpps zmm1{k5}{sae}, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, dword [rdx]{1to8}"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x42, 0x0a], "vgetexpps ymm1, dword [rdx]{1to8}"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x42, 0x0a], "vgetexpps ymm1{k5}, dword [rdx]{1to8}"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0xca], "vgetexpps ymm1{k5}{z}, ymm2"); // VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, ymmword [rdx]"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0xca], "vgetexpps ymm1, ymm2"); // VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0xca], "vgetexpps ymm1{k5}, ymm2"); // VGETEXPPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0x0a], "vgetexpps ymm1, ymmword [rdx]"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0x0a], "vgetexpps ymm1{k5}, ymmword [rdx]"); // VGETEXPPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, qword [rdx]{1to8}"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x42, 0x0a], "vgetexppd zmm1, qword [rdx]{1to8}"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x42, 0x0a], "vgetexppd zmm1{k5}, qword [rdx]{1to8}"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, qword [rdx]{1to2}"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x42, 0x0a], "vgetexppd xmm1, qword [rdx]{1to2}"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x42, 0x0a], "vgetexppd xmm1{k5}, qword [rdx]{1to2}"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, zmmword [rdx]"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0xca], "vgetexppd zmm1, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0xca], "vgetexppd zmm1{k5}, zmm2"); // VGETEXPPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0x0a], "vgetexppd zmm1, zmmword [rdx]"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0x0a], "vgetexppd zmm1{k5}, zmmword [rdx]"); // VGETEXPPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0xca], "vgetexppd xmm1{k5}{z}, xmm2"); // VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, xmmword [rdx]"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0xca], "vgetexppd xmm1, xmm2"); // VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0xca], "vgetexppd xmm1{k5}, xmm2"); // VGETEXPPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0x0a], "vgetexppd xmm1, xmmword [rdx]"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0x0a], "vgetexppd xmm1{k5}, xmmword [rdx]"); // VGETEXPPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, dword [rdx]{1to16}"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x42, 0x0a], "vgetexpps zmm1, dword [rdx]{1to16}"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x42, 0x0a], "vgetexpps zmm1{k5}, dword [rdx]{1to16}"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, dword [rdx]{1to4}"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x42, 0x0a], "vgetexpps xmm1, dword [rdx]{1to4}"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x42, 0x0a], "vgetexpps xmm1{k5}, dword [rdx]{1to4}"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, zmmword [rdx]"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0xca], "vgetexpps zmm1, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0xca], "vgetexpps zmm1{k5}, zmm2"); // VGETEXPPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0x0a], "vgetexpps zmm1, zmmword [rdx]"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0x0a], "vgetexpps zmm1{k5}, zmmword [rdx]"); // VGETEXPPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0xca], "vgetexpps xmm1{k5}{z}, xmm2"); // VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, xmmword [rdx]"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0xca], "vgetexpps xmm1, xmm2"); // VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0xca], "vgetexpps xmm1{k5}, xmm2"); // VGETEXPPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0x0a], "vgetexpps xmm1, xmmword [rdx]"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0x0a], "vgetexpps xmm1{k5}, xmmword [rdx]"); // VGETEXPPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x43, 0xca], "vgetexpsd xmm1{sae}, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x43, 0xca], "vgetexpsd xmm1{k5}{sae}, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0x0a], "vgetexpsd xmm1{k5}{z}, xmm0, qword [rdx]"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0xca], "vgetexpsd xmm1, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0xca], "vgetexpsd xmm1{k5}, xmm0, xmm2"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0x0a], "vgetexpsd xmm1, xmm0, qword [rdx]"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0x0a], "vgetexpsd xmm1{k5}, xmm0, qword [rdx]"); // VGETEXPSD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x43, 0xca], "vgetexpss xmm1{k5}{z}{sae}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x43, 0xca], "vgetexpss xmm1{sae}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x43, 0xca], "vgetexpss xmm1{k5}{sae}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0xca], "vgetexpss xmm1{k5}{z}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x0a], "vgetexpss xmm1{k5}{z}, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0xca], "vgetexpss xmm1, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0xca], "vgetexpss xmm1{k5}, xmm0, xmm2"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x0a], "vgetexpss xmm1, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0x0a], "vgetexpss xmm1{k5}, xmm0, dword [rdx]"); // VGETEXPSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, qword [rdx]{1to4}"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x44, 0x0a], "vplzcntq ymm1, qword [rdx]{1to4}"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x44, 0x0a], "vplzcntq ymm1{k5}, qword [rdx]{1to4}"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0xca], "vplzcntq ymm1{k5}{z}, ymm2"); // VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, ymmword [rdx]"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0xca], "vplzcntq ymm1, ymm2"); // VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0xca], "vplzcntq ymm1{k5}, ymm2"); // VPLZCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0x0a], "vplzcntq ymm1, ymmword [rdx]"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0x0a], "vplzcntq ymm1{k5}, ymmword [rdx]"); // VPLZCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, dword [rdx]{1to8}"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x44, 0x0a], "vplzcntd ymm1, dword [rdx]{1to8}"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x44, 0x0a], "vplzcntd ymm1{k5}, dword [rdx]{1to8}"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0xca], "vplzcntd ymm1{k5}{z}, ymm2"); // VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, ymmword [rdx]"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0xca], "vplzcntd ymm1, ymm2"); // VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0xca], "vplzcntd ymm1{k5}, ymm2"); // VPLZCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0x0a], "vplzcntd ymm1, ymmword [rdx]"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0x0a], "vplzcntd ymm1{k5}, ymmword [rdx]"); // VPLZCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, qword [rdx]{1to8}"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x44, 0x0a], "vplzcntq zmm1, qword [rdx]{1to8}"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x44, 0x0a], "vplzcntq zmm1{k5}, qword [rdx]{1to8}"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, qword [rdx]{1to2}"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x44, 0x0a], "vplzcntq xmm1, qword [rdx]{1to2}"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x44, 0x0a], "vplzcntq xmm1{k5}, qword [rdx]{1to2}"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0xca], "vplzcntq zmm1{k5}{z}, zmm2"); // VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, zmmword [rdx]"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0xca], "vplzcntq zmm1, zmm2"); // VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0xca], "vplzcntq zmm1{k5}, zmm2"); // VPLZCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0x0a], "vplzcntq zmm1, zmmword [rdx]"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0x0a], "vplzcntq zmm1{k5}, zmmword [rdx]"); // VPLZCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0xca], "vplzcntq xmm1{k5}{z}, xmm2"); // VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, xmmword [rdx]"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0xca], "vplzcntq xmm1, xmm2"); // VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0xca], "vplzcntq xmm1{k5}, xmm2"); // VPLZCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0x0a], "vplzcntq xmm1, xmmword [rdx]"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0x0a], "vplzcntq xmm1{k5}, xmmword [rdx]"); // VPLZCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, dword [rdx]{1to16}"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x44, 0x0a], "vplzcntd zmm1, dword [rdx]{1to16}"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x44, 0x0a], "vplzcntd zmm1{k5}, dword [rdx]{1to16}"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, dword [rdx]{1to4}"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x44, 0x0a], "vplzcntd xmm1, dword [rdx]{1to4}"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x44, 0x0a], "vplzcntd xmm1{k5}, dword [rdx]{1to4}"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0xca], "vplzcntd zmm1{k5}{z}, zmm2"); // VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, zmmword [rdx]"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0xca], "vplzcntd zmm1, zmm2"); // VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0xca], "vplzcntd zmm1{k5}, zmm2"); // VPLZCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0x0a], "vplzcntd zmm1, zmmword [rdx]"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0x0a], "vplzcntd zmm1{k5}, zmmword [rdx]"); // VPLZCNTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0xca], "vplzcntd xmm1{k5}{z}, xmm2"); // VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, xmmword [rdx]"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0xca], "vplzcntd xmm1, xmm2"); // VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0xca], "vplzcntd xmm1{k5}, xmm2"); // VPLZCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0x0a], "vplzcntd xmm1, xmmword [rdx]"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0x0a], "vplzcntd xmm1{k5}, xmmword [rdx]"); // VPLZCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, qword [rdx]{1to4}"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0xca], "vpsrlvq ymm1{k5}{z}, ymm0, ymm2"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0xca], "vpsrlvq ymm1, ymm0, ymm2"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0xca], "vpsrlvq ymm1{k5}, ymm0, ymm2"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, ymmword [rdx]"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, dword [rdx]{1to8}"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0xca], "vpsrlvd ymm1{k5}{z}, ymm0, ymm2"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0xca], "vpsrlvd ymm1, ymm0, ymm2"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0xca], "vpsrlvd ymm1{k5}, ymm0, ymm2"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, ymmword [rdx]"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, qword [rdx]{1to8}"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, qword [rdx]{1to2}"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0xca], "vpsrlvq zmm1{k5}{z}, zmm0, zmm2"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0xca], "vpsrlvq zmm1, zmm0, zmm2"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0xca], "vpsrlvq zmm1{k5}, zmm0, zmm2"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, zmmword [rdx]"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0xca], "vpsrlvq xmm1{k5}{z}, xmm0, xmm2"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0xca], "vpsrlvq xmm1, xmm0, xmm2"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0xca], "vpsrlvq xmm1{k5}, xmm0, xmm2"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, xmmword [rdx]"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, dword [rdx]{1to16}"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, dword [rdx]{1to4}"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0xca], "vpsrlvd zmm1{k5}{z}, zmm0, zmm2"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0xca], "vpsrlvd zmm1, zmm0, zmm2"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0xca], "vpsrlvd zmm1{k5}, zmm0, zmm2"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, zmmword [rdx]"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0xca], "vpsrlvd xmm1{k5}{z}, xmm0, xmm2"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0xca], "vpsrlvd xmm1, xmm0, xmm2"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0xca], "vpsrlvd xmm1{k5}, xmm0, xmm2"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, xmmword [rdx]"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x46, 0x0a], "vpsravq ymm1, ymm0, qword [rdx]{1to4}"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0xca], "vpsravq ymm1{k5}{z}, ymm0, ymm2"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0xca], "vpsravq ymm1, ymm0, ymm2"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0xca], "vpsravq ymm1{k5}, ymm0, ymm2"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0x0a], "vpsravq ymm1, ymm0, ymmword [rdx]"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRAVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x46, 0x0a], "vpsravd ymm1, ymm0, dword [rdx]{1to8}"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0xca], "vpsravd ymm1{k5}{z}, ymm0, ymm2"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0xca], "vpsravd ymm1, ymm0, ymm2"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0xca], "vpsravd ymm1{k5}, ymm0, ymm2"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0x0a], "vpsravd ymm1, ymm0, ymmword [rdx]"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSRAVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x46, 0x0a], "vpsravq zmm1, zmm0, qword [rdx]{1to8}"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x46, 0x0a], "vpsravq xmm1, xmm0, qword [rdx]{1to2}"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0xca], "vpsravq zmm1{k5}{z}, zmm0, zmm2"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0xca], "vpsravq zmm1, zmm0, zmm2"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0xca], "vpsravq zmm1{k5}, zmm0, zmm2"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0x0a], "vpsravq zmm1, zmm0, zmmword [rdx]"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRAVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0xca], "vpsravq xmm1{k5}{z}, xmm0, xmm2"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0xca], "vpsravq xmm1, xmm0, xmm2"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0xca], "vpsravq xmm1{k5}, xmm0, xmm2"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0x0a], "vpsravq xmm1, xmm0, xmmword [rdx]"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x46, 0x0a], "vpsravd zmm1, zmm0, dword [rdx]{1to16}"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x46, 0x0a], "vpsravd xmm1, xmm0, dword [rdx]{1to4}"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0xca], "vpsravd zmm1{k5}{z}, zmm0, zmm2"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0xca], "vpsravd zmm1, zmm0, zmm2"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0xca], "vpsravd zmm1{k5}, zmm0, zmm2"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0x0a], "vpsravd zmm1, zmm0, zmmword [rdx]"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSRAVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0xca], "vpsravd xmm1{k5}{z}, xmm0, xmm2"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0xca], "vpsravd xmm1, xmm0, xmm2"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0xca], "vpsravd xmm1{k5}, xmm0, xmm2"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0x0a], "vpsravd xmm1, xmm0, xmmword [rdx]"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSRAVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x47, 0x0a], "vpsllvq ymm1, ymm0, qword [rdx]{1to4}"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0xca], "vpsllvq ymm1{k5}{z}, ymm0, ymm2"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0xca], "vpsllvq ymm1, ymm0, ymm2"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0xca], "vpsllvq ymm1{k5}, ymm0, ymm2"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0x0a], "vpsllvq ymm1, ymm0, ymmword [rdx]"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSLLVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x47, 0x0a], "vpsllvd ymm1, ymm0, dword [rdx]{1to8}"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0xca], "vpsllvd ymm1{k5}{z}, ymm0, ymm2"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0xca], "vpsllvd ymm1, ymm0, ymm2"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0xca], "vpsllvd ymm1{k5}, ymm0, ymm2"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0x0a], "vpsllvd ymm1, ymm0, ymmword [rdx]"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSLLVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x47, 0x0a], "vpsllvq zmm1, zmm0, qword [rdx]{1to8}"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x47, 0x0a], "vpsllvq xmm1, xmm0, qword [rdx]{1to2}"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0xca], "vpsllvq zmm1{k5}{z}, zmm0, zmm2"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0xca], "vpsllvq zmm1, zmm0, zmm2"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0xca], "vpsllvq zmm1{k5}, zmm0, zmm2"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0x0a], "vpsllvq zmm1, zmm0, zmmword [rdx]"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSLLVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0xca], "vpsllvq xmm1{k5}{z}, xmm0, xmm2"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0xca], "vpsllvq xmm1, xmm0, xmm2"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0xca], "vpsllvq xmm1{k5}, xmm0, xmm2"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0x0a], "vpsllvq xmm1, xmm0, xmmword [rdx]"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x47, 0x0a], "vpsllvd zmm1, zmm0, dword [rdx]{1to16}"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x47, 0x0a], "vpsllvd xmm1, xmm0, dword [rdx]{1to4}"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0xca], "vpsllvd zmm1{k5}{z}, zmm0, zmm2"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0xca], "vpsllvd zmm1, zmm0, zmm2"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0xca], "vpsllvd zmm1{k5}, zmm0, zmm2"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0x0a], "vpsllvd zmm1, zmm0, zmmword [rdx]"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSLLVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0xca], "vpsllvd xmm1{k5}{z}, xmm0, xmm2"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0xca], "vpsllvd xmm1, xmm0, xmm2"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0xca], "vpsllvd xmm1{k5}, xmm0, xmm2"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0x0a], "vpsllvd xmm1, xmm0, xmmword [rdx]"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSLLVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4c, 0x0a], "vrcp14pd ymm1, qword [rdx]{1to4}"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, qword [rdx]{1to4}"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0xca], "vrcp14pd ymm1{k5}{z}, ymm2"); // VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, ymmword [rdx]"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0xca], "vrcp14pd ymm1, ymm2"); // VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0xca], "vrcp14pd ymm1{k5}, ymm2"); // VRCP14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0x0a], "vrcp14pd ymm1, ymmword [rdx]"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, ymmword [rdx]"); // VRCP14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, dword [rdx]{1to8}"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4c, 0x0a], "vrcp14ps ymm1, dword [rdx]{1to8}"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, dword [rdx]{1to8}"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0xca], "vrcp14ps ymm1{k5}{z}, ymm2"); // VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, ymmword [rdx]"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0xca], "vrcp14ps ymm1, ymm2"); // VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0xca], "vrcp14ps ymm1{k5}, ymm2"); // VRCP14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0x0a], "vrcp14ps ymm1, ymmword [rdx]"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, ymmword [rdx]"); // VRCP14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4c, 0x0a], "vrcp14pd zmm1, qword [rdx]{1to8}"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, qword [rdx]{1to8}"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, qword [rdx]{1to2}"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4c, 0x0a], "vrcp14pd xmm1, qword [rdx]{1to2}"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, qword [rdx]{1to2}"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0xca], "vrcp14pd zmm1{k5}{z}, zmm2"); // VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, zmmword [rdx]"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0xca], "vrcp14pd zmm1, zmm2"); // VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0xca], "vrcp14pd zmm1{k5}, zmm2"); // VRCP14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0x0a], "vrcp14pd zmm1, zmmword [rdx]"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, zmmword [rdx]"); // VRCP14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0xca], "vrcp14pd xmm1{k5}{z}, xmm2"); // VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, xmmword [rdx]"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0xca], "vrcp14pd xmm1, xmm2"); // VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0xca], "vrcp14pd xmm1{k5}, xmm2"); // VRCP14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0x0a], "vrcp14pd xmm1, xmmword [rdx]"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, xmmword [rdx]"); // VRCP14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4c, 0x0a], "vrcp14ps zmm1, dword [rdx]{1to16}"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, dword [rdx]{1to16}"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, dword [rdx]{1to4}"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4c, 0x0a], "vrcp14ps xmm1, dword [rdx]{1to4}"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, dword [rdx]{1to4}"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0xca], "vrcp14ps zmm1{k5}{z}, zmm2"); // VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, zmmword [rdx]"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0xca], "vrcp14ps zmm1, zmm2"); // VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0xca], "vrcp14ps zmm1{k5}, zmm2"); // VRCP14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0x0a], "vrcp14ps zmm1, zmmword [rdx]"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, zmmword [rdx]"); // VRCP14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0xca], "vrcp14ps xmm1{k5}{z}, xmm2"); // VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, xmmword [rdx]"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0xca], "vrcp14ps xmm1, xmm2"); // VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0xca], "vrcp14ps xmm1{k5}, xmm2"); // VRCP14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0x0a], "vrcp14ps xmm1, xmmword [rdx]"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, xmmword [rdx]"); // VRCP14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0xca], "vrcp14sd xmm1{k5}{z}, xmm0, xmm2"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0x0a], "vrcp14sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0xca], "vrcp14sd xmm1, xmm0, xmm2"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0xca], "vrcp14sd xmm1{k5}, xmm0, xmm2"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0x0a], "vrcp14sd xmm1, xmm0, qword [rdx]"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0x0a], "vrcp14sd xmm1{k5}, xmm0, qword [rdx]"); // VRCP14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0xca], "vrcp14ss xmm1{k5}{z}, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x0a], "vrcp14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0xca], "vrcp14ss xmm1, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0xca], "vrcp14ss xmm1{k5}, xmm0, xmm2"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x0a], "vrcp14ss xmm1, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x0a], "vrcp14ss xmm1{k5}, xmm0, dword [rdx]"); // VRCP14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, qword [rdx]{1to4}"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4e, 0x0a], "vrsqrt14pd ymm1, qword [rdx]{1to4}"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, qword [rdx]{1to4}"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}{z}, ymm2"); // VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, ymmword [rdx]"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0xca], "vrsqrt14pd ymm1, ymm2"); // VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}, ymm2"); // VRSQRT14PD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0x0a], "vrsqrt14pd ymm1, ymmword [rdx]"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, ymmword [rdx]"); // VRSQRT14PD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, dword [rdx]{1to8}"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4e, 0x0a], "vrsqrt14ps ymm1, dword [rdx]{1to8}"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, dword [rdx]{1to8}"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}{z}, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0xca], "vrsqrt14ps ymm1, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}, ymm2"); // VRSQRT14PS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x0a], "vrsqrt14ps ymm1, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, ymmword [rdx]"); // VRSQRT14PS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4e, 0x0a], "vrsqrt14pd zmm1, qword [rdx]{1to8}"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, qword [rdx]{1to8}"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, qword [rdx]{1to2}"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4e, 0x0a], "vrsqrt14pd xmm1, qword [rdx]{1to2}"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, qword [rdx]{1to2}"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}{z}, zmm2"); // VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, zmmword [rdx]"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0xca], "vrsqrt14pd zmm1, zmm2"); // VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}, zmm2"); // VRSQRT14PD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0x0a], "vrsqrt14pd zmm1, zmmword [rdx]"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, zmmword [rdx]"); // VRSQRT14PD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}{z}, xmm2"); // VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, xmmword [rdx]"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0xca], "vrsqrt14pd xmm1, xmm2"); // VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}, xmm2"); // VRSQRT14PD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0x0a], "vrsqrt14pd xmm1, xmmword [rdx]"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, xmmword [rdx]"); // VRSQRT14PD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4e, 0x0a], "vrsqrt14ps zmm1, dword [rdx]{1to16}"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, dword [rdx]{1to16}"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, dword [rdx]{1to4}"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4e, 0x0a], "vrsqrt14ps xmm1, dword [rdx]{1to4}"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, dword [rdx]{1to4}"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}{z}, zmm2"); // VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, zmmword [rdx]"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0xca], "vrsqrt14ps zmm1, zmm2"); // VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}, zmm2"); // VRSQRT14PS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0x0a], "vrsqrt14ps zmm1, zmmword [rdx]"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, zmmword [rdx]"); // VRSQRT14PS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}{z}, xmm2"); // VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, xmmword [rdx]"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0xca], "vrsqrt14ps xmm1, xmm2"); // VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}, xmm2"); // VRSQRT14PS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0x0a], "vrsqrt14ps xmm1, xmmword [rdx]"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, xmmword [rdx]"); // VRSQRT14PS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0xca], "vrsqrt14sd xmm1, xmm0, xmm2"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}, xmm0, xmm2"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0x0a], "vrsqrt14sd xmm1, xmm0, qword [rdx]"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}, xmm0, qword [rdx]"); // VRSQRT14SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0xca], "vrsqrt14ss xmm1, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}, xmm0, xmm2"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x0a], "vrsqrt14ss xmm1, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}, xmm0, dword [rdx]"); // VRSQRT14SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, dword [rdx]{1to8}"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0xca], "vpdpbusd ymm1{k5}{z}, ymm0, ymm2"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0xca], "vpdpbusd ymm1, ymm0, ymm2"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0xca], "vpdpbusd ymm1{k5}, ymm0, ymm2"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, ymmword [rdx]"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, ymmword [rdx]"); // VPDPBUSD_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, dword [rdx]{1to16}"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, dword [rdx]{1to4}"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0xca], "vpdpbusd zmm1{k5}{z}, zmm0, zmm2"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0xca], "vpdpbusd zmm1, zmm0, zmm2"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0xca], "vpdpbusd zmm1{k5}, zmm0, zmm2"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, zmmword [rdx]"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, zmmword [rdx]"); // VPDPBUSD_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0xca], "vpdpbusd xmm1{k5}{z}, xmm0, xmm2"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0xca], "vpdpbusd xmm1, xmm0, xmm2"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0xca], "vpdpbusd xmm1{k5}, xmm0, xmm2"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, xmmword [rdx]"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, xmmword [rdx]"); // VPDPBUSD_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, dword [rdx]{1to8}"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0xca], "vpdpbusds ymm1{k5}{z}, ymm0, ymm2"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0xca], "vpdpbusds ymm1, ymm0, ymm2"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0xca], "vpdpbusds ymm1{k5}, ymm0, ymm2"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, ymmword [rdx]"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, ymmword [rdx]"); // VPDPBUSDS_YMMi32_MASKmskw_YMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, dword [rdx]{1to16}"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, dword [rdx]{1to4}"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0xca], "vpdpbusds zmm1{k5}{z}, zmm0, zmm2"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0xca], "vpdpbusds zmm1, zmm0, zmm2"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0xca], "vpdpbusds zmm1{k5}, zmm0, zmm2"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, zmmword [rdx]"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, zmmword [rdx]"); // VPDPBUSDS_ZMMi32_MASKmskw_ZMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0xca], "vpdpbusds xmm1{k5}{z}, xmm0, xmm2"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0xca], "vpdpbusds xmm1, xmm0, xmm2"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0xca], "vpdpbusds xmm1{k5}, xmm0, xmm2"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, xmmword [rdx]"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, xmmword [rdx]"); // VPDPBUSDS_XMMi32_MASKmskw_XMMu8_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, dword [rdx]{1to8}"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0xca], "vpdpwssd ymm1{k5}{z}, ymm0, ymm2"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0xca], "vpdpwssd ymm1, ymm0, ymm2"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0xca], "vpdpwssd ymm1{k5}, ymm0, ymm2"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, ymmword [rdx]"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, ymmword [rdx]"); // VPDPWSSD_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, dword [rdx]{1to16}"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, dword [rdx]{1to4}"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0xca], "vpdpwssd zmm1{k5}{z}, zmm0, zmm2"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0xca], "vpdpwssd zmm1, zmm0, zmm2"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0xca], "vpdpwssd zmm1{k5}, zmm0, zmm2"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, zmmword [rdx]"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, zmmword [rdx]"); // VPDPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0xca], "vpdpwssd xmm1{k5}{z}, xmm0, xmm2"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0xca], "vpdpwssd xmm1, xmm0, xmm2"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0xca], "vpdpwssd xmm1{k5}, xmm0, xmm2"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, xmmword [rdx]"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, xmmword [rdx]"); // VPDPWSSD_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, dword [rdx]{1to8}"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0xca], "vpdpwssds ymm1{k5}{z}, ymm0, ymm2"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0xca], "vpdpwssds ymm1, ymm0, ymm2"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0xca], "vpdpwssds ymm1{k5}, ymm0, ymm2"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, ymmword [rdx]"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, ymmword [rdx]"); // VPDPWSSDS_YMMi32_MASKmskw_YMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, dword [rdx]{1to16}"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, dword [rdx]{1to4}"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0xca], "vpdpwssds zmm1{k5}{z}, zmm0, zmm2"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0xca], "vpdpwssds zmm1, zmm0, zmm2"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0xca], "vpdpwssds zmm1{k5}, zmm0, zmm2"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, zmmword [rdx]"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, zmmword [rdx]"); // VPDPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0xca], "vpdpwssds xmm1{k5}{z}, xmm0, xmm2"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0xca], "vpdpwssds xmm1, xmm0, xmm2"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0xca], "vpdpwssds xmm1{k5}, xmm0, xmm2"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, xmmword [rdx]"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, xmmword [rdx]"); // VPDPWSSDS_XMMi32_MASKmskw_XMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0xca], "vpopcntw ymm1{k5}{z}, ymm2"); // VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0x0a], "vpopcntw ymm1{k5}{z}, ymmword [rdx]"); // VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0xca], "vpopcntw ymm1, ymm2"); // VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0xca], "vpopcntw ymm1{k5}, ymm2"); // VPOPCNTW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0x0a], "vpopcntw ymm1, ymmword [rdx]"); // VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0x0a], "vpopcntw ymm1{k5}, ymmword [rdx]"); // VPOPCNTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0xca], "vpopcntb ymm1{k5}{z}, ymm2"); // VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0x0a], "vpopcntb ymm1{k5}{z}, ymmword [rdx]"); // VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0xca], "vpopcntb ymm1, ymm2"); // VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0xca], "vpopcntb ymm1{k5}, ymm2"); // VPOPCNTB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0x0a], "vpopcntb ymm1, ymmword [rdx]"); // VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0x0a], "vpopcntb ymm1{k5}, ymmword [rdx]"); // VPOPCNTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0xca], "vpopcntw zmm1{k5}{z}, zmm2"); // VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0x0a], "vpopcntw zmm1{k5}{z}, zmmword [rdx]"); // VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0xca], "vpopcntw zmm1, zmm2"); // VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0xca], "vpopcntw zmm1{k5}, zmm2"); // VPOPCNTW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0x0a], "vpopcntw zmm1, zmmword [rdx]"); // VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0x0a], "vpopcntw zmm1{k5}, zmmword [rdx]"); // VPOPCNTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0xca], "vpopcntw xmm1{k5}{z}, xmm2"); // VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0x0a], "vpopcntw xmm1{k5}{z}, xmmword [rdx]"); // VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0xca], "vpopcntw xmm1, xmm2"); // VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0xca], "vpopcntw xmm1{k5}, xmm2"); // VPOPCNTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0x0a], "vpopcntw xmm1, xmmword [rdx]"); // VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0x0a], "vpopcntw xmm1{k5}, xmmword [rdx]"); // VPOPCNTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0xca], "vpopcntb zmm1{k5}{z}, zmm2"); // VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0x0a], "vpopcntb zmm1{k5}{z}, zmmword [rdx]"); // VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0xca], "vpopcntb zmm1, zmm2"); // VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0xca], "vpopcntb zmm1{k5}, zmm2"); // VPOPCNTB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0x0a], "vpopcntb zmm1, zmmword [rdx]"); // VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0x0a], "vpopcntb zmm1{k5}, zmmword [rdx]"); // VPOPCNTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0xca], "vpopcntb xmm1{k5}{z}, xmm2"); // VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0x0a], "vpopcntb xmm1{k5}{z}, xmmword [rdx]"); // VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0xca], "vpopcntb xmm1, xmm2"); // VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0xca], "vpopcntb xmm1{k5}, xmm2"); // VPOPCNTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0x0a], "vpopcntb xmm1, xmmword [rdx]"); // VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0x0a], "vpopcntb xmm1{k5}, xmmword [rdx]"); // VPOPCNTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, qword [rdx]{1to4}"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x55, 0x0a], "vpopcntq ymm1, qword [rdx]{1to4}"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x55, 0x0a], "vpopcntq ymm1{k5}, qword [rdx]{1to4}"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0xca], "vpopcntq ymm1{k5}{z}, ymm2"); // VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, ymmword [rdx]"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0xca], "vpopcntq ymm1, ymm2"); // VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0xca], "vpopcntq ymm1{k5}, ymm2"); // VPOPCNTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0x0a], "vpopcntq ymm1, ymmword [rdx]"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0x0a], "vpopcntq ymm1{k5}, ymmword [rdx]"); // VPOPCNTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, dword [rdx]{1to8}"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x55, 0x0a], "vpopcntd ymm1, dword [rdx]{1to8}"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x55, 0x0a], "vpopcntd ymm1{k5}, dword [rdx]{1to8}"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0xca], "vpopcntd ymm1{k5}{z}, ymm2"); // VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, ymmword [rdx]"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0xca], "vpopcntd ymm1, ymm2"); // VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0xca], "vpopcntd ymm1{k5}, ymm2"); // VPOPCNTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0x0a], "vpopcntd ymm1, ymmword [rdx]"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0x0a], "vpopcntd ymm1{k5}, ymmword [rdx]"); // VPOPCNTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, qword [rdx]{1to8}"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x55, 0x0a], "vpopcntq zmm1, qword [rdx]{1to8}"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x55, 0x0a], "vpopcntq zmm1{k5}, qword [rdx]{1to8}"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, qword [rdx]{1to2}"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x55, 0x0a], "vpopcntq xmm1, qword [rdx]{1to2}"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x55, 0x0a], "vpopcntq xmm1{k5}, qword [rdx]{1to2}"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0xca], "vpopcntq zmm1{k5}{z}, zmm2"); // VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, zmmword [rdx]"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0xca], "vpopcntq zmm1, zmm2"); // VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0xca], "vpopcntq zmm1{k5}, zmm2"); // VPOPCNTQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0x0a], "vpopcntq zmm1, zmmword [rdx]"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0x0a], "vpopcntq zmm1{k5}, zmmword [rdx]"); // VPOPCNTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0xca], "vpopcntq xmm1{k5}{z}, xmm2"); // VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, xmmword [rdx]"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0xca], "vpopcntq xmm1, xmm2"); // VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0xca], "vpopcntq xmm1{k5}, xmm2"); // VPOPCNTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0x0a], "vpopcntq xmm1, xmmword [rdx]"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0x0a], "vpopcntq xmm1{k5}, xmmword [rdx]"); // VPOPCNTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, dword [rdx]{1to16}"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x55, 0x0a], "vpopcntd zmm1, dword [rdx]{1to16}"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x55, 0x0a], "vpopcntd zmm1{k5}, dword [rdx]{1to16}"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, dword [rdx]{1to4}"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x55, 0x0a], "vpopcntd xmm1, dword [rdx]{1to4}"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x55, 0x0a], "vpopcntd xmm1{k5}, dword [rdx]{1to4}"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0xca], "vpopcntd zmm1{k5}{z}, zmm2"); // VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, zmmword [rdx]"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0xca], "vpopcntd zmm1, zmm2"); // VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0xca], "vpopcntd zmm1{k5}, zmm2"); // VPOPCNTD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0x0a], "vpopcntd zmm1, zmmword [rdx]"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0x0a], "vpopcntd zmm1{k5}, zmmword [rdx]"); // VPOPCNTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0xca], "vpopcntd xmm1{k5}{z}, xmm2"); // VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, xmmword [rdx]"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0xca], "vpopcntd xmm1, xmm2"); // VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0xca], "vpopcntd xmm1{k5}, xmm2"); // VPOPCNTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0x0a], "vpopcntd xmm1, xmmword [rdx]"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0x0a], "vpopcntd xmm1{k5}, xmmword [rdx]"); // VPOPCNTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0xca], "vpbroadcastd ymm1{k5}{z}, xmm2"); // VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0x0a], "vpbroadcastd ymm1{k5}{z}, dword [rdx]"); // VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0xca], "vpbroadcastd ymm1, xmm2"); // VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0xca], "vpbroadcastd ymm1{k5}, xmm2"); // VPBROADCASTD_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0x0a], "vpbroadcastd ymm1, dword [rdx]"); // VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0x0a], "vpbroadcastd ymm1{k5}, dword [rdx]"); // VPBROADCASTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0xca], "vpbroadcastd zmm1{k5}{z}, xmm2"); // VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0x0a], "vpbroadcastd zmm1{k5}{z}, dword [rdx]"); // VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0xca], "vpbroadcastd zmm1, xmm2"); // VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0xca], "vpbroadcastd zmm1{k5}, xmm2"); // VPBROADCASTD_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0x0a], "vpbroadcastd zmm1, dword [rdx]"); // VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0x0a], "vpbroadcastd zmm1{k5}, dword [rdx]"); // VPBROADCASTD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0xca], "vpbroadcastd xmm1{k5}{z}, xmm2"); // VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}{z}, dword [rdx]"); // VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0xca], "vpbroadcastd xmm1, xmm2"); // VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0xca], "vpbroadcastd xmm1{k5}, xmm2"); // VPBROADCASTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0x0a], "vpbroadcastd xmm1, dword [rdx]"); // VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}, dword [rdx]"); // VPBROADCASTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0xca], "vpbroadcastq ymm1{k5}{z}, xmm2"); // VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0x0a], "vpbroadcastq ymm1{k5}{z}, qword [rdx]"); // VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0xca], "vpbroadcastq ymm1, xmm2"); // VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0xca], "vpbroadcastq ymm1{k5}, xmm2"); // VPBROADCASTQ_YMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0x0a], "vpbroadcastq ymm1, qword [rdx]"); // VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0x0a], "vpbroadcastq ymm1{k5}, qword [rdx]"); // VPBROADCASTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}{z}, xmm2"); // VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}{z}, qword [rdx]"); // VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0xca], "vbroadcasti32x2 ymm1, xmm2"); // VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}, xmm2"); // VBROADCASTI32X2_YMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0x0a], "vbroadcasti32x2 ymm1, qword [rdx]"); // VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}, qword [rdx]"); // VBROADCASTI32X2_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0xca], "vpbroadcastq zmm1{k5}{z}, xmm2"); // VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0x0a], "vpbroadcastq zmm1{k5}{z}, qword [rdx]"); // VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0xca], "vpbroadcastq zmm1, xmm2"); // VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0xca], "vpbroadcastq zmm1{k5}, xmm2"); // VPBROADCASTQ_ZMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0x0a], "vpbroadcastq zmm1, qword [rdx]"); // VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0x0a], "vpbroadcastq zmm1{k5}, qword [rdx]"); // VPBROADCASTQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0xca], "vpbroadcastq xmm1{k5}{z}, xmm2"); // VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}{z}, qword [rdx]"); // VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0xca], "vpbroadcastq xmm1, xmm2"); // VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0xca], "vpbroadcastq xmm1{k5}, xmm2"); // VPBROADCASTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0x0a], "vpbroadcastq xmm1, qword [rdx]"); // VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}, qword [rdx]"); // VPBROADCASTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}{z}, xmm2"); // VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}{z}, qword [rdx]"); // VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0xca], "vbroadcasti32x2 zmm1, xmm2"); // VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}, xmm2"); // VBROADCASTI32X2_ZMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0x0a], "vbroadcasti32x2 zmm1, qword [rdx]"); // VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}, qword [rdx]"); // VBROADCASTI32X2_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}{z}, xmm2"); // VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}{z}, qword [rdx]"); // VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0xca], "vbroadcasti32x2 xmm1, xmm2"); // VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}, xmm2"); // VBROADCASTI32X2_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0x0a], "vbroadcasti32x2 xmm1, qword [rdx]"); // VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}, qword [rdx]"); // VBROADCASTI32X2_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}{z}, xmmword [rdx]"); // VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x5a, 0x0a], "vbroadcasti64x2 ymm1, xmmword [rdx]"); // VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}, xmmword [rdx]"); // VBROADCASTI64X2_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}{z}, xmmword [rdx]"); // VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x5a, 0x0a], "vbroadcasti32x4 ymm1, xmmword [rdx]"); // VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}, xmmword [rdx]"); // VBROADCASTI32X4_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}{z}, xmmword [rdx]"); // VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x0a], "vbroadcasti64x2 zmm1, xmmword [rdx]"); // VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}, xmmword [rdx]"); // VBROADCASTI64X2_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}{z}, xmmword [rdx]"); // VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x0a], "vbroadcasti32x4 zmm1, xmmword [rdx]"); // VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}, xmmword [rdx]"); // VBROADCASTI32X4_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}{z}, ymmword [rdx]"); // VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x0a], "vbroadcasti64x4 zmm1, ymmword [rdx]"); // VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}, ymmword [rdx]"); // VBROADCASTI64X4_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}{z}, ymmword [rdx]"); // VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x0a], "vbroadcasti32x8 zmm1, ymmword [rdx]"); // VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}, ymmword [rdx]"); // VBROADCASTI32X8_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0xca], "vpexpandw ymm1{k5}{z}, ymm2"); // VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0x0a], "vpexpandw ymm1{k5}{z}, ymmword [rdx]"); // VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0xca], "vpexpandw ymm1, ymm2"); // VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0xca], "vpexpandw ymm1{k5}, ymm2"); // VPEXPANDW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0x0a], "vpexpandw ymm1, ymmword [rdx]"); // VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0x0a], "vpexpandw ymm1{k5}, ymmword [rdx]"); // VPEXPANDW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0xca], "vpexpandb ymm1{k5}{z}, ymm2"); // VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0x0a], "vpexpandb ymm1{k5}{z}, ymmword [rdx]"); // VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0xca], "vpexpandb ymm1, ymm2"); // VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0xca], "vpexpandb ymm1{k5}, ymm2"); // VPEXPANDB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0x0a], "vpexpandb ymm1, ymmword [rdx]"); // VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0x0a], "vpexpandb ymm1{k5}, ymmword [rdx]"); // VPEXPANDB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0xca], "vpexpandw zmm1{k5}{z}, zmm2"); // VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0x0a], "vpexpandw zmm1{k5}{z}, zmmword [rdx]"); // VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0xca], "vpexpandw zmm1, zmm2"); // VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0xca], "vpexpandw zmm1{k5}, zmm2"); // VPEXPANDW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0x0a], "vpexpandw zmm1, zmmword [rdx]"); // VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0x0a], "vpexpandw zmm1{k5}, zmmword [rdx]"); // VPEXPANDW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0xca], "vpexpandw xmm1{k5}{z}, xmm2"); // VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0x0a], "vpexpandw xmm1{k5}{z}, xmmword [rdx]"); // VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0xca], "vpexpandw xmm1, xmm2"); // VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0xca], "vpexpandw xmm1{k5}, xmm2"); // VPEXPANDW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0x0a], "vpexpandw xmm1, xmmword [rdx]"); // VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0x0a], "vpexpandw xmm1{k5}, xmmword [rdx]"); // VPEXPANDW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0xca], "vpexpandb zmm1{k5}{z}, zmm2"); // VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0x0a], "vpexpandb zmm1{k5}{z}, zmmword [rdx]"); // VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0xca], "vpexpandb zmm1, zmm2"); // VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0xca], "vpexpandb zmm1{k5}, zmm2"); // VPEXPANDB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0x0a], "vpexpandb zmm1, zmmword [rdx]"); // VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0x0a], "vpexpandb zmm1{k5}, zmmword [rdx]"); // VPEXPANDB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0xca], "vpexpandb xmm1{k5}{z}, xmm2"); // VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0x0a], "vpexpandb xmm1{k5}{z}, xmmword [rdx]"); // VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0xca], "vpexpandb xmm1, xmm2"); // VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0xca], "vpexpandb xmm1{k5}, xmm2"); // VPEXPANDB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0x0a], "vpexpandb xmm1, xmmword [rdx]"); // VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0x0a], "vpexpandb xmm1{k5}, xmmword [rdx]"); // VPEXPANDB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x63, 0xca], "vpcompressw ymm2{k5}{z}, ymm1"); // VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca], "vpcompressw ymm2, ymm1"); // VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0xca], "vpcompressw ymm2{k5}, ymm1"); // VPCOMPRESSW_YMMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0x0a], "vpcompressw ymmword [rdx], ymm1"); // VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0x0a], "vpcompressw ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSW_MEMu16_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0xca], "vpcompressb ymm2{k5}{z}, ymm1"); // VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca], "vpcompressb ymm2, ymm1"); // VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0xca], "vpcompressb ymm2{k5}, ymm1"); // VPCOMPRESSB_YMMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x0a], "vpcompressb ymmword [rdx], ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x0a], "vpcompressb ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSB_MEMu8_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x63, 0xca], "vpcompressw zmm2{k5}{z}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca], "vpcompressw zmm2, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0xca], "vpcompressw zmm2{k5}, zmm1"); // VPCOMPRESSW_ZMMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0x0a], "vpcompressw zmmword [rdx], zmm1"); // VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0x0a], "vpcompressw zmmword [rdx]{k5}, zmm1"); // VPCOMPRESSW_MEMu16_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x63, 0xca], "vpcompressw xmm2{k5}{z}, xmm1"); // VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca], "vpcompressw xmm2, xmm1"); // VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0xca], "vpcompressw xmm2{k5}, xmm1"); // VPCOMPRESSW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0x0a], "vpcompressw xmmword [rdx], xmm1"); // VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0x0a], "vpcompressw xmmword [rdx]{k5}, xmm1"); // VPCOMPRESSW_MEMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x63, 0xca], "vpcompressb zmm2{k5}{z}, zmm1"); // VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca], "vpcompressb zmm2, zmm1"); // VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0xca], "vpcompressb zmm2{k5}, zmm1"); // VPCOMPRESSB_ZMMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0x0a], "vpcompressb zmmword [rdx], zmm1"); // VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0x0a], "vpcompressb zmmword [rdx]{k5}, zmm1"); // VPCOMPRESSB_MEMu8_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x63, 0xca], "vpcompressb xmm2{k5}{z}, xmm1"); // VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca], "vpcompressb xmm2, xmm1"); // VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0xca], "vpcompressb xmm2{k5}, xmm1"); // VPCOMPRESSB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0x0a], "vpcompressb xmmword [rdx], xmm1"); // VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0x0a], "vpcompressb xmmword [rdx]{k5}, xmm1"); // VPCOMPRESSB_MEMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x64, 0x0a], "vpblendmq ymm1, ymm0, qword [rdx]{1to4}"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0xca], "vpblendmq ymm1{k5}{z}, ymm0, ymm2"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0xca], "vpblendmq ymm1, ymm0, ymm2"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0xca], "vpblendmq ymm1{k5}, ymm0, ymm2"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0x0a], "vpblendmq ymm1, ymm0, ymmword [rdx]"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, ymmword [rdx]"); // VPBLENDMQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x64, 0x0a], "vpblendmd ymm1, ymm0, dword [rdx]{1to8}"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0xca], "vpblendmd ymm1{k5}{z}, ymm0, ymm2"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0xca], "vpblendmd ymm1, ymm0, ymm2"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0xca], "vpblendmd ymm1{k5}, ymm0, ymm2"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0x0a], "vpblendmd ymm1, ymm0, ymmword [rdx]"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, ymmword [rdx]"); // VPBLENDMD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x64, 0x0a], "vpblendmq zmm1, zmm0, qword [rdx]{1to8}"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x64, 0x0a], "vpblendmq xmm1, xmm0, qword [rdx]{1to2}"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0xca], "vpblendmq zmm1{k5}{z}, zmm0, zmm2"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0xca], "vpblendmq zmm1, zmm0, zmm2"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0xca], "vpblendmq zmm1{k5}, zmm0, zmm2"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0x0a], "vpblendmq zmm1, zmm0, zmmword [rdx]"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, zmmword [rdx]"); // VPBLENDMQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0xca], "vpblendmq xmm1{k5}{z}, xmm0, xmm2"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0xca], "vpblendmq xmm1, xmm0, xmm2"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0xca], "vpblendmq xmm1{k5}, xmm0, xmm2"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0x0a], "vpblendmq xmm1, xmm0, xmmword [rdx]"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, xmmword [rdx]"); // VPBLENDMQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x64, 0x0a], "vpblendmd zmm1, zmm0, dword [rdx]{1to16}"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x64, 0x0a], "vpblendmd xmm1, xmm0, dword [rdx]{1to4}"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0xca], "vpblendmd zmm1{k5}{z}, zmm0, zmm2"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0xca], "vpblendmd zmm1, zmm0, zmm2"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0xca], "vpblendmd zmm1{k5}, zmm0, zmm2"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0x0a], "vpblendmd zmm1, zmm0, zmmword [rdx]"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, zmmword [rdx]"); // VPBLENDMD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0xca], "vpblendmd xmm1{k5}{z}, xmm0, xmm2"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0xca], "vpblendmd xmm1, xmm0, xmm2"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0xca], "vpblendmd xmm1{k5}, xmm0, xmm2"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0x0a], "vpblendmd xmm1, xmm0, xmmword [rdx]"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, xmmword [rdx]"); // VPBLENDMD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x65, 0x0a], "vblendmpd ymm1, ymm0, qword [rdx]{1to4}"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0xca], "vblendmpd ymm1{k5}{z}, ymm0, ymm2"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0xca], "vblendmpd ymm1, ymm0, ymm2"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0xca], "vblendmpd ymm1{k5}, ymm0, ymm2"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0x0a], "vblendmpd ymm1, ymm0, ymmword [rdx]"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, ymmword [rdx]"); // VBLENDMPD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x65, 0x0a], "vblendmps ymm1, ymm0, dword [rdx]{1to8}"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0xca], "vblendmps ymm1{k5}{z}, ymm0, ymm2"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0xca], "vblendmps ymm1, ymm0, ymm2"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0xca], "vblendmps ymm1{k5}, ymm0, ymm2"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0x0a], "vblendmps ymm1, ymm0, ymmword [rdx]"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, ymmword [rdx]"); // VBLENDMPS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x65, 0x0a], "vblendmpd zmm1, zmm0, qword [rdx]{1to8}"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x65, 0x0a], "vblendmpd xmm1, xmm0, qword [rdx]{1to2}"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0xca], "vblendmpd zmm1{k5}{z}, zmm0, zmm2"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0xca], "vblendmpd zmm1, zmm0, zmm2"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0xca], "vblendmpd zmm1{k5}, zmm0, zmm2"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0x0a], "vblendmpd zmm1, zmm0, zmmword [rdx]"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, zmmword [rdx]"); // VBLENDMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0xca], "vblendmpd xmm1{k5}{z}, xmm0, xmm2"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0xca], "vblendmpd xmm1, xmm0, xmm2"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0xca], "vblendmpd xmm1{k5}, xmm0, xmm2"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0x0a], "vblendmpd xmm1, xmm0, xmmword [rdx]"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, xmmword [rdx]"); // VBLENDMPD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x65, 0x0a], "vblendmps zmm1, zmm0, dword [rdx]{1to16}"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x65, 0x0a], "vblendmps xmm1, xmm0, dword [rdx]{1to4}"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0xca], "vblendmps zmm1{k5}{z}, zmm0, zmm2"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0xca], "vblendmps zmm1, zmm0, zmm2"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0xca], "vblendmps zmm1{k5}, zmm0, zmm2"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0x0a], "vblendmps zmm1, zmm0, zmmword [rdx]"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, zmmword [rdx]"); // VBLENDMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0xca], "vblendmps xmm1{k5}{z}, xmm0, xmm2"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0xca], "vblendmps xmm1, xmm0, xmm2"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0xca], "vblendmps xmm1{k5}, xmm0, xmm2"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0x0a], "vblendmps xmm1, xmm0, xmmword [rdx]"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, xmmword [rdx]"); // VBLENDMPS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0xca], "vpblendmw ymm1{k5}{z}, ymm0, ymm2"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0x0a], "vpblendmw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0xca], "vpblendmw ymm1, ymm0, ymm2"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0xca], "vpblendmw ymm1{k5}, ymm0, ymm2"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0x0a], "vpblendmw ymm1, ymm0, ymmword [rdx]"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0x0a], "vpblendmw ymm1{k5}, ymm0, ymmword [rdx]"); // VPBLENDMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0xca], "vpblendmb ymm1{k5}{z}, ymm0, ymm2"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0x0a], "vpblendmb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0xca], "vpblendmb ymm1, ymm0, ymm2"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0xca], "vpblendmb ymm1{k5}, ymm0, ymm2"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0x0a], "vpblendmb ymm1, ymm0, ymmword [rdx]"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0x0a], "vpblendmb ymm1{k5}, ymm0, ymmword [rdx]"); // VPBLENDMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0xca], "vpblendmw zmm1{k5}{z}, zmm0, zmm2"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0x0a], "vpblendmw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0xca], "vpblendmw zmm1, zmm0, zmm2"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0xca], "vpblendmw zmm1{k5}, zmm0, zmm2"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0x0a], "vpblendmw zmm1, zmm0, zmmword [rdx]"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0x0a], "vpblendmw zmm1{k5}, zmm0, zmmword [rdx]"); // VPBLENDMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0xca], "vpblendmw xmm1{k5}{z}, xmm0, xmm2"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0x0a], "vpblendmw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0xca], "vpblendmw xmm1, xmm0, xmm2"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0xca], "vpblendmw xmm1{k5}, xmm0, xmm2"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0x0a], "vpblendmw xmm1, xmm0, xmmword [rdx]"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0x0a], "vpblendmw xmm1{k5}, xmm0, xmmword [rdx]"); // VPBLENDMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0xca], "vpblendmb zmm1{k5}{z}, zmm0, zmm2"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0x0a], "vpblendmb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0xca], "vpblendmb zmm1, zmm0, zmm2"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0xca], "vpblendmb zmm1{k5}, zmm0, zmm2"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0x0a], "vpblendmb zmm1, zmm0, zmmword [rdx]"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0x0a], "vpblendmb zmm1{k5}, zmm0, zmmword [rdx]"); // VPBLENDMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0xca], "vpblendmb xmm1{k5}{z}, xmm0, xmm2"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0x0a], "vpblendmb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0xca], "vpblendmb xmm1, xmm0, xmm2"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0xca], "vpblendmb xmm1{k5}, xmm0, xmm2"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0x0a], "vpblendmb xmm1, xmm0, xmmword [rdx]"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0x0a], "vpblendmb xmm1{k5}, xmm0, xmmword [rdx]"); // VPBLENDMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0xca], "vpshldvw ymm1{k5}{z}, ymm0, ymm2"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0x0a], "vpshldvw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0xca], "vpshldvw ymm1, ymm0, ymm2"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0xca], "vpshldvw ymm1{k5}, ymm0, ymm2"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0x0a], "vpshldvw ymm1, ymm0, ymmword [rdx]"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0x0a], "vpshldvw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHLDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0xca], "vpshldvw zmm1{k5}{z}, zmm0, zmm2"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0x0a], "vpshldvw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0xca], "vpshldvw zmm1, zmm0, zmm2"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0xca], "vpshldvw zmm1{k5}, zmm0, zmm2"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0x0a], "vpshldvw zmm1, zmm0, zmmword [rdx]"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0x0a], "vpshldvw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHLDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0xca], "vpshldvw xmm1{k5}{z}, xmm0, xmm2"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0x0a], "vpshldvw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0xca], "vpshldvw xmm1, xmm0, xmm2"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0xca], "vpshldvw xmm1{k5}, xmm0, xmm2"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0x0a], "vpshldvw xmm1, xmm0, xmmword [rdx]"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0x0a], "vpshldvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHLDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x71, 0x0a], "vpshldvq ymm1, ymm0, qword [rdx]{1to4}"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0xca], "vpshldvq ymm1{k5}{z}, ymm0, ymm2"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0xca], "vpshldvq ymm1, ymm0, ymm2"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0xca], "vpshldvq ymm1{k5}, ymm0, ymm2"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0x0a], "vpshldvq ymm1, ymm0, ymmword [rdx]"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHLDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x71, 0x0a], "vpshldvd ymm1, ymm0, dword [rdx]{1to8}"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0xca], "vpshldvd ymm1{k5}{z}, ymm0, ymm2"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0xca], "vpshldvd ymm1, ymm0, ymm2"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0xca], "vpshldvd ymm1{k5}, ymm0, ymm2"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0x0a], "vpshldvd ymm1, ymm0, ymmword [rdx]"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHLDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x71, 0x0a], "vpshldvq zmm1, zmm0, qword [rdx]{1to8}"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x71, 0x0a], "vpshldvq xmm1, xmm0, qword [rdx]{1to2}"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0xca], "vpshldvq zmm1{k5}{z}, zmm0, zmm2"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0xca], "vpshldvq zmm1, zmm0, zmm2"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0xca], "vpshldvq zmm1{k5}, zmm0, zmm2"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0x0a], "vpshldvq zmm1, zmm0, zmmword [rdx]"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHLDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0xca], "vpshldvq xmm1{k5}{z}, xmm0, xmm2"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0xca], "vpshldvq xmm1, xmm0, xmm2"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0xca], "vpshldvq xmm1{k5}, xmm0, xmm2"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0x0a], "vpshldvq xmm1, xmm0, xmmword [rdx]"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHLDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x71, 0x0a], "vpshldvd zmm1, zmm0, dword [rdx]{1to16}"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x71, 0x0a], "vpshldvd xmm1, xmm0, dword [rdx]{1to4}"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0xca], "vpshldvd zmm1{k5}{z}, zmm0, zmm2"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0xca], "vpshldvd zmm1, zmm0, zmm2"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0xca], "vpshldvd zmm1{k5}, zmm0, zmm2"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0x0a], "vpshldvd zmm1, zmm0, zmmword [rdx]"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHLDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0xca], "vpshldvd xmm1{k5}{z}, xmm0, xmm2"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0xca], "vpshldvd xmm1, xmm0, xmm2"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0xca], "vpshldvd xmm1{k5}, xmm0, xmm2"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0x0a], "vpshldvd xmm1, xmm0, xmmword [rdx]"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHLDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0xca], "vpshrdvw ymm1{k5}{z}, ymm0, ymm2"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0x0a], "vpshrdvw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0xca], "vpshrdvw ymm1, ymm0, ymm2"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0xca], "vpshrdvw ymm1{k5}, ymm0, ymm2"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0x0a], "vpshrdvw ymm1, ymm0, ymmword [rdx]"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0x0a], "vpshrdvw ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHRDVW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0xca], "vpshrdvw zmm1{k5}{z}, zmm0, zmm2"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0x0a], "vpshrdvw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0xca], "vpshrdvw zmm1, zmm0, zmm2"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0xca], "vpshrdvw zmm1{k5}, zmm0, zmm2"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0x0a], "vpshrdvw zmm1, zmm0, zmmword [rdx]"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0x0a], "vpshrdvw zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHRDVW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0xca], "vpshrdvw xmm1{k5}{z}, xmm0, xmm2"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0x0a], "vpshrdvw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0xca], "vpshrdvw xmm1, xmm0, xmm2"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0xca], "vpshrdvw xmm1{k5}, xmm0, xmm2"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0x0a], "vpshrdvw xmm1, xmm0, xmmword [rdx]"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0x0a], "vpshrdvw xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHRDVW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, qword [rdx]{1to4}"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0xca], "vpshrdvq ymm1{k5}{z}, ymm0, ymm2"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0xca], "vpshrdvq ymm1, ymm0, ymm2"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0xca], "vpshrdvq ymm1{k5}, ymm0, ymm2"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, ymmword [rdx]"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHRDVQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, dword [rdx]{1to8}"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0xca], "vpshrdvd ymm1{k5}{z}, ymm0, ymm2"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0xca], "vpshrdvd ymm1, ymm0, ymm2"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0xca], "vpshrdvd ymm1{k5}, ymm0, ymm2"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, ymmword [rdx]"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, ymmword [rdx]"); // VPSHRDVD_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, qword [rdx]{1to8}"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, qword [rdx]{1to2}"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0xca], "vpshrdvq zmm1{k5}{z}, zmm0, zmm2"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0xca], "vpshrdvq zmm1, zmm0, zmm2"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0xca], "vpshrdvq zmm1{k5}, zmm0, zmm2"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, zmmword [rdx]"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHRDVQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0xca], "vpshrdvq xmm1{k5}{z}, xmm0, xmm2"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0xca], "vpshrdvq xmm1, xmm0, xmm2"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0xca], "vpshrdvq xmm1{k5}, xmm0, xmm2"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, xmmword [rdx]"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHRDVQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, dword [rdx]{1to16}"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, dword [rdx]{1to4}"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0xca], "vpshrdvd zmm1{k5}{z}, zmm0, zmm2"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0xca], "vpshrdvd zmm1, zmm0, zmm2"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0xca], "vpshrdvd zmm1{k5}, zmm0, zmm2"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, zmmword [rdx]"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, zmmword [rdx]"); // VPSHRDVD_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0xca], "vpshrdvd xmm1{k5}{z}, xmm0, xmm2"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0xca], "vpshrdvd xmm1, xmm0, xmm2"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0xca], "vpshrdvd xmm1{k5}, xmm0, xmm2"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, xmmword [rdx]"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, xmmword [rdx]"); // VPSHRDVD_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0xca], "vpermi2w ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0x0a], "vpermi2w ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0xca], "vpermi2w ymm1, ymm0, ymm2"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0xca], "vpermi2w ymm1{k5}, ymm0, ymm2"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0x0a], "vpermi2w ymm1, ymm0, ymmword [rdx]"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0x0a], "vpermi2w ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0xca], "vpermi2b ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0x0a], "vpermi2b ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0xca], "vpermi2b ymm1, ymm0, ymm2"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0xca], "vpermi2b ymm1{k5}, ymm0, ymm2"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0x0a], "vpermi2b ymm1, ymm0, ymmword [rdx]"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0x0a], "vpermi2b ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0xca], "vpermi2w zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0x0a], "vpermi2w zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0xca], "vpermi2w zmm1, zmm0, zmm2"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0xca], "vpermi2w zmm1{k5}, zmm0, zmm2"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0x0a], "vpermi2w zmm1, zmm0, zmmword [rdx]"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0x0a], "vpermi2w zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0xca], "vpermi2w xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0x0a], "vpermi2w xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0xca], "vpermi2w xmm1, xmm0, xmm2"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0xca], "vpermi2w xmm1{k5}, xmm0, xmm2"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0x0a], "vpermi2w xmm1, xmm0, xmmword [rdx]"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0x0a], "vpermi2w xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0xca], "vpermi2b zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0x0a], "vpermi2b zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0xca], "vpermi2b zmm1, zmm0, zmm2"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0xca], "vpermi2b zmm1{k5}, zmm0, zmm2"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0x0a], "vpermi2b zmm1, zmm0, zmmword [rdx]"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0x0a], "vpermi2b zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0xca], "vpermi2b xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0x0a], "vpermi2b xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0xca], "vpermi2b xmm1, xmm0, xmm2"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0xca], "vpermi2b xmm1{k5}, xmm0, xmm2"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0x0a], "vpermi2b xmm1, xmm0, xmmword [rdx]"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0x0a], "vpermi2b xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x76, 0x0a], "vpermi2q ymm1, ymm0, qword [rdx]{1to4}"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0xca], "vpermi2q ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0xca], "vpermi2q ymm1, ymm0, ymm2"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0xca], "vpermi2q ymm1{k5}, ymm0, ymm2"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0x0a], "vpermi2q ymm1, ymm0, ymmword [rdx]"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x76, 0x0a], "vpermi2d ymm1, ymm0, dword [rdx]{1to8}"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0xca], "vpermi2d ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0xca], "vpermi2d ymm1, ymm0, ymm2"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0xca], "vpermi2d ymm1{k5}, ymm0, ymm2"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0x0a], "vpermi2d ymm1, ymm0, ymmword [rdx]"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x76, 0x0a], "vpermi2q zmm1, zmm0, qword [rdx]{1to8}"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x76, 0x0a], "vpermi2q xmm1, xmm0, qword [rdx]{1to2}"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0xca], "vpermi2q zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0xca], "vpermi2q zmm1, zmm0, zmm2"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0xca], "vpermi2q zmm1{k5}, zmm0, zmm2"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0x0a], "vpermi2q zmm1, zmm0, zmmword [rdx]"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0xca], "vpermi2q xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0xca], "vpermi2q xmm1, xmm0, xmm2"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0xca], "vpermi2q xmm1{k5}, xmm0, xmm2"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0x0a], "vpermi2q xmm1, xmm0, xmmword [rdx]"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x76, 0x0a], "vpermi2d zmm1, zmm0, dword [rdx]{1to16}"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x76, 0x0a], "vpermi2d xmm1, xmm0, dword [rdx]{1to4}"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0xca], "vpermi2d zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0xca], "vpermi2d zmm1, zmm0, zmm2"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0xca], "vpermi2d zmm1{k5}, zmm0, zmm2"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0x0a], "vpermi2d zmm1, zmm0, zmmword [rdx]"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0xca], "vpermi2d xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0xca], "vpermi2d xmm1, xmm0, xmm2"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0xca], "vpermi2d xmm1{k5}, xmm0, xmm2"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0x0a], "vpermi2d xmm1, xmm0, xmmword [rdx]"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, qword [rdx]{1to4}"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0xca], "vpermi2pd ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0xca], "vpermi2pd ymm1, ymm0, ymm2"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0xca], "vpermi2pd ymm1{k5}, ymm0, ymm2"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, ymmword [rdx]"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, dword [rdx]{1to8}"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0xca], "vpermi2ps ymm1{k5}{z}, ymm0, ymm2"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0xca], "vpermi2ps ymm1, ymm0, ymm2"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0xca], "vpermi2ps ymm1{k5}, ymm0, ymm2"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, ymmword [rdx]"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMI2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, qword [rdx]{1to8}"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, qword [rdx]{1to2}"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0xca], "vpermi2pd zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0xca], "vpermi2pd zmm1, zmm0, zmm2"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0xca], "vpermi2pd zmm1{k5}, zmm0, zmm2"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, zmmword [rdx]"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0xca], "vpermi2pd xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0xca], "vpermi2pd xmm1, xmm0, xmm2"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0xca], "vpermi2pd xmm1{k5}, xmm0, xmm2"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, xmmword [rdx]"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, dword [rdx]{1to16}"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, dword [rdx]{1to4}"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0xca], "vpermi2ps zmm1{k5}{z}, zmm0, zmm2"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0xca], "vpermi2ps zmm1, zmm0, zmm2"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0xca], "vpermi2ps zmm1{k5}, zmm0, zmm2"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, zmmword [rdx]"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMI2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0xca], "vpermi2ps xmm1{k5}{z}, xmm0, xmm2"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0xca], "vpermi2ps xmm1, xmm0, xmm2"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0xca], "vpermi2ps xmm1{k5}, xmm0, xmm2"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, xmmword [rdx]"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMI2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0xca], "vpbroadcastb ymm1{k5}{z}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x0a], "vpbroadcastb ymm1{k5}{z}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0xca], "vpbroadcastb ymm1, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0xca], "vpbroadcastb ymm1{k5}, xmm2"); // VPBROADCASTB_YMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x0a], "vpbroadcastb ymm1, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x0a], "vpbroadcastb ymm1{k5}, byte [rdx]"); // VPBROADCASTB_YMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0xca], "vpbroadcastb zmm1{k5}{z}, xmm2"); // VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0x0a], "vpbroadcastb zmm1{k5}{z}, byte [rdx]"); // VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0xca], "vpbroadcastb zmm1, xmm2"); // VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0xca], "vpbroadcastb zmm1{k5}, xmm2"); // VPBROADCASTB_ZMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0x0a], "vpbroadcastb zmm1, byte [rdx]"); // VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0x0a], "vpbroadcastb zmm1{k5}, byte [rdx]"); // VPBROADCASTB_ZMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0xca], "vpbroadcastb xmm1{k5}{z}, xmm2"); // VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}{z}, byte [rdx]"); // VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0xca], "vpbroadcastb xmm1, xmm2"); // VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0xca], "vpbroadcastb xmm1{k5}, xmm2"); // VPBROADCASTB_XMMu8_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0x0a], "vpbroadcastb xmm1, byte [rdx]"); // VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}, byte [rdx]"); // VPBROADCASTB_XMMu8_MASKmskw_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0xca], "vpbroadcastw ymm1{k5}{z}, xmm2"); // VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0x0a], "vpbroadcastw ymm1{k5}{z}, word [rdx]"); // VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0xca], "vpbroadcastw ymm1, xmm2"); // VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0xca], "vpbroadcastw ymm1{k5}, xmm2"); // VPBROADCASTW_YMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0x0a], "vpbroadcastw ymm1, word [rdx]"); // VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0x0a], "vpbroadcastw ymm1{k5}, word [rdx]"); // VPBROADCASTW_YMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0xca], "vpbroadcastw zmm1{k5}{z}, xmm2"); // VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0x0a], "vpbroadcastw zmm1{k5}{z}, word [rdx]"); // VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0xca], "vpbroadcastw zmm1, xmm2"); // VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0xca], "vpbroadcastw zmm1{k5}, xmm2"); // VPBROADCASTW_ZMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0x0a], "vpbroadcastw zmm1, word [rdx]"); // VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0x0a], "vpbroadcastw zmm1{k5}, word [rdx]"); // VPBROADCASTW_ZMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0xca], "vpbroadcastw xmm1{k5}{z}, xmm2"); // VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}{z}, word [rdx]"); // VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0xca], "vpbroadcastw xmm1, xmm2"); // VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0xca], "vpbroadcastw xmm1{k5}, xmm2"); // VPBROADCASTW_XMMu16_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0x0a], "vpbroadcastw xmm1, word [rdx]"); // VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}, word [rdx]"); // VPBROADCASTW_XMMu16_MASKmskw_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7a, 0xca], "vpbroadcastb ymm1{k5}{z}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7a, 0xca], "vpbroadcastb ymm1, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7a, 0xca], "vpbroadcastb ymm1{k5}, edx"); // VPBROADCASTB_YMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7a, 0xca], "vpbroadcastb zmm1{k5}{z}, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7a, 0xca], "vpbroadcastb zmm1, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7a, 0xca], "vpbroadcastb zmm1{k5}, edx"); // VPBROADCASTB_ZMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}{z}, edx"); // VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7a, 0xca], "vpbroadcastb xmm1, edx"); // VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}, edx"); // VPBROADCASTB_XMMu8_MASKmskw_GPR32u8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7b, 0xca], "vpbroadcastw ymm1{k5}{z}, edx"); // VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7b, 0xca], "vpbroadcastw ymm1, edx"); // VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7b, 0xca], "vpbroadcastw ymm1{k5}, edx"); // VPBROADCASTW_YMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7b, 0xca], "vpbroadcastw zmm1{k5}{z}, edx"); // VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7b, 0xca], "vpbroadcastw zmm1, edx"); // VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7b, 0xca], "vpbroadcastw zmm1{k5}, edx"); // VPBROADCASTW_ZMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}{z}, edx"); // VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7b, 0xca], "vpbroadcastw xmm1, edx"); // VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}, edx"); // VPBROADCASTW_XMMu16_MASKmskw_GPR32u16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7c, 0xca], "vpbroadcastq ymm1{k5}{z}, rdx"); // VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7c, 0xca], "vpbroadcastq ymm1, rdx"); // VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7c, 0xca], "vpbroadcastq ymm1{k5}, rdx"); // VPBROADCASTQ_YMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7c, 0xca], "vpbroadcastd ymm1{k5}{z}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7c, 0xca], "vpbroadcastd ymm1, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7c, 0xca], "vpbroadcastd ymm1{k5}, edx"); // VPBROADCASTD_YMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7c, 0xca], "vpbroadcastq zmm1{k5}{z}, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7c, 0xca], "vpbroadcastq zmm1, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7c, 0xca], "vpbroadcastq zmm1{k5}, rdx"); // VPBROADCASTQ_ZMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7c, 0xca], "vpbroadcastq xmm1{k5}{z}, rdx"); // VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7c, 0xca], "vpbroadcastq xmm1, rdx"); // VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7c, 0xca], "vpbroadcastq xmm1{k5}, rdx"); // VPBROADCASTQ_XMMu64_MASKmskw_GPR64u64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7c, 0xca], "vpbroadcastd zmm1{k5}{z}, edx"); // VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7c, 0xca], "vpbroadcastd zmm1, edx"); // VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7c, 0xca], "vpbroadcastd zmm1{k5}, edx"); // VPBROADCASTD_ZMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}{z}, edx"); // VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7c, 0xca], "vpbroadcastd xmm1, edx"); // VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}, edx"); // VPBROADCASTD_XMMu32_MASKmskw_GPR32u32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0xca], "vpermt2w ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0x0a], "vpermt2w ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0xca], "vpermt2w ymm1, ymm0, ymm2"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0xca], "vpermt2w ymm1{k5}, ymm0, ymm2"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0x0a], "vpermt2w ymm1, ymm0, ymmword [rdx]"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0x0a], "vpermt2w ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2W_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0xca], "vpermt2b ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0x0a], "vpermt2b ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0xca], "vpermt2b ymm1, ymm0, ymm2"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0xca], "vpermt2b ymm1{k5}, ymm0, ymm2"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0x0a], "vpermt2b ymm1, ymm0, ymmword [rdx]"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0x0a], "vpermt2b ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2B_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0xca], "vpermt2w zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0x0a], "vpermt2w zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0xca], "vpermt2w zmm1, zmm0, zmm2"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0xca], "vpermt2w zmm1{k5}, zmm0, zmm2"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0x0a], "vpermt2w zmm1, zmm0, zmmword [rdx]"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0x0a], "vpermt2w zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2W_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0xca], "vpermt2w xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0x0a], "vpermt2w xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0xca], "vpermt2w xmm1, xmm0, xmm2"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0xca], "vpermt2w xmm1{k5}, xmm0, xmm2"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0x0a], "vpermt2w xmm1, xmm0, xmmword [rdx]"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0x0a], "vpermt2w xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2W_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0xca], "vpermt2b zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0x0a], "vpermt2b zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0xca], "vpermt2b zmm1, zmm0, zmm2"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0xca], "vpermt2b zmm1{k5}, zmm0, zmm2"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0x0a], "vpermt2b zmm1, zmm0, zmmword [rdx]"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0x0a], "vpermt2b zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2B_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0xca], "vpermt2b xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0x0a], "vpermt2b xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0xca], "vpermt2b xmm1, xmm0, xmm2"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0xca], "vpermt2b xmm1{k5}, xmm0, xmm2"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0x0a], "vpermt2b xmm1, xmm0, xmmword [rdx]"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0x0a], "vpermt2b xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2B_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, qword [rdx]{1to4}"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0xca], "vpermt2q ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0xca], "vpermt2q ymm1, ymm0, ymm2"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0xca], "vpermt2q ymm1{k5}, ymm0, ymm2"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, ymmword [rdx]"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2Q_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, dword [rdx]{1to8}"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0xca], "vpermt2d ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0xca], "vpermt2d ymm1, ymm0, ymm2"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0xca], "vpermt2d ymm1{k5}, ymm0, ymm2"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, ymmword [rdx]"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2D_YMMu32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, qword [rdx]{1to8}"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, qword [rdx]{1to2}"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0xca], "vpermt2q zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0xca], "vpermt2q zmm1, zmm0, zmm2"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0xca], "vpermt2q zmm1{k5}, zmm0, zmm2"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, zmmword [rdx]"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2Q_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0xca], "vpermt2q xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0xca], "vpermt2q xmm1, xmm0, xmm2"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0xca], "vpermt2q xmm1{k5}, xmm0, xmm2"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, xmmword [rdx]"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2Q_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, dword [rdx]{1to16}"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, dword [rdx]{1to4}"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0xca], "vpermt2d zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0xca], "vpermt2d zmm1, zmm0, zmm2"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0xca], "vpermt2d zmm1{k5}, zmm0, zmm2"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, zmmword [rdx]"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2D_ZMMu32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0xca], "vpermt2d xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0xca], "vpermt2d xmm1, xmm0, xmm2"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0xca], "vpermt2d xmm1{k5}, xmm0, xmm2"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, xmmword [rdx]"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2D_XMMu32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, qword [rdx]{1to4}"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0xca], "vpermt2pd ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0xca], "vpermt2pd ymm1, ymm0, ymm2"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0xca], "vpermt2pd ymm1{k5}, ymm0, ymm2"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, ymmword [rdx]"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, dword [rdx]{1to8}"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0xca], "vpermt2ps ymm1{k5}{z}, ymm0, ymm2"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0xca], "vpermt2ps ymm1, ymm0, ymm2"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0xca], "vpermt2ps ymm1{k5}, ymm0, ymm2"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, ymmword [rdx]"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMT2PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, qword [rdx]{1to8}"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, qword [rdx]{1to2}"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0xca], "vpermt2pd zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0xca], "vpermt2pd zmm1, zmm0, zmm2"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0xca], "vpermt2pd zmm1{k5}, zmm0, zmm2"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, zmmword [rdx]"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0xca], "vpermt2pd xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0xca], "vpermt2pd xmm1, xmm0, xmm2"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0xca], "vpermt2pd xmm1{k5}, xmm0, xmm2"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, xmmword [rdx]"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, dword [rdx]{1to16}"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, dword [rdx]{1to4}"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0xca], "vpermt2ps zmm1{k5}{z}, zmm0, zmm2"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0xca], "vpermt2ps zmm1, zmm0, zmm2"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0xca], "vpermt2ps zmm1{k5}, zmm0, zmm2"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, zmmword [rdx]"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMT2PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0xca], "vpermt2ps xmm1{k5}{z}, xmm0, xmm2"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0xca], "vpermt2ps xmm1, xmm0, xmm2"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0xca], "vpermt2ps xmm1{k5}, xmm0, xmm2"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, xmmword [rdx]"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMT2PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, qword [rdx]{1to4}"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0xca], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymm2"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0xca], "vpmultishiftqb ymm1, ymm0, ymm2"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0xca], "vpmultishiftqb ymm1{k5}, ymm0, ymm2"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, ymmword [rdx]"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, ymmword [rdx]"); // VPMULTISHIFTQB_YMMu8_MASKmskw_YMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, qword [rdx]{1to8}"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, qword [rdx]{1to2}"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0xca], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmm2"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0xca], "vpmultishiftqb zmm1, zmm0, zmm2"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0xca], "vpmultishiftqb zmm1{k5}, zmm0, zmm2"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, zmmword [rdx]"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, zmmword [rdx]"); // VPMULTISHIFTQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmm2"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0xca], "vpmultishiftqb xmm1, xmm0, xmm2"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}, xmm0, xmm2"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, xmmword [rdx]"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, xmmword [rdx]"); // VPMULTISHIFTQB_XMMu8_MASKmskw_XMMu8_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0xca], "vexpandpd ymm1{k5}{z}, ymm2"); // VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0x0a], "vexpandpd ymm1{k5}{z}, ymmword [rdx]"); // VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0xca], "vexpandpd ymm1, ymm2"); // VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0xca], "vexpandpd ymm1{k5}, ymm2"); // VEXPANDPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0x0a], "vexpandpd ymm1, ymmword [rdx]"); // VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0x0a], "vexpandpd ymm1{k5}, ymmword [rdx]"); // VEXPANDPD_YMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0xca], "vexpandps ymm1{k5}{z}, ymm2"); // VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0x0a], "vexpandps ymm1{k5}{z}, ymmword [rdx]"); // VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0xca], "vexpandps ymm1, ymm2"); // VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0xca], "vexpandps ymm1{k5}, ymm2"); // VEXPANDPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0x0a], "vexpandps ymm1, ymmword [rdx]"); // VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0x0a], "vexpandps ymm1{k5}, ymmword [rdx]"); // VEXPANDPS_YMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0xca], "vexpandpd zmm1{k5}{z}, zmm2"); // VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0x0a], "vexpandpd zmm1{k5}{z}, zmmword [rdx]"); // VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0xca], "vexpandpd zmm1, zmm2"); // VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0xca], "vexpandpd zmm1{k5}, zmm2"); // VEXPANDPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0x0a], "vexpandpd zmm1, zmmword [rdx]"); // VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0x0a], "vexpandpd zmm1{k5}, zmmword [rdx]"); // VEXPANDPD_ZMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0xca], "vexpandpd xmm1{k5}{z}, xmm2"); // VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0x0a], "vexpandpd xmm1{k5}{z}, xmmword [rdx]"); // VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0xca], "vexpandpd xmm1, xmm2"); // VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0xca], "vexpandpd xmm1{k5}, xmm2"); // VEXPANDPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0x0a], "vexpandpd xmm1, xmmword [rdx]"); // VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0x0a], "vexpandpd xmm1{k5}, xmmword [rdx]"); // VEXPANDPD_XMMf64_MASKmskw_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0xca], "vexpandps zmm1{k5}{z}, zmm2"); // VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0x0a], "vexpandps zmm1{k5}{z}, zmmword [rdx]"); // VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0xca], "vexpandps zmm1, zmm2"); // VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0xca], "vexpandps zmm1{k5}, zmm2"); // VEXPANDPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0x0a], "vexpandps zmm1, zmmword [rdx]"); // VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0x0a], "vexpandps zmm1{k5}, zmmword [rdx]"); // VEXPANDPS_ZMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0xca], "vexpandps xmm1{k5}{z}, xmm2"); // VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0x0a], "vexpandps xmm1{k5}{z}, xmmword [rdx]"); // VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0xca], "vexpandps xmm1, xmm2"); // VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0xca], "vexpandps xmm1{k5}, xmm2"); // VEXPANDPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0x0a], "vexpandps xmm1, xmmword [rdx]"); // VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0x0a], "vexpandps xmm1{k5}, xmmword [rdx]"); // VEXPANDPS_XMMf32_MASKmskw_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0xca], "vpexpandq ymm1{k5}{z}, ymm2"); // VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0x0a], "vpexpandq ymm1{k5}{z}, ymmword [rdx]"); // VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0xca], "vpexpandq ymm1, ymm2"); // VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0xca], "vpexpandq ymm1{k5}, ymm2"); // VPEXPANDQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0x0a], "vpexpandq ymm1, ymmword [rdx]"); // VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0x0a], "vpexpandq ymm1{k5}, ymmword [rdx]"); // VPEXPANDQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0xca], "vpexpandd ymm1{k5}{z}, ymm2"); // VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0x0a], "vpexpandd ymm1{k5}{z}, ymmword [rdx]"); // VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0xca], "vpexpandd ymm1, ymm2"); // VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0xca], "vpexpandd ymm1{k5}, ymm2"); // VPEXPANDD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0x0a], "vpexpandd ymm1, ymmword [rdx]"); // VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0x0a], "vpexpandd ymm1{k5}, ymmword [rdx]"); // VPEXPANDD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0xca], "vpexpandq zmm1{k5}{z}, zmm2"); // VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0x0a], "vpexpandq zmm1{k5}{z}, zmmword [rdx]"); // VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0xca], "vpexpandq zmm1, zmm2"); // VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0xca], "vpexpandq zmm1{k5}, zmm2"); // VPEXPANDQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0x0a], "vpexpandq zmm1, zmmword [rdx]"); // VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0x0a], "vpexpandq zmm1{k5}, zmmword [rdx]"); // VPEXPANDQ_ZMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0xca], "vpexpandq xmm1{k5}{z}, xmm2"); // VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0x0a], "vpexpandq xmm1{k5}{z}, xmmword [rdx]"); // VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0xca], "vpexpandq xmm1, xmm2"); // VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0xca], "vpexpandq xmm1{k5}, xmm2"); // VPEXPANDQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0x0a], "vpexpandq xmm1, xmmword [rdx]"); // VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0x0a], "vpexpandq xmm1{k5}, xmmword [rdx]"); // VPEXPANDQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0xca], "vpexpandd zmm1{k5}{z}, zmm2"); // VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0x0a], "vpexpandd zmm1{k5}{z}, zmmword [rdx]"); // VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0xca], "vpexpandd zmm1, zmm2"); // VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0xca], "vpexpandd zmm1{k5}, zmm2"); // VPEXPANDD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0x0a], "vpexpandd zmm1, zmmword [rdx]"); // VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0x0a], "vpexpandd zmm1{k5}, zmmword [rdx]"); // VPEXPANDD_ZMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0xca], "vpexpandd xmm1{k5}{z}, xmm2"); // VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0x0a], "vpexpandd xmm1{k5}{z}, xmmword [rdx]"); // VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0xca], "vpexpandd xmm1, xmm2"); // VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0xca], "vpexpandd xmm1{k5}, xmm2"); // VPEXPANDD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0x0a], "vpexpandd xmm1, xmmword [rdx]"); // VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0x0a], "vpexpandd xmm1{k5}, xmmword [rdx]"); // VPEXPANDD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8a, 0xca], "vcompresspd ymm2{k5}{z}, ymm1"); // VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0xca], "vcompresspd ymm2, ymm1"); // VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0xca], "vcompresspd ymm2{k5}, ymm1"); // VCOMPRESSPD_YMMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0x0a], "vcompresspd ymmword [rdx], ymm1"); // VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0x0a], "vcompresspd ymmword [rdx]{k5}, ymm1"); // VCOMPRESSPD_MEMf64_MASKmskw_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8a, 0xca], "vcompressps ymm2{k5}{z}, ymm1"); // VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0xca], "vcompressps ymm2, ymm1"); // VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0xca], "vcompressps ymm2{k5}, ymm1"); // VCOMPRESSPS_YMMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0x0a], "vcompressps ymmword [rdx], ymm1"); // VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0x0a], "vcompressps ymmword [rdx]{k5}, ymm1"); // VCOMPRESSPS_MEMf32_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8a, 0xca], "vcompresspd zmm2{k5}{z}, zmm1"); // VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0xca], "vcompresspd zmm2, zmm1"); // VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0xca], "vcompresspd zmm2{k5}, zmm1"); // VCOMPRESSPD_ZMMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x0a], "vcompresspd zmmword [rdx], zmm1"); // VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0x0a], "vcompresspd zmmword [rdx]{k5}, zmm1"); // VCOMPRESSPD_MEMf64_MASKmskw_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8a, 0xca], "vcompresspd xmm2{k5}{z}, xmm1"); // VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0xca], "vcompresspd xmm2, xmm1"); // VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0xca], "vcompresspd xmm2{k5}, xmm1"); // VCOMPRESSPD_XMMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0x0a], "vcompresspd xmmword [rdx], xmm1"); // VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0x0a], "vcompresspd xmmword [rdx]{k5}, xmm1"); // VCOMPRESSPD_MEMf64_MASKmskw_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8a, 0xca], "vcompressps zmm2{k5}{z}, zmm1"); // VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0xca], "vcompressps zmm2, zmm1"); // VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0xca], "vcompressps zmm2{k5}, zmm1"); // VCOMPRESSPS_ZMMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x0a], "vcompressps zmmword [rdx], zmm1"); // VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0x0a], "vcompressps zmmword [rdx]{k5}, zmm1"); // VCOMPRESSPS_MEMf32_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8a, 0xca], "vcompressps xmm2{k5}{z}, xmm1"); // VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0xca], "vcompressps xmm2, xmm1"); // VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0xca], "vcompressps xmm2{k5}, xmm1"); // VCOMPRESSPS_XMMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0x0a], "vcompressps xmmword [rdx], xmm1"); // VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0x0a], "vcompressps xmmword [rdx]{k5}, xmm1"); // VCOMPRESSPS_MEMf32_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8b, 0xca], "vpcompressq ymm2{k5}{z}, ymm1"); // VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0xca], "vpcompressq ymm2, ymm1"); // VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0xca], "vpcompressq ymm2{k5}, ymm1"); // VPCOMPRESSQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0x0a], "vpcompressq ymmword [rdx], ymm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0x0a], "vpcompressq ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8b, 0xca], "vpcompressd ymm2{k5}{z}, ymm1"); // VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0xca], "vpcompressd ymm2, ymm1"); // VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0xca], "vpcompressd ymm2{k5}, ymm1"); // VPCOMPRESSD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0x0a], "vpcompressd ymmword [rdx], ymm1"); // VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0x0a], "vpcompressd ymmword [rdx]{k5}, ymm1"); // VPCOMPRESSD_MEMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8b, 0xca], "vpcompressq zmm2{k5}{z}, zmm1"); // VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0xca], "vpcompressq zmm2, zmm1"); // VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0xca], "vpcompressq zmm2{k5}, zmm1"); // VPCOMPRESSQ_ZMMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x0a], "vpcompressq zmmword [rdx], zmm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0x0a], "vpcompressq zmmword [rdx]{k5}, zmm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8b, 0xca], "vpcompressq xmm2{k5}{z}, xmm1"); // VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0xca], "vpcompressq xmm2, xmm1"); // VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0xca], "vpcompressq xmm2{k5}, xmm1"); // VPCOMPRESSQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0x0a], "vpcompressq xmmword [rdx], xmm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0x0a], "vpcompressq xmmword [rdx]{k5}, xmm1"); // VPCOMPRESSQ_MEMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8b, 0xca], "vpcompressd zmm2{k5}{z}, zmm1"); // VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0xca], "vpcompressd zmm2, zmm1"); // VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0xca], "vpcompressd zmm2{k5}, zmm1"); // VPCOMPRESSD_ZMMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x0a], "vpcompressd zmmword [rdx], zmm1"); // VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0x0a], "vpcompressd zmmword [rdx]{k5}, zmm1"); // VPCOMPRESSD_MEMu32_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8b, 0xca], "vpcompressd xmm2{k5}{z}, xmm1"); // VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0xca], "vpcompressd xmm2, xmm1"); // VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0xca], "vpcompressd xmm2{k5}, xmm1"); // VPCOMPRESSD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0x0a], "vpcompressd xmmword [rdx], xmm1"); // VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0x0a], "vpcompressd xmmword [rdx]{k5}, xmm1"); // VPCOMPRESSD_MEMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0xca], "vpermw ymm1{k5}{z}, ymm0, ymm2"); // VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0x0a], "vpermw ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0xca], "vpermw ymm1, ymm0, ymm2"); // VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0xca], "vpermw ymm1{k5}, ymm0, ymm2"); // VPERMW_YMMu16_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0x0a], "vpermw ymm1, ymm0, ymmword [rdx]"); // VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0x0a], "vpermw ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMW_YMMu16_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0xca], "vpermb ymm1{k5}{z}, ymm0, ymm2"); // VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0x0a], "vpermb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0xca], "vpermb ymm1, ymm0, ymm2"); // VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0xca], "vpermb ymm1{k5}, ymm0, ymm2"); // VPERMB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0x0a], "vpermb ymm1, ymm0, ymmword [rdx]"); // VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0x0a], "vpermb ymm1{k5}, ymm0, ymmword [rdx]"); // VPERMB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0xca], "vpermw zmm1{k5}{z}, zmm0, zmm2"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0x0a], "vpermw zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0xca], "vpermw zmm1, zmm0, zmm2"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0xca], "vpermw zmm1{k5}, zmm0, zmm2"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0x0a], "vpermw zmm1, zmm0, zmmword [rdx]"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0x0a], "vpermw zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMW_ZMMu16_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0xca], "vpermw xmm1{k5}{z}, xmm0, xmm2"); // VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0x0a], "vpermw xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0xca], "vpermw xmm1, xmm0, xmm2"); // VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0xca], "vpermw xmm1{k5}, xmm0, xmm2"); // VPERMW_XMMu16_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0x0a], "vpermw xmm1, xmm0, xmmword [rdx]"); // VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0x0a], "vpermw xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMW_XMMu16_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0xca], "vpermb zmm1{k5}{z}, zmm0, zmm2"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0x0a], "vpermb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0xca], "vpermb zmm1, zmm0, zmm2"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0xca], "vpermb zmm1{k5}, zmm0, zmm2"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0x0a], "vpermb zmm1, zmm0, zmmword [rdx]"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0x0a], "vpermb zmm1{k5}, zmm0, zmmword [rdx]"); // VPERMB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0xca], "vpermb xmm1{k5}{z}, xmm0, xmm2"); // VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0x0a], "vpermb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0xca], "vpermb xmm1, xmm0, xmm2"); // VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0xca], "vpermb xmm1{k5}, xmm0, xmm2"); // VPERMB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0x0a], "vpermb xmm1, xmm0, xmmword [rdx]"); // VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0x0a], "vpermb xmm1{k5}, xmm0, xmmword [rdx]"); // VPERMB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0xca], "vpshufbitqmb k1, ymm0, ymm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, ymm0, ymm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0x0a], "vpshufbitqmb k1, ymm0, ymmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, ymm0, ymmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_YMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0xca], "vpshufbitqmb k1, zmm0, zmm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, zmm0, zmm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0x0a], "vpshufbitqmb k1, zmm0, zmmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, zmm0, zmmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_ZMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0xca], "vpshufbitqmb k1, xmm0, xmm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, xmm0, xmm2"); // VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0x0a], "vpshufbitqmb k1, xmm0, xmmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, xmm0, xmmword [rdx]"); // VPSHUFBITQMB_MASKmskw_MASKmskw_XMMu64_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x96, 0xca], "vfmaddsub132pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0xca], "vfmaddsub132pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0xca], "vfmaddsub132pd ymm1, ymm0, ymm2"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}, ymm0, ymm2"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x96, 0xca], "vfmaddsub132ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0xca], "vfmaddsub132ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0xca], "vfmaddsub132ps ymm1, ymm0, ymm2"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}, ymm0, ymm2"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0xca], "vfmaddsub132pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0xca], "vfmaddsub132pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0xca], "vfmaddsub132pd zmm1, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}, zmm0, zmm2"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0xca], "vfmaddsub132pd xmm1, xmm0, xmm2"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}, xmm0, xmm2"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0xca], "vfmaddsub132ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0xca], "vfmaddsub132ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0xca], "vfmaddsub132ps zmm1, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}, zmm0, zmm2"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0xca], "vfmaddsub132ps xmm1, xmm0, xmm2"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}, xmm0, xmm2"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x97, 0xca], "vfmsubadd132pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0xca], "vfmsubadd132pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0xca], "vfmsubadd132pd ymm1, ymm0, ymm2"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}, ymm0, ymm2"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x97, 0xca], "vfmsubadd132ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0xca], "vfmsubadd132ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0xca], "vfmsubadd132ps ymm1, ymm0, ymm2"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}, ymm0, ymm2"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0xca], "vfmsubadd132pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0xca], "vfmsubadd132pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0xca], "vfmsubadd132pd zmm1, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}, zmm0, zmm2"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0xca], "vfmsubadd132pd xmm1, xmm0, xmm2"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}, xmm0, xmm2"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0xca], "vfmsubadd132ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0xca], "vfmsubadd132ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0xca], "vfmsubadd132ps zmm1, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}, zmm0, zmm2"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0xca], "vfmsubadd132ps xmm1, xmm0, xmm2"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}, xmm0, xmm2"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x98, 0xca], "vfmadd132pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0xca], "vfmadd132pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0xca], "vfmadd132pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0xca], "vfmadd132pd ymm1, ymm0, ymm2"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0xca], "vfmadd132pd ymm1{k5}, ymm0, ymm2"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, ymmword [rdx]"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x98, 0xca], "vfmadd132ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0xca], "vfmadd132ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0xca], "vfmadd132ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0xca], "vfmadd132ps ymm1, ymm0, ymm2"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0xca], "vfmadd132ps ymm1{k5}, ymm0, ymm2"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, ymmword [rdx]"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0xca], "vfmadd132pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0xca], "vfmadd132pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0xca], "vfmadd132pd zmm1, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0xca], "vfmadd132pd zmm1{k5}, zmm0, zmm2"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, zmmword [rdx]"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0xca], "vfmadd132pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0xca], "vfmadd132pd xmm1, xmm0, xmm2"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0xca], "vfmadd132pd xmm1{k5}, xmm0, xmm2"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, xmmword [rdx]"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0xca], "vfmadd132ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0xca], "vfmadd132ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0xca], "vfmadd132ps zmm1, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0xca], "vfmadd132ps zmm1{k5}, zmm0, zmm2"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, zmmword [rdx]"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0xca], "vfmadd132ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0xca], "vfmadd132ps xmm1, xmm0, xmm2"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0xca], "vfmadd132ps xmm1{k5}, xmm0, xmm2"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, xmmword [rdx]"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x99, 0xca], "vfmadd132sd xmm1{rz-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x99, 0xca], "vfmadd132sd xmm1{rd-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0x0a], "vfmadd132sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0xca], "vfmadd132sd xmm1, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0xca], "vfmadd132sd xmm1{k5}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0x0a], "vfmadd132sd xmm1, xmm0, qword [rdx]"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0x0a], "vfmadd132sd xmm1{k5}, xmm0, qword [rdx]"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x99, 0xca], "vfmadd132ss xmm1{rz-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x99, 0xca], "vfmadd132ss xmm1{rd-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x0a], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0xca], "vfmadd132ss xmm1{k5}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x0a], "vfmadd132ss xmm1, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x0a], "vfmadd132ss xmm1{k5}, xmm0, dword [rdx]"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x99, 0xca], "vfmadd132sd xmm1{ru-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x99, 0xca], "vfmadd132sd xmm1{rne-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x99, 0xca], "vfmadd132ss xmm1{ru-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x99, 0xca], "vfmadd132ss xmm1{rne-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9a, 0xca], "vfmsub132pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0xca], "vfmsub132pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0xca], "vfmsub132pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0xca], "vfmsub132pd ymm1, ymm0, ymm2"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0xca], "vfmsub132pd ymm1{k5}, ymm0, ymm2"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, ymmword [rdx]"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9a, 0xca], "vfmsub132ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0xca], "vfmsub132ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0xca], "vfmsub132ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0xca], "vfmsub132ps ymm1, ymm0, ymm2"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0xca], "vfmsub132ps ymm1{k5}, ymm0, ymm2"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, ymmword [rdx]"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0xca], "vfmsub132pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0xca], "vfmsub132pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0xca], "vfmsub132pd zmm1, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}, zmm0, zmm2"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, zmmword [rdx]"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0xca], "vfmsub132pd xmm1, xmm0, xmm2"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}, xmm0, xmm2"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, xmmword [rdx]"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0xca], "vfmsub132ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0xca], "vfmsub132ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0xca], "vfmsub132ps zmm1, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}, zmm0, zmm2"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, zmmword [rdx]"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0xca], "vfmsub132ps xmm1, xmm0, xmm2"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}, xmm0, xmm2"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, xmmword [rdx]"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9b, 0xca], "vfmsub132sd xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9b, 0xca], "vfmsub132sd xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0xca], "vfmsub132sd xmm1, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0x0a], "vfmsub132sd xmm1, xmm0, qword [rdx]"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}, xmm0, qword [rdx]"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9b, 0xca], "vfmsub132ss xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9b, 0xca], "vfmsub132ss xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0xca], "vfmsub132ss xmm1, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0x0a], "vfmsub132ss xmm1, xmm0, dword [rdx]"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}, xmm0, dword [rdx]"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9b, 0xca], "vfmsub132sd xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9b, 0xca], "vfmsub132sd xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9b, 0xca], "vfmsub132ss xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9b, 0xca], "vfmsub132ss xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9c, 0xca], "vfnmadd132pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0xca], "vfnmadd132pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0xca], "vfnmadd132pd ymm1, ymm0, ymm2"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}, ymm0, ymm2"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, ymmword [rdx]"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9c, 0xca], "vfnmadd132ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0xca], "vfnmadd132ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0xca], "vfnmadd132ps ymm1, ymm0, ymm2"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}, ymm0, ymm2"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, ymmword [rdx]"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0xca], "vfnmadd132pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0xca], "vfnmadd132pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0xca], "vfnmadd132pd zmm1, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}, zmm0, zmm2"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, zmmword [rdx]"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0xca], "vfnmadd132pd xmm1, xmm0, xmm2"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}, xmm0, xmm2"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, xmmword [rdx]"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0xca], "vfnmadd132ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0xca], "vfnmadd132ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0xca], "vfnmadd132ps zmm1, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}, zmm0, zmm2"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, zmmword [rdx]"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0xca], "vfnmadd132ps xmm1, xmm0, xmm2"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}, xmm0, xmm2"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, xmmword [rdx]"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9d, 0xca], "vfnmadd132sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9d, 0xca], "vfnmadd132sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0xca], "vfnmadd132sd xmm1, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0x0a], "vfnmadd132sd xmm1, xmm0, qword [rdx]"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9d, 0xca], "vfnmadd132ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9d, 0xca], "vfnmadd132ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0xca], "vfnmadd132ss xmm1, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0x0a], "vfnmadd132ss xmm1, xmm0, dword [rdx]"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9d, 0xca], "vfnmadd132sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9d, 0xca], "vfnmadd132sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9d, 0xca], "vfnmadd132ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9d, 0xca], "vfnmadd132ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9e, 0xca], "vfnmsub132pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0xca], "vfnmsub132pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0xca], "vfnmsub132pd ymm1, ymm0, ymm2"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}, ymm0, ymm2"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, ymmword [rdx]"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB132PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9e, 0xca], "vfnmsub132ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0xca], "vfnmsub132ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0xca], "vfnmsub132ps ymm1, ymm0, ymm2"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}, ymm0, ymm2"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, ymmword [rdx]"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB132PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0xca], "vfnmsub132pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0xca], "vfnmsub132pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0xca], "vfnmsub132pd zmm1, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}, zmm0, zmm2"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, zmmword [rdx]"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB132PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0xca], "vfnmsub132pd xmm1, xmm0, xmm2"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}, xmm0, xmm2"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, xmmword [rdx]"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB132PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0xca], "vfnmsub132ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0xca], "vfnmsub132ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0xca], "vfnmsub132ps zmm1, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}, zmm0, zmm2"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, zmmword [rdx]"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB132PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0xca], "vfnmsub132ps xmm1, xmm0, xmm2"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}, xmm0, xmm2"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, xmmword [rdx]"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB132PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9f, 0xca], "vfnmsub132sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9f, 0xca], "vfnmsub132sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0xca], "vfnmsub132sd xmm1, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0x0a], "vfnmsub132sd xmm1, xmm0, qword [rdx]"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9f, 0xca], "vfnmsub132ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9f, 0xca], "vfnmsub132ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0xca], "vfnmsub132ss xmm1, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0x0a], "vfnmsub132ss xmm1, xmm0, dword [rdx]"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9f, 0xca], "vfnmsub132sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9f, 0xca], "vfnmsub132sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB132SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9f, 0xca], "vfnmsub132ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9f, 0xca], "vfnmsub132ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB132SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa6, 0xca], "vfmaddsub213pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0xca], "vfmaddsub213pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0xca], "vfmaddsub213pd ymm1, ymm0, ymm2"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}, ymm0, ymm2"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa6, 0xca], "vfmaddsub213ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0xca], "vfmaddsub213ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0xca], "vfmaddsub213ps ymm1, ymm0, ymm2"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}, ymm0, ymm2"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0xca], "vfmaddsub213pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0xca], "vfmaddsub213pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0xca], "vfmaddsub213pd zmm1, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}, zmm0, zmm2"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0xca], "vfmaddsub213pd xmm1, xmm0, xmm2"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}, xmm0, xmm2"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0xca], "vfmaddsub213ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0xca], "vfmaddsub213ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0xca], "vfmaddsub213ps zmm1, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}, zmm0, zmm2"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0xca], "vfmaddsub213ps xmm1, xmm0, xmm2"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}, xmm0, xmm2"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa7, 0xca], "vfmsubadd213pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0xca], "vfmsubadd213pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0xca], "vfmsubadd213pd ymm1, ymm0, ymm2"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}, ymm0, ymm2"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa7, 0xca], "vfmsubadd213ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0xca], "vfmsubadd213ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0xca], "vfmsubadd213ps ymm1, ymm0, ymm2"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}, ymm0, ymm2"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0xca], "vfmsubadd213pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0xca], "vfmsubadd213pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0xca], "vfmsubadd213pd zmm1, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}, zmm0, zmm2"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0xca], "vfmsubadd213pd xmm1, xmm0, xmm2"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}, xmm0, xmm2"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0xca], "vfmsubadd213ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0xca], "vfmsubadd213ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0xca], "vfmsubadd213ps zmm1, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}, zmm0, zmm2"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0xca], "vfmsubadd213ps xmm1, xmm0, xmm2"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}, xmm0, xmm2"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa8, 0xca], "vfmadd213pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0xca], "vfmadd213pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0xca], "vfmadd213pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0xca], "vfmadd213pd ymm1, ymm0, ymm2"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0xca], "vfmadd213pd ymm1{k5}, ymm0, ymm2"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, ymmword [rdx]"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa8, 0xca], "vfmadd213ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0xca], "vfmadd213ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0xca], "vfmadd213ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0xca], "vfmadd213ps ymm1, ymm0, ymm2"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0xca], "vfmadd213ps ymm1{k5}, ymm0, ymm2"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, ymmword [rdx]"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0xca], "vfmadd213pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0xca], "vfmadd213pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0xca], "vfmadd213pd zmm1, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}, zmm0, zmm2"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, zmmword [rdx]"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0xca], "vfmadd213pd xmm1, xmm0, xmm2"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}, xmm0, xmm2"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, xmmword [rdx]"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0xca], "vfmadd213ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0xca], "vfmadd213ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0xca], "vfmadd213ps zmm1, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}, zmm0, zmm2"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, zmmword [rdx]"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0xca], "vfmadd213ps xmm1, xmm0, xmm2"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}, xmm0, xmm2"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, xmmword [rdx]"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa9, 0xca], "vfmadd213sd xmm1{rz-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa9, 0xca], "vfmadd213sd xmm1{rd-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0xca], "vfmadd213sd xmm1, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0x0a], "vfmadd213sd xmm1, xmm0, qword [rdx]"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}, xmm0, qword [rdx]"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa9, 0xca], "vfmadd213ss xmm1{rz-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa9, 0xca], "vfmadd213ss xmm1{rd-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0xca], "vfmadd213ss xmm1, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0x0a], "vfmadd213ss xmm1, xmm0, dword [rdx]"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}, xmm0, dword [rdx]"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa9, 0xca], "vfmadd213sd xmm1{ru-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa9, 0xca], "vfmadd213sd xmm1{rne-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa9, 0xca], "vfmadd213ss xmm1{ru-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa9, 0xca], "vfmadd213ss xmm1{rne-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xaa, 0xca], "vfmsub213pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0xca], "vfmsub213pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0xca], "vfmsub213pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0xca], "vfmsub213pd ymm1, ymm0, ymm2"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0xca], "vfmsub213pd ymm1{k5}, ymm0, ymm2"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, ymmword [rdx]"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xaa, 0xca], "vfmsub213ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0xca], "vfmsub213ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0xca], "vfmsub213ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0xca], "vfmsub213ps ymm1, ymm0, ymm2"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0xca], "vfmsub213ps ymm1{k5}, ymm0, ymm2"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, ymmword [rdx]"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0xca], "vfmsub213pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0xca], "vfmsub213pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0xca], "vfmsub213pd zmm1, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}, zmm0, zmm2"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, zmmword [rdx]"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0xca], "vfmsub213pd xmm1, xmm0, xmm2"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}, xmm0, xmm2"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, xmmword [rdx]"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0xca], "vfmsub213ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0xca], "vfmsub213ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0xca], "vfmsub213ps zmm1, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}, zmm0, zmm2"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, zmmword [rdx]"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0xca], "vfmsub213ps xmm1, xmm0, xmm2"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}, xmm0, xmm2"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, xmmword [rdx]"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xab, 0xca], "vfmsub213sd xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xab, 0xca], "vfmsub213sd xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0x0a], "vfmsub213sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0xca], "vfmsub213sd xmm1, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0xca], "vfmsub213sd xmm1{k5}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0x0a], "vfmsub213sd xmm1, xmm0, qword [rdx]"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0x0a], "vfmsub213sd xmm1{k5}, xmm0, qword [rdx]"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xab, 0xca], "vfmsub213ss xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xab, 0xca], "vfmsub213ss xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0x0a], "vfmsub213ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0xca], "vfmsub213ss xmm1, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0xca], "vfmsub213ss xmm1{k5}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0x0a], "vfmsub213ss xmm1, xmm0, dword [rdx]"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0x0a], "vfmsub213ss xmm1{k5}, xmm0, dword [rdx]"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xab, 0xca], "vfmsub213sd xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xab, 0xca], "vfmsub213sd xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xab, 0xca], "vfmsub213ss xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xab, 0xca], "vfmsub213ss xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xac, 0xca], "vfnmadd213pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0xca], "vfnmadd213pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0xca], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0xca], "vfnmadd213pd ymm1, ymm0, ymm2"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0xca], "vfnmadd213pd ymm1{k5}, ymm0, ymm2"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, ymmword [rdx]"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xac, 0xca], "vfnmadd213ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0xca], "vfnmadd213ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0xca], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0xca], "vfnmadd213ps ymm1, ymm0, ymm2"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0xca], "vfnmadd213ps ymm1{k5}, ymm0, ymm2"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, ymmword [rdx]"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0xca], "vfnmadd213pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0xca], "vfnmadd213pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0xca], "vfnmadd213pd zmm1, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}, zmm0, zmm2"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, zmmword [rdx]"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0xca], "vfnmadd213pd xmm1, xmm0, xmm2"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}, xmm0, xmm2"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, xmmword [rdx]"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0xca], "vfnmadd213ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0xca], "vfnmadd213ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0xca], "vfnmadd213ps zmm1, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}, zmm0, zmm2"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, zmmword [rdx]"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0xca], "vfnmadd213ps xmm1, xmm0, xmm2"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}, xmm0, xmm2"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, xmmword [rdx]"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xad, 0xca], "vfnmadd213sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xad, 0xca], "vfnmadd213sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0xca], "vfnmadd213sd xmm1, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0x0a], "vfnmadd213sd xmm1, xmm0, qword [rdx]"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xad, 0xca], "vfnmadd213ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xad, 0xca], "vfnmadd213ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0xca], "vfnmadd213ss xmm1, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0x0a], "vfnmadd213ss xmm1, xmm0, dword [rdx]"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xad, 0xca], "vfnmadd213sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xad, 0xca], "vfnmadd213sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xad, 0xca], "vfnmadd213ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xad, 0xca], "vfnmadd213ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xae, 0xca], "vfnmsub213pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0xca], "vfnmsub213pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0xca], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0xca], "vfnmsub213pd ymm1, ymm0, ymm2"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0xca], "vfnmsub213pd ymm1{k5}, ymm0, ymm2"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, ymmword [rdx]"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB213PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xae, 0xca], "vfnmsub213ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0xca], "vfnmsub213ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0xca], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0xca], "vfnmsub213ps ymm1, ymm0, ymm2"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0xca], "vfnmsub213ps ymm1{k5}, ymm0, ymm2"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, ymmword [rdx]"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB213PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0xca], "vfnmsub213pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0xca], "vfnmsub213pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0xca], "vfnmsub213pd zmm1, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}, zmm0, zmm2"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, zmmword [rdx]"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB213PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0xca], "vfnmsub213pd xmm1, xmm0, xmm2"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}, xmm0, xmm2"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, xmmword [rdx]"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB213PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0xca], "vfnmsub213ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0xca], "vfnmsub213ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0xca], "vfnmsub213ps zmm1, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}, zmm0, zmm2"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, zmmword [rdx]"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB213PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0xca], "vfnmsub213ps xmm1, xmm0, xmm2"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}, xmm0, xmm2"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, xmmword [rdx]"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB213PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xaf, 0xca], "vfnmsub213sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaf, 0xca], "vfnmsub213sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0xca], "vfnmsub213sd xmm1, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0x0a], "vfnmsub213sd xmm1, xmm0, qword [rdx]"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xaf, 0xca], "vfnmsub213ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaf, 0xca], "vfnmsub213ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0xca], "vfnmsub213ss xmm1, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0x0a], "vfnmsub213ss xmm1, xmm0, dword [rdx]"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaf, 0xca], "vfnmsub213sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaf, 0xca], "vfnmsub213sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB213SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaf, 0xca], "vfnmsub213ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaf, 0xca], "vfnmsub213ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB213SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, qword [rdx]{1to4}"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0xca], "vpmadd52luq ymm1{k5}{z}, ymm0, ymm2"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0xca], "vpmadd52luq ymm1, ymm0, ymm2"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0xca], "vpmadd52luq ymm1{k5}, ymm0, ymm2"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, ymmword [rdx]"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMADD52LUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, qword [rdx]{1to8}"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, qword [rdx]{1to2}"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0xca], "vpmadd52luq zmm1{k5}{z}, zmm0, zmm2"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0xca], "vpmadd52luq zmm1, zmm0, zmm2"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0xca], "vpmadd52luq zmm1{k5}, zmm0, zmm2"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, zmmword [rdx]"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMADD52LUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}{z}, xmm0, xmm2"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0xca], "vpmadd52luq xmm1, xmm0, xmm2"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}, xmm0, xmm2"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, xmmword [rdx]"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADD52LUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, qword [rdx]{1to4}"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0xca], "vpmadd52huq ymm1{k5}{z}, ymm0, ymm2"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0xca], "vpmadd52huq ymm1, ymm0, ymm2"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0xca], "vpmadd52huq ymm1{k5}, ymm0, ymm2"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, ymmword [rdx]"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, ymmword [rdx]"); // VPMADD52HUQ_YMMu64_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, qword [rdx]{1to8}"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, qword [rdx]{1to2}"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0xca], "vpmadd52huq zmm1{k5}{z}, zmm0, zmm2"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0xca], "vpmadd52huq zmm1, zmm0, zmm2"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0xca], "vpmadd52huq zmm1{k5}, zmm0, zmm2"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, zmmword [rdx]"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, zmmword [rdx]"); // VPMADD52HUQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}{z}, xmm0, xmm2"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0xca], "vpmadd52huq xmm1, xmm0, xmm2"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}, xmm0, xmm2"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, xmmword [rdx]"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, xmmword [rdx]"); // VPMADD52HUQ_XMMu64_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb6, 0xca], "vfmaddsub231pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0xca], "vfmaddsub231pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0xca], "vfmaddsub231pd ymm1, ymm0, ymm2"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}, ymm0, ymm2"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb6, 0xca], "vfmaddsub231ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0xca], "vfmaddsub231ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0xca], "vfmaddsub231ps ymm1, ymm0, ymm2"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}, ymm0, ymm2"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, ymmword [rdx]"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADDSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0xca], "vfmaddsub231pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0xca], "vfmaddsub231pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0xca], "vfmaddsub231pd zmm1, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}, zmm0, zmm2"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0xca], "vfmaddsub231pd xmm1, xmm0, xmm2"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}, xmm0, xmm2"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0xca], "vfmaddsub231ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0xca], "vfmaddsub231ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0xca], "vfmaddsub231ps zmm1, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}, zmm0, zmm2"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, zmmword [rdx]"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADDSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0xca], "vfmaddsub231ps xmm1, xmm0, xmm2"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}, xmm0, xmm2"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, xmmword [rdx]"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADDSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb7, 0xca], "vfmsubadd231pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0xca], "vfmsubadd231pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0xca], "vfmsubadd231pd ymm1, ymm0, ymm2"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}, ymm0, ymm2"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb7, 0xca], "vfmsubadd231ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0xca], "vfmsubadd231ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0xca], "vfmsubadd231ps ymm1, ymm0, ymm2"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}, ymm0, ymm2"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, ymmword [rdx]"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUBADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0xca], "vfmsubadd231pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0xca], "vfmsubadd231pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0xca], "vfmsubadd231pd zmm1, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}, zmm0, zmm2"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0xca], "vfmsubadd231pd xmm1, xmm0, xmm2"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}, xmm0, xmm2"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0xca], "vfmsubadd231ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0xca], "vfmsubadd231ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0xca], "vfmsubadd231ps zmm1, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}, zmm0, zmm2"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, zmmword [rdx]"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUBADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0xca], "vfmsubadd231ps xmm1, xmm0, xmm2"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}, xmm0, xmm2"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, xmmword [rdx]"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUBADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb8, 0xca], "vfmadd231pd zmm1{rz-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0xca], "vfmadd231pd zmm1{rd-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0xca], "vfmadd231pd ymm1{k5}{z}, ymm0, ymm2"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0xca], "vfmadd231pd ymm1, ymm0, ymm2"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0xca], "vfmadd231pd ymm1{k5}, ymm0, ymm2"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, ymmword [rdx]"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb8, 0xca], "vfmadd231ps zmm1{rz-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0xca], "vfmadd231ps zmm1{rd-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0xca], "vfmadd231ps ymm1{k5}{z}, ymm0, ymm2"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0xca], "vfmadd231ps ymm1, ymm0, ymm2"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0xca], "vfmadd231ps ymm1{k5}, ymm0, ymm2"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, ymmword [rdx]"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0xca], "vfmadd231pd zmm1{ru-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0xca], "vfmadd231pd zmm1{rne-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0xca], "vfmadd231pd zmm1, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}, zmm0, zmm2"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, zmmword [rdx]"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0xca], "vfmadd231pd xmm1, xmm0, xmm2"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}, xmm0, xmm2"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, xmmword [rdx]"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0xca], "vfmadd231ps zmm1{ru-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0xca], "vfmadd231ps zmm1{rne-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0xca], "vfmadd231ps zmm1, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}, zmm0, zmm2"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, zmmword [rdx]"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}{z}, xmm0, xmm2"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0xca], "vfmadd231ps xmm1, xmm0, xmm2"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}, xmm0, xmm2"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, xmmword [rdx]"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb9, 0xca], "vfmadd231sd xmm1{rz-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb9, 0xca], "vfmadd231sd xmm1{rd-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0xca], "vfmadd231sd xmm1, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0x0a], "vfmadd231sd xmm1, xmm0, qword [rdx]"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}, xmm0, qword [rdx]"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb9, 0xca], "vfmadd231ss xmm1{rz-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb9, 0xca], "vfmadd231ss xmm1{rd-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0xca], "vfmadd231ss xmm1, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0x0a], "vfmadd231ss xmm1, xmm0, dword [rdx]"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}, xmm0, dword [rdx]"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb9, 0xca], "vfmadd231sd xmm1{ru-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb9, 0xca], "vfmadd231sd xmm1{rne-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb9, 0xca], "vfmadd231ss xmm1{ru-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb9, 0xca], "vfmadd231ss xmm1{rne-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xba, 0xca], "vfmsub231pd zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0xca], "vfmsub231pd zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0xca], "vfmsub231pd ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0xca], "vfmsub231pd ymm1, ymm0, ymm2"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0xca], "vfmsub231pd ymm1{k5}, ymm0, ymm2"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, ymmword [rdx]"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xba, 0xca], "vfmsub231ps zmm1{rz-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0xca], "vfmsub231ps zmm1{rd-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0xca], "vfmsub231ps ymm1{k5}{z}, ymm0, ymm2"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0xca], "vfmsub231ps ymm1, ymm0, ymm2"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0xca], "vfmsub231ps ymm1{k5}, ymm0, ymm2"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, ymmword [rdx]"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0xca], "vfmsub231pd zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0xca], "vfmsub231pd zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0xca], "vfmsub231pd zmm1, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0xca], "vfmsub231pd zmm1{k5}, zmm0, zmm2"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, zmmword [rdx]"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0xca], "vfmsub231pd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0xca], "vfmsub231pd xmm1, xmm0, xmm2"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0xca], "vfmsub231pd xmm1{k5}, xmm0, xmm2"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, xmmword [rdx]"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0xca], "vfmsub231ps zmm1{ru-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0xca], "vfmsub231ps zmm1{rne-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0xca], "vfmsub231ps zmm1, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0xca], "vfmsub231ps zmm1{k5}, zmm0, zmm2"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, zmmword [rdx]"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0xca], "vfmsub231ps xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0xca], "vfmsub231ps xmm1, xmm0, xmm2"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0xca], "vfmsub231ps xmm1{k5}, xmm0, xmm2"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, xmmword [rdx]"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbb, 0xca], "vfmsub231sd xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbb, 0xca], "vfmsub231sd xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0xca], "vfmsub231sd xmm1, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0x0a], "vfmsub231sd xmm1, xmm0, qword [rdx]"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}, xmm0, qword [rdx]"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbb, 0xca], "vfmsub231ss xmm1{rz-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbb, 0xca], "vfmsub231ss xmm1{rd-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0xca], "vfmsub231ss xmm1, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0x0a], "vfmsub231ss xmm1, xmm0, dword [rdx]"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}, xmm0, dword [rdx]"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbb, 0xca], "vfmsub231sd xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbb, 0xca], "vfmsub231sd xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbb, 0xca], "vfmsub231ss xmm1{ru-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbb, 0xca], "vfmsub231ss xmm1{rne-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbc, 0xca], "vfnmadd231pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0xca], "vfnmadd231pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0xca], "vfnmadd231pd ymm1, ymm0, ymm2"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}, ymm0, ymm2"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, ymmword [rdx]"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbc, 0xca], "vfnmadd231ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0xca], "vfnmadd231ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0xca], "vfnmadd231ps ymm1, ymm0, ymm2"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}, ymm0, ymm2"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, ymmword [rdx]"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMADD231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0xca], "vfnmadd231pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0xca], "vfnmadd231pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0xca], "vfnmadd231pd zmm1, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}, zmm0, zmm2"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, zmmword [rdx]"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0xca], "vfnmadd231pd xmm1, xmm0, xmm2"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}, xmm0, xmm2"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, xmmword [rdx]"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0xca], "vfnmadd231ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0xca], "vfnmadd231ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0xca], "vfnmadd231ps zmm1, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}, zmm0, zmm2"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, zmmword [rdx]"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMADD231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0xca], "vfnmadd231ps xmm1, xmm0, xmm2"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}, xmm0, xmm2"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, xmmword [rdx]"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMADD231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbd, 0xca], "vfnmadd231sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbd, 0xca], "vfnmadd231sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0xca], "vfnmadd231sd xmm1, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0x0a], "vfnmadd231sd xmm1, xmm0, qword [rdx]"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbd, 0xca], "vfnmadd231ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbd, 0xca], "vfnmadd231ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0xca], "vfnmadd231ss xmm1, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0x0a], "vfnmadd231ss xmm1, xmm0, dword [rdx]"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbd, 0xca], "vfnmadd231sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbd, 0xca], "vfnmadd231sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbd, 0xca], "vfnmadd231ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbd, 0xca], "vfnmadd231ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMADD231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbe, 0xca], "vfnmsub231pd zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0xca], "vfnmsub231pd zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, qword [rdx]{1to4}"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, qword [rdx]{1to4}"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0xca], "vfnmsub231pd ymm1, ymm0, ymm2"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}, ymm0, ymm2"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_YMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, ymmword [rdx]"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB231PD_YMMf64_MASKmskw_YMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbe, 0xca], "vfnmsub231ps zmm1{rz-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0xca], "vfnmsub231ps zmm1{rd-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, dword [rdx]{1to8}"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymm2"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0xca], "vfnmsub231ps ymm1, ymm0, ymm2"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}, ymm0, ymm2"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, ymmword [rdx]"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, ymmword [rdx]"); // VFNMSUB231PS_YMMf32_MASKmskw_YMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0xca], "vfnmsub231pd zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, qword [rdx]{1to8}"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, qword [rdx]{1to8}"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0xca], "vfnmsub231pd zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, qword [rdx]{1to2}"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, qword [rdx]{1to2}"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0xca], "vfnmsub231pd zmm1, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}, zmm0, zmm2"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, zmmword [rdx]"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB231PD_ZMMf64_MASKmskw_ZMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0xca], "vfnmsub231pd xmm1, xmm0, xmm2"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}, xmm0, xmm2"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, xmmword [rdx]"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB231PD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0xca], "vfnmsub231ps zmm1{ru-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, dword [rdx]{1to16}"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0xca], "vfnmsub231ps zmm1{rne-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, dword [rdx]{1to4}"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0xca], "vfnmsub231ps zmm1, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}, zmm0, zmm2"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, zmmword [rdx]"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, zmmword [rdx]"); // VFNMSUB231PS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0xca], "vfnmsub231ps xmm1, xmm0, xmm2"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}, xmm0, xmm2"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, xmmword [rdx]"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, xmmword [rdx]"); // VFNMSUB231PS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbf, 0xca], "vfnmsub231sd xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbf, 0xca], "vfnmsub231sd xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0xca], "vfnmsub231sd xmm1, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0x0a], "vfnmsub231sd xmm1, xmm0, qword [rdx]"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}, xmm0, qword [rdx]"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbf, 0xca], "vfnmsub231ss xmm1{rz-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbf, 0xca], "vfnmsub231ss xmm1{rd-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0xca], "vfnmsub231ss xmm1, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0x0a], "vfnmsub231ss xmm1, xmm0, dword [rdx]"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}, xmm0, dword [rdx]"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbf, 0xca], "vfnmsub231sd xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbf, 0xca], "vfnmsub231sd xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB231SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbf, 0xca], "vfnmsub231ss xmm1{ru-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbf, 0xca], "vfnmsub231ss xmm1{rne-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); // VFNMSUB231SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, qword [rdx]{1to4}"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xc4, 0x0a], "vpconflictq ymm1, qword [rdx]{1to4}"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, qword [rdx]{1to4}"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0xca], "vpconflictq ymm1{k5}{z}, ymm2"); // VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, ymmword [rdx]"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0xca], "vpconflictq ymm1, ymm2"); // VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0xca], "vpconflictq ymm1{k5}, ymm2"); // VPCONFLICTQ_YMMu64_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0x0a], "vpconflictq ymm1, ymmword [rdx]"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, ymmword [rdx]"); // VPCONFLICTQ_YMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, dword [rdx]{1to8}"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xc4, 0x0a], "vpconflictd ymm1, dword [rdx]{1to8}"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, dword [rdx]{1to8}"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0xca], "vpconflictd ymm1{k5}{z}, ymm2"); // VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, ymmword [rdx]"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0xca], "vpconflictd ymm1, ymm2"); // VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0xca], "vpconflictd ymm1{k5}, ymm2"); // VPCONFLICTD_YMMu32_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0x0a], "vpconflictd ymm1, ymmword [rdx]"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, ymmword [rdx]"); // VPCONFLICTD_YMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, qword [rdx]{1to8}"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc4, 0x0a], "vpconflictq zmm1, qword [rdx]{1to8}"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, qword [rdx]{1to8}"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, qword [rdx]{1to2}"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xc4, 0x0a], "vpconflictq xmm1, qword [rdx]{1to2}"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, qword [rdx]{1to2}"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0xca], "vpconflictq zmm1{k5}{z}, zmm2"); // VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, zmmword [rdx]"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0xca], "vpconflictq zmm1, zmm2"); // VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0xca], "vpconflictq zmm1{k5}, zmm2"); // VPCONFLICTQ_ZMMu64_MASKmskw_ZMMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0x0a], "vpconflictq zmm1, zmmword [rdx]"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, zmmword [rdx]"); // VPCONFLICTQ_ZMMu64_MASKmskw_MEMu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0xca], "vpconflictq xmm1{k5}{z}, xmm2"); // VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, xmmword [rdx]"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0xca], "vpconflictq xmm1, xmm2"); // VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0xca], "vpconflictq xmm1{k5}, xmm2"); // VPCONFLICTQ_XMMu64_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0x0a], "vpconflictq xmm1, xmmword [rdx]"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, xmmword [rdx]"); // VPCONFLICTQ_XMMu64_MASKmskw_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, dword [rdx]{1to16}"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc4, 0x0a], "vpconflictd zmm1, dword [rdx]{1to16}"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, dword [rdx]{1to16}"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, dword [rdx]{1to4}"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xc4, 0x0a], "vpconflictd xmm1, dword [rdx]{1to4}"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, dword [rdx]{1to4}"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0xca], "vpconflictd zmm1{k5}{z}, zmm2"); // VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, zmmword [rdx]"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0xca], "vpconflictd zmm1, zmm2"); // VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0xca], "vpconflictd zmm1{k5}, zmm2"); // VPCONFLICTD_ZMMu32_MASKmskw_ZMMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0x0a], "vpconflictd zmm1, zmmword [rdx]"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, zmmword [rdx]"); // VPCONFLICTD_ZMMu32_MASKmskw_MEMu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0xca], "vpconflictd xmm1{k5}{z}, xmm2"); // VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, xmmword [rdx]"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0xca], "vpconflictd xmm1, xmm2"); // VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0xca], "vpconflictd xmm1{k5}, xmm2"); // VPCONFLICTD_XMMu32_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0x0a], "vpconflictd xmm1, xmmword [rdx]"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, xmmword [rdx]"); // VPCONFLICTD_XMMu32_MASKmskw_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}{sae}, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xc8, 0xca], "vexp2pd zmm1{sae}, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xc8, 0xca], "vexp2pd zmm1{k5}{sae}, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}{sae}, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xc8, 0xca], "vexp2ps zmm1{sae}, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xc8, 0xca], "vexp2ps zmm1{k5}{sae}, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc8, 0x0a], "vexp2pd zmm1, qword [rdx]{1to8}"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, qword [rdx]{1to8}"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, zmmword [rdx]"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0xca], "vexp2pd zmm1, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0xca], "vexp2pd zmm1{k5}, zmm2"); // VEXP2PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0x0a], "vexp2pd zmm1, zmmword [rdx]"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, zmmword [rdx]"); // VEXP2PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc8, 0x0a], "vexp2ps zmm1, dword [rdx]{1to16}"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, dword [rdx]{1to16}"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, zmmword [rdx]"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0xca], "vexp2ps zmm1, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0xca], "vexp2ps zmm1{k5}, zmm2"); // VEXP2PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0x0a], "vexp2ps zmm1, zmmword [rdx]"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, zmmword [rdx]"); // VEXP2PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}{sae}, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xca, 0xca], "vrcp28pd zmm1{sae}, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xca, 0xca], "vrcp28pd zmm1{k5}{sae}, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}{sae}, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xca, 0xca], "vrcp28ps zmm1{sae}, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xca, 0xca], "vrcp28ps zmm1{k5}{sae}, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xca, 0x0a], "vrcp28pd zmm1, qword [rdx]{1to8}"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, qword [rdx]{1to8}"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, zmmword [rdx]"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0xca], "vrcp28pd zmm1, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0xca], "vrcp28pd zmm1{k5}, zmm2"); // VRCP28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0x0a], "vrcp28pd zmm1, zmmword [rdx]"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, zmmword [rdx]"); // VRCP28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xca, 0x0a], "vrcp28ps zmm1, dword [rdx]{1to16}"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, dword [rdx]{1to16}"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, zmmword [rdx]"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0xca], "vrcp28ps zmm1, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0xca], "vrcp28ps zmm1{k5}, zmm2"); // VRCP28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0x0a], "vrcp28ps zmm1, zmmword [rdx]"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, zmmword [rdx]"); // VRCP28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcb, 0xca], "vrcp28sd xmm1{sae}, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcb, 0xca], "vrcp28sd xmm1{k5}{sae}, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0x0a], "vrcp28sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0xca], "vrcp28sd xmm1, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0xca], "vrcp28sd xmm1{k5}, xmm0, xmm2"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0x0a], "vrcp28sd xmm1, xmm0, qword [rdx]"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0x0a], "vrcp28sd xmm1{k5}, xmm0, qword [rdx]"); // VRCP28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcb, 0xca], "vrcp28ss xmm1{sae}, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcb, 0xca], "vrcp28ss xmm1{k5}{sae}, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0x0a], "vrcp28ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0xca], "vrcp28ss xmm1, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0xca], "vrcp28ss xmm1{k5}, xmm0, xmm2"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0x0a], "vrcp28ss xmm1, xmm0, dword [rdx]"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0x0a], "vrcp28ss xmm1{k5}, xmm0, dword [rdx]"); // VRCP28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}{sae}, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcc, 0xca], "vrsqrt28pd zmm1{sae}, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{sae}, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}{sae}, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcc, 0xca], "vrsqrt28ps zmm1{sae}, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{sae}, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, qword [rdx]{1to8}"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xcc, 0x0a], "vrsqrt28pd zmm1, qword [rdx]{1to8}"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, qword [rdx]{1to8}"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, zmmword [rdx]"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0xca], "vrsqrt28pd zmm1, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}, zmm2"); // VRSQRT28PD_ZMMf64_MASKmskw_ZMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0x0a], "vrsqrt28pd zmm1, zmmword [rdx]"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, zmmword [rdx]"); // VRSQRT28PD_ZMMf64_MASKmskw_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, dword [rdx]{1to16}"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xcc, 0x0a], "vrsqrt28ps zmm1, dword [rdx]{1to16}"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, dword [rdx]{1to16}"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, zmmword [rdx]"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0xca], "vrsqrt28ps zmm1, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}, zmm2"); // VRSQRT28PS_ZMMf32_MASKmskw_ZMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0x0a], "vrsqrt28ps zmm1, zmmword [rdx]"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, zmmword [rdx]"); // VRSQRT28PS_ZMMf32_MASKmskw_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcd, 0xca], "vrsqrt28sd xmm1{sae}, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{sae}, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}{z}, xmm0, qword [rdx]"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0xca], "vrsqrt28sd xmm1, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}, xmm0, xmm2"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_XMMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0x0a], "vrsqrt28sd xmm1, xmm0, qword [rdx]"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}, xmm0, qword [rdx]"); // VRSQRT28SD_XMMf64_MASKmskw_XMMf64_MEMf64_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcd, 0xca], "vrsqrt28ss xmm1{sae}, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{sae}, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}{z}, xmm0, dword [rdx]"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0xca], "vrsqrt28ss xmm1, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}, xmm0, xmm2"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_XMMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0x0a], "vrsqrt28ss xmm1, xmm0, dword [rdx]"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}, xmm0, dword [rdx]"); // VRSQRT28SS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512ER, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymm2"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0xca], "vgf2p8mulb ymm1, ymm0, ymm2"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}, ymm0, ymm2"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0x0a], "vgf2p8mulb ymm1, ymm0, ymmword [rdx]"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}, ymm0, ymmword [rdx]"); // VGF2P8MULB_YMMu8_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmm2"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0xca], "vgf2p8mulb zmm1, zmm0, zmm2"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}, zmm0, zmm2"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0x0a], "vgf2p8mulb zmm1, zmm0, zmmword [rdx]"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}, zmm0, zmmword [rdx]"); // VGF2P8MULB_ZMMu8_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmm2"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0xca], "vgf2p8mulb xmm1, xmm0, xmm2"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}, xmm0, xmm2"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0x0a], "vgf2p8mulb xmm1, xmm0, xmmword [rdx]"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [rdx]"); // VGF2P8MULB_XMMu8_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); // VAESENC_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x0a], "vaesenc ymm1, ymm0, ymmword [rdx]"); // VAESENC_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0xca], "vaesenc zmm1, zmm0, zmm2"); // VAESENC_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x0a], "vaesenc zmm1, zmm0, zmmword [rdx]"); // VAESENC_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); // VAESENC_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0x0a], "vaesenc xmm1, xmm0, xmmword [rdx]"); // VAESENC_XMMu128_XMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0xca], "vaesenclast ymm1, ymm0, ymm2"); // VAESENCLAST_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0x0a], "vaesenclast ymm1, ymm0, ymmword [rdx]"); // VAESENCLAST_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0xca], "vaesenclast zmm1, zmm0, zmm2"); // VAESENCLAST_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0x0a], "vaesenclast zmm1, zmm0, zmmword [rdx]"); // VAESENCLAST_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0xca], "vaesenclast xmm1, xmm0, xmm2"); // VAESENCLAST_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0x0a], "vaesenclast xmm1, xmm0, xmmword [rdx]"); // VAESENCLAST_XMMu128_XMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0xca], "vaesdec ymm1, ymm0, ymm2"); // VAESDEC_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0x0a], "vaesdec ymm1, ymm0, ymmword [rdx]"); // VAESDEC_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0xca], "vaesdec zmm1, zmm0, zmm2"); // VAESDEC_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0x0a], "vaesdec zmm1, zmm0, zmmword [rdx]"); // VAESDEC_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0xca], "vaesdec xmm1, xmm0, xmm2"); // VAESDEC_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0x0a], "vaesdec xmm1, xmm0, xmmword [rdx]"); // VAESDEC_XMMu128_XMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0xca], "vaesdeclast ymm1, ymm0, ymm2"); // VAESDECLAST_YMMu128_YMMu128_YMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0x0a], "vaesdeclast ymm1, ymm0, ymmword [rdx]"); // VAESDECLAST_YMMu128_YMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0xca], "vaesdeclast zmm1, zmm0, zmm2"); // VAESDECLAST_ZMMu128_ZMMu128_ZMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0x0a], "vaesdeclast zmm1, zmm0, zmmword [rdx]"); // VAESDECLAST_ZMMu128_ZMMu128_MEMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0xca], "vaesdeclast xmm1, xmm0, xmm2"); // VAESDECLAST_XMMu128_XMMu128_XMMu128_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0x0a], "vaesdeclast xmm1, xmm0, xmmword [rdx]"); // VAESDECLAST_XMMu128_XMMu128_MEMu128_AVX512, extension: AVX512EVEX } #[test] fn tests_f2_0f38() { test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, ymm1"); // VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0xca], "vpmovuswb xmm2, ymm1"); // VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0xca], "vpmovuswb xmm2{k5}, ymm1"); // VPMOVUSWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x0a], "vpmovuswb xmmword [rdx], ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x0a], "vpmovuswb xmmword [rdx]{k5}, ymm1"); // VPMOVUSWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x10, 0xca], "vpmovuswb ymm2{k5}{z}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0xca], "vpmovuswb ymm2, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0xca], "vpmovuswb ymm2{k5}, zmm1"); // VPMOVUSWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0x0a], "vpmovuswb ymmword [rdx], zmm1"); // VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0x0a], "vpmovuswb ymmword [rdx]{k5}, zmm1"); // VPMOVUSWB_MEMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, xmm1"); // VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0xca], "vpmovuswb xmm2, xmm1"); // VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0xca], "vpmovuswb xmm2{k5}, xmm1"); // VPMOVUSWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0x0a], "vpmovuswb qword [rdx], xmm1"); // VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0x0a], "vpmovuswb qword [rdx]{k5}, xmm1"); // VPMOVUSWB_MEMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, ymm1"); // VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0xca], "vpmovusdb xmm2, ymm1"); // VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0xca], "vpmovusdb xmm2{k5}, ymm1"); // VPMOVUSDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0x0a], "vpmovusdb qword [rdx], ymm1"); // VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0x0a], "vpmovusdb qword [rdx]{k5}, ymm1"); // VPMOVUSDB_MEMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, zmm1"); // VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0xca], "vpmovusdb xmm2, zmm1"); // VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0xca], "vpmovusdb xmm2{k5}, zmm1"); // VPMOVUSDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0x0a], "vpmovusdb xmmword [rdx], zmm1"); // VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0x0a], "vpmovusdb xmmword [rdx]{k5}, zmm1"); // VPMOVUSDB_MEMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, xmm1"); // VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0xca], "vpmovusdb xmm2, xmm1"); // VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0xca], "vpmovusdb xmm2{k5}, xmm1"); // VPMOVUSDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0x0a], "vpmovusdb dword [rdx], xmm1"); // VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0x0a], "vpmovusdb dword [rdx]{k5}, xmm1"); // VPMOVUSDB_MEMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, ymm1"); // VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0xca], "vpmovusqb xmm2, ymm1"); // VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0xca], "vpmovusqb xmm2{k5}, ymm1"); // VPMOVUSQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0x0a], "vpmovusqb dword [rdx], ymm1"); // VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0x0a], "vpmovusqb dword [rdx]{k5}, ymm1"); // VPMOVUSQB_MEMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, zmm1"); // VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0xca], "vpmovusqb xmm2, zmm1"); // VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0xca], "vpmovusqb xmm2{k5}, zmm1"); // VPMOVUSQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x0a], "vpmovusqb qword [rdx], zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x0a], "vpmovusqb qword [rdx]{k5}, zmm1"); // VPMOVUSQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0xca], "vpmovusqb xmm2, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0xca], "vpmovusqb xmm2{k5}, xmm1"); // VPMOVUSQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0x0a], "vpmovusqb word [rdx], xmm1"); // VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0x0a], "vpmovusqb word [rdx]{k5}, xmm1"); // VPMOVUSQB_MEMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, ymm1"); // VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0xca], "vpmovusdw xmm2, ymm1"); // VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0xca], "vpmovusdw xmm2{k5}, ymm1"); // VPMOVUSDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0x0a], "vpmovusdw xmmword [rdx], ymm1"); // VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0x0a], "vpmovusdw xmmword [rdx]{k5}, ymm1"); // VPMOVUSDW_MEMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x13, 0xca], "vpmovusdw ymm2{k5}{z}, zmm1"); // VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0xca], "vpmovusdw ymm2, zmm1"); // VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0xca], "vpmovusdw ymm2{k5}, zmm1"); // VPMOVUSDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0x0a], "vpmovusdw ymmword [rdx], zmm1"); // VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0x0a], "vpmovusdw ymmword [rdx]{k5}, zmm1"); // VPMOVUSDW_MEMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, xmm1"); // VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0xca], "vpmovusdw xmm2, xmm1"); // VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0xca], "vpmovusdw xmm2{k5}, xmm1"); // VPMOVUSDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0x0a], "vpmovusdw qword [rdx], xmm1"); // VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0x0a], "vpmovusdw qword [rdx]{k5}, xmm1"); // VPMOVUSDW_MEMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, ymm1"); // VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0xca], "vpmovusqw xmm2, ymm1"); // VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0xca], "vpmovusqw xmm2{k5}, ymm1"); // VPMOVUSQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0x0a], "vpmovusqw qword [rdx], ymm1"); // VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0x0a], "vpmovusqw qword [rdx]{k5}, ymm1"); // VPMOVUSQW_MEMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, zmm1"); // VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0xca], "vpmovusqw xmm2, zmm1"); // VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0xca], "vpmovusqw xmm2{k5}, zmm1"); // VPMOVUSQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0x0a], "vpmovusqw xmmword [rdx], zmm1"); // VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0x0a], "vpmovusqw xmmword [rdx]{k5}, zmm1"); // VPMOVUSQW_MEMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, xmm1"); // VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0xca], "vpmovusqw xmm2, xmm1"); // VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0xca], "vpmovusqw xmm2{k5}, xmm1"); // VPMOVUSQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0x0a], "vpmovusqw dword [rdx], xmm1"); // VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0x0a], "vpmovusqw dword [rdx]{k5}, xmm1"); // VPMOVUSQW_MEMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, ymm1"); // VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0xca], "vpmovusqd xmm2, ymm1"); // VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0xca], "vpmovusqd xmm2{k5}, ymm1"); // VPMOVUSQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0x0a], "vpmovusqd xmmword [rdx], ymm1"); // VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0x0a], "vpmovusqd xmmword [rdx]{k5}, ymm1"); // VPMOVUSQD_MEMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x15, 0xca], "vpmovusqd ymm2{k5}{z}, zmm1"); // VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0xca], "vpmovusqd ymm2, zmm1"); // VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0xca], "vpmovusqd ymm2{k5}, zmm1"); // VPMOVUSQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0x0a], "vpmovusqd ymmword [rdx], zmm1"); // VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0x0a], "vpmovusqd ymmword [rdx]{k5}, zmm1"); // VPMOVUSQD_MEMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, xmm1"); // VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0xca], "vpmovusqd xmm2, xmm1"); // VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0xca], "vpmovusqd xmm2{k5}, xmm1"); // VPMOVUSQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0x0a], "vpmovusqd qword [rdx], xmm1"); // VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0x0a], "vpmovusqd qword [rdx]{k5}, xmm1"); // VPMOVUSQD_MEMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, ymm1"); // VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0xca], "vpmovswb xmm2, ymm1"); // VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0xca], "vpmovswb xmm2{k5}, ymm1"); // VPMOVSWB_XMMi8_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0x0a], "vpmovswb xmmword [rdx], ymm1"); // VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0x0a], "vpmovswb xmmword [rdx]{k5}, ymm1"); // VPMOVSWB_MEMi8_MASKmskw_YMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x20, 0xca], "vpmovswb ymm2{k5}{z}, zmm1"); // VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0xca], "vpmovswb ymm2, zmm1"); // VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0xca], "vpmovswb ymm2{k5}, zmm1"); // VPMOVSWB_YMMi8_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0x0a], "vpmovswb ymmword [rdx], zmm1"); // VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0x0a], "vpmovswb ymmword [rdx]{k5}, zmm1"); // VPMOVSWB_MEMi8_MASKmskw_ZMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, xmm1"); // VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0xca], "vpmovswb xmm2, xmm1"); // VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0xca], "vpmovswb xmm2{k5}, xmm1"); // VPMOVSWB_XMMi8_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0x0a], "vpmovswb qword [rdx], xmm1"); // VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0x0a], "vpmovswb qword [rdx]{k5}, xmm1"); // VPMOVSWB_MEMi8_MASKmskw_XMMi16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, ymm1"); // VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0xca], "vpmovsdb xmm2, ymm1"); // VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0xca], "vpmovsdb xmm2{k5}, ymm1"); // VPMOVSDB_XMMi8_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0x0a], "vpmovsdb qword [rdx], ymm1"); // VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0x0a], "vpmovsdb qword [rdx]{k5}, ymm1"); // VPMOVSDB_MEMi8_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, zmm1"); // VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0xca], "vpmovsdb xmm2, zmm1"); // VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0xca], "vpmovsdb xmm2{k5}, zmm1"); // VPMOVSDB_XMMi8_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0x0a], "vpmovsdb xmmword [rdx], zmm1"); // VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0x0a], "vpmovsdb xmmword [rdx]{k5}, zmm1"); // VPMOVSDB_MEMi8_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, xmm1"); // VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0xca], "vpmovsdb xmm2, xmm1"); // VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0xca], "vpmovsdb xmm2{k5}, xmm1"); // VPMOVSDB_XMMi8_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0x0a], "vpmovsdb dword [rdx], xmm1"); // VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0x0a], "vpmovsdb dword [rdx]{k5}, xmm1"); // VPMOVSDB_MEMi8_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, ymm1"); // VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0xca], "vpmovsqb xmm2, ymm1"); // VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0xca], "vpmovsqb xmm2{k5}, ymm1"); // VPMOVSQB_XMMi8_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0x0a], "vpmovsqb dword [rdx], ymm1"); // VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0x0a], "vpmovsqb dword [rdx]{k5}, ymm1"); // VPMOVSQB_MEMi8_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, zmm1"); // VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0xca], "vpmovsqb xmm2, zmm1"); // VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0xca], "vpmovsqb xmm2{k5}, zmm1"); // VPMOVSQB_XMMi8_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0x0a], "vpmovsqb qword [rdx], zmm1"); // VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0x0a], "vpmovsqb qword [rdx]{k5}, zmm1"); // VPMOVSQB_MEMi8_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, xmm1"); // VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0xca], "vpmovsqb xmm2, xmm1"); // VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0xca], "vpmovsqb xmm2{k5}, xmm1"); // VPMOVSQB_XMMi8_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0x0a], "vpmovsqb word [rdx], xmm1"); // VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0x0a], "vpmovsqb word [rdx]{k5}, xmm1"); // VPMOVSQB_MEMi8_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, ymm1"); // VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0xca], "vpmovsdw xmm2, ymm1"); // VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0xca], "vpmovsdw xmm2{k5}, ymm1"); // VPMOVSDW_XMMi16_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0x0a], "vpmovsdw xmmword [rdx], ymm1"); // VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0x0a], "vpmovsdw xmmword [rdx]{k5}, ymm1"); // VPMOVSDW_MEMi16_MASKmskw_YMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x23, 0xca], "vpmovsdw ymm2{k5}{z}, zmm1"); // VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0xca], "vpmovsdw ymm2, zmm1"); // VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0xca], "vpmovsdw ymm2{k5}, zmm1"); // VPMOVSDW_YMMi16_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0x0a], "vpmovsdw ymmword [rdx], zmm1"); // VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0x0a], "vpmovsdw ymmword [rdx]{k5}, zmm1"); // VPMOVSDW_MEMi16_MASKmskw_ZMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, xmm1"); // VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0xca], "vpmovsdw xmm2, xmm1"); // VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0xca], "vpmovsdw xmm2{k5}, xmm1"); // VPMOVSDW_XMMi16_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0x0a], "vpmovsdw qword [rdx], xmm1"); // VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0x0a], "vpmovsdw qword [rdx]{k5}, xmm1"); // VPMOVSDW_MEMi16_MASKmskw_XMMi32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, ymm1"); // VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0xca], "vpmovsqw xmm2, ymm1"); // VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0xca], "vpmovsqw xmm2{k5}, ymm1"); // VPMOVSQW_XMMi16_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0x0a], "vpmovsqw qword [rdx], ymm1"); // VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0x0a], "vpmovsqw qword [rdx]{k5}, ymm1"); // VPMOVSQW_MEMi16_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, zmm1"); // VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0xca], "vpmovsqw xmm2, zmm1"); // VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0xca], "vpmovsqw xmm2{k5}, zmm1"); // VPMOVSQW_XMMi16_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0x0a], "vpmovsqw xmmword [rdx], zmm1"); // VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0x0a], "vpmovsqw xmmword [rdx]{k5}, zmm1"); // VPMOVSQW_MEMi16_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, xmm1"); // VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0xca], "vpmovsqw xmm2, xmm1"); // VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0xca], "vpmovsqw xmm2{k5}, xmm1"); // VPMOVSQW_XMMi16_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0x0a], "vpmovsqw dword [rdx], xmm1"); // VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0x0a], "vpmovsqw dword [rdx]{k5}, xmm1"); // VPMOVSQW_MEMi16_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, ymm1"); // VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0xca], "vpmovsqd xmm2, ymm1"); // VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0xca], "vpmovsqd xmm2{k5}, ymm1"); // VPMOVSQD_XMMi32_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0x0a], "vpmovsqd xmmword [rdx], ymm1"); // VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0x0a], "vpmovsqd xmmword [rdx]{k5}, ymm1"); // VPMOVSQD_MEMi32_MASKmskw_YMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x25, 0xca], "vpmovsqd ymm2{k5}{z}, zmm1"); // VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0xca], "vpmovsqd ymm2, zmm1"); // VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0xca], "vpmovsqd ymm2{k5}, zmm1"); // VPMOVSQD_YMMi32_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0x0a], "vpmovsqd ymmword [rdx], zmm1"); // VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0x0a], "vpmovsqd ymmword [rdx]{k5}, zmm1"); // VPMOVSQD_MEMi32_MASKmskw_ZMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, xmm1"); // VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0xca], "vpmovsqd xmm2, xmm1"); // VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0xca], "vpmovsqd xmm2{k5}, xmm1"); // VPMOVSQD_XMMi32_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0x0a], "vpmovsqd qword [rdx], xmm1"); // VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0x0a], "vpmovsqd qword [rdx]{k5}, xmm1"); // VPMOVSQD_MEMi32_MASKmskw_XMMi64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0xca], "vptestnmw k1, ymm0, ymm2"); // VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0xca], "vptestnmw k1{k5}, ymm0, ymm2"); // VPTESTNMW_MASKmskw_MASKmskw_YMMu16_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0x0a], "vptestnmw k1, ymm0, ymmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0x0a], "vptestnmw k1{k5}, ymm0, ymmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_YMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0xca], "vptestnmb k1, ymm0, ymm2"); // VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0xca], "vptestnmb k1{k5}, ymm0, ymm2"); // VPTESTNMB_MASKmskw_MASKmskw_YMMu8_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0x0a], "vptestnmb k1, ymm0, ymmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0x0a], "vptestnmb k1{k5}, ymm0, ymmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_YMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0xca], "vptestnmw k1, zmm0, zmm2"); // VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0xca], "vptestnmw k1{k5}, zmm0, zmm2"); // VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0x0a], "vptestnmw k1, zmm0, zmmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0x0a], "vptestnmw k1{k5}, zmm0, zmmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_ZMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0xca], "vptestnmw k1, xmm0, xmm2"); // VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0xca], "vptestnmw k1{k5}, xmm0, xmm2"); // VPTESTNMW_MASKmskw_MASKmskw_XMMu16_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0x0a], "vptestnmw k1, xmm0, xmmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0x0a], "vptestnmw k1{k5}, xmm0, xmmword [rdx]"); // VPTESTNMW_MASKmskw_MASKmskw_XMMu16_MEMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0xca], "vptestnmb k1, zmm0, zmm2"); // VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0xca], "vptestnmb k1{k5}, zmm0, zmm2"); // VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0x0a], "vptestnmb k1, zmm0, zmmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0x0a], "vptestnmb k1{k5}, zmm0, zmmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_ZMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0xca], "vptestnmb k1, xmm0, xmm2"); // VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0xca], "vptestnmb k1{k5}, xmm0, xmm2"); // VPTESTNMB_MASKmskw_MASKmskw_XMMu8_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0x0a], "vptestnmb k1, xmm0, xmmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0x0a], "vptestnmb k1{k5}, xmm0, xmmword [rdx]"); // VPTESTNMB_MASKmskw_MASKmskw_XMMu8_MEMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x38, 0x27, 0x0a], "vptestnmq k1, ymm0, qword [rdx]{1to4}"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x3d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, qword [rdx]{1to4}"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0xca], "vptestnmq k1, ymm0, ymm2"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0xca], "vptestnmq k1{k5}, ymm0, ymm2"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0x0a], "vptestnmq k1, ymm0, ymmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, ymmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x27, 0x0a], "vptestnmd k1, ymm0, dword [rdx]{1to8}"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, dword [rdx]{1to8}"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0xca], "vptestnmd k1, ymm0, ymm2"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0xca], "vptestnmd k1{k5}, ymm0, ymm2"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0x0a], "vptestnmd k1, ymm0, ymmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, ymmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x58, 0x27, 0x0a], "vptestnmq k1, zmm0, qword [rdx]{1to8}"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x5d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, qword [rdx]{1to8}"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x18, 0x27, 0x0a], "vptestnmq k1, xmm0, qword [rdx]{1to2}"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x1d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, qword [rdx]{1to2}"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0xca], "vptestnmq k1, zmm0, zmm2"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0xca], "vptestnmq k1{k5}, zmm0, zmm2"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0x0a], "vptestnmq k1, zmm0, zmmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, zmmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0xca], "vptestnmq k1, xmm0, xmm2"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0xca], "vptestnmq k1{k5}, xmm0, xmm2"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0x0a], "vptestnmq k1, xmm0, xmmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, xmmword [rdx]"); // VPTESTNMQ_MASKmskw_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x27, 0x0a], "vptestnmd k1, zmm0, dword [rdx]{1to16}"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, dword [rdx]{1to16}"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x27, 0x0a], "vptestnmd k1, xmm0, dword [rdx]{1to4}"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, dword [rdx]{1to4}"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0xca], "vptestnmd k1, zmm0, zmm2"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0xca], "vptestnmd k1{k5}, zmm0, zmm2"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0x0a], "vptestnmd k1, zmm0, zmmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, zmmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0xca], "vptestnmd k1, xmm0, xmm2"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0xca], "vptestnmd k1{k5}, xmm0, xmm2"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0x0a], "vptestnmd k1, xmm0, xmmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, xmmword [rdx]"); // VPTESTNMD_MASKmskw_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x28, 0xca], "vpmovm2w ymm1, k2"); // VPMOVM2W_YMMu16_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x28, 0xca], "vpmovm2b ymm1, k2"); // VPMOVM2B_YMMu8_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x28, 0xca], "vpmovm2w zmm1, k2"); // VPMOVM2W_ZMMu16_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x28, 0xca], "vpmovm2w xmm1, k2"); // VPMOVM2W_XMMu16_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x28, 0xca], "vpmovm2b zmm1, k2"); // VPMOVM2B_ZMMu8_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xca], "vpmovm2b xmm1, k2"); // VPMOVM2B_XMMu8_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x29, 0xca], "vpmovw2m k1, ymm2"); // VPMOVW2M_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xca], "vpmovb2m k1, ymm2"); // VPMOVB2M_MASKmskw_YMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x29, 0xca], "vpmovw2m k1, zmm2"); // VPMOVW2M_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x29, 0xca], "vpmovw2m k1, xmm2"); // VPMOVW2M_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x29, 0xca], "vpmovb2m k1, zmm2"); // VPMOVB2M_MASKmskw_ZMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x29, 0xca], "vpmovb2m k1, xmm2"); // VPMOVB2M_MASKmskw_XMMu8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x2a, 0xca], "vpbroadcastmb2q ymm1, k2"); // VPBROADCASTMB2Q_YMMu64_MASKu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x2a, 0xca], "vpbroadcastmb2q zmm1, k2"); // VPBROADCASTMB2Q_ZMMu64_MASKu64_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x2a, 0xca], "vpbroadcastmb2q xmm1, k2"); // VPBROADCASTMB2Q_XMMu64_MASKu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, ymm1"); // VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0xca], "vpmovwb xmm2, ymm1"); // VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0xca], "vpmovwb xmm2{k5}, ymm1"); // VPMOVWB_XMMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0x0a], "vpmovwb xmmword [rdx], ymm1"); // VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0x0a], "vpmovwb xmmword [rdx]{k5}, ymm1"); // VPMOVWB_MEMu8_MASKmskw_YMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x30, 0xca], "vpmovwb ymm2{k5}{z}, zmm1"); // VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0xca], "vpmovwb ymm2, zmm1"); // VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0xca], "vpmovwb ymm2{k5}, zmm1"); // VPMOVWB_YMMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0x0a], "vpmovwb ymmword [rdx], zmm1"); // VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0x0a], "vpmovwb ymmword [rdx]{k5}, zmm1"); // VPMOVWB_MEMu8_MASKmskw_ZMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, xmm1"); // VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0xca], "vpmovwb xmm2, xmm1"); // VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0xca], "vpmovwb xmm2{k5}, xmm1"); // VPMOVWB_XMMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0x0a], "vpmovwb qword [rdx], xmm1"); // VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0x0a], "vpmovwb qword [rdx]{k5}, xmm1"); // VPMOVWB_MEMu8_MASKmskw_XMMu16_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, ymm1"); // VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0xca], "vpmovdb xmm2, ymm1"); // VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0xca], "vpmovdb xmm2{k5}, ymm1"); // VPMOVDB_XMMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0x0a], "vpmovdb qword [rdx], ymm1"); // VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0x0a], "vpmovdb qword [rdx]{k5}, ymm1"); // VPMOVDB_MEMu8_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, zmm1"); // VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0xca], "vpmovdb xmm2, zmm1"); // VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0xca], "vpmovdb xmm2{k5}, zmm1"); // VPMOVDB_XMMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0x0a], "vpmovdb xmmword [rdx], zmm1"); // VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0x0a], "vpmovdb xmmword [rdx]{k5}, zmm1"); // VPMOVDB_MEMu8_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, xmm1"); // VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0xca], "vpmovdb xmm2, xmm1"); // VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0xca], "vpmovdb xmm2{k5}, xmm1"); // VPMOVDB_XMMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0x0a], "vpmovdb dword [rdx], xmm1"); // VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0x0a], "vpmovdb dword [rdx]{k5}, xmm1"); // VPMOVDB_MEMu8_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, ymm1"); // VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0xca], "vpmovqb xmm2, ymm1"); // VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0xca], "vpmovqb xmm2{k5}, ymm1"); // VPMOVQB_XMMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0x0a], "vpmovqb dword [rdx], ymm1"); // VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0x0a], "vpmovqb dword [rdx]{k5}, ymm1"); // VPMOVQB_MEMu8_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, zmm1"); // VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0xca], "vpmovqb xmm2, zmm1"); // VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0xca], "vpmovqb xmm2{k5}, zmm1"); // VPMOVQB_XMMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0x0a], "vpmovqb qword [rdx], zmm1"); // VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0x0a], "vpmovqb qword [rdx]{k5}, zmm1"); // VPMOVQB_MEMu8_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, xmm1"); // VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0xca], "vpmovqb xmm2, xmm1"); // VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0xca], "vpmovqb xmm2{k5}, xmm1"); // VPMOVQB_XMMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0x0a], "vpmovqb word [rdx], xmm1"); // VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0x0a], "vpmovqb word [rdx]{k5}, xmm1"); // VPMOVQB_MEMu8_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, ymm1"); // VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0xca], "vpmovdw xmm2, ymm1"); // VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0xca], "vpmovdw xmm2{k5}, ymm1"); // VPMOVDW_XMMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0x0a], "vpmovdw xmmword [rdx], ymm1"); // VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0x0a], "vpmovdw xmmword [rdx]{k5}, ymm1"); // VPMOVDW_MEMu16_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x33, 0xca], "vpmovdw ymm2{k5}{z}, zmm1"); // VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0xca], "vpmovdw ymm2, zmm1"); // VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0xca], "vpmovdw ymm2{k5}, zmm1"); // VPMOVDW_YMMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0x0a], "vpmovdw ymmword [rdx], zmm1"); // VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0x0a], "vpmovdw ymmword [rdx]{k5}, zmm1"); // VPMOVDW_MEMu16_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, xmm1"); // VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0xca], "vpmovdw xmm2, xmm1"); // VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0xca], "vpmovdw xmm2{k5}, xmm1"); // VPMOVDW_XMMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0x0a], "vpmovdw qword [rdx], xmm1"); // VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0x0a], "vpmovdw qword [rdx]{k5}, xmm1"); // VPMOVDW_MEMu16_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, ymm1"); // VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0xca], "vpmovqw xmm2, ymm1"); // VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0xca], "vpmovqw xmm2{k5}, ymm1"); // VPMOVQW_XMMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0x0a], "vpmovqw qword [rdx], ymm1"); // VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0x0a], "vpmovqw qword [rdx]{k5}, ymm1"); // VPMOVQW_MEMu16_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, zmm1"); // VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0xca], "vpmovqw xmm2, zmm1"); // VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0xca], "vpmovqw xmm2{k5}, zmm1"); // VPMOVQW_XMMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0x0a], "vpmovqw xmmword [rdx], zmm1"); // VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0x0a], "vpmovqw xmmword [rdx]{k5}, zmm1"); // VPMOVQW_MEMu16_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, xmm1"); // VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0xca], "vpmovqw xmm2, xmm1"); // VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0xca], "vpmovqw xmm2{k5}, xmm1"); // VPMOVQW_XMMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0x0a], "vpmovqw dword [rdx], xmm1"); // VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0x0a], "vpmovqw dword [rdx]{k5}, xmm1"); // VPMOVQW_MEMu16_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, ymm1"); // VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0xca], "vpmovqd xmm2, ymm1"); // VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0xca], "vpmovqd xmm2{k5}, ymm1"); // VPMOVQD_XMMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0x0a], "vpmovqd xmmword [rdx], ymm1"); // VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0x0a], "vpmovqd xmmword [rdx]{k5}, ymm1"); // VPMOVQD_MEMu32_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x35, 0xca], "vpmovqd ymm2{k5}{z}, zmm1"); // VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0xca], "vpmovqd ymm2, zmm1"); // VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0xca], "vpmovqd ymm2{k5}, zmm1"); // VPMOVQD_YMMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0x0a], "vpmovqd ymmword [rdx], zmm1"); // VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0x0a], "vpmovqd ymmword [rdx]{k5}, zmm1"); // VPMOVQD_MEMu32_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, xmm1"); // VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0xca], "vpmovqd xmm2, xmm1"); // VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0xca], "vpmovqd xmm2{k5}, xmm1"); // VPMOVQD_XMMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0x0a], "vpmovqd qword [rdx], xmm1"); // VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0x0a], "vpmovqd qword [rdx]{k5}, xmm1"); // VPMOVQD_MEMu32_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x38, 0xca], "vpmovm2q ymm1, k2"); // VPMOVM2Q_YMMu64_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x38, 0xca], "vpmovm2d ymm1, k2"); // VPMOVM2D_YMMu32_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x38, 0xca], "vpmovm2q zmm1, k2"); // VPMOVM2Q_ZMMu64_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x38, 0xca], "vpmovm2q xmm1, k2"); // VPMOVM2Q_XMMu64_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x38, 0xca], "vpmovm2d zmm1, k2"); // VPMOVM2D_ZMMu32_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x38, 0xca], "vpmovm2d xmm1, k2"); // VPMOVM2D_XMMu32_MASKmskw_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x39, 0xca], "vpmovq2m k1, ymm2"); // VPMOVQ2M_MASKmskw_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x39, 0xca], "vpmovd2m k1, ymm2"); // VPMOVD2M_MASKmskw_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x39, 0xca], "vpmovq2m k1, zmm2"); // VPMOVQ2M_MASKmskw_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x39, 0xca], "vpmovq2m k1, xmm2"); // VPMOVQ2M_MASKmskw_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x39, 0xca], "vpmovd2m k1, zmm2"); // VPMOVD2M_MASKmskw_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x39, 0xca], "vpmovd2m k1, xmm2"); // VPMOVD2M_MASKmskw_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // VPBROADCASTMW2D_YMMu32_MASKu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xca], "vpbroadcastmw2d zmm1, k2"); // VPBROADCASTMW2D_ZMMu32_MASKu32_AVX512CD, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x3a, 0xca], "vpbroadcastmw2d xmm1, k2"); // VPBROADCASTMW2D_XMMu32_MASKu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0xca], "vdpbf16ps ymm1{k5}{z}, ymm0, ymm2"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0xca], "vdpbf16ps ymm1, ymm0, ymm2"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0xca], "vdpbf16ps ymm1{k5}, ymm0, ymm2"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, ymmword [rdx]"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, ymmword [rdx]"); // VDPBF16PS_YMMf32_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, dword [rdx]{1to16}"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, dword [rdx]{1to4}"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0xca], "vdpbf16ps zmm1{k5}{z}, zmm0, zmm2"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0xca], "vdpbf16ps zmm1, zmm0, zmm2"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0xca], "vdpbf16ps zmm1{k5}, zmm0, zmm2"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, zmmword [rdx]"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, zmmword [rdx]"); // VDPBF16PS_ZMMf32_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0xca], "vdpbf16ps xmm1{k5}{z}, xmm0, xmm2"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0xca], "vdpbf16ps xmm1, xmm0, xmm2"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0xca], "vdpbf16ps xmm1{k5}, xmm0, xmm2"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, xmmword [rdx]"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, xmmword [rdx]"); // VDPBF16PS_XMMf32_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [rdx]{1to8}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0xca], "vcvtneps2bf16 xmm1, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, ymm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0x0a], "vcvtneps2bf16 xmm1, ymmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, ymmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, dword [rdx]{1to16}"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x72, 0x0a], "vcvtneps2bf16 ymm1, dword [rdx]{1to16}"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, dword [rdx]{1to16}"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [rdx]{1to4}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [rdx]{1to4}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [rdx]{1to4}"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}{z}, zmm2"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, zmmword [rdx]"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0xca], "vcvtneps2bf16 ymm1, zmm2"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}, zmm2"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0x0a], "vcvtneps2bf16 ymm1, zmmword [rdx]"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, zmmword [rdx]"); // VCVTNEPS2BF16_YMMbf16_MASKmskw_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, xmm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, xmmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0xca], "vcvtneps2bf16 xmm1, xmm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, xmm2"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0x0a], "vcvtneps2bf16 xmm1, xmmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, xmmword [rdx]"); // VCVTNEPS2BF16_XMMbf16_MASKmskw_MEMf32_AVX512_VL128, extension: AVX512EVEX } #[test] fn tests_f3_0f38() { test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x0a], "vp2intersectd k1, xmm0, xmmword [rdx]"); // VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); // VP2INTERSECTD_MASKmskw_XMMu32_XMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0xca], "vcvtne2ps2bf16 xmm1, xmm0, xmm2"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmm2"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x68, 0x0a], "vp2intersectd k1, xmm0, dword [rdx]{1to4}"); // VP2INTERSECTD_MASKmskw_XMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, dword [rdx]{1to4}"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x1d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, dword [rdx]{1to4}"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0x0a], "vp2intersectd k1, ymm0, ymmword [rdx]"); // VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0xca], "vp2intersectd k1, ymm0, ymm2"); // VP2INTERSECTD_MASKmskw_YMMu32_YMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, ymmword [rdx]"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0xca], "vcvtne2ps2bf16 ymm1, ymm0, ymm2"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x9b, 0x0a], "v4fmaddss xmm1, xmm0, xmmword [rdx]"); // V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x0a], "v4fnmaddss xmm1, xmm0, xmmword [rdx]"); // V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymmword [rdx]"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymm2"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x9b, 0x0a], "v4fmaddss xmm1{k5}, xmm0, xmmword [rdx]"); // V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x0a], "v4fnmaddss xmm1{k5}, xmm0, xmmword [rdx]"); // V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x68, 0x0a], "vp2intersectd k1, ymm0, dword [rdx]{1to8}"); // VP2INTERSECTD_MASKmskw_YMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, dword [rdx]{1to8}"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x3d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, dword [rdx]{1to8}"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x52, 0x0a], "vp4dpwssd zmm1, zmm0, xmmword [rdx]"); // VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x53, 0x0a], "vp4dpwssds zmm1, zmm0, xmmword [rdx]"); // VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0x0a], "vp2intersectd k1, zmm0, zmmword [rdx]"); // VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0xca], "vp2intersectd k1, zmm0, zmm2"); // VP2INTERSECTD_MASKmskw_ZMMu32_ZMMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, zmmword [rdx]"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0xca], "vcvtne2ps2bf16 zmm1, zmm0, zmm2"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x0a], "v4fmaddps zmm1, zmm0, xmmword [rdx]"); // V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x0a], "v4fnmaddps zmm1, zmm0, xmmword [rdx]"); // V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x52, 0x0a], "vp4dpwssd zmm1{k5}, zmm0, xmmword [rdx]"); // VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x53, 0x0a], "vp4dpwssds zmm1{k5}, zmm0, xmmword [rdx]"); // VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmmword [rdx]"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmm2"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x9a, 0x0a], "v4fmaddps zmm1{k5}, zmm0, xmmword [rdx]"); // V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}, zmm0, xmmword [rdx]"); // V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x68, 0x0a], "vp2intersectd k1, zmm0, dword [rdx]{1to16}"); // VP2INTERSECTD_MASKmskw_ZMMu32_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, dword [rdx]{1to16}"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x5d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, dword [rdx]{1to16}"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmmword [rdx]"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmm2"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_XMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0x9d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, dword [rdx]{1to4}"); // VCVTNE2PS2BF16_XMMbf16_MASKmskw_XMMf32_MEMf32_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymmword [rdx]"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymm2"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_YMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x9b, 0x0a], "v4fmaddss xmm1{k5}{z}, xmm0, xmmword [rdx]"); // V4FMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0xab, 0x0a], "v4fnmaddss xmm1{k5}{z}, xmm0, xmmword [rdx]"); // V4FNMADDSS_XMMf32_MASKmskw_XMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xbd, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, dword [rdx]{1to8}"); // VCVTNE2PS2BF16_YMMbf16_MASKmskw_YMMf32_MEMf32_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x52, 0x0a], "vp4dpwssd zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VP4DPWSSD_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x53, 0x0a], "vp4dpwssds zmm1{k5}{z}, zmm0, xmmword [rdx]"); // VP4DPWSSDS_ZMMi32_MASKmskw_ZMMi16_MEMu32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmmword [rdx]"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmm2"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_ZMMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x9a, 0x0a], "v4fmaddps zmm1{k5}{z}, zmm0, xmmword [rdx]"); // V4FMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}{z}, zmm0, xmmword [rdx]"); // V4FNMADDPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [rdx]{1to16}"); // VCVTNE2PS2BF16_ZMMbf16_MASKmskw_ZMMf32_MEMf32_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x0a], "vp2intersectq k1, xmm0, xmmword [rdx]"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0xca], "vp2intersectq k1, xmm0, xmm2"); // VP2INTERSECTQ_MASKmskw_XMMu64_XMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x0a], "vp2intersectq k1, xmm0, qword [rdx]{1to2}"); // VP2INTERSECTQ_MASKmskw_XMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x0a], "vp2intersectq k1, ymm0, ymmword [rdx]"); // VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0xca], "vp2intersectq k1, ymm0, ymm2"); // VP2INTERSECTQ_MASKmskw_YMMu64_YMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x38, 0x68, 0x0a], "vp2intersectq k1, ymm0, qword [rdx]{1to4}"); // VP2INTERSECTQ_MASKmskw_YMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0x0a], "vp2intersectq k1, zmm0, zmmword [rdx]"); // VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0xca], "vp2intersectq k1, zmm0, zmm2"); // VP2INTERSECTQ_MASKmskw_ZMMu64_ZMMu64_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf2, 0xff, 0x58, 0x68, 0x0a], "vp2intersectq k1, zmm0, qword [rdx]{1to8}"); // VP2INTERSECTQ_MASKmskw_ZMMu64_MEMu64_AVX512, extension: AVX512EVEX } #[test] fn tests_66_0f3a() { test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x0a, 0xcc], "vpermq ymm1, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}{z}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0xca, 0xcc], "vpermq ymm1, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}, ymm2, 0xcc"); // VPERMQ_YMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0x0a, 0xcc], "vpermq ymm1, ymmword [rdx], 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, ymmword [rdx], 0xcc"); // VPERMQ_YMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x00, 0x0a, 0xcc], "vpermq zmm1, qword [rdx]{1to8}, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}{z}, zmm2, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0xca, 0xcc], "vpermq zmm1, zmm2, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}, zmm2, 0xcc"); // VPERMQ_ZMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0x0a, 0xcc], "vpermq zmm1, zmmword [rdx], 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, zmmword [rdx], 0xcc"); // VPERMQ_ZMMu64_MASKmskw_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x01, 0x0a, 0xcc], "vpermpd ymm1, qword [rdx]{1to4}, 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}{z}, ymm2, 0xcc"); // VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0xca, 0xcc], "vpermpd ymm1, ymm2, 0xcc"); // VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}, ymm2, 0xcc"); // VPERMPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0x0a, 0xcc], "vpermpd ymm1, ymmword [rdx], 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, ymmword [rdx], 0xcc"); // VPERMPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x01, 0x0a, 0xcc], "vpermpd zmm1, qword [rdx]{1to8}, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}{z}, zmm2, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0xca, 0xcc], "vpermpd zmm1, zmm2, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}, zmm2, 0xcc"); // VPERMPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0x0a, 0xcc], "vpermpd zmm1, zmmword [rdx], 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, zmmword [rdx], 0xcc"); // VPERMPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0xca, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0xca, 0xcc], "valignq ymm1, ymm0, ymm2, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0xca, 0xcc], "valignq ymm1{k5}, ymm0, ymm2, 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, ymmword [rdx], 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VALIGNQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0xca, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0xca, 0xcc], "valignd ymm1, ymm0, ymm2, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0xca, 0xcc], "valignd ymm1{k5}, ymm0, ymm2, 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, ymmword [rdx], 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VALIGND_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0xca, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0xca, 0xcc], "valignq zmm1, zmm0, zmm2, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0xca, 0xcc], "valignq zmm1{k5}, zmm0, zmm2, 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, zmmword [rdx], 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VALIGNQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0xca, 0xcc], "valignq xmm1, xmm0, xmm2, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}, xmm0, xmm2, 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, xmmword [rdx], 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VALIGNQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0xca, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0xca, 0xcc], "valignd zmm1, zmm0, zmm2, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0xca, 0xcc], "valignd zmm1{k5}, zmm0, zmm2, 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, zmmword [rdx], 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VALIGND_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0xca, 0xcc], "valignd xmm1, xmm0, xmm2, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}, xmm0, xmm2, 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, xmmword [rdx], 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VALIGND_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x0a, 0xcc], "vpermilps ymm1, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}{z}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0xca, 0xcc], "vpermilps ymm1, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}, ymm2, 0xcc"); // VPERMILPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0x0a, 0xcc], "vpermilps ymm1, ymmword [rdx], 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, ymmword [rdx], 0xcc"); // VPERMILPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x04, 0x0a, 0xcc], "vpermilps zmm1, dword [rdx]{1to16}, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, dword [rdx]{1to16}, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x04, 0x0a, 0xcc], "vpermilps xmm1, dword [rdx]{1to4}, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, dword [rdx]{1to4}, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}{z}, zmm2, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0xca, 0xcc], "vpermilps zmm1, zmm2, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}, zmm2, 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0x0a, 0xcc], "vpermilps zmm1, zmmword [rdx], 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, zmmword [rdx], 0xcc"); // VPERMILPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}{z}, xmm2, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0xca, 0xcc], "vpermilps xmm1, xmm2, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}, xmm2, 0xcc"); // VPERMILPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0x0a, 0xcc], "vpermilps xmm1, xmmword [rdx], 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, xmmword [rdx], 0xcc"); // VPERMILPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, qword [rdx]{1to4}, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}{z}, ymm2, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0xca, 0xcc], "vpermilpd ymm1, ymm2, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}, ymm2, 0xcc"); // VPERMILPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, ymmword [rdx], 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, ymmword [rdx], 0xcc"); // VPERMILPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, qword [rdx]{1to8}, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, qword [rdx]{1to2}, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, qword [rdx]{1to2}, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, qword [rdx]{1to2}, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}{z}, zmm2, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0xca, 0xcc], "vpermilpd zmm1, zmm2, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}, zmm2, 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, zmmword [rdx], 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, zmmword [rdx], 0xcc"); // VPERMILPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}{z}, xmm2, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0xca, 0xcc], "vpermilpd xmm1, xmm2, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}, xmm2, 0xcc"); // VPERMILPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, xmmword [rdx], 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, xmmword [rdx], 0xcc"); // VPERMILPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{sae}, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{sae}, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, dword [rdx]{1to8}, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}{z}, ymm2, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0xca, 0xcc], "vrndscaleps ymm1, ymm2, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}, ymm2, 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, ymmword [rdx], 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, ymmword [rdx], 0xcc"); // VRNDSCALEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, dword [rdx]{1to16}, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, dword [rdx]{1to16}, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, dword [rdx]{1to4}, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, dword [rdx]{1to4}, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0xca, 0xcc], "vrndscaleps zmm1, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}, zmm2, 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, zmmword [rdx], 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, zmmword [rdx], 0xcc"); // VRNDSCALEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}{z}, xmm2, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0xca, 0xcc], "vrndscaleps xmm1, xmm2, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}, xmm2, 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, xmmword [rdx], 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, xmmword [rdx], 0xcc"); // VRNDSCALEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{sae}, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{sae}, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, qword [rdx]{1to4}, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}{z}, ymm2, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0xca, 0xcc], "vrndscalepd ymm1, ymm2, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}, ymm2, 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, ymmword [rdx], 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, ymmword [rdx], 0xcc"); // VRNDSCALEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, qword [rdx]{1to8}, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, qword [rdx]{1to2}, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, qword [rdx]{1to2}, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, qword [rdx]{1to2}, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0xca, 0xcc], "vrndscalepd zmm1, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}, zmm2, 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, zmmword [rdx], 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, zmmword [rdx], 0xcc"); // VRNDSCALEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}{z}, xmm2, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0xca, 0xcc], "vrndscalepd xmm1, xmm2, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}, xmm2, 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, xmmword [rdx], 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, xmmword [rdx], 0xcc"); // VRNDSCALEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0xca, 0xcc], "vrndscaless xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VRNDSCALESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}, xmm0, xmm2, 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VRNDSCALESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0xca, 0xcc], "vpalignr ymm1, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}, ymm0, ymm2, 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x0a, 0xcc], "vpalignr ymm1, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPALIGNR_YMMu8_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0xca, 0xcc], "vpalignr zmm1, zmm0, zmm2, 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}, zmm0, zmm2, 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0x0a, 0xcc], "vpalignr zmm1, zmm0, zmmword [rdx], 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPALIGNR_ZMMu8_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0xca, 0xcc], "vpalignr xmm1, xmm0, xmm2, 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}, xmm0, xmm2, 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x0a, 0xcc], "vpalignr xmm1, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPALIGNR_XMMu8_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0xca, 0xcc], "vpextrb edx, xmm1, 0xcc"); // VPEXTRB_GPR32u8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x0a, 0xcc], "vpextrb byte [rdx], xmm1, 0xcc"); // VPEXTRB_MEMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0xca, 0xcc], "vpextrw edx, xmm1, 0xcc"); // VPEXTRW_GPR32u16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x0a, 0xcc], "vpextrw word [rdx], xmm1, 0xcc"); // VPEXTRW_MEMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0xca, 0xcc], "vpextrq rdx, xmm1, 0xcc"); // VPEXTRQ_GPR64u64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x0a, 0xcc], "vpextrq qword [rdx], xmm1, 0xcc"); // VPEXTRQ_MEMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0xca, 0xcc], "vpextrd edx, xmm1, 0xcc"); // VPEXTRD_GPR32u32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x16, 0x0a, 0xcc], "vpextrd dword [rdx], xmm1, 0xcc"); // VPEXTRD_MEMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0xca, 0xcc], "vextractps edx, xmm1, 0xcc"); // VEXTRACTPS_GPR32f32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x0a, 0xcc], "vextractps dword [rdx], xmm1, 0xcc"); // VEXTRACTPS_MEMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1, ymm0, xmm2, 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1, ymm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1, ymm0, xmm2, 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1, ymm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1, zmm0, xmm2, 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1, zmm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmmword [rdx], 0xcc"); // VINSERTF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1, zmm0, xmm2, 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1, zmm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmmword [rdx], 0xcc"); // VINSERTF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, ymm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, ymm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTF64X2_MEMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, ymm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, ymm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTF64X2_XMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [rdx], zmm1, 0xcc"); // VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF64X2_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, zmm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTF32X4_XMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx], zmm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF32X4_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymmword [rdx], 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1, zmm0, ymm2, 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1, zmm0, ymmword [rdx], 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymmword [rdx], 0xcc"); // VINSERTF64X4_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymmword [rdx], 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1, zmm0, ymm2, 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1, zmm0, ymmword [rdx], 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymmword [rdx], 0xcc"); // VINSERTF32X8_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2, zmm1, 0xcc"); // VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTF64X4_YMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF64X4_MEMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2, zmm1, 0xcc"); // VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_YMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTF32X8_MEMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{sae}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, ymm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, ymm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, ymm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx], ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [rdx]{k5}, ymm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}, zmm1, 0xcc"); // VCVTPS2PH_YMMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [rdx], zmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [rdx]{k5}, zmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, xmm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, xmm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, xmm1, 0xcc"); // VCVTPS2PH_XMMf16_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [rdx], xmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [rdx]{k5}, xmm1, 0xcc"); // VCVTPS2PH_MEMf16_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, qword [rdx]{1to4}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0xca, 0xcc], "vpcmpuq k1, ymm0, ymm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, dword [rdx]{1to8}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0xca, 0xcc], "vpcmpud k1, ymm0, ymm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, qword [rdx]{1to8}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, qword [rdx]{1to2}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0xca, 0xcc], "vpcmpuq k1, zmm0, zmm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0xca, 0xcc], "vpcmpuq k1, xmm0, xmm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPUQ_MASKmskw_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, dword [rdx]{1to16}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, dword [rdx]{1to4}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0xca, 0xcc], "vpcmpud k1, zmm0, zmm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0xca, 0xcc], "vpcmpud k1, xmm0, xmm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPUD_MASKmskw_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, qword [rdx]{1to4}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0xca, 0xcc], "vpcmpq k1, ymm0, ymm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_YMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_YMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, dword [rdx]{1to8}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0xca, 0xcc], "vpcmpd k1, ymm0, ymm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_YMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_YMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, qword [rdx]{1to8}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, qword [rdx]{1to2}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0xca, 0xcc], "vpcmpq k1, zmm0, zmm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_ZMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_ZMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0xca, 0xcc], "vpcmpq k1, xmm0, xmm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_XMMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPQ_MASKmskw_MASKmskw_XMMi64_MEMi64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, dword [rdx]{1to16}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, dword [rdx]{1to4}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0xca, 0xcc], "vpcmpd k1, zmm0, zmm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_ZMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_ZMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0xca, 0xcc], "vpcmpd k1, xmm0, xmm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_XMMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPD_MASKmskw_MASKmskw_XMMi32_MEMi32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0xca, 0xcc], "vpinsrb xmm1, xmm0, edx, 0xcc"); // VPINSRB_XMMu8_XMMu8_GPR32u8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x0a, 0xcc], "vpinsrb xmm1, xmm0, byte [rdx], 0xcc"); // VPINSRB_XMMu8_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0xca, 0xcc], "vinsertps xmm1, xmm0, xmm2, 0xcc"); // VINSERTPS_XMMf32_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x0a, 0xcc], "vinsertps xmm1, xmm0, dword [rdx], 0xcc"); // VINSERTPS_XMMf32_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0xca, 0xcc], "vpinsrq xmm1, xmm0, rdx, 0xcc"); // VPINSRQ_XMMu64_XMMu64_GPR64u64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x0a, 0xcc], "vpinsrq xmm1, xmm0, qword [rdx], 0xcc"); // VPINSRQ_XMMu64_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0xca, 0xcc], "vpinsrd xmm1, xmm0, edx, 0xcc"); // VPINSRD_XMMu32_XMMu32_GPR32u32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x22, 0x0a, 0xcc], "vpinsrd xmm1, xmm0, dword [rdx], 0xcc"); // VPINSRD_XMMu32_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1, ymm0, ymm2, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFF64X2_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1, ymm0, ymm2, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFF32X4_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1, zmm0, zmm2, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFF64X2_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1, zmm0, zmm2, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFF32X4_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0xca, 0xcc], "vpternlogq ymm1, ymm0, ymm2, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymm2, 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0xca, 0xcc], "vpternlogd ymm1, ymm0, ymm2, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymm2, 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPTERNLOGD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0xca, 0xcc], "vpternlogq zmm1, zmm0, zmm2, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmm2, 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0xca, 0xcc], "vpternlogq xmm1, xmm0, xmm2, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmm2, 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0xca, 0xcc], "vpternlogd zmm1, zmm0, zmm2, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmm2, 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPTERNLOGD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0xca, 0xcc], "vpternlogd xmm1, xmm0, xmm2, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmm2, 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPTERNLOGD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{sae}, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{sae}, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, qword [rdx]{1to4}, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}{z}, ymm2, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0xca, 0xcc], "vgetmantpd ymm1, ymm2, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}, ymm2, 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, ymmword [rdx], 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, ymmword [rdx], 0xcc"); // VGETMANTPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x26, 0xca, 0xcc], "vgetmantps zmm1{sae}, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{sae}, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, dword [rdx]{1to8}, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}{z}, ymm2, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0xca, 0xcc], "vgetmantps ymm1, ymm2, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}, ymm2, 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, ymmword [rdx], 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, ymmword [rdx], 0xcc"); // VGETMANTPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, qword [rdx]{1to8}, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, qword [rdx]{1to2}, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, qword [rdx]{1to2}, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, qword [rdx]{1to2}, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0xca, 0xcc], "vgetmantpd zmm1, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}, zmm2, 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, zmmword [rdx], 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, zmmword [rdx], 0xcc"); // VGETMANTPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}{z}, xmm2, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0xca, 0xcc], "vgetmantpd xmm1, xmm2, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}, xmm2, 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, xmmword [rdx], 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, xmmword [rdx], 0xcc"); // VGETMANTPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, dword [rdx]{1to16}, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, dword [rdx]{1to16}, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, dword [rdx]{1to4}, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, dword [rdx]{1to4}, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0xca, 0xcc], "vgetmantps zmm1, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}, zmm2, 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, zmmword [rdx], 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, zmmword [rdx], 0xcc"); // VGETMANTPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}{z}, xmm2, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0xca, 0xcc], "vgetmantps xmm1, xmm2, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}, xmm2, 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, xmmword [rdx], 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, xmmword [rdx], 0xcc"); // VGETMANTPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0xca, 0xcc], "vgetmantsd xmm1, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}, xmm0, xmm2, 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1, xmm0, qword [rdx], 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VGETMANTSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x27, 0xca, 0xcc], "vgetmantss xmm1{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0xca, 0xcc], "vgetmantss xmm1, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}, xmm0, xmm2, 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0x0a, 0xcc], "vgetmantss xmm1, xmm0, dword [rdx], 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VGETMANTSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1, ymm0, xmm2, 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1, ymm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1, ymm0, xmm2, 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1, ymm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1, zmm0, xmm2, 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1, zmm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmmword [rdx], 0xcc"); // VINSERTI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1, zmm0, xmm2, 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1, zmm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmmword [rdx], 0xcc"); // VINSERTI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, ymm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, ymm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTI64X2_MEMu64_MASKmskw_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, ymm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, ymm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, ymm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [rdx], ymm1, 0xcc"); // VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [rdx]{k5}, ymm1, 0xcc"); // VEXTRACTI32X4_MEMu32_MASKmskw_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, zmm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTI64X2_XMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [rdx], zmm1, 0xcc"); // VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTI64X2_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, zmm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, zmm1, 0xcc"); // VEXTRACTI32X4_XMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [rdx], zmm1, 0xcc"); // VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTI32X4_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymmword [rdx], 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1, zmm0, ymm2, 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1, zmm0, ymmword [rdx], 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymmword [rdx], 0xcc"); // VINSERTI64X4_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymmword [rdx], 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1, zmm0, ymm2, 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1, zmm0, ymmword [rdx], 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymmword [rdx], 0xcc"); // VINSERTI32X8_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2, zmm1, 0xcc"); // VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTI64X4_YMMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTI64X4_MEMu64_MASKmskw_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}{z}, zmm1, 0xcc"); // VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2, zmm1, 0xcc"); // VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}, zmm1, 0xcc"); // VEXTRACTI32X8_YMMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [rdx], zmm1, 0xcc"); // VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [rdx]{k5}, zmm1, 0xcc"); // VEXTRACTI32X8_MEMu32_MASKmskw_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0xca, 0xcc], "vpcmpuw k1, ymm0, ymm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0xca, 0xcc], "vpcmpub k1, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpub k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0xca, 0xcc], "vpcmpuw k1, zmm0, zmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0xca, 0xcc], "vpcmpuw k1, xmm0, xmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPUW_MASKmskw_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0xca, 0xcc], "vpcmpub k1, zmm0, zmm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpub k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0xca, 0xcc], "vpcmpub k1, xmm0, xmm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpub k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPUB_MASKmskw_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0xca, 0xcc], "vpcmpw k1, ymm0, ymm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_YMMi16_YMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpw k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_YMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0xca, 0xcc], "vpcmpb k1, ymm0, ymm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, ymm0, ymm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_YMMi8_YMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpb k1, ymm0, ymmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_YMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0xca, 0xcc], "vpcmpw k1, zmm0, zmm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_ZMMi16_ZMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpw k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_ZMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0xca, 0xcc], "vpcmpw k1, xmm0, xmm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPW_MASKmskw_MASKmskw_XMMi16_XMMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpw k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPW_MASKmskw_MASKmskw_XMMi16_MEMi16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0xca, 0xcc], "vpcmpb k1, zmm0, zmm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, zmm0, zmm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_ZMMi8_ZMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpb k1, zmm0, zmmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_ZMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0xca, 0xcc], "vpcmpb k1, xmm0, xmm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, xmm0, xmm2, 0xcc"); // VPCMPB_MASKmskw_MASKmskw_XMMi8_XMMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpb k1, xmm0, xmmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPCMPB_MASKmskw_MASKmskw_XMMi8_MEMi8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymm2, 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_YMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VDBPSADBW_YMMu16_MASKmskw_YMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1, zmm0, zmm2, 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmm2, 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_ZMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1, zmm0, zmmword [rdx], 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VDBPSADBW_ZMMu16_MASKmskw_ZMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1, xmm0, xmm2, 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmm2, 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_XMMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1, xmm0, xmmword [rdx], 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VDBPSADBW_XMMu16_MASKmskw_XMMu8_MEMu8_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1, ymm0, ymm2, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFI64X2_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1, ymm0, ymm2, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, ymmword [rdx], 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VSHUFI32X4_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1, zmm0, zmm2, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI64X2_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1, zmm0, zmm2, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VSHUFI32X4_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0xca, 0xcc], "vpclmulqdq ymm1, ymm0, ymm2, 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x0a, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPCLMULQDQ_YMMu128_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0xca, 0xcc], "vpclmulqdq zmm1, zmm0, zmm2, 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x0a, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPCLMULQDQ_ZMMu128_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0xca, 0xcc], "vpclmulqdq xmm1, xmm0, xmm2, 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x0a, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPCLMULQDQ_XMMu128_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x50, 0xca, 0xcc], "vrangepd zmm1{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0xca, 0xcc], "vrangepd ymm1, ymm0, ymm2, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}, ymm0, ymm2, 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, ymmword [rdx], 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VRANGEPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x50, 0xca, 0xcc], "vrangeps zmm1{sae}, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0xca, 0xcc], "vrangeps ymm1, ymm0, ymm2, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}, ymm0, ymm2, 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, ymmword [rdx], 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VRANGEPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0xca, 0xcc], "vrangepd zmm1, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}, zmm0, zmm2, 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, zmmword [rdx], 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VRANGEPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0xca, 0xcc], "vrangepd xmm1, xmm0, xmm2, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}, xmm0, xmm2, 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, xmmword [rdx], 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VRANGEPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0xca, 0xcc], "vrangeps zmm1, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}, zmm0, zmm2, 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, zmmword [rdx], 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VRANGEPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0xca, 0xcc], "vrangeps xmm1, xmm0, xmm2, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}, xmm0, xmm2, 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, xmmword [rdx], 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VRANGEPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x51, 0xca, 0xcc], "vrangesd xmm1{sae}, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0xca, 0xcc], "vrangesd xmm1, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}, xmm0, xmm2, 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0x0a, 0xcc], "vrangesd xmm1, xmm0, qword [rdx], 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VRANGESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x51, 0xca, 0xcc], "vrangess xmm1{sae}, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0xca, 0xcc], "vrangess xmm1, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}, xmm0, xmm2, 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0x0a, 0xcc], "vrangess xmm1, xmm0, dword [rdx], 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VRANGESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1, ymm0, ymm2, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymm2, 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPD_YMMf64_MASKmskw_YMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0xca, 0xcc], "vfixupimmps ymm1, ymm0, ymm2, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymm2, 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VFIXUPIMMPS_YMMf32_MASKmskw_YMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPD_ZMMf64_MASKmskw_ZMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1, xmm0, xmm2, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmm2, 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0xca, 0xcc], "vfixupimmps zmm1, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmm2, 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VFIXUPIMMPS_ZMMf32_MASKmskw_ZMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0xca, 0xcc], "vfixupimmps xmm1, xmm0, xmm2, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmm2, 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VFIXUPIMMPS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1, xmm0, qword [rdx], 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VFIXUPIMMSD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0xca, 0xcc], "vfixupimmss xmm1, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}, xmm0, xmm2, 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1, xmm0, dword [rdx], 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VFIXUPIMMSS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x56, 0xca, 0xcc], "vreducepd zmm1{sae}, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{sae}, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, qword [rdx]{1to4}, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x56, 0x0a, 0xcc], "vreducepd ymm1, qword [rdx]{1to4}, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, qword [rdx]{1to4}, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}{z}, ymm2, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0xca, 0xcc], "vreducepd ymm1, ymm2, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}, ymm2, 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0x0a, 0xcc], "vreducepd ymm1, ymmword [rdx], 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, ymmword [rdx], 0xcc"); // VREDUCEPD_YMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}{sae}, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x56, 0xca, 0xcc], "vreduceps zmm1{sae}, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{sae}, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, dword [rdx]{1to8}, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x56, 0x0a, 0xcc], "vreduceps ymm1, dword [rdx]{1to8}, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, dword [rdx]{1to8}, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}{z}, ymm2, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, ymmword [rdx], 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0xca, 0xcc], "vreduceps ymm1, ymm2, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}, ymm2, 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0x0a, 0xcc], "vreduceps ymm1, ymmword [rdx], 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, ymmword [rdx], 0xcc"); // VREDUCEPS_YMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, qword [rdx]{1to8}, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x56, 0x0a, 0xcc], "vreducepd zmm1, qword [rdx]{1to8}, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, qword [rdx]{1to8}, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, qword [rdx]{1to2}, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x56, 0x0a, 0xcc], "vreducepd xmm1, qword [rdx]{1to2}, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, qword [rdx]{1to2}, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0xca, 0xcc], "vreducepd zmm1, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}, zmm2, 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0x0a, 0xcc], "vreducepd zmm1, zmmword [rdx], 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, zmmword [rdx], 0xcc"); // VREDUCEPD_ZMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}{z}, xmm2, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0xca, 0xcc], "vreducepd xmm1, xmm2, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}, xmm2, 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0x0a, 0xcc], "vreducepd xmm1, xmmword [rdx], 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, xmmword [rdx], 0xcc"); // VREDUCEPD_XMMf64_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, dword [rdx]{1to16}, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x56, 0x0a, 0xcc], "vreduceps zmm1, dword [rdx]{1to16}, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, dword [rdx]{1to16}, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, dword [rdx]{1to4}, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x56, 0x0a, 0xcc], "vreduceps xmm1, dword [rdx]{1to4}, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, dword [rdx]{1to4}, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, zmmword [rdx], 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0xca, 0xcc], "vreduceps zmm1, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}, zmm2, 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0x0a, 0xcc], "vreduceps zmm1, zmmword [rdx], 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, zmmword [rdx], 0xcc"); // VREDUCEPS_ZMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}{z}, xmm2, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, xmmword [rdx], 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0xca, 0xcc], "vreduceps xmm1, xmm2, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}, xmm2, 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0x0a, 0xcc], "vreduceps xmm1, xmmword [rdx], 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, xmmword [rdx], 0xcc"); // VREDUCEPS_XMMf32_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x57, 0xca, 0xcc], "vreducesd xmm1{sae}, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, qword [rdx], 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0xca, 0xcc], "vreducesd xmm1, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}, xmm0, xmm2, 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0x0a, 0xcc], "vreducesd xmm1, xmm0, qword [rdx], 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}, xmm0, qword [rdx], 0xcc"); // VREDUCESD_XMMf64_MASKmskw_XMMf64_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x57, 0xca, 0xcc], "vreducess xmm1{sae}, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}{z}, xmm0, dword [rdx], 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0xca, 0xcc], "vreducess xmm1, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}, xmm0, xmm2, 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0x0a, 0xcc], "vreducess xmm1, xmm0, dword [rdx], 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}, xmm0, dword [rdx], 0xcc"); // VREDUCESS_XMMf32_MASKmskw_XMMf32_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [rdx]{1to4}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0xca, 0xcc], "vfpclasspd k1, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, ymm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_YMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x0a, 0xcc], "vfpclasspd k1, ymmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, ymmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [rdx]{1to8}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [rdx]{1to8}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0xca, 0xcc], "vfpclassps k1, ymm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, ymm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_YMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0x0a, 0xcc], "vfpclassps k1, ymmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, ymmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL256, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [rdx]{1to8}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [rdx]{1to8}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [rdx]{1to2}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [rdx]{1to2}, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0xca, 0xcc], "vfpclasspd k1, zmm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, zmm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_ZMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0x0a, 0xcc], "vfpclasspd k1, zmmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, zmmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0xca, 0xcc], "vfpclasspd k1, xmm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, xmm2, 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0x0a, 0xcc], "vfpclasspd k1, xmmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, xmmword [rdx], 0xcc"); // VFPCLASSPD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [rdx]{1to16}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [rdx]{1to16}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [rdx]{1to4}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [rdx]{1to4}, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0xca, 0xcc], "vfpclassps k1, zmm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, zmm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_ZMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0x0a, 0xcc], "vfpclassps k1, zmmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, zmmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0xca, 0xcc], "vfpclassps k1, xmm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, xmm2, 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0x0a, 0xcc], "vfpclassps k1, xmmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, xmmword [rdx], 0xcc"); // VFPCLASSPS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512_VL128, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0xca, 0xcc], "vfpclasssd k1, xmm2, 0xcc"); // VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0xca, 0xcc], "vfpclasssd k1{k5}, xmm2, 0xcc"); // VFPCLASSSD_MASKmskw_MASKmskw_XMMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0x0a, 0xcc], "vfpclasssd k1, qword [rdx], 0xcc"); // VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0x0a, 0xcc], "vfpclasssd k1{k5}, qword [rdx], 0xcc"); // VFPCLASSSD_MASKmskw_MASKmskw_MEMf64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0xca, 0xcc], "vfpclassss k1, xmm2, 0xcc"); // VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0xca, 0xcc], "vfpclassss k1{k5}, xmm2, 0xcc"); // VFPCLASSSS_MASKmskw_MASKmskw_XMMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0x0a, 0xcc], "vfpclassss k1, dword [rdx], 0xcc"); // VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0x0a, 0xcc], "vfpclassss k1{k5}, dword [rdx], 0xcc"); // VFPCLASSSS_MASKmskw_MASKmskw_MEMf32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0xca, 0xcc], "vpshldw ymm1, ymm0, ymm2, 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0x0a, 0xcc], "vpshldw ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0xca, 0xcc], "vpshldw zmm1, zmm0, zmm2, 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0x0a, 0xcc], "vpshldw zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0xca, 0xcc], "vpshldw xmm1, xmm0, xmm2, 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0x0a, 0xcc], "vpshldw xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0xca, 0xcc], "vpshldq ymm1, ymm0, ymm2, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0xca, 0xcc], "vpshldd ymm1, ymm0, ymm2, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHLDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0xca, 0xcc], "vpshldq zmm1, zmm0, zmm2, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0xca, 0xcc], "vpshldq xmm1, xmm0, xmm2, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0xca, 0xcc], "vpshldd zmm1, zmm0, zmm2, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHLDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0xca, 0xcc], "vpshldd xmm1, xmm0, xmm2, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHLDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vpshrdw ymm1, ymm0, ymm2, 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_YMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vpshrdw ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDW_YMMu16_MASKmskw_YMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vpshrdw zmm1, zmm0, zmm2, 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_ZMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vpshrdw zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDW_ZMMu16_MASKmskw_ZMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vpshrdw xmm1, xmm0, xmm2, 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_XMMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vpshrdw xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDW_XMMu16_MASKmskw_XMMu16_MEMu16_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0xca, 0xcc], "vpshrdq ymm1, ymm0, ymm2, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDQ_YMMu64_MASKmskw_YMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, dword [rdx]{1to8}, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0xca, 0xcc], "vpshrdd ymm1, ymm0, ymm2, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymm2, 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_YMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, ymmword [rdx], 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VPSHRDD_YMMu32_MASKmskw_YMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0xca, 0xcc], "vpshrdq zmm1, zmm0, zmm2, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDQ_ZMMu64_MASKmskw_ZMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0xca, 0xcc], "vpshrdq xmm1, xmm0, xmm2, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDQ_XMMu64_MASKmskw_XMMu64_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, dword [rdx]{1to16}, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, dword [rdx]{1to4}, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0xca, 0xcc], "vpshrdd zmm1, zmm0, zmm2, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmm2, 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_ZMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, zmmword [rdx], 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VPSHRDD_ZMMu32_MASKmskw_ZMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0xca, 0xcc], "vpshrdd xmm1, xmm0, xmm2, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmm2, 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_XMMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, xmmword [rdx], 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VPSHRDD_XMMu32_MASKmskw_XMMu32_MEMu32_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, qword [rdx]{1to4}, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymm2, 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_YMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_YMMu8_MASKmskw_YMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, qword [rdx]{1to8}, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, qword [rdx]{1to2}, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmm2, 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_ZMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_ZMMu8_MASKmskw_ZMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmm2, 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_XMMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmmword [rdx], 0xcc"); // VGF2P8AFFINEINVQB_XMMu8_MASKmskw_XMMu8_MEMu64_IMM8_AVX512, extension: AVX512EVEX } yaxpeax-x86-1.2.2/test/long_mode/mod.rs000064400000000000000000007007771046102023000160210ustar 00000000000000extern crate rand; mod regspec; mod operand; mod opcode; #[cfg(feature="fmt")] mod display; #[cfg(feature="std")] mod descriptions; mod evex_generated; mod reuse_test; use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, LengthedInstruction}; use yaxpeax_x86::long_mode::InstDecoder; fn test_invalid(data: &[u8]) { test_invalid_under(&InstDecoder::default(), data); } fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) { let mut reader = yaxpeax_arch::U8Reader::new(data); if let Ok(inst) = decoder.decode(&mut reader) { // realistically, the chances an error only shows up under non-fmt builds seems unlikely, // but try to report *something* in such cases. cfg_if::cfg_if! { if #[cfg(feature="fmt")] { panic!("decoded {:?} from {:02x?} under decoder {}", inst.opcode(), data, decoder); } else { // don't warn about the unused inst here let _ = inst; panic!("decoded instruction from {:02x?} under decoder ", data); } } } else { // this is fine } } fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), data, expected); } fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { let text = format!("{}", instr); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); } else { eprintln!("non-fmt build cannot compare text equality") } } // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u64.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } #[test] fn test_modrm_decode() { // just modrm test_display(&[0x33, 0x08], "xor ecx, dword [rax]"); test_display(&[0x33, 0x20], "xor esp, dword [rax]"); test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor eax, dword [rip + 0x12345678]"); test_display(&[0x33, 0x41, 0x23], "xor eax, dword [rcx + 0x23]"); test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor eax, dword [rcx + 0x43650123]"); test_display(&[0x33, 0xc1], "xor eax, ecx"); // modrm + rex.w test_display(&[0x48, 0x33, 0x08], "xor rcx, qword [rax]"); test_display(&[0x48, 0x33, 0x20], "xor rsp, qword [rax]"); test_display(&[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor rax, qword [rip + 0x12345678]"); test_display(&[0x48, 0x33, 0x41, 0x23], "xor rax, qword [rcx + 0x23]"); test_display(&[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor rax, qword [rcx + 0x43650123]"); test_display(&[0x48, 0x33, 0xc1], "xor rax, rcx"); // modrm + rex.r test_display(&[0x44, 0x33, 0x08], "xor r9d, dword [rax]"); test_display(&[0x44, 0x33, 0x20], "xor r12d, dword [rax]"); test_display(&[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, dword [rip + 0x12345678]"); test_display(&[0x44, 0x33, 0x41, 0x23], "xor r8d, dword [rcx + 0x23]"); test_display(&[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, dword [rcx + 0x43650123]"); test_display(&[0x44, 0x33, 0xc1], "xor r8d, ecx"); // modrm + rex.rb test_display(&[0x45, 0x33, 0x08], "xor r9d, dword [r8]"); test_display(&[0x45, 0x33, 0x20], "xor r12d, dword [r8]"); test_display(&[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor r8d, dword [rip + 0x12345678]"); test_display(&[0x45, 0x33, 0x41, 0x23], "xor r8d, dword [r9 + 0x23]"); test_display(&[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor r8d, dword [r9 + 0x43650123]"); test_display(&[0x45, 0x33, 0xc1], "xor r8d, r9d"); // sib test_display(&[0x33, 0x04, 0x0a], "xor eax, dword [rdx + rcx * 1]"); test_display(&[0x33, 0x04, 0x4a], "xor eax, dword [rdx + rcx * 2]"); test_display(&[0x33, 0x04, 0x8a], "xor eax, dword [rdx + rcx * 4]"); test_display(&[0x33, 0x04, 0xca], "xor eax, dword [rdx + rcx * 8]"); test_display(&[0x33, 0x04, 0x20], "xor eax, dword [rax]"); test_display(&[0x33, 0x04, 0x60], "xor eax, dword [rax]"); test_display(&[0x33, 0x04, 0xa0], "xor eax, dword [rax]"); test_display(&[0x33, 0x04, 0xe0], "xor eax, dword [rax]"); test_display(&[0x42, 0x33, 0x04, 0x20], "xor eax, dword [rax + r12 * 1]"); test_display(&[0x42, 0x33, 0x04, 0x60], "xor eax, dword [rax + r12 * 2]"); test_display(&[0x42, 0x33, 0x04, 0xa0], "xor eax, dword [rax + r12 * 4]"); test_display(&[0x42, 0x33, 0x04, 0xe0], "xor eax, dword [rax + r12 * 8]"); test_display(&[0x43, 0x33, 0x04, 0x20], "xor eax, dword [r8 + r12 * 1]"); test_display(&[0x43, 0x33, 0x04, 0x60], "xor eax, dword [r8 + r12 * 2]"); test_display(&[0x43, 0x33, 0x04, 0xa0], "xor eax, dword [r8 + r12 * 4]"); test_display(&[0x43, 0x33, 0x04, 0xe0], "xor eax, dword [r8 + r12 * 8]"); test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); test_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); test_display(&[0x33, 0x44, 0x65, 0x11], "xor eax, dword [rbp + 0x11]"); test_display(&[0x41, 0x33, 0x44, 0x65, 0x11], "xor eax, dword [r13 + 0x11]"); test_display(&[0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [rbp + 0x44332211]"); test_display(&[0x41, 0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [r13 + 0x44332211]"); test_display(&[0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); test_display(&[0x41, 0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); // specifically sib with base == 0b101 // mod bits 00 test_display(&[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]"); test_display(&[0x43, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r12 * 1 + 0x50403020]"); // mod bits 01 test_display(&[0x42, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [rbp + r12 * 1 + 0x20]"); test_display(&[0x43, 0x33, 0x74, 0x25, 0x20], "xor esi, dword [r13 + r12 * 1 + 0x20]"); // mod bits 10 test_display(&[0x42, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [rbp + r12 * 1 + 0x50403020]"); test_display(&[0x43, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [r13 + r12 * 1 + 0x50403020]"); } #[test] fn test_mmx() { test_display(&[0x4f, 0x0f, 0xf7, 0xc1], "maskmovq mm0, mm1"); test_display(&[0x0f, 0xf7, 0xc1], "maskmovq mm0, mm1"); test_invalid(&[0x0f, 0xf7, 0x01]); test_display(&[0x4f, 0x0f, 0xe7, 0x03], "movntq qword [r11], mm0"); test_display(&[0x0f, 0xe7, 0x03], "movntq qword [rbx], mm0"); test_invalid(&[0x0f, 0xe7, 0xc3]); test_display(&[0x4f, 0x0f, 0xc3, 0x03], "movnti qword [r11], r8"); test_invalid(&[0x66, 0x0f, 0xc3, 0x03]); test_display(&[0x0f, 0xc3, 0x03], "movnti dword [rbx], eax"); test_invalid(&[0x0f, 0xc3, 0xc3]); test_display(&[0x4f, 0x0f, 0x7e, 0xcf], "movd r15, mm1"); test_display(&[0x41, 0x0f, 0x7e, 0xcf], "movd r15d, mm1"); test_display(&[0x4f, 0x0f, 0x7f, 0xcf], "movq mm7, mm1"); test_display(&[0x4f, 0x0f, 0x7f, 0x0f], "movq qword [r15], mm1"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, eax, 0x14"); test_display(&[0x4f, 0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, r8d, 0x14"); test_display(&[0x4f, 0x0f, 0xc4, 0x00, 0x14], "pinsrw mm0, word [r8], 0x14"); test_display(&[0x4f, 0x0f, 0xd1, 0xcf], "psrlw mm1, mm7"); test_display(&[0x4f, 0x0f, 0xd1, 0x00], "psrlw mm0, qword [r8]"); test_invalid(&[0x4f, 0x0f, 0xd7, 0x00]); test_display(&[0x4f, 0x0f, 0xd7, 0xcf], "pmovmskb r9d, mm7"); test_display(&[0x0f, 0x3a, 0x0f, 0xc1, 0x23], "palignr mm0, mm1, 0x23"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfd, 0xd2], "paddw mm2, mm2"); test_display(&[0x0f, 0x6f, 0xe9], "movq mm5, mm1"); test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw mm7, qword [rip + 0x77ccbbaa]"); test_display(&[0x0f, 0x38, 0x00, 0xda], "pshufb mm3, mm2"); test_display(&[0x0f, 0x74, 0xc2], "pcmpeqb mm0, mm2"); test_display(&[0x0f, 0x75, 0xc2], "pcmpeqw mm0, mm2"); test_display(&[0x0f, 0x76, 0xc2], "pcmpeqd mm0, mm2"); test_display(&[0x66, 0x0f, 0xc5, 0xd8, 0xff], "pextrw ebx, xmm0, 0xff"); test_invalid(&[0x66, 0x0f, 0xc5, 0x08, 0xff]); test_display(&[0x0f, 0xc5, 0xd1, 0x00], "pextrw edx, mm1, 0x0"); test_invalid(&[0x0f, 0xc5, 0x01, 0x00]); test_display(&[0x0f, 0xd8, 0xc2], "psubusb mm0, mm2"); test_display(&[0x0f, 0xd9, 0xc2], "psubusw mm0, mm2"); test_display(&[0x0f, 0xda, 0xc2], "pminub mm0, mm2"); test_display(&[0x0f, 0xdb, 0xc2], "pand mm0, mm2"); test_display(&[0x0f, 0xdc, 0xc2], "paddusb mm0, mm2"); test_display(&[0x0f, 0xdd, 0xc2], "paddusw mm0, mm2"); test_display(&[0x0f, 0xde, 0xc2], "pmaxub mm0, mm2"); test_display(&[0x0f, 0xdf, 0xc2], "pandn mm0, mm2"); test_display(&[0x0f, 0xe8, 0xc2], "psubsb mm0, mm2"); test_display(&[0x0f, 0xe9, 0xc2], "psubsw mm0, mm2"); test_display(&[0x0f, 0xea, 0xc2], "pminsw mm0, mm2"); test_display(&[0x0f, 0xeb, 0xc2], "por mm0, mm2"); test_display(&[0x0f, 0xec, 0xc2], "paddsb mm0, mm2"); test_display(&[0x0f, 0xed, 0xc2], "paddsw mm0, mm2"); test_display(&[0x0f, 0xee, 0xc2], "pmaxsw mm0, mm2"); test_display(&[0x0f, 0xef, 0xc2], "pxor mm0, mm2"); test_invalid(&[0x0f, 0xf0, 0xc2]); test_display(&[0x0f, 0xf1, 0xc2], "psllw mm0, mm2"); test_display(&[0x0f, 0xf2, 0xc2], "pslld mm0, mm2"); test_display(&[0x0f, 0xf3, 0xc2], "psllq mm0, mm2"); test_display(&[0x0f, 0xf4, 0xc2], "pmuludq mm0, mm2"); test_display(&[0x0f, 0xf5, 0xc2], "pmaddwd mm0, mm2"); test_display(&[0x0f, 0xf6, 0xc2], "psadbw mm0, mm2"); test_display(&[0x0f, 0xf8, 0xc2], "psubb mm0, mm2"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfa, 0xc2], "psubd mm0, mm2"); test_display(&[0x0f, 0xfb, 0xc2], "psubq mm0, mm2"); test_display(&[0x0f, 0xfc, 0xc2], "paddb mm0, mm2"); test_display(&[0x0f, 0xfd, 0xc2], "paddw mm0, mm2"); test_display(&[0x0f, 0xfe, 0xc2], "paddd mm0, mm2"); test_display(&[0x0f, 0xf1, 0x02], "psllw mm0, qword [rdx]"); test_display(&[0x0f, 0xf2, 0x02], "pslld mm0, qword [rdx]"); test_display(&[0x0f, 0xf3, 0x02], "psllq mm0, qword [rdx]"); test_display(&[0x0f, 0xf4, 0x02], "pmuludq mm0, qword [rdx]"); test_display(&[0x0f, 0xf5, 0x02], "pmaddwd mm0, qword [rdx]"); test_display(&[0x0f, 0xf6, 0x02], "psadbw mm0, qword [rdx]"); test_display(&[0x0f, 0xf8, 0x02], "psubb mm0, qword [rdx]"); test_display(&[0x0f, 0xf9, 0x02], "psubw mm0, qword [rdx]"); test_display(&[0x0f, 0xfa, 0x02], "psubd mm0, qword [rdx]"); test_display(&[0x0f, 0xfb, 0x02], "psubq mm0, qword [rdx]"); test_display(&[0x0f, 0xfc, 0x02], "paddb mm0, qword [rdx]"); test_display(&[0x0f, 0xfd, 0x02], "paddw mm0, qword [rdx]"); test_display(&[0x0f, 0xfe, 0x02], "paddd mm0, qword [rdx]"); } #[test] fn test_cvt() { test_display(&[0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm7"); test_display(&[0x48, 0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm7"); test_display(&[0x4f, 0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm15"); test_display(&[0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2ps xmm9, mm7"); test_display(&[0x4f, 0x0f, 0x2a, 0x00], "cvtpi2ps xmm8, qword [r8]"); test_display(&[0x4f, 0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_display(&[0x66, 0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm9, mm7"); test_display(&[0x4f, 0xf3, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm1, edi"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm9, r15"); test_display(&[0x4f, 0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_display(&[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm9, r15"); test_display(&[0x4f, 0xf2, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm0, dword [rax]"); test_display(&[0xf2, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm8, qword [r8]"); test_display(&[0x4f, 0xf3, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm0, dword [rax]"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm8, qword [r8]"); test_display(&[0x4f, 0x66, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm0, dword [rax]"); test_display(&[0x66, 0x4f, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm8, qword [r8]"); } #[test] fn test_aesni() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_aesni(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdb, 0xcf], "aesimc xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdc, 0xcf], "aesenc xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdd, 0xcf], "aesenclast xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xde, 0xcf], "aesdec xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x38, 0xdf, 0xcf], "aesdeclast xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], "aeskeygenassist xmm1, xmmword [rdi], 0xaa"); test_instr(&[0x66, 0x4f, 0x0f, 0x3a, 0xdf, 0xcf, 0xaa], "aeskeygenassist xmm9, xmm15, 0xaa"); } #[test] fn test_sse2() { fn test_instr(bytes: &[u8], text: &'static str) { // sse and sse2 are part of amd64, so x86_64, meaning even the minimal decoder must support // them. test_display_under(&InstDecoder::minimal(), bytes, text); } test_instr(&[0xf2, 0x0f, 0x10, 0x0c, 0xc7], "movsd xmm1, qword [rdi + rax * 8]"); test_instr(&[0xf2, 0x0f, 0x11, 0x0c, 0xc7], "movsd qword [rdi + rax * 8], xmm1"); test_instr(&[0x66, 0x0f, 0x11, 0x0c, 0xc7], "movupd xmmword [rdi + rax * 8], xmm1"); test_instr(&[0x66, 0x4f, 0x0f, 0x12, 0x03], "movlpd xmm8, qword [r11]"); // reg-mem is movlpd test_instr(&[0x66, 0x4f, 0x0f, 0x13, 0x03], "movlpd qword [r11], xmm8"); test_invalid(&[0x66, 0x4f, 0x0f, 0x13, 0xc3]); test_instr(&[0x66, 0x4f, 0x0f, 0x14, 0x03], "unpcklpd xmm8, xmmword [r11]"); test_instr(&[0x66, 0x4f, 0x0f, 0x14, 0xc3], "unpcklpd xmm8, xmm11"); test_instr(&[0x66, 0x4f, 0x0f, 0x15, 0x03], "unpckhpd xmm8, xmmword [r11]"); test_instr(&[0x66, 0x4f, 0x0f, 0x15, 0xc3], "unpckhpd xmm8, xmm11"); test_instr(&[0x66, 0x4f, 0x0f, 0x16, 0x03], "movhpd xmm8, qword [r11]"); test_instr(&[0x66, 0x4f, 0x0f, 0x17, 0x03], "movhpd qword [r11], xmm8"); test_invalid(&[0x66, 0x4f, 0x0f, 0x17, 0xc3]); test_instr(&[0x66, 0x4f, 0x0f, 0x28, 0xd0], "movapd xmm10, xmm8"); test_instr(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm9, mm7"); test_instr(&[0x66, 0x4f, 0x0f, 0x2a, 0x0f], "cvtpi2pd xmm9, qword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm9, r15"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2a, 0x0f], "cvtsi2sd xmm9, qword [r15]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2b, 0x0f], "movntpd xmmword [r15], xmm9"); test_instr(&[0x66, 0x4f, 0x0f, 0x2c, 0xcf], "cvttpd2pi mm1, xmm15"); test_instr(&[0x66, 0x4f, 0x0f, 0x2c, 0x0f], "cvttpd2pi mm1, xmmword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2c, 0xcf], "cvttsd2si r9, xmm15"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2c, 0x0f], "cvttsd2si r9, qword [r15]"); test_instr(&[0xf2, 0x40, 0x0f, 0x2c, 0xcf], "cvttsd2si ecx, xmm7"); test_instr(&[0xf2, 0x40, 0x0f, 0x2c, 0x0f], "cvttsd2si ecx, qword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2d, 0xcf], "cvtpd2pi mm1, xmm15"); test_instr(&[0x66, 0x4f, 0x0f, 0x2d, 0x0f], "cvtpd2pi mm1, xmmword [r15]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2d, 0xcf], "cvtsd2si r9, xmm15"); test_instr(&[0xf2, 0x4f, 0x0f, 0x2d, 0x0f], "cvtsd2si r9, qword [r15]"); test_instr(&[0xf2, 0x40, 0x0f, 0x2d, 0xcf], "cvtsd2si ecx, xmm7"); test_instr(&[0xf2, 0x40, 0x0f, 0x2d, 0x0f], "cvtsd2si ecx, qword [rdi]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2e, 0xcf], "ucomisd xmm9, xmm15"); test_instr(&[0x66, 0x4f, 0x0f, 0x2e, 0x0f], "ucomisd xmm9, qword [r15]"); test_instr(&[0x66, 0x4f, 0x0f, 0x2f, 0xcf], "comisd xmm9, xmm15"); test_instr(&[0x66, 0x4f, 0x0f, 0x2f, 0x0f], "comisd xmm9, qword [r15]"); /* * .... 660f38 * .... 660f7f */ test_invalid(&[0x66, 0x4f, 0x0f, 0x50, 0x01]); test_instr(&[0x66, 0x4f, 0x0f, 0x50, 0xc1], "movmskpd r8d, xmm9"); test_instr(&[0x66, 0x4f, 0x0f, 0x51, 0x01], "sqrtpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x51, 0x01], "sqrtsd xmm8, qword [r9]"); test_invalid(&[0x66, 0x4f, 0x0f, 0x52, 0x01]); test_invalid(&[0x66, 0x4f, 0x0f, 0x53, 0x01]); test_instr(&[0x66, 0x4f, 0x0f, 0x54, 0x01], "andpd xmm8, xmmword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x55, 0x01], "andnpd xmm8, xmmword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x56, 0x01], "orpd xmm8, xmmword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x57, 0x01], "xorpd xmm8, xmmword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x58, 0x01], "addpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x58, 0x01], "addsd xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x59, 0x01], "mulpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x59, 0x01], "mulsd xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5a, 0x01], "cvtpd2ps xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x5a, 0x01], "cvtsd2ss xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5b, 0x01], "cvtps2dq xmm8, xmmword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5c, 0x01], "subpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x5c, 0x01], "subsd xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5d, 0x01], "minpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x5d, 0x01], "minsd xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5e, 0x01], "divpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x5e, 0x01], "divsd xmm8, qword [r9]"); test_instr(&[0x66, 0x4f, 0x0f, 0x5f, 0x01], "maxpd xmm8, xmmword [r9]"); test_instr(&[0xf2, 0x4f, 0x0f, 0x5f, 0x01], "maxsd xmm8, qword [r9]"); test_instr( &[0x66, 0x4f, 0x0f, 0x60, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklbw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x61, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklwd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x62, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckldq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x63, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packsswb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x64, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x65, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x66, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x67, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packuswb xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x68, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhbw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x69, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhwd xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6a, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6b, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packssdw xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6c, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklqdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6d, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhqdq xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6e, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movq xmm11, qword [r12 + r11 * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x4f, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqa xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_instr(&[0x66, 0x48, 0x0f, 0x6e, 0xc0], "movq xmm0, rax"); test_instr(&[0x66, 0x0f, 0x70, 0xc0, 0x4e], "pshufd xmm0, xmm0, 0x4e"); test_instr(&[0xf2, 0x0f, 0x70, 0xc0, 0x4e], "pshuflw xmm0, xmm0, 0x4e"); test_instr(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_invalid(&[0x66, 0x4f, 0x0f, 0x71, 0x10, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x71, 0xd0, 0x8f], "psrlw xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x71, 0x20, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x71, 0xe0, 0x8f], "psraw xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x71, 0x30, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x71, 0xf0, 0x8f], "psllw xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x72, 0x10, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x72, 0xd0, 0x8f], "psrld xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x72, 0x20, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x72, 0xe0, 0x8f], "psrad xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x72, 0x30, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x72, 0xf0, 0x8f], "pslld xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x73, 0x10, 0x8f]); test_invalid(&[0x66, 0x4f, 0x0f, 0x73, 0x18, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x73, 0xd0, 0x8f], "psrlq xmm8, 0x8f"); test_instr(&[0x66, 0x4f, 0x0f, 0x73, 0xd8, 0x8f], "psrldq xmm8, 0x8f"); test_invalid(&[0x66, 0x4f, 0x0f, 0x73, 0x30, 0x8f]); test_invalid(&[0x66, 0x4f, 0x0f, 0x73, 0x38, 0x8f]); test_instr(&[0x66, 0x4f, 0x0f, 0x73, 0xf0, 0x8f], "psllq xmm8, 0x8f"); test_instr(&[0x66, 0x4f, 0x0f, 0x73, 0xf8, 0x8f], "pslldq xmm8, 0x8f"); test_instr(&[0x66, 0x0f, 0x7e, 0xc1], "movd ecx, xmm0"); test_instr(&[0x66, 0x48, 0x0f, 0x7e, 0xc1], "movq rcx, xmm0"); test_instr(&[0x66, 0x48, 0x0f, 0x7e, 0x01], "movq qword [rcx], xmm0"); test_instr(&[0x66, 0x4f, 0x0f, 0x7e, 0xc1], "movq r9, xmm8"); test_instr( &[0x66, 0x4f, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqa xmmword [r12 + r11 * 4 - 0x334455cc], xmm11" ); test_instr(&[0x66, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm8, xmm11, 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmppd xmm8, xmmword [r11], 0x8"); test_instr(&[0xf2, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm0, xmm3, 0x8"); test_instr(&[0xf2, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm8, xmm11, 0x8"); test_instr(&[0xf2, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpsd xmm8, qword [r11], 0x8"); test_instr(&[0x66, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm0, ebx, 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm8, r11d, 0x8"); test_instr(&[0x66, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm0, word [rbx], 0x8"); test_instr(&[0x66, 0x4f, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm8, word [r11], 0x8"); // test_instr(&[0x66, 0x0f, 0xc5, 0xc3, 0x08], "pextrw eax, xmm3, 0x8"); // test_instr(&[0x66, 0x4f, 0x0f, 0xc5, 0xc3, 0x08], "pextrw r8d, xmm11, 0x8"); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x03, 0x08]); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x40, 0x08]); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x80, 0x08]); test_instr(&[0x66, 0x4f, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm8, xmmword [r11], 0x8"); test_instr(&[0x66, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm0, xmmword [rbx], 0x8"); test_instr(&[0x66, 0x0f, 0xc6, 0xc3, 0x08], "shufpd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x0f, 0xd1, 0xc1], "psrlw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd1, 0x01], "psrlw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd2, 0xc1], "psrld xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd2, 0x01], "psrld xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd3, 0xc1], "psrlq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd3, 0x01], "psrlq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd4, 0xc1], "paddq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd4, 0x01], "paddq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd5, 0xc1], "pmullw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd5, 0x01], "pmullw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd6, 0xc1], "movq xmm1, xmm0"); test_instr(&[0x66, 0x0f, 0xd6, 0x01], "movq qword [rcx], xmm0"); test_invalid(&[0xf3, 0x4f, 0x0f, 0xd6, 0x03]); test_instr(&[0xf3, 0x4f, 0x0f, 0xd6, 0xc3], "movq2dq xmm8, mm3"); test_instr(&[0xf2, 0x4f, 0x0f, 0xd6, 0xc3], "movdq2q mm0, xmm11"); test_instr(&[0x66, 0x0f, 0xd7, 0xc1], "pmovmskb eax, xmm1"); test_instr(&[0x66, 0x4f, 0x0f, 0xd7, 0xc1], "pmovmskb r8d, xmm9"); test_invalid(&[0x66, 0x0f, 0xd7, 0x01]); test_instr(&[0x66, 0x0f, 0xd8, 0xc1], "psubusb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd8, 0x01], "psubusb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xd9, 0xc1], "psubusw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd9, 0x01], "psubusw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xda, 0xc1], "pminub xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xda, 0x01], "pminub xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdb, 0xc1], "pand xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdb, 0x01], "pand xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdc, 0xc1], "paddusb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdc, 0x01], "paddusb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdd, 0xc1], "paddusw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdd, 0x01], "paddusw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xde, 0xc1], "pmaxub xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xde, 0x01], "pmaxub xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xdf, 0xc1], "pandn xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdf, 0x01], "pandn xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe0, 0xc1], "pavgb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe0, 0x01], "pavgb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe1, 0xc1], "psraw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe1, 0x01], "psraw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe2, 0xc1], "psrad xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe2, 0x01], "psrad xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe3, 0xc1], "pavgw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe3, 0x01], "pavgw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe4, 0xc1], "pmulhuw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe4, 0x01], "pmulhuw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe5, 0xc1], "pmulhw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe5, 0x01], "pmulhw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe6, 0xc1], "cvttpd2dq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe6, 0x01], "cvttpd2dq xmm0, xmmword [rcx]"); test_invalid(&[0x66, 0x0f, 0xe7, 0xc1]); test_instr(&[0x66, 0x0f, 0xe7, 0x01], "movntdq xmmword [rcx], xmm0"); test_instr(&[0x66, 0x0f, 0xe8, 0xc1], "psubsb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe8, 0x01], "psubsb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xe9, 0xc1], "psubsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe9, 0x01], "psubsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xea, 0xc1], "pminsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xea, 0x01], "pminsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc3], "por xmm0, xmm3"); test_instr(&[0x66, 0x0f, 0xeb, 0xc4], "por xmm0, xmm4"); test_instr(&[0x66, 0x0f, 0xeb, 0xd3], "por xmm2, xmm3"); test_instr(&[0x66, 0x0f, 0xeb, 0x12], "por xmm2, xmmword [rdx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc1], "por xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xeb, 0x01], "por xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xec, 0xc1], "paddsb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xec, 0x01], "paddsb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xed, 0xc1], "paddsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xed, 0x01], "paddsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xee, 0xc1], "pmaxsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xee, 0x01], "pmaxsw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xef, 0xc1], "pxor xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xef, 0x01], "pxor xmm0, xmmword [rcx]"); test_invalid(&[0x66, 0x0f, 0xf0, 0xc1]); test_invalid(&[0x66, 0x0f, 0xf0, 0x01]); test_instr(&[0x66, 0x0f, 0xf1, 0xc1], "psllw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf1, 0x01], "psllw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf2, 0xc1], "pslld xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf2, 0x01], "pslld xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf3, 0xc1], "psllq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf3, 0x01], "psllq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf4, 0xc1], "pmuludq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf4, 0x01], "pmuludq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf5, 0xc1], "pmaddwd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf5, 0x01], "pmaddwd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf6, 0xc1], "psadbw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf6, 0x01], "psadbw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf7, 0xc1], "maskmovdqu xmm0, xmm1"); test_invalid(&[0x66, 0x0f, 0xf7, 0x01]); test_instr(&[0x66, 0x0f, 0xf8, 0xc1], "psubb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf8, 0x01], "psubb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xf9, 0xc1], "psubw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf9, 0x01], "psubw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfa, 0xc1], "psubd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfa, 0x01], "psubd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfb, 0xc1], "psubq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfb, 0x01], "psubq xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfc, 0xc1], "paddb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfc, 0x01], "paddb xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfd, 0xc1], "paddw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfd, 0x01], "paddw xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xfe, 0xc1], "paddd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfe, 0x01], "paddd xmm0, xmmword [rcx]"); test_instr(&[0x66, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf2, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf3, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0x66, 0x0f, 0xff, 0x01], "ud0 eax, dword [rcx]"); test_instr(&[0x66, 0x4f, 0x0f, 0xff, 0xc1], "ud0 r8d, r9d"); test_instr(&[0x66, 0x0f, 0x74, 0xc1], "pcmpeqb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0x74, 0x12], "pcmpeqb xmm2, xmmword [rdx]"); test_instr(&[0x66, 0x0f, 0xf8, 0xc8], "psubb xmm1, xmm0"); test_instr(&[0x66, 0x0f, 0xf8, 0xd0], "psubb xmm2, xmm0"); test_instr(&[0x66, 0x0f, 0xf8, 0x12], "psubb xmm2, xmmword [rdx]"); } #[test] fn test_sse3() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse3(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse3(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0xf2, 0x0f, 0xf0, 0x0f], "lddqu xmm1, xmmword [rdi]"); test_instr_invalid(&[0xf2, 0x0f, 0xf0, 0xcf]); test_instr(&[0xf2, 0x0f, 0xd0, 0x0f], "addsubps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0xd0, 0xcf], "addsubps xmm1, xmm7"); test_invalid(&[0xf3, 0x0f, 0xd0, 0x0f]); test_instr(&[0xf2, 0x4f, 0x0f, 0xd0, 0xcf], "addsubps xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0xd0, 0x0f], "addsubpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0xd0, 0xcf], "addsubpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0xd0, 0xcf], "addsubpd xmm9, xmm15"); test_instr(&[0xf2, 0x0f, 0x7c, 0x0f], "haddps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0x7c, 0xcf], "haddps xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x7c, 0xcf], "haddps xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x7c, 0x0f], "haddpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0x7c, 0xcf], "haddpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0x7c, 0xcf], "haddpd xmm9, xmm15"); test_instr(&[0xf2, 0x0f, 0x7d, 0x0f], "hsubps xmm1, xmmword [rdi]"); test_instr(&[0xf2, 0x0f, 0x7d, 0xcf], "hsubps xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x7d, 0xcf], "hsubps xmm9, xmm15"); test_instr(&[0x66, 0x0f, 0x7d, 0x0f], "hsubpd xmm1, xmmword [rdi]"); test_instr(&[0x66, 0x0f, 0x7d, 0xcf], "hsubpd xmm1, xmm7"); test_instr(&[0x66, 0x4f, 0x0f, 0x7d, 0xcf], "hsubpd xmm9, xmm15"); test_instr(&[0xf3, 0x0f, 0x12, 0x0f], "movsldup xmm1, xmmword [rdi]"); test_instr(&[0xf3, 0x0f, 0x12, 0xcf], "movsldup xmm1, xmm7"); test_instr(&[0xf3, 0x4f, 0x0f, 0x12, 0xcf], "movsldup xmm9, xmm15"); test_instr(&[0xf3, 0x0f, 0x16, 0x0f], "movshdup xmm1, xmmword [rdi]"); test_instr(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_instr(&[0xf3, 0x4f, 0x0f, 0x16, 0xcf], "movshdup xmm9, xmm15"); test_instr(&[0xf2, 0x0f, 0x12, 0x0f], "movddup xmm1, qword [rdi]"); test_instr(&[0xf2, 0x0f, 0x12, 0xcf], "movddup xmm1, xmm7"); test_instr(&[0xf2, 0x4f, 0x0f, 0x12, 0xcf], "movddup xmm9, xmm15"); test_instr(&[0x0f, 0x01, 0xc8], "monitor"); test_invalid(&[0x66, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc8]); test_instr(&[0x0f, 0x01, 0xc9], "mwait"); test_invalid(&[0x66, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc9]); } #[test] fn test_sse4_2() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4_2(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0x37, 0x03], "pcmpgtq xmm0, xmmword [rbx]"); test_instr(&[0x66, 0x0f, 0x38, 0x37, 0xc3], "pcmpgtq xmm0, xmm3"); test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0x06], "crc32 eax, byte [rsi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0xc6], "crc32 eax, dh"); test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0x06], "crc32 eax, dword [rsi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, esi"); test_instr(&[0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, si"); test_instr(&[0x66, 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc6], "crc32 rax, rsi"); test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0xc6, 0x54], "pcmpestrm xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0x06, 0x54], "pcmpestrm xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0xc6, 0x54], "pcmpestri xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0x06, 0x54], "pcmpestri xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0xc6, 0x54], "pcmpistrm xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0x06, 0x54], "pcmpistrm xmm0, xmmword [rsi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0xc6, 0x54], "pcmpistri xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0x06, 0x54], "pcmpistri xmm0, xmmword [rsi], 0x54"); } #[test] fn test_sse4_1() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4_1(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4_2 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], "blendps xmm2, xmmword [rcx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0xc1, 0x22], "blendps xmm0, xmm1, 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], "blendpd xmm2, xmmword [rcx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0xc1, 0x22], "blendpd xmm0, xmm1, 0x22"); test_instr(&[0x66, 0x0f, 0x38, 0x10, 0x06], "pblendvb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x10, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x14, 0x06], "blendvps xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x14, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x15, 0x06], "blendvpd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x15, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x17, 0x06], "ptest xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x17, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x20, 0x06], "pmovsxbw xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x20, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x21, 0x06], "pmovsxbd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x21, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x22, 0x06], "pmovsxbq xmm0, word [rsi]"); test_invalid(&[0x0f, 0x38, 0x22, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x23, 0x06], "pmovsxwd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x23, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x24, 0x06], "pmovsxwq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x24, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x25, 0x06], "pmovsxdq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x25, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x28, 0x06], "pmuldq xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x28, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x29, 0x06], "pcmpeqq xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x29, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x2a, 0x06], "movntdqa xmm0, xmmword [rsi]"); test_invalid(&[0x66, 0x0f, 0x38, 0x2a, 0xc6]); test_invalid(&[0x0f, 0x38, 0x2a, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x2b, 0x06], "packusdw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x2b, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x30, 0x06], "pmovzxbw xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x30, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x31, 0x06], "pmovzxbd xmm0, dword [rsi]"); test_invalid(&[0x0f, 0x38, 0x31, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x32, 0x06], "pmovzxbq xmm0, word [rsi]"); test_invalid(&[0x0f, 0x38, 0x32, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x33, 0x06], "pmovzxwd xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x33, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x34, 0x06], "pmovzxwq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x34, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x35, 0x06], "pmovzxdq xmm0, qword [rsi]"); test_invalid(&[0x0f, 0x38, 0x35, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x38, 0x06], "pminsb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x38, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x39, 0x06], "pminsd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x39, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3a, 0x06], "pminuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3a, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3b, 0x06], "pminud xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3b, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3c, 0x06], "pmaxsb xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3c, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3d, 0x06], "pmaxsd xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3d, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3e, 0x06], "pmaxuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3e, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3f, 0x06], "pmaxud xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x3f, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x40, 0x06], "pmulld xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x40, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x41, 0x06], "phminposuw xmm0, xmmword [rsi]"); test_invalid(&[0x0f, 0x38, 0x41, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x08, 0x06, 0x31], "roundps xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x08, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x09, 0x06, 0x31], "roundpd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x09, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0a, 0x06, 0x31], "roundss xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0a, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0b, 0x06, 0x31], "roundsd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0b, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0e, 0x06, 0x31], "pblendw xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0e, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x14, 0x06, 0x31], "pextrb xmm0, byte [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x14, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x15, 0x06, 0x31], "pextrw xmm0, word [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x15, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrd xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x16, 0x06]); test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrq xmm0, qword [rsi], 0x31"); test_instr(&[0x66, 0x0f, 0x3a, 0x17, 0x06, 0x31], "extractps xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x17, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x20, 0x06, 0x31], "pinsrb xmm0, byte [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x20, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x21, 0x06, 0x31], "insertps xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x21, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrd xmm0, dword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x22, 0x06]); test_instr(&[0x66, 0x48, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrq xmm0, qword [rsi], 0x31"); test_instr(&[0x66, 0x0f, 0x3a, 0x40, 0x06, 0x31], "dpps xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x40, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x41, 0x06, 0x31], "dppd xmm0, xmmword [rsi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x41, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x42, 0x06, 0x44], "mpsadbw xmm0, xmmword [rsi], 0x44"); test_invalid(&[0x0f, 0x3a, 0x42, 0x06]); } #[test] fn test_ssse3() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_ssse3(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_ssse3(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0x00, 0xda], "pshufb xmm3, xmm2"); test_instr(&[0x66, 0x0f, 0x38, 0x00, 0x06], "pshufb xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x00, 0x06], "pshufb mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x01, 0x06], "phaddw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x01, 0x06], "phaddw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x02, 0x06], "phaddd xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x02, 0x06], "phaddd mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x03, 0x06], "phaddsw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x03, 0x06], "phaddsw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x04, 0x06], "pmaddubsw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x04, 0x06], "pmaddubsw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x05, 0x06], "phsubw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x05, 0x06], "phsubw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x06, 0x06], "phsubd xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x06, 0x06], "phsubd mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x07, 0x06], "phsubsw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x07, 0x06], "phsubsw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x08, 0x06], "psignb xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x08, 0x06], "psignb mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x09, 0x06], "psignw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x09, 0x06], "psignw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x0a, 0x06], "psignd xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x0a, 0x06], "psignd mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x0b, 0x06], "pmulhrsw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x0b, 0x06], "pmulhrsw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1c, 0x06], "pabsb xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x1c, 0x06], "pabsb mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1d, 0x06], "pabsw xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x1d, 0x06], "pabsw mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1e, 0x06], "pabsd xmm0, xmmword [rsi]"); test_instr(&[0x0f, 0x38, 0x1e, 0x06], "pabsd mm0, qword [rsi]"); test_instr(&[0x66, 0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr xmm0, xmmword [rsi], 0x30"); test_instr(&[0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr mm0, qword [rsi], 0x30"); } #[test] fn test_0f01() { // drawn heavily from "Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group // Number" for x in &[0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, 0x2e, 0x2f] { test_invalid(&[0x0f, 0x01, *x]); } test_display(&[0x0f, 0x01, 0x38], "invlpg byte [rax]"); test_display(&[0x0f, 0x01, 0x3f], "invlpg byte [rdi]"); test_display(&[0x0f, 0x01, 0x40, 0xff], "sgdt ptr [rax - 0x1]"); test_display(&[0x0f, 0x01, 0x41, 0xff], "sgdt ptr [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0x49, 0xff], "sidt ptr [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0x51, 0xff], "lgdt ptr [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0x59, 0xff], "lidt ptr [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0x61, 0xff], "smsw word [rcx - 0x1]"); test_invalid(&[0x0f, 0x01, 0x69, 0xff]); test_display(&[0x0f, 0x01, 0x71, 0xff], "lmsw word [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0x79, 0xff], "invlpg byte [rcx - 0x1]"); test_display(&[0x0f, 0x01, 0xc0], "enclv"); test_display(&[0x0f, 0x01, 0xc1], "vmcall"); test_display(&[0x0f, 0x01, 0xc2], "vmlaunch"); test_display(&[0x0f, 0x01, 0xc3], "vmresume"); test_display(&[0x0f, 0x01, 0xc4], "vmxoff"); test_display(&[0x0f, 0x01, 0xc5], "pconfig"); test_invalid(&[0x0f, 0x01, 0xc6]); test_invalid(&[0x0f, 0x01, 0xc7]); test_display(&[0x0f, 0x01, 0xc8], "monitor"); test_display(&[0x0f, 0x01, 0xc9], "mwait"); test_display(&[0x0f, 0x01, 0xca], "clac"); test_display(&[0x0f, 0x01, 0xcb], "stac"); test_invalid(&[0x0f, 0x01, 0xcc]); test_invalid(&[0x0f, 0x01, 0xcd]); test_invalid(&[0x0f, 0x01, 0xce]); test_display(&[0x0f, 0x01, 0xcf], "encls"); test_display(&[0x0f, 0x01, 0xd0], "xgetbv"); test_display(&[0x0f, 0x01, 0xd1], "xsetbv"); test_invalid(&[0x0f, 0x01, 0xd2]); test_invalid(&[0x0f, 0x01, 0xd3]); test_display(&[0x0f, 0x01, 0xd4], "vmfunc"); test_display(&[0x0f, 0x01, 0xd5], "xend"); test_display(&[0x0f, 0x01, 0xd6], "xtest"); test_display(&[0x0f, 0x01, 0xd7], "enclu"); test_display(&[0x0f, 0x01, 0xd8], "vmrun rax"); test_display(&[0x0f, 0x01, 0xd9], "vmmcall"); test_display(&[0x0f, 0x01, 0xda], "vmload rax"); test_display(&[0x0f, 0x01, 0xdb], "vmsave rax"); test_display(&[0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x0f, 0x01, 0xdd], "clgi"); test_display(&[0x0f, 0x01, 0xde], "skinit eax"); test_display(&[0x0f, 0x01, 0xdf], "invlpga rax, ecx"); test_display(&[0x0f, 0x01, 0xfe], "invlpgb rax, edx, ecx"); test_display(&[0x0f, 0x01, 0xff], "tlbsync"); test_display(&[0x2e, 0x67, 0x65, 0x2e, 0x46, 0x0f, 0x01, 0xff], "tlbsync"); test_display(&[0x4f, 0x0f, 0x01, 0xe0], "smsw r8w"); test_display(&[0x0f, 0x01, 0xe0], "smsw ax"); test_display(&[0x0f, 0x01, 0xe1], "smsw cx"); test_display(&[0x0f, 0x01, 0xe2], "smsw dx"); test_display(&[0x0f, 0x01, 0xe3], "smsw bx"); test_display(&[0x0f, 0x01, 0xe4], "smsw sp"); test_display(&[0x0f, 0x01, 0xe5], "smsw bp"); test_display(&[0x0f, 0x01, 0xe6], "smsw si"); test_display(&[0x0f, 0x01, 0xe7], "smsw di"); test_invalid(&[0x0f, 0x01, 0xe8]); test_invalid(&[0x0f, 0x01, 0xe8]); test_invalid(&[0x0f, 0x01, 0xe9]); test_invalid(&[0x0f, 0x01, 0xea]); test_invalid(&[0x0f, 0x01, 0xeb]); test_display(&[0x0f, 0x01, 0xee], "rdpkru"); test_display(&[0x0f, 0x01, 0xef], "wrpkru"); test_invalid(&[0xf2, 0x0f, 0x01, 0xee]); test_invalid(&[0xf2, 0x0f, 0x01, 0xef]); test_display(&[0x4f, 0x0f, 0x01, 0xf0], "lmsw r8w"); test_display(&[0x0f, 0x01, 0xf0], "lmsw ax"); test_display(&[0x0f, 0x01, 0xf1], "lmsw cx"); test_display(&[0x0f, 0x01, 0xf2], "lmsw dx"); test_display(&[0x0f, 0x01, 0xf3], "lmsw bx"); test_display(&[0x0f, 0x01, 0xf4], "lmsw sp"); test_display(&[0x0f, 0x01, 0xf5], "lmsw bp"); test_display(&[0x0f, 0x01, 0xf6], "lmsw si"); test_display(&[0x0f, 0x01, 0xf7], "lmsw di"); test_display(&[0x0f, 0x01, 0xf8], "swapgs"); test_display(&[0x0f, 0x01, 0xf9], "rdtscp"); test_display(&[0x0f, 0x01, 0xfa], "monitorx"); test_display(&[0x0f, 0x01, 0xfb], "mwaitx"); test_display(&[0x0f, 0x01, 0xfc], "clzero"); test_display(&[0x0f, 0x01, 0xfd], "rdpru ecx"); } #[test] fn test_0fae() { let intel = InstDecoder::minimal().with_intel_quirks(); let amd = InstDecoder::minimal().with_amd_quirks(); let default = InstDecoder::default(); let minimal = InstDecoder::minimal(); // drawn heavily from "Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group // Number" test_invalid(&[0xf3, 0x0f, 0xae, 0x87]); test_invalid(&[0xf3, 0x0f, 0xae, 0x04, 0x4f]); test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x0c, 0x4f], "fxrstor ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x14, 0x4f], "ldmxcsr dword [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x1c, 0x4f], "stmxcsr dword [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x24, 0x4f], "xsave ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors ptr [rsp + 0x40]"); test_display(&[0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec ptr [rsp + 0x40]"); test_display(&[0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves ptr [rsp + 0x40]"); test_display(&[0x4f, 0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors64 ptr [r12 + r12 * 1 + 0x40]"); test_display(&[0x4f, 0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec64 ptr [r12 + r12 * 1 + 0x40]"); test_display(&[0x4f, 0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves64 ptr [r12 + r12 * 1 + 0x40]"); test_display(&[0x0f, 0xc7, 0x74, 0x24, 0x40], "vmptrld qword [rsp + 0x40]"); test_display(&[0x0f, 0xc7, 0x7c, 0x24, 0x40], "vmptrst qword [rsp + 0x40]"); test_display(&[0x0f, 0xae, 0x2c, 0x4f], "xrstor ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x34, 0x4f], "xsaveopt ptr [rdi + rcx * 2]"); test_display(&[0x0f, 0xae, 0x3c, 0x4f], "clflush zmmword [rdi + rcx * 2]"); for (modrm, text) in &[(0xe8u8, "lfence"), (0xf0u8, "mfence"), (0xf8u8, "sfence")] { test_display_under(&intel, &[0x0f, 0xae, *modrm], text); test_display_under(&amd, &[0x0f, 0xae, *modrm], text); test_display_under(&default, &[0x0f, 0xae, *modrm], text); test_display_under(&minimal, &[0x0f, 0xae, *modrm], text); // it turns out intel and amd accept m != 0 for {l,m,s}fence: // from intel: // ``` // Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this // instruction, the processor ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded // by any opcode of the form 0F AE Fx, where x is in the range 0-7. // ``` // whereas amd does not discuss the r/m field at all. at least as of zen, amd also accepts // these encodings. for m in 1u8..8u8 { test_display_under(&intel, &[0x0f, 0xae, modrm | m], text); test_display_under(&amd, &[0x0f, 0xae, modrm | m], text); test_display_under(&default, &[0x0f, 0xae, modrm | m], text); test_invalid_under(&minimal, &[0x0f, 0xae, modrm | m]); } } } #[test] fn test_system() { test_display(&[0x66, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8]"); test_display(&[0x67, 0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8d]"); test_display(&[0x4f, 0x0f, 0xb2, 0x00], "lss r8, mword [r8]"); test_display(&[0x0f, 0xb2, 0x00], "lss rax, dword [rax]"); test_invalid(&[0x45, 0x0f, 0x22, 0xc8]); test_invalid(&[0x45, 0x0f, 0x20, 0xc8]); test_display(&[0x40, 0x0f, 0x22, 0xd0], "mov cr2, rax"); test_display(&[0x0f, 0x22, 0xd0], "mov cr2, rax"); test_invalid(&[0x44, 0x0f, 0x22, 0xcf]); test_display(&[0x0f, 0x22, 0xd7], "mov cr2, rdi"); test_display(&[0x0f, 0x20, 0xd0], "mov rax, cr2"); test_invalid(&[0x45, 0x0f, 0x23, 0xc8]); test_invalid(&[0x45, 0x0f, 0x21, 0xc8]); test_display(&[0x40, 0x0f, 0x23, 0xc8], "mov dr1, rax"); test_display(&[0x0f, 0x23, 0xc8], "mov dr1, rax"); test_display(&[0x0f, 0x21, 0xc8], "mov rax, dr1"); test_display(&[0x0f, 0x06], "clts"); } #[test] fn test_arithmetic() { test_display(&[0x81, 0xec, 0x10, 0x03, 0x00, 0x00], "sub esp, 0x310"); test_display(&[0x0f, 0xaf, 0xc2], "imul eax, edx"); test_display(&[0x4b, 0x69, 0x43, 0x6f, 0x6d, 0x70, 0x6c, 0x65], "imul rax, qword [r11 + 0x6f], 0x656c706d"); test_display(&[0x66, 0x0f, 0xaf, 0xd1], "imul dx, cx"); test_display(&[0xf6, 0xe8], "imul al"); test_display(&[0xf6, 0x28], "imul byte [rax]"); test_display(&[0x4b, 0x6b, 0x43, 0x6f, 0x6d], "imul rax, qword [r11 + 0x6f], 0x6d"); test_display(&[0x4f, 0x4e, 0x00, 0xcc], "add spl, r9b"); } #[test] #[allow(non_snake_case)] fn test_E_decode() { test_display(&[0xff, 0x75, 0xb8], "push qword [rbp - 0x48]"); test_display(&[0xff, 0x75, 0x08], "push qword [rbp + 0x8]"); } #[test] fn test_sse() { test_display(&[0xf3, 0x0f, 0x10, 0x0c, 0xc7], "movss xmm1, dword [rdi + rax * 8]"); test_display(&[0xf3, 0x0f, 0x11, 0x0c, 0xc7], "movss dword [rdi + rax * 8], xmm1"); test_display(&[0x4f, 0x0f, 0x28, 0x00], "movaps xmm8, xmmword [r8]"); test_display(&[0x4f, 0x0f, 0x29, 0x00], "movaps xmmword [r8], xmm8"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0xc1], "cvtsi2ss xmm8, r9"); test_display(&[0xf3, 0x4f, 0x0f, 0x2a, 0x01], "cvtsi2ss xmm8, qword [r9]"); test_display(&[0x4f, 0x0f, 0x2b, 0x00], "movntps xmmword [r8], xmm8"); test_display(&[0xf3, 0x4f, 0x0f, 0x2c, 0xc1], "cvttss2si r8, xmm9"); test_display(&[0xf3, 0x4f, 0x0f, 0x2c, 0x01], "cvttss2si r8, dword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x2d, 0xc1], "cvtss2si r8, xmm9"); test_display(&[0xf3, 0x4f, 0x0f, 0x2d, 0x01], "cvtss2si r8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x2e, 0x00], "ucomiss xmm8, dword [r8]"); test_display(&[0x4f, 0x0f, 0x2f, 0x00], "comiss xmm8, dword [r8]"); test_display(&[0x0f, 0x28, 0xd0], "movaps xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]"); test_display(&[0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [rax]"); test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); test_display(&[0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8]"); test_display(&[0x67, 0x4f, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]"); test_display(&[0x67, 0x66, 0x4f, 0x0f, 0x28, 0x00], "movapd xmm8, xmmword [r8d]"); test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd xmmword [rax], xmm0"); test_invalid(&[0x4f, 0x0f, 0x50, 0x00]); test_display(&[0x4f, 0x0f, 0x50, 0xc1], "movmskps r8d, xmm9"); test_display(&[0x4f, 0x0f, 0x51, 0x01], "sqrtps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x51, 0x01], "sqrtss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x52, 0x01], "rsqrtps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x52, 0x01], "rsqrtss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x53, 0x01], "rcpps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x53, 0x01], "rcpss xmm8, dword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x53, 0xc1], "rcpss xmm8, xmm9"); test_display(&[0x4f, 0x0f, 0x54, 0x01], "andps xmm8, xmmword [r9]"); test_display(&[0x4f, 0x0f, 0x55, 0x01], "andnps xmm8, xmmword [r9]"); test_display(&[0x4f, 0x0f, 0x56, 0x01], "orps xmm8, xmmword [r9]"); test_display(&[0x4f, 0x0f, 0x57, 0x01], "xorps xmm8, xmmword [r9]"); test_display(&[0x4f, 0x0f, 0x58, 0x01], "addps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x58, 0x01], "addss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x59, 0x01], "mulps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x59, 0x01], "mulss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x5a, 0x01], "cvtps2pd xmm8, qword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5a, 0x01], "cvtss2sd xmm8, qword [r9]"); test_display(&[0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5b, 0x01], "cvttps2dq xmm8, xmmword [r9]"); test_display(&[0x67, 0x4f, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm8, xmmword [r9d]"); test_display(&[0x4f, 0x0f, 0x5c, 0x01], "subps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5c, 0x01], "subss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x5d, 0x01], "minps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5d, 0x01], "minss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x5e, 0x01], "divps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5e, 0x01], "divss xmm8, dword [r9]"); test_display(&[0x4f, 0x0f, 0x5f, 0x01], "maxps xmm8, xmmword [r9]"); test_display(&[0xf3, 0x4f, 0x0f, 0x5f, 0x01], "maxss xmm8, dword [r9]"); test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [rax], 0x7f"); test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [r8], 0x7f"); test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0"); test_display(&[0x66, 0x4f, 0x0f, 0xef, 0xc0], "pxor xmm8, xmm8"); test_display(&[0xf2, 0x0f, 0x10, 0x0c, 0xc6], "movsd xmm1, qword [rsi + rax * 8]"); test_display(&[0xf3, 0x0f, 0x10, 0x04, 0x86], "movss xmm0, dword [rsi + rax * 4]"); test_display(&[0xf2, 0x0f, 0x59, 0xc8], "mulsd xmm1, xmm0"); test_display(&[0xf3, 0x0f, 0x59, 0xc8], "mulss xmm1, xmm0"); test_display(&[0xf2, 0x4f, 0x0f, 0x59, 0xc8], "mulsd xmm9, xmm8"); test_display( &[0xf3, 0x4f, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqu xmm11, xmmword [r12 + r11 * 4 - 0x334455cc]" ); test_display(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_display(&[0xf3, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); test_display(&[0xf3, 0x4f, 0x0f, 0x7e, 0xc1], "movd r9, mm0"); // use of rex.w demotes to movd r/mm test_display(&[0xf3, 0x40, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); test_display(&[0xf3, 0x41, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm9"); test_display(&[0xf3, 0x42, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); test_display(&[0xf3, 0x44, 0x0f, 0x7e, 0xc1], "movq xmm8, xmm1"); test_display(&[0xf3, 0x48, 0x0f, 0x7e, 0xc1], "movd rcx, mm0"); test_display( &[0xf3, 0x4f, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqu xmmword [r12 + r11 * 4 - 0x334455cc], xmm11" ); test_display(&[0xf3, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm0, xmm3, 0x8"); test_display(&[0xf3, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm8, xmm11, 0x8"); test_display(&[0xf3, 0x4f, 0x0f, 0xc2, 0x03, 0x08], "cmpss xmm8, dword [r11], 0x8"); } // SETLE, SETNG, ... #[test] fn test_mov() { test_display(&[0xa0, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov al, byte [0x3412341200c46293]"); test_display(&[0x67, 0xa0, 0x93, 0x62, 0xc4, 0x00], "mov al, byte [0xc46293]"); test_display(&[0xa1, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov eax, dword [0x3412341200c46293]"); test_display(&[0x67, 0xa1, 0x93, 0x62, 0xc4, 0x00], "mov eax, dword [0xc46293]"); test_display(&[0xa2, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov byte [0x3412341200c46293], al"); test_display(&[0x67, 0xa2, 0x93, 0x62, 0xc4, 0x00], "mov byte [0xc46293], al"); test_display(&[0xa3, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], "mov dword [0x3412341200c46293], eax"); test_display(&[0x67, 0xa3, 0x93, 0x62, 0xc4, 0x00], "mov dword [0xc46293], eax"); test_display(&[0xba, 0x01, 0x00, 0x00, 0x00], "mov edx, 0x1"); test_display(&[0x48, 0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00], "mov qword [rsp], 0x0"); test_display(&[0x48, 0x89, 0x44, 0x24, 0x08], "mov qword [rsp + 0x8], rax"); test_display(&[0x48, 0x89, 0x43, 0x18], "mov qword [rbx + 0x18], rax"); test_display(&[0x48, 0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00], "mov qword [rbx + 0x10], 0x0"); test_display(&[0x49, 0x89, 0x4e, 0x08], "mov qword [r14 + 0x8], rcx"); test_display(&[0x48, 0x8b, 0x32], "mov rsi, qword [rdx]"); test_display(&[0x4d, 0x8b, 0x4c, 0x10, 0xf8], "mov r9, qword [r8 + rdx * 1 - 0x8]"); test_display(&[0x49, 0x89, 0x46, 0x10], "mov qword [r14 + 0x10], rax"); test_display(&[0x4d, 0x0f, 0x43, 0xec], "cmovnb r13, r12"); test_display(&[0x0f, 0xb6, 0x06], "movzx eax, byte [rsi]"); test_display(&[0x0f, 0xb7, 0x06], "movzx eax, word [rsi]"); test_display(&[0x89, 0x55, 0x94], "mov dword [rbp - 0x6c], edx"); test_display(&[0x65, 0x4c, 0x89, 0x04, 0x25, 0xa8, 0x01, 0x00, 0x00], "mov qword gs:[0x1a8], r8"); test_display(&[0x0f, 0xbe, 0x83, 0xb4, 0x00, 0x00, 0x00], "movsx eax, byte [rbx + 0xb4]"); test_display(&[0x46, 0x63, 0xc1], "movsxd r8, ecx"); test_display(&[0x48, 0x63, 0x04, 0xba], "movsxd rax, dword [rdx + rdi * 4]"); test_display(&[0xf3, 0x0f, 0x6f, 0x07], "movdqu xmm0, xmmword [rdi]"); test_display(&[0xf3, 0x0f, 0x7f, 0x45, 0x00], "movdqu xmmword [rbp], xmm0"); test_display(&[0x0f, 0x97, 0xc0], "seta al"); test_display(&[0x0f, 0x97, 0xc8], "seta al"); test_display(&[0x0f, 0x97, 0x00], "seta byte [rax]"); test_display(&[0x0f, 0x97, 0x08], "seta byte [rax]"); // test_display(&[0xd6], "salc"); test_display(&[0x8e, 0x00], "mov es, word [rax]"); // cs is not an allowed destination test_invalid(&[0x8e, 0x08]); test_display(&[0x8e, 0x10], "mov ss, word [rax]"); test_display(&[0x8e, 0x18], "mov ds, word [rax]"); test_display(&[0x8e, 0x20], "mov fs, word [rax]"); test_display(&[0x8e, 0x28], "mov gs, word [rax]"); test_invalid(&[0x8e, 0x30]); test_invalid(&[0x8e, 0x38]); } #[test] fn test_xchg() { test_display(&[0x90], "nop"); test_display(&[0x91], "xchg eax, ecx"); test_display(&[0x4f, 0x91], "xchg rax, r9"); test_display(&[0x66, 0x91], "xchg ax, cx"); test_display(&[0x4f, 0x90], "xchg rax, r8"); test_display(&[0x41, 0x90], "xchg eax, r8d"); } #[test] fn test_stack() { test_display(&[0x66, 0x41, 0x50], "push r8w"); } #[test] fn test_prefixes() { test_display(&[0x66, 0x41, 0x31, 0xc0], "xor r8w, ax"); test_display(&[0x66, 0x41, 0x32, 0xc0], "xor al, r8b"); test_display(&[0x40, 0x32, 0xc5], "xor al, bpl"); test_invalid(&[0xf0, 0x33, 0xc0]); test_display(&[0xf0, 0x31, 0x00], "lock xor dword [rax], eax"); test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor byte [rax], 0x0"); test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [rdi], edx"); test_display(&[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], "xacquire lock btc word [rbx], dx"); test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]); test_display(&[0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x66, 0x0f, 0xc1, 0xcc], "xadd sp, cx"); test_display(&[0xf2, 0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0xf3, 0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0x66, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf2, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf3, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); } #[test] fn test_control_flow() { test_display(&[0x73, 0x31], "jnb $+0x31"); test_display(&[0x72, 0x5a], "jb $+0x5a"); test_display(&[0x72, 0xf0], "jb $-0x10"); test_display(&[0x0f, 0x86, 0x8b, 0x01, 0x00, 0x00], "jna $+0x18b"); test_display(&[0x0f, 0x85, 0x3b, 0x25, 0x00, 0x00], "jnz $+0x253b"); test_display(&[0x74, 0x47], "jz $+0x47"); test_display(&[0xff, 0x15, 0x7e, 0x72, 0x24, 0x00], "call qword [rip + 0x24727e]"); test_display(&[0xff, 0x24, 0xcd, 0x70, 0xa0, 0xbc, 0x01], "jmp qword [rcx * 8 + 0x1bca070]"); test_display(&[0xff, 0xe0], "jmp rax"); test_display(&[0x66, 0xff, 0xe0], "jmp rax"); test_display(&[0x67, 0xff, 0xe0], "jmp rax"); test_invalid(&[0xff, 0xd8]); test_display(&[0xff, 0x18], "callf mword [rax]"); test_display(&[0xe0, 0x12], "loopnz $+0x12"); test_display(&[0xe1, 0x12], "loopz $+0x12"); test_display(&[0xe2, 0x12], "loop $+0x12"); test_display(&[0xe3, 0x12], "jrcxz $+0x12"); test_display(&[0xe3, 0xf0], "jrcxz $-0x10"); test_display(&[0xc3], "ret"); } #[test] fn bad_instructions() { // too long test_invalid(&[ 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x33, 0xc0, ]); } #[test] fn test_test_cmp() { test_display(&[0xf6, 0x05, 0x2c, 0x9b, 0xff, 0xff, 0x01], "test byte [rip - 0x64d4], 0x1"); test_display(&[0x48, 0x3d, 0x01, 0xf0, 0xff, 0xff], "cmp rax, -0xfff"); test_display(&[0x3d, 0x01, 0xf0, 0xff, 0xff], "cmp eax, -0xfff"); test_display(&[0x48, 0x83, 0xf8, 0xff], "cmp rax, -0x1"); test_display(&[0x48, 0x39, 0xc6], "cmp rsi, rax"); } #[test] fn test_push_pop() { test_display(&[0x5b], "pop rbx"); test_display(&[0x41, 0x5e], "pop r14"); test_display(&[0x68, 0x7f, 0x63, 0xc4, 0x00], "push 0xc4637f"); test_display(&[0x66, 0x8f, 0x00], "pop word [rax]"); test_display(&[0x8f, 0x00], "pop qword [rax]"); test_display(&[0x48, 0x8f, 0x00], "pop qword [rax]"); } #[test] fn test_bmi1() { let bmi1 = InstDecoder::minimal().with_bmi1(); let no_bmi1 = InstDecoder::minimal(); test_display_under(&bmi1, &[0xf3, 0x41, 0x0f, 0xbc, 0xd3], "tzcnt edx, r11d"); test_display_under(&bmi1, &[0xf2, 0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); test_display_under(&bmi1, &[0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); test_display_under(&no_bmi1, &[0xf3, 0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); // just 0f38 test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf2, 0x01], "andn eax, ebx, dword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf2, 0x01], "andn rax, rbx, qword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x09], "blsr eax, dword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x09], "blsr rax, qword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x11], "blsmsk eax, dword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x11], "blsmsk rax, qword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0x78, 0xf3, 0x19], "blsi eax, dword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0xf8, 0xf3, 0x19], "blsi rax, qword [r9]"); test_display_under(&bmi1, &[0xc4, 0xc2, 0x60, 0xf7, 0x01], "bextr eax, dword [r9], ebx"); test_display_under(&bmi1, &[0xc4, 0xc2, 0xe0, 0xf7, 0x01], "bextr rax, qword [r9], rbx"); } #[test] fn test_bmi2() { let bmi2 = InstDecoder::minimal().with_bmi2(); // f2 0f3a test_display_under(&bmi2, &[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], "rorx eax, dword [r9], 0x5"); test_display_under(&bmi2, &[0xc4, 0xc3, 0xfb, 0xf0, 0x01, 0x05], "rorx rax, qword [r9], 0x5"); // f2 0f38 map test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf5, 0x07], "pdep eax, ebx, dword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf5, 0x07], "pdep rax, rbx, qword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf6, 0x07], "mulx eax, ebx, dword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf6, 0x07], "mulx rax, rbx, qword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xc2, 0x63, 0xf7, 0x01], "shrx eax, dword [r9], ebx"); test_display_under(&bmi2, &[0xc4, 0xc2, 0xe3, 0xf7, 0x01], "shrx rax, qword [r9], rbx"); // f3 0f38 map test_display_under(&bmi2, &[0xc4, 0xe2, 0x62, 0xf5, 0x07], "pext eax, ebx, dword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe2, 0xf5, 0x07], "pext rax, rbx, qword [rdi]"); test_display_under(&bmi2, &[0xc4, 0xc2, 0x62, 0xf7, 0x01], "sarx eax, dword [r9], ebx"); test_display_under(&bmi2, &[0xc4, 0xc2, 0xe2, 0xf7, 0x01], "sarx rax, qword [r9], rbx"); // just 0f38 test_display_under(&bmi2, &[0xc4, 0xe2, 0x60, 0xf5, 0x07], "bzhi eax, dword [rdi], ebx"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe0, 0xf5, 0x07], "bzhi rax, qword [rdi], rbx"); // 66 0f38 test_display_under(&bmi2, &[0xc4, 0xc2, 0x61, 0xf7, 0x01], "shlx eax, dword [r9], ebx"); test_display_under(&bmi2, &[0xc4, 0xc2, 0xe1, 0xf7, 0x01], "shlx rax, qword [r9], rbx"); } #[test] fn test_popcnt() { let popcnt = InstDecoder::minimal().with_popcnt(); let intel_popcnt = InstDecoder::minimal().with_intel_quirks().with_sse4_2(); let no_popcnt = InstDecoder::minimal(); test_display_under(&popcnt, &[0xf3, 0x0f, 0xb8, 0xc1], "popcnt eax, ecx"); test_display_under(&intel_popcnt, &[0xf3, 0x0f, 0xb8, 0xc1], "popcnt eax, ecx"); test_display_under(&popcnt, &[0xf3, 0x4f, 0x0f, 0xb8, 0xc1], "popcnt r8, r9"); test_display_under(&intel_popcnt, &[0xf3, 0x4f, 0x0f, 0xb8, 0xc1], "popcnt r8, r9"); test_invalid_under(&no_popcnt, &[0xf3, 0x4f, 0x0f, 0xb8, 0xc1]); } #[test] fn test_bitwise() { test_display_under(&InstDecoder::minimal(), &[0x41, 0x0f, 0xbc, 0xd3], "bsf edx, r11d"); test_display_under(&InstDecoder::minimal(), &[0x0f, 0xbb, 0x17], "btc dword [rdi], edx"); test_display_under(&InstDecoder::minimal(), &[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [rdi], edx"); test_display(&[0x48, 0x0f, 0xa3, 0xd0], "bt rax, rdx"); test_display(&[0x48, 0x0f, 0xab, 0xd0], "bts rax, rdx"); test_display(&[0x48, 0x0f, 0xb3, 0xd0], "btr rax, rdx"); test_display(&[0x0f, 0xb3, 0xd0], "btr eax, edx"); test_display(&[0x66, 0x41, 0x0f, 0xb3, 0xc0], "btr r8w, ax"); test_display(&[0xd2, 0xe0], "shl al, cl"); } #[test] fn test_misc() { test_display(&[0xf1], "int 0x1"); test_display(&[0xf5], "cmc"); test_display(&[0xc8, 0x01, 0x02, 0x03], "enter 0x201, 0x3"); test_display(&[0xc9], "leave"); test_display(&[0xca, 0x12, 0x34], "retf 0x3412"); test_display(&[0xcb], "retf"); test_display(&[0x66, 0xcf], "iret"); test_display(&[0xcf], "iretd"); test_display(&[0x48, 0xcf], "iretq"); test_display(&[0x66, 0x4f, 0xcf], "iretq"); test_display(&[0xf2, 0x0f, 0x38, 0xf0, 0xc1], "crc32 eax, cl"); test_display(&[0xf2, 0x0f, 0x38, 0xf1, 0xc1], "crc32 eax, ecx"); test_display(&[0xfe, 0x00], "inc byte [rax]"); test_display(&[0xfe, 0x08], "dec byte [rax]"); test_display(&[0xff, 0x00], "inc dword [rax]"); test_display(&[0x48, 0xff, 0x00], "inc qword [rax]"); test_display(&[0xe4, 0x99], "in al, 0x99"); test_display(&[0xe5, 0x99], "in eax, 0x99"); test_display(&[0x67, 0xe5, 0x99], "in eax, 0x99"); test_display(&[0x4f, 0xe5, 0x99], "in eax, 0x99"); test_display(&[0xe6, 0x99], "out 0x99, al"); test_display(&[0x4f, 0xe7, 0x99], "out 0x99, eax"); test_display(&[0xec], "in al, dx"); test_display(&[0xed], "in eax, dx"); test_display(&[0xee], "out dx, al"); test_display(&[0xef], "out dx, eax"); test_display(&[0xcd, 0x00], "int 0x0"); test_display(&[0xcd, 0xff], "int 0xff"); test_display(&[0x9c], "pushf"); test_display(&[0x48, 0x98], "cdqe"); test_display(&[0x98], "cwde"); test_display(&[0x66, 0x99], "cwd"); test_display(&[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00], "nop word [rax + rax * 1]"); test_display(&[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00], "nop word [rax + rax * 1]"); test_display(&[0x48, 0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12], "lea rsp, qword [rdi + rax * 8 + 0x12000020]"); test_display(&[0x33, 0xc0], "xor eax, eax"); test_display(&[0x48, 0x8d, 0x53, 0x08], "lea rdx, qword [rbx + 0x8]"); test_invalid(&[0x8d, 0xdd]); test_display(&[0x31, 0xc9], "xor ecx, ecx"); test_display(&[0x48, 0x29, 0xc8], "sub rax, rcx"); test_display(&[0x48, 0x03, 0x0b], "add rcx, qword [rbx]"); test_display(&[0x48, 0x8d, 0x0c, 0x12], "lea rcx, qword [rdx + rdx * 1]"); test_display(&[0xf6, 0xc2, 0x18], "test dl, 0x18"); test_display(&[0x41, 0xf6, 0xc7, 0x03], "test r15b, 0x3"); test_display(&[0xf3, 0x48, 0xab], "rep stos qword es:[rdi], rax"); test_display(&[0xf3, 0x48, 0xa5], "rep movs qword es:[rdi], qword ds:[rsi]"); test_display(&[0xf3, 0x45, 0x0f, 0xbc, 0xd7], "tzcnt r10d, r15d"); test_display(&[0xf3, 0x0f, 0xae, 0x26], "ptwrite dword [rsi]"); test_display(&[0xf3, 0x0f, 0xae, 0xe6], "ptwrite esi"); test_invalid(&[0x66, 0xf3, 0x0f, 0xae, 0xe6]); test_display(&[0xf3, 0x49, 0x0f, 0xae, 0x26], "ptwrite qword [r14]"); test_display(&[0xf3, 0x0f, 0xae, 0xc4], "rdfsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xc4], "rdfsbase r12"); test_display(&[0xf3, 0x0f, 0xae, 0xcc], "rdgsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xcc], "rdgsbase r12"); test_display(&[0xf3, 0x0f, 0xae, 0xd4], "wrfsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xd4], "wrfsbase r12"); test_display(&[0xf3, 0x0f, 0xae, 0xdc], "wrgsbase esp"); test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xdc], "wrgsbase r12"); test_display(&[0x66, 0x0f, 0xae, 0x3f], "clflushopt zmmword [rdi]"); test_display(&[0x0f, 0xae, 0x3f], "clflush zmmword [rdi]"); test_invalid(&[0x66, 0x0f, 0xae, 0xff]); test_display(&[0x66, 0x0f, 0xae, 0x37], "clwb zmmword [rdi]"); test_display(&[0x66, 0x0f, 0xae, 0xf7], "tpause edi"); test_display(&[0xf3, 0x0f, 0xae, 0xf1], "umonitor rcx"); test_display(&[0xf2, 0x0f, 0xae, 0xf1], "umwait ecx"); test_display(&[0xf2, 0x4f, 0x0f, 0xae, 0xf1], "umwait r9"); test_display(&[0x66, 0x0f, 0x38, 0x80, 0x2f], "invept rbp, xmmword [rdi]"); test_display(&[0x66, 0x49, 0x0f, 0x38, 0x80, 0x2f], "invept rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x80, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x80, 0x2f]); test_display(&[0x66, 0x0f, 0x38, 0x81, 0x2f], "invvpid rbp, xmmword [rdi]"); test_display(&[0x66, 0x49, 0x0f, 0x38, 0x81, 0x2f], "invvpid rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x81, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x81, 0x2f]); test_display(&[0x66, 0x0f, 0x38, 0x82, 0x2f], "invpcid rbp, xmmword [rdi]"); test_display(&[0x66, 0x49, 0x0f, 0x38, 0x82, 0x2f], "invpcid rbp, xmmword [r15]"); test_invalid(&[0x0f, 0x38, 0x82, 0x2f]); test_invalid(&[0x43, 0x0f, 0x38, 0x82, 0x2f]); test_display(&[0x66, 0x0f, 0xae, 0xf1], "tpause ecx"); test_display(&[0x66, 0x4f, 0x0f, 0xae, 0xf1], "tpause r9"); } #[test] fn evex() { test_display(&[0x62, 0xe1, 0x7c, 0x00, 0x14, 0x0a], "vunpcklps xmm17, xmm16, xmmword [rdx]"); test_display(&[0x62, 0xe1, 0x7c, 0x08, 0x14, 0x0a], "vunpcklps xmm17, xmm0, xmmword [rdx]"); test_display(&[0x62, 0x01, 0x7c, 0x00, 0x14, 0xca], "vunpcklps xmm25, xmm16, xmm26"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa zmm0, zmmword [rax + rax * 2 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa xmm0, xmmword [rax + rax * 2 + 0x10]"); test_invalid(&[0x62, 0xf2, 0x7d, 0x1d, 0x66, 0x50, 0x01, 0x11]); // vpbroadcastmw2d. similar to `vpmovm2*`, out-of-range `k` are just masked down. test_display(&[0x62, 0xd2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // vpmovm2b (and larger forms). for some reason the source operand is a mask register but uses // modrm bits as a register selector. out-of-range `k` seem to just get masked down.. test_display(&[0x62, 0xd2, 0x7e, 0x08, 0x28, 0xc2], "vpmovm2b xmm0, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xc1], "vpmovm2b xmm0, k1"); // vpmovb2m (and larger forms). out-of-range `k` are invalid in 64-bit mode, are part of the // `bound` instruction for 32- and 16-bit modes. test_invalid(&[0x62, 0x72, 0x7e, 0x28, 0x29, 0xfd]); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xfd], "vpmovb2m k7, ymm5"); test_display(&[0x62, 0x12, 0x7d, 0x06, 0xa0, 0x04, 0x2f], "vpscatterdd dword [r15 + xmm29 * 1], k6, xmm8"); test_display(&[0x62, 0x12, 0x7d, 0x06, 0xa0, 0x14, 0x0f], "vpscatterdd dword [r15 + xmm25 * 1], k6, xmm10"); test_display(&[0x62, 0x12, 0x7d, 0x26, 0xa0, 0x14, 0x0f], "vpscatterdd dword [r15 + ymm25 * 1], k6, ymm10"); test_display(&[0x62, 0x12, 0x7d, 0x46, 0xa0, 0x14, 0x0f], "vpscatterdd dword [r15 + zmm25 * 1], k6, zmm10"); test_display(&[0x62, 0x12, 0xfd, 0x46, 0xa0, 0x14, 0x0f], "vpscatterdq qword [r15 + zmm25 * 1], k6, zmm10"); test_display(&[0x62, 0x12, 0x7d, 0x46, 0xa1, 0x14, 0x0f], "vpscatterqd dword [r15 + zmm25 * 1], k6, zmm10"); test_display(&[0x62, 0x12, 0xfd, 0x46, 0xa1, 0x14, 0x0f], "vpscatterqq qword [r15 + zmm25 * 1], k6, zmm10"); } #[test] fn test_vex() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } fn test_avx2(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx().with_avx2(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } fn test_instr_vex_aesni(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx().with_aesni(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } // prefix 03 test_invalid(&[0xc4, 0b000_00011, 0b1_1111_001, 0x00, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x00, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b1_1111_101, 0x00, 0b11_001_010, 0x77], "vpermq ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_001, 0x01, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x01, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b1_1111_101, 0x01, 0b11_001_010, 0x77], "vpermpd ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_001, 0x02, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x02, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b11_001_010, 0x77], "vpblendd xmm9, xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b00_001_010, 0x77], "vpblendd xmm9, xmm0, xmmword [r10], 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b11_001_010, 0x77], "vpblendd ymm9, ymm0, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b00_001_010, 0x77], "vpblendd ymm9, ymm0, ymmword [r10], 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x04, 0b11_001_010, 0x77], "vpermilps xmm9, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x04, 0b11_001_010, 0x77], "vpermilps ymm9, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x05, 0b11_001_010, 0x77], "vpermilpd xmm9, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x05, 0b11_001_010, 0x77], "vpermilpd ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x06, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b11_001_010, 0x77], "vperm2f128 ymm9, ymm0, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b00_001_010, 0x77], "vperm2f128 ymm9, ymm0, ymmword [r10], 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0c, 0b11_001_010, 0x77], "vblendps xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0c, 0b11_001_010, 0x77], "vblendps ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0d, 0b11_001_010, 0x77], "vblendpd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0d, 0b11_001_010, 0x77], "vblendpd ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0e, 0b11_001_010, 0x77], "vpblendw xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0e, 0b11_001_010, 0x77], "vpblendw ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x08, 0b11_001_010, 0x77], "vroundps xmm9, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x08, 0b11_001_010, 0x77], "vroundps ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x08, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x08, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x09, 0b11_001_010, 0x77], "vroundpd xmm9, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x09, 0b11_001_010, 0x77], "vroundpd ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x09, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x09, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0a, 0b11_001_010, 0x77], "vroundss xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0a, 0b11_001_010, 0x77], "vroundss xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x0b, 0b11_001_010, 0x77], "vroundsd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x0b, 0b11_001_010, 0x77], "vroundsd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x0f, 0b11_001_010, 0x77], "vpalignr xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b1_0111_101, 0x0f, 0b11_001_010, 0x77], "vpalignr ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b11_001_010, 0x77], "vpextrb r10d, xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b00_001_010, 0x77], "vpextrb byte [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x14, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x14, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b11_001_010, 0x77], "vpextrw r10d, xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b00_001_010, 0x77], "vpextrw word [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x15, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x15, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrd r10d, xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrd dword [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x16, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b1_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrq r10, xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0x16, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b1_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrq qword [r10], xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b11_001_010, 0x77], "vextractps r10d, xmm9, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b00_001_010, 0x77], "vextractps dword [r10], xmm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0x18, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x18, 0b11_001_010, 0x77], "vinsertf128 ymm9, ymm8, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0x18, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_101, 0x19, 0b11_001_010, 0x77], "vextractf128 xmm10, ymm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0x18, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b0_0111_101, 0x38, 0b11_001_010, 0x77], "vinserti128 ymm9, ymm8, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0x18, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x39, 0b11_001_010, 0x77], "vextracti128 xmm10, ymm9, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b11_001_010, 0x77], "vpinsrb xmm9, xmm8, r10d, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b00_001_010, 0x77], "vpinsrb xmm9, xmm8, byte [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x20, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x21, 0b11_001_010, 0x77], "vinsertps xmm9, xmm8, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x21, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrd xmm9, xmm8, r10d, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrd xmm9, xmm8, dword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrq xmm9, xmm8, r10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrq xmm9, xmm8, qword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x40, 0b11_001_010, 0x77], "vdpps xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_101, 0x40, 0b11_001_010, 0x77], "vdpps ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x41, 0b11_001_010, 0x77], "vdppd xmm9, xmm8, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x41, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x42, 0b11_001_010, 0x77], "vmpsadbw xmm9, xmm8, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_0111_101, 0x42, 0b11_001_010, 0x77], "vmpsadbw ymm9, ymm8, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b11_001_010, 0x77], "vperm2i128 ymm9, ymm0, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b00_001_010, 0x77], "vperm2i128 ymm9, ymm0, ymmword [r10], 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_001, 0x46, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_1111_101, 0x46, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_0111_001, 0x4c, 0b11_001_010, 0x77], "vpblendvb xmm9, xmm8, xmm10, xmm7"); test_avx2(&[0xc4, 0b000_00011, 0b0_0111_101, 0x4c, 0b11_001_010, 0x77], "vpblendvb ymm9, ymm8, ymm10, ymm7"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0x4c, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0x4c, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x60, 0b11_001_010, 0x77], "vpcmpestrm xmm9, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x60, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x61, 0b11_001_010, 0x77], "vpcmpestri xmm9, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x61, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x62, 0b11_001_010, 0x77], "vpcmpistrm xmm9, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x62, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00011, 0b0_1111_001, 0x63, 0b11_001_010, 0x77], "vpcmpistri xmm9, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b0_1111_101, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_001, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b0_0111_101, 0x63, 0b11_001_010, 0x77]); test_instr_vex_aesni(&[0xc4, 0b000_00011, 0b1_1111_001, 0xdf, 0b11_001_010, 0x77], "vaeskeygenassist xmm9, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_001, 0xdf, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00011, 0b1_0111_101, 0xdf, 0b11_001_010, 0x77]); // prefix 02 test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x00, 0b11_001_010], "vpshufb xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x00, 0b11_001_010], "vpshufb ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x01, 0b11_001_010], "vphaddw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x01, 0b11_001_010], "vphaddw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x02, 0b11_001_010], "vphaddd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x02, 0b11_001_010], "vphaddd ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x03, 0b11_001_010], "vphaddsw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x03, 0b11_001_010], "vphaddsw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x04, 0b11_001_010], "vpmaddubsw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x04, 0b11_001_010], "vpmaddubsw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x05, 0b11_001_010], "vphsubw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x05, 0b11_001_010], "vphsubw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x06, 0b11_001_010], "vphsubd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x06, 0b11_001_010], "vphsubd ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x07, 0b11_001_010], "vphsubsw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x07, 0b11_001_010], "vphsubsw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x08, 0b11_001_010], "vpsignb xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x08, 0b11_001_010], "vpsignb ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x09, 0b11_001_010], "vpsignw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x09, 0b11_001_010], "vpsignw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x0a, 0b11_001_010], "vpsignd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x0a, 0b11_001_010], "vpsignd ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x0b, 0b11_001_010], "vpmulhrsw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x0b, 0b11_001_010], "vpmulhrsw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x0c, 0b11_001_010], "vpermilps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_101, 0x0c, 0b11_001_010], "vpermilps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x0d, 0b11_001_010], "vpermilpd xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_101, 0x0d, 0b11_001_010], "vpermilpd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x0e, 0b11_001_010], "vtestps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x0e, 0b11_001_010], "vtestps ymm9, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x0f, 0b11_001_010], "vtestpd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x0f, 0b11_001_010], "vtestpd ymm9, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b11_001_010], "vpermps ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b00_001_010], "vpermps ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x16, 0b00_011_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x16, 0b00_011_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x17, 0b11_001_010], "vptest xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x17, 0b11_001_010], "vptest ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x17, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x17, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b00_001_010], "vbroadcastss xmm9, dword [r10]"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_001, 0x18, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x18, 0b00_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x19, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x19, 0b00_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1a, 0b00_001_010], "vbroadcastf128 ymm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x1a, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x1a, 0b00_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b00_001_010], "vbroadcasti128 ymm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x5a, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x5a, 0b00_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b11_001_010], "vbroadcastss xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b11_001_010], "vbroadcastss ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x18, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x18, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b11_001_010], "vbroadcastsd ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_001, 0x1a, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x1a, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x1c, 0b11_001_010], "vpabsb xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1c, 0b11_001_010], "vpabsb ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x1c, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x1d, 0b11_001_010], "vpabsw xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1d, 0b11_001_010], "vpabsw ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x1d, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x1e, 0b11_001_010], "vpabsd xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x1e, 0b11_001_010], "vpabsd ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x1e, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x20, 0b11_001_010], "vpmovsxbw xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x20, 0b11_001_010], "vpmovsxbw ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x20, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x21, 0b11_001_010], "vpmovsxbd xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x21, 0b11_001_010], "vpmovsxbd ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x21, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x22, 0b11_001_010], "vpmovsxbq xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x22, 0b11_001_010], "vpmovsxbq ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x22, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x23, 0b11_001_010], "vpmovsxwd xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x23, 0b11_001_010], "vpmovsxwd ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x23, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x24, 0b11_001_010], "vpmovsxwq xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x24, 0b11_001_010], "vpmovsxwq ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x24, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x25, 0b11_001_010], "vpmovsxdq xmm9, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x25, 0b11_001_010], "vpmovsxdq ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x25, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x28, 0b11_001_010], "vpmuldq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x28, 0b11_001_010], "vpmuldq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x29, 0b11_001_010], "vpcmpeqq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x29, 0b11_001_010], "vpcmpeqq ymm9, ymm8, ymm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2a, 0b11_001_010]); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x2a, 0b00_001_010], "vmovntdqa xmm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2a, 0b00_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x2a, 0b00_001_010], "vmovntdqa ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x2b, 0b11_001_010], "vpackusdw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b11_001_010], "vpackusdw ymm9, ymm8, ymm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b00_001_010], "vpackusdw ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x30, 0b11_001_010], "vpmovzxbw xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x30, 0b11_001_010], "vpmovzxbw ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x31, 0b11_001_010], "vpmovzxbd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x31, 0b11_001_010], "vpmovzxbd ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x32, 0b11_001_010], "vpmovzxbq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x32, 0b11_001_010], "vpmovzxbq ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x33, 0b11_001_010], "vpmovzxwd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x33, 0b11_001_010], "vpmovzxwd ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x34, 0b11_001_010], "vpmovzxwq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x34, 0b11_001_010], "vpmovzxwq ymm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x35, 0b11_001_010], "vpmovzxdq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_101, 0x35, 0b11_001_010], "vpmovzxdq ymm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x36, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x36, 0b11_001_010], "vpermd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x37, 0b11_001_010], "vpcmpgtq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x37, 0b11_001_010], "vpcmpgtq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x38, 0b11_001_010], "vpminsb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x38, 0b11_001_010], "vpminsb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x39, 0b11_001_010], "vpminsd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x39, 0b11_001_010], "vpminsd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3a, 0b11_001_010], "vpminuw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3a, 0b11_001_010], "vpminuw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3b, 0b11_001_010], "vpminud xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3b, 0b11_001_010], "vpminud ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3c, 0b11_001_010], "vpmaxsb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3c, 0b11_001_010], "vpmaxsb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3d, 0b11_001_010], "vpmaxsd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3d, 0b11_001_010], "vpmaxsd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3e, 0b11_001_010], "vpmaxuw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3e, 0b11_001_010], "vpmaxuw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x3f, 0b11_001_010], "vpmaxud xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x3f, 0b11_001_010], "vpmaxud ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_0111_001, 0x40, 0b11_001_010], "vpmulld xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_0111_101, 0x40, 0b11_001_010], "vpmulld ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00010, 0b0_1111_001, 0x41, 0b11_001_010], "vphminposuw xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_001, 0x41, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0x41, 0b11_001_010]); // TODO: should something be at opcode 42 here? // test_instr(&[0xc4, 0b000_00010, 0b1_0111_001, 0x42, 0b11_001_010], "vphminposuw xmm"); // test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0x41, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b00_001_010], "vpsrlvd xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b00_001_010], "vpsrlvd ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b11_001_010], "vpsrlvd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b11_001_010], "vpsrlvd ymm9, ymm0, ymm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b00_001_010], "vpsrlvq xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b00_001_010], "vpsrlvq ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b11_001_010], "vpsrlvq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b11_001_010], "vpsrlvq ymm9, ymm0, ymm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x46, 0b00_001_010], "vpsravd xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x46, 0b00_001_010], "vpsravd ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_001, 0x46, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_1111_101, 0x46, 0b00_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b00_001_010], "vpsllvd xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b00_001_010], "vpsllvd ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b11_001_010], "vpsllvd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b11_001_010], "vpsllvd ymm9, ymm0, ymm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b00_001_010], "vpsllvq xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b00_001_010], "vpsllvq ymm9, ymm0, ymmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b11_001_010], "vpsllvq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b11_001_010], "vpsllvq ymm9, ymm0, ymm10"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b00_001_010], "vpmaskmovd xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8c, 0b00_001_010], "vpmaskmovd ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8c, 0b00_001_010], "vpmaskmovq xmm9, xmm0, xmmword [r10]"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8c, 0b00_001_010], "vpmaskmovq ymm9, ymm0, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b00_001_010], "vpmaskmovd xmmword [r10], xmm0, xmm9"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x8e, 0b00_001_010], "vpmaskmovd ymmword [r10], ymm0, ymm9"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x8e, 0b00_001_010], "vpmaskmovq xmmword [r10], xmm0, xmm9"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x8e, 0b00_001_010], "vpmaskmovq ymmword [r10], ymm0, ymm9"); test_invalid(&[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdd xmm8, dword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdd ymm8, dword [r9 + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdq xmm8, qword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdq ymm8, qword [r9 + xmm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm8, dword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm8, dword [r9 + ymm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqq xmm8, qword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqq ymm8, qword [r9 + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdps xmm8, dword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdps ymm8, dword [r9 + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdpd xmm8, qword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdpd ymm8, qword [r9 + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqps xmm8, dword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqps xmm8, dword [r9 + ymm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqpd xmm8, qword [r9 + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqpd ymm8, qword [r9 + ymm12 * 4], ymm0"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b0_1111_001, 0xdb, 0b11_001_010], "vaesimc xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00010, 0b0_0111_101, 0xdb, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00010, 0b1_0111_101, 0xdb, 0b11_001_010]); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_001, 0xdc, 0b11_001_010], "vaesenc xmm9, xmm8, xmm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_101, 0xdc, 0b11_001_010], "vaesenc ymm9, ymm8, ymm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_001, 0xdd, 0b11_001_010], "vaesenclast xmm9, xmm8, xmm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_101, 0xdd, 0b11_001_010], "vaesenclast ymm9, ymm8, ymm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_001, 0xde, 0b11_001_010], "vaesdec xmm9, xmm8, xmm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_101, 0xde, 0b11_001_010], "vaesdec ymm9, ymm8, ymm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_001, 0xdf, 0b11_001_010], "vaesdeclast xmm9, xmm8, xmm10"); test_instr_vex_aesni(&[0xc4, 0b000_00010, 0b1_0111_101, 0xdf, 0b11_001_010], "vaesdeclast ymm9, ymm8, ymm10"); // prefix 01 test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x10, 0b00_001_010], "vmovsd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x10, 0b00_001_010], "vmovsd xmm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x10, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x11, 0b00_001_010], "vmovsd qword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x11, 0b00_001_010], "vmovsd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0x11, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x11, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x10, 0b00_001_010], "vmovss xmm9, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x10, 0b00_001_010], "vmovss xmm9, dword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_010, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_110, 0x10, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x10, 0b00_001_010], "vmovups xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x10, 0b00_001_010], "vmovups ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x11, 0b11_001_010], "vmovsd xmm10, xmm8, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x11, 0b11_001_010], "vmovsd xmm10, xmm8, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x11, 0b00_001_010], "vmovss dword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x11, 0b00_001_010], "vmovss dword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x11, 0b00_001_010], "vmovups xmmword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x11, 0b00_001_010], "vmovups ymmword [r10], ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x12, 0b00_001_010], "vmovddup xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x12, 0b00_001_010], "vmovddup ymm9, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_011, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_111, 0x12, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b11_001_010], "vmovhlps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b00_001_010], "vmovlps xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x12, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0x12, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x12, 0b00_001_010], "vmovlpd xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x12, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x13, 0b00_001_010], "vmovlpd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x13, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x13, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x14, 0b00_001_010], "vunpcklps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x14, 0b00_001_010], "vunpcklps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x14, 0b00_001_010], "vunpcklpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x14, 0b00_001_010], "vunpcklpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0x15, 0b00_001_010], "vunpckhps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0x15, 0b00_001_010], "vunpckhps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x15, 0b00_001_010], "vunpckhpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x15, 0b00_001_010], "vunpckhpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x16, 0b11_001_010], "vmovshdup xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x16, 0b11_001_010], "vmovshdup ymm9, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_010, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_110, 0x16, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x16, 0b00_001_010], "vmovhps xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x16, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x16, 0b00_001_010], "vmovhpd xmm9, xmm8, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x16, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x16, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x17, 0b00_001_010], "vmovhps qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_100, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_000, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_100, 0x17, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x17, 0b00_001_010], "vmovhpd qword [r10], xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x17, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x28, 0b11_001_010], "vmovaps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x28, 0b11_001_010], "vmovaps ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x29, 0b11_001_010], "vmovaps xmm10, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x29, 0b11_001_010], "vmovaps ymm10, ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x28, 0b11_001_010], "vmovapd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x28, 0b11_001_010], "vmovapd ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x29, 0b11_001_010], "vmovapd xmm10, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x29, 0b11_001_010], "vmovapd ymm10, ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10d"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2a, 0b11_001_010], "vcvtsi2ss xmm9, xmm0, r10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10d"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10d"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, r10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm9, xmm0, qword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, edx"); test_instr(&[0xc5, 0b0_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm9, xmm0, edx"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b00_001_010], "vmovntps xmmword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b00_001_010], "vmovntps ymmword [r10], ymm9"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b00_001_010], "vmovntpd xmmword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b00_001_010], "vmovntpd ymmword [r10], ymm9"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2c, 0b00_001_010], "vcvttss2si r9d, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2c, 0b00_001_010], "vcvttss2si r9, dword [r10]"); test_instr(&[0xc5, 0b0_1111_010, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_010, 0x2c, 0b00_001_010], "vcvttss2si r9d, dword [rdx]"); test_instr(&[0xc5, 0b0_1111_110, 0x2c, 0b11_001_010], "vcvttss2si r9d, xmm2"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, qword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si r9d, qword [rdx]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9d, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x2d, 0b00_001_010], "vcvtss2si r9, dword [r10]"); test_instr(&[0xc5, 0b0_1111_010, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_110, 0x2d, 0b11_001_010], "vcvtss2si r9d, xmm2"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9d, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b00_001_010], "vcvtsd2si r9d, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si r9, qword [r10]"); test_instr(&[0xc5, 0b0_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm2"); test_instr(&[0xc5, 0b0_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si r9d, xmm2"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b00_001_010], "vucomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b00_001_010], "vucomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b11_001_010], "vucomisd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b11_001_010], "vucomisd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b00_001_010], "vcomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b00_001_010], "vcomisd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b11_001_010], "vcomisd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b11_001_010], "vcomisd xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_001, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_101, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_001, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_101, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_001, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_101, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_001, 0x2f, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_0111_101, 0x2f, 0b11_001_010]); test_instr(&[0xc5, 0b0_1111_000, 0x2e, 0b11_001_010], "vucomiss xmm9, xmm2"); test_instr(&[0xc5, 0b0_1111_100, 0x2e, 0b00_001_010], "vucomiss xmm9, dword [rdx]"); test_instr(&[0xc5, 0b0_1111_000, 0x2f, 0b11_001_010], "vcomiss xmm9, xmm2"); test_instr(&[0xc5, 0b0_1111_100, 0x2f, 0b00_001_010], "vcomiss xmm9, dword [rdx]"); test_invalid(&[0xc5, 0b0_1111_111, 0x2f, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x50, 0b11_001_010], "vmovmskps r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x50, 0b11_001_010], "vmovmskps r9d, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_000, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_100, 0x50, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x50, 0b11_001_010], "vmovmskpd r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x50, 0b11_001_010], "vmovmskpd r9d, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x50, 0b11_001_010], "vmovmskpd r9d, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x50, 0b11_001_010], "vmovmskpd r9d, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_101, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_101, 0x50, 0b00_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x51, 0b00_001_010], "vsqrtpd xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x51, 0b00_001_010], "vsqrtpd ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x51, 0b00_001_010], "vsqrtsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x51, 0b00_001_010], "vsqrtps xmm9, xmmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_000, 0x51, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x51, 0b00_001_010], "vsqrtps ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x51, 0b00_001_010], "vsqrtss xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x52, 0b11_001_010], "vrsqrtps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x52, 0b11_001_010], "vrsqrtps ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x52, 0b11_001_010], "vrsqrtss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x52, 0b11_001_010], "vrsqrtss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x53, 0b11_001_010], "vrcpps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x53, 0b11_001_010], "vrcpps ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x53, 0b11_001_010], "vrcpss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x53, 0b11_001_010], "vrcpss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x54, 0b11_001_010], "vandps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x54, 0b11_001_010], "vandps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x55, 0b11_001_010], "vandnps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x55, 0b11_001_010], "vandnps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x54, 0b00_001_010], "vandpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x54, 0b00_001_010], "vandpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x55, 0b00_001_010], "vandnpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x55, 0b00_001_010], "vandnpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x56, 0b00_001_010], "vorpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x56, 0b00_001_010], "vorpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x56, 0b00_001_010], "vorps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x56, 0b00_001_010], "vorps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x57, 0b11_001_010], "vxorps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x57, 0b11_001_010], "vxorps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x57, 0b11_001_010], "vxorpd xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x57, 0b11_001_010], "vxorpd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x58, 0b11_001_010], "vaddps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x58, 0b11_001_010], "vaddps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b11_001_010], "vaddss xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b11_001_010], "vaddss xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b00_001_010], "vaddss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x58, 0b00_001_010], "vaddpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x58, 0b00_001_010], "vaddpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x58, 0b00_001_010], "vaddsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x59, 0b00_001_010], "vmulps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x59, 0b00_001_010], "vmulps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x59, 0b00_001_010], "vmulpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x59, 0b00_001_010], "vmulpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x59, 0b00_001_010], "vmulss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x59, 0b00_001_010], "vmulsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b11_001_010], "vcvtps2pd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b11_001_010], "vcvtps2pd ymm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b00_001_010], "vcvtps2pd xmm9, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b00_001_010], "vcvtps2pd ymm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x5a, 0b11_001_010], "vcvtpd2ps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x5a, 0b11_001_010], "vcvtpd2ps xmm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x5a, 0b11_001_010], "vcvtsd2ss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x5a, 0b11_001_010], "vcvtsd2ss xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x5a, 0b00_001_010], "vcvtsd2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0x5a, 0b00_001_010], "vcvtsd2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_011, 0x5a, 0b00_001_010], "vcvtsd2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_111, 0x5a, 0b00_001_010], "vcvtsd2ss xmm9, xmm0, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x5a, 0b11_001_010], "vcvtss2sd xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x5a, 0b11_001_010], "vcvtss2sd xmm9, xmm0, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x5a, 0b00_001_010], "vcvtss2sd xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x5a, 0b00_001_010], "vcvtss2sd xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x5a, 0b00_001_010], "vcvtss2sd xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x5a, 0b00_001_010], "vcvtss2sd xmm9, xmm0, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x5b, 0b11_001_010], "vcvtps2dq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x5b, 0b11_001_010], "vcvtps2dq ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x5b, 0b11_001_010], "vcvttps2dq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0x5b, 0b11_001_010], "vcvttps2dq ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b11_001_010], "vcvtdq2ps xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b00_001_010], "vcvtdq2ps xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b11_001_010], "vcvtdq2ps ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b00_001_010], "vcvtdq2ps ymm9, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0x5c, 0b00_001_010], "vsubps xmm9, xmm0, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_100, 0x5c, 0b00_001_010], "vsubps ymm9, ymm0, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_010, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_110, 0x5c, 0b00_001_010], "vsubss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x5c, 0b00_001_010], "vsubpd xmm9, xmm0, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x5c, 0b00_001_010], "vsubpd ymm9, ymm0, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_011, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_111, 0x5c, 0b00_001_010], "vsubsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5d, 0b00_001_010], "vminps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5d, 0b00_001_010], "vminps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5d, 0b00_001_010], "vminss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5d, 0b00_001_010], "vminpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5d, 0b00_001_010], "vminpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5d, 0b00_001_010], "vminsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5e, 0b00_001_010], "vdivpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5e, 0b00_001_010], "vdivps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5e, 0b00_001_010], "vdivpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5e, 0b00_001_010], "vdivss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5e, 0b00_001_010], "vdivsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0x5f, 0b00_001_010], "vmaxps xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x5f, 0b00_001_010], "vmaxpd xmm9, xmm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_010, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0x5f, 0b00_001_010], "vmaxps ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x5f, 0b00_001_010], "vmaxpd ymm9, ymm8, ymmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_110, 0x5f, 0b00_001_010], "vmaxss xmm9, xmm8, dword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x5f, 0b00_001_010], "vmaxsd xmm9, xmm8, qword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x60, 0b11_001_010], "vpunpcklbw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x60, 0b11_001_010], "vpunpcklbw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x61, 0b11_001_010], "vpunpcklwd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x61, 0b11_001_010], "vpunpcklwd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x62, 0b11_001_010], "vpunpckldq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x62, 0b11_001_010], "vpunpckldq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x63, 0b11_001_010], "vpacksswb xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0x63, 0b11_001_010], "vpacksswb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x64, 0b11_001_010], "vpcmpgtb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x64, 0b11_001_010], "vpcmpgtb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x65, 0b11_001_010], "vpcmpgtw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x65, 0b11_001_010], "vpcmpgtw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x66, 0b11_001_010], "vpcmpgtd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x66, 0b11_001_010], "vpcmpgtd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x67, 0b11_001_010], "vpackuswb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x67, 0b11_001_010], "vpackuswb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x68, 0b11_001_010], "vpunpckhbw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x68, 0b11_001_010], "vpunpckhbw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x69, 0b11_001_010], "vpunpckhwd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x69, 0b11_001_010], "vpunpckhwd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x6a, 0b11_001_010], "vpunpckhdq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x6a, 0b11_001_010], "vpunpckhdq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0x6b, 0b11_001_010], "vpackssdw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0x6b, 0b11_001_010], "vpackssdw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6c, 0b11_001_010], "vpunpcklqdq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x6c, 0b11_001_010], "vpunpcklqdq ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6d, 0b11_001_010], "vpunpckhqdq xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x6d, 0b11_001_010], "vpunpckhqdq ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b11_001_010], "vmovq xmm9, r10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b00_001_010], "vmovq xmm9, qword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x6e, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x6f, 0b11_001_010], "vmovdqa xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x6f, 0b11_001_010], "vmovdqa ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x6f, 0b11_001_010], "vmovdqu xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x6f, 0b11_001_010], "vmovdqu ymm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x70, 0b11_001_010, 0x77], "vpshufd xmm9, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x70, 0b11_001_010, 0x77], "vpshufd ymm9, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0x70, 0b11_001_010, 0x77], "vpshufhw xmm9, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_110, 0x70, 0b11_001_010, 0x77], "vpshufhw ymm9, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0x70, 0b11_001_010, 0x77], "vpshuflw xmm9, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_111, 0x70, 0b11_001_010, 0x77], "vpshuflw ymm9, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_010_010, 0x77], "vpsrlw xmm0, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x71, 0b11_010_010, 0x77], "vpsrlw xmm8, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_010_010, 0x77], "vpsrlw ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b00_011_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_100_010, 0x77], "vpsraw xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_100_010, 0x77], "vpsraw ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_101_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_110_010, 0x77], "vpsllw xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_110_010, 0x77], "vpsllw ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_000_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_010_010, 0x77], "vpsrld xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_010_010, 0x77], "vpsrld ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_011_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_100_010, 0x77], "vpsrad xmm0, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_100_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_100_010, 0x77], "vpsrad ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_101_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_110_010, 0x77], "vpslld xmm0, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_110_010, 0x77]); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_110_010, 0x77], "vpslld ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b00_111_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_000_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_010_010, 0x77], "vpsrlq xmm0, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_011_010, 0x77], "vpsrldq xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_010_010, 0x77], "vpsrlq ymm0, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_011_010, 0x77], "vpsrldq ymm0, ymm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_100_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_101_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_110_010, 0x77], "vpsllq xmm0, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_111_010, 0x77], "vpslldq xmm0, xmm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_110_010, 0x77], "vpsllq ymm0, ymm10, 0x77"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_111_010, 0x77], "vpslldq ymm0, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x74, 0b11_001_010], "vpcmpeqb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0x74, 0b11_001_010], "vpcmpeqb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x75, 0b11_001_010], "vpcmpeqw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0x75, 0b11_001_010], "vpcmpeqw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x76, 0b11_001_010], "vpcmpeqd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0x76, 0b11_001_010], "vpcmpeqd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x7c, 0b11_001_010], "vhaddpd xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x7c, 0b11_001_010], "vhaddpd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x7c, 0b11_001_010], "vhaddps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x7c, 0b11_001_010], "vhaddps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0x7d, 0b11_001_010], "vhsubpd xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0x7d, 0b11_001_010], "vhsubpd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0x7d, 0b11_001_010], "vhsubps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0x7d, 0b11_001_010], "vhsubps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x7e, 0b11_001_010], "vmovd r10d, xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_101, 0x7e, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0x7e, 0b11_001_010], "vmovq r10, xmm9"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0x7e, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0x7f, 0b11_001_010], "vmovdqa xmm10, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_101, 0x7f, 0b11_001_010], "vmovdqa ymm10, ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_010, 0x7f, 0b11_001_010], "vmovdqu xmm10, xmm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_110, 0x7f, 0b11_001_010], "vmovdqu ymm10, ymm9"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_010_001], "vldmxcsr dword [r9]"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_100, 0xae, 0b00_010_001]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b11_010_001]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_011_001], "vstmxcsr dword [r9]"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_100, 0xae, 0b00_011_001]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b11_011_001]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_000, 0xc2, 0b11_001_010, 0x77], "vcmpps xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_100, 0xc2, 0b11_001_010, 0x77], "vcmpps ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xc2, 0b11_001_010, 0x77], "vcmppd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0xc2, 0b11_001_010, 0x77], "vcmppd ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0xc2, 0b11_001_010, 0x77], "vcmpsd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0xc2, 0b11_001_010, 0x77], "vcmpsd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xc4, 0b11_001_010, 0x77], "vpinsrw xmm9, xmm8, r10d, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0xc4, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_001, 0xc5, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0xc5, 0b11_001_010, 0x77], "vpextrw r9d, xmm10, 0x77"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0xc5, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0xc5, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xc6, 0b11_001_010, 0x77], "vshufpd xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_101, 0xc6, 0b11_001_010, 0x77], "vshufpd ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_000, 0xc6, 0b11_001_010, 0x77], "vshufps xmm9, xmm8, xmm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_100, 0xc6, 0b11_001_010, 0x77], "vshufps ymm9, ymm8, ymm10, 0x77"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd0, 0b11_001_010], "vaddsubpd xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd0, 0b11_001_010], "vaddsubpd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_011, 0xd0, 0b11_001_010], "vaddsubps xmm9, xmm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_111, 0xd0, 0b11_001_010], "vaddsubps ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd1, 0b11_001_010], "vpsrlw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b11_001_010], "vpsrlw ymm9, ymm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b00_001_010], "vpsrlw ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd2, 0b11_001_010], "vpsrld xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b11_001_010], "vpsrld ymm9, ymm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b00_001_010], "vpsrld ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd3, 0b11_001_010], "vpsrlq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b11_001_010], "vpsrlq ymm9, ymm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b00_001_010], "vpsrlq ymm9, ymm8, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd4, 0b11_001_010], "vpaddq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd4, 0b11_001_010], "vpaddq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xd5, 0b11_001_010], "vpmullw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xd5, 0b11_001_010], "vpmullw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_1111_001, 0xd7, 0b11_001_010], "vpmovmskb r9d, xmm10"); test_invalid(&[0xc4, 0b000_00001, 0b0_1111_001, 0xd7, 0b00_001_010]); test_avx2(&[0xc4, 0b000_00001, 0b0_1111_101, 0xd7, 0b11_001_010], "vpmovmskb r9d, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd8, 0b11_001_010], "vpsubusb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd8, 0b11_001_010], "vpsubusb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xd9, 0b11_001_010], "vpsubusw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xd9, 0b11_001_010], "vpsubusw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xda, 0b11_001_010], "vpminub xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xda, 0b11_001_010], "vpminub ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xdb, 0b11_001_010], "vpand xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xdb, 0b11_001_010], "vpand ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xdc, 0b11_001_010], "vpaddusb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xdc, 0b11_001_010], "vpaddusb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xdd, 0b11_001_010], "vpaddusw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xdd, 0b11_001_010], "vpaddusw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xde, 0b11_001_010], "vpmaxub xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xde, 0b11_001_010], "vpmaxub ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xdf, 0b11_001_010], "vpandn xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xdf, 0b11_001_010], "vpandn ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe0, 0b11_001_010], "vpavgb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe0, 0b11_001_010], "vpavgb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe1, 0b11_001_010], "vpsraw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe1, 0b11_001_010], "vpsraw ymm9, ymm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe2, 0b11_001_010], "vpsrad xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe2, 0b11_001_010], "vpsrad ymm9, ymm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe3, 0b11_001_010], "vpavgw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe3, 0b11_001_010], "vpavgw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe4, 0b11_001_010], "vpmulhuw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe4, 0b11_001_010], "vpmulhuw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe5, 0b11_001_010], "vpmulhw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe5, 0b11_001_010], "vpmulhw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe6, 0b11_001_010], "vcvttpd2dq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe6, 0b11_001_010], "vcvttpd2dq xmm9, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_010, 0xe6, 0b11_001_010], "vcvtdq2pd xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_110, 0xe6, 0b11_001_010], "vcvtdq2pd ymm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0xe6, 0b11_001_010], "vcvtpd2dq xmm9, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0xe6, 0b11_001_010], "vcvtpd2dq xmm9, ymm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b00_001_010], "vmovntdq xmmword [r10], xmm9"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b00_001_010], "vmovntdq ymmword [r10], ymm9"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe8, 0b11_001_010], "vpsubsb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe8, 0b11_001_010], "vpsubsb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xe9, 0b11_001_010], "vpsubsw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xe9, 0b11_001_010], "vpsubsw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xea, 0b11_001_010], "vpminsw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xea, 0b11_001_010], "vpminsw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xeb, 0b11_001_010], "vpor xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xeb, 0b11_001_010], "vpor ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xec, 0b11_001_010], "vpaddsb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xec, 0b11_001_010], "vpaddsb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xed, 0b11_001_010], "vpaddsw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xed, 0b11_001_010], "vpaddsw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xee, 0b11_001_010], "vpmaxsw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xee, 0b11_001_010], "vpmaxsw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b0_0111_001, 0xef, 0b11_001_010], "vpxor xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b0_0111_101, 0xef, 0b11_001_010], "vpxor ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b00_001_010], "vlddqu xmm9, xmmword [r10]"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_111, 0xf0, 0b00_001_010], "vlddqu ymm9, ymmword [r10]"); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_0111_111, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_111, 0xf0, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf1, 0b11_001_010], "vpsllw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf1, 0b11_001_010], "vpsllw ymm9, ymm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf2, 0b11_001_010], "vpslld xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf2, 0b11_001_010], "vpslld ymm9, ymm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf3, 0b11_001_010], "vpsllq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf3, 0b11_001_010], "vpsllq ymm9, ymm8, xmm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf4, 0b11_001_010], "vpmuludq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf4, 0b11_001_010], "vpmuludq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xf5, 0b11_001_010], "vpmaddwd xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0xf5, 0b11_001_010], "vpmaddwd ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xf6, 0b11_001_010], "vpsadbw xmm9, xmm0, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_1111_101, 0xf6, 0b11_001_010], "vpsadbw ymm9, ymm0, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_1111_001, 0xf7, 0b11_001_010], "vmaskmovdqu xmm9, xmm10"); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_001, 0xf7, 0b00_001_010]); test_invalid(&[0xc4, 0b000_00001, 0b1_1111_101, 0xf7, 0b11_001_010]); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf8, 0b11_001_010], "vpsubb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf8, 0b11_001_010], "vpsubb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xf9, 0b11_001_010], "vpsubw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xf9, 0b11_001_010], "vpsubw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfa, 0b11_001_010], "vpsubd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfa, 0b11_001_010], "vpsubd ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfb, 0b11_001_010], "vpsubq xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfb, 0b11_001_010], "vpsubq ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfc, 0b11_001_010], "vpaddb xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfc, 0b11_001_010], "vpaddb ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfd, 0b11_001_010], "vpaddw xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfd, 0b11_001_010], "vpaddw ymm9, ymm8, ymm10"); test_instr(&[0xc4, 0b000_00001, 0b1_0111_001, 0xfe, 0b11_001_010], "vpaddd xmm9, xmm8, xmm10"); test_avx2(&[0xc4, 0b000_00001, 0b1_0111_101, 0xfe, 0b11_001_010], "vpaddd ymm9, ymm8, ymm10"); test_instr(&[0xc5, 0xf8, 0x10, 0x00], "vmovups xmm0, xmmword [rax]"); test_instr(&[0xc5, 0xf8, 0x10, 0x01], "vmovups xmm0, xmmword [rcx]"); test_instr(&[0xc5, 0x78, 0x10, 0x0f], "vmovups xmm9, xmmword [rdi]"); test_instr(&[0xc5, 0xf8, 0x10, 0xcf], "vmovups xmm1, xmm7"); test_instr(&[0xc5, 0xf9, 0x10, 0x0f], "vmovupd xmm1, xmmword [rdi]"); test_instr(&[0xc5, 0xfa, 0x7e, 0x10], "vmovq xmm2, qword [rax]"); test_instr(&[0xc5, 0xfc, 0x10, 0x0f], "vmovups ymm1, ymmword [rdi]"); test_instr(&[0xc5, 0xfd, 0x10, 0x0f], "vmovupd ymm1, ymmword [rdi]"); test_instr(&[0xc5, 0xfe, 0x10, 0x0f], "vmovss xmm1, dword [rdi]"); test_instr(&[0xc5, 0xff, 0x10, 0xcf], "vmovsd xmm1, xmm0, xmm7"); test_instr(&[0xc5, 0xff, 0x10, 0x01], "vmovsd xmm0, qword [rcx]"); test_instr(&[0xc5, 0xf9, 0x6e, 0xc6], "vmovd xmm0, esi"); test_instr(&[0xc5, 0xf9, 0x6e, 0x13], "vmovd xmm2, dword [rbx]"); test_instr(&[0xc5, 0xf9, 0x7e, 0xc6], "vmovd esi, xmm0"); test_instr(&[0xc5, 0xf9, 0x7e, 0x13], "vmovd dword [rbx], xmm2"); test_instr_invalid(&[0x4f, 0xc5, 0xf8, 0x10, 0x00]); test_instr_invalid(&[0xf0, 0xc5, 0xf8, 0x10, 0x00]); test_instr(&[0xc4, 0x02, 0x71, 0x00, 0x0f], "vpshufb xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x00, 0x0f], "vpshufb ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x00, 0xcd], "vpshufb xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x00, 0xcd], "vpshufb ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x01, 0x0f], "vphaddw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x01, 0x0f], "vphaddw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x01, 0xcd], "vphaddw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x01, 0xcd], "vphaddw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x02, 0x0f], "vphaddd xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x02, 0x0f], "vphaddd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x02, 0xcd], "vphaddd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x02, 0xcd], "vphaddd ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x03, 0x0f], "vphaddsw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x03, 0x0f], "vphaddsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x03, 0xcd], "vphaddsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x03, 0xcd], "vphaddsw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x04, 0x0f], "vpmaddubsw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x04, 0x0f], "vpmaddubsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x04, 0xcd], "vpmaddubsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x04, 0xcd], "vpmaddubsw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x05, 0x0f], "vphsubw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x05, 0x0f], "vphsubw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x05, 0xcd], "vphsubw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x05, 0xcd], "vphsubw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x06, 0x0f], "vphsubd xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x06, 0x0f], "vphsubd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x06, 0xcd], "vphsubd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x06, 0xcd], "vphsubd ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x07, 0x0f], "vphsubsw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x07, 0x0f], "vphsubsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x07, 0xcd], "vphsubsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x07, 0xcd], "vphsubsw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x08, 0x0f], "vpsignb xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x08, 0x0f], "vpsignb ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x08, 0xcd], "vpsignb xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x08, 0xcd], "vpsignb ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x09, 0x0f], "vpsignw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x09, 0x0f], "vpsignw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x09, 0xcd], "vpsignw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x09, 0xcd], "vpsignw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x0a, 0x0f], "vpsignd xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x0a, 0x0f], "vpsignd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0a, 0xcd], "vpsignd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0a, 0xcd], "vpsignd ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x0b, 0x0f], "vpmulhrsw xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x0b, 0x0f], "vpmulhrsw ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0b, 0xcd], "vpmulhrsw xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0b, 0xcd], "vpmulhrsw ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x0c, 0x0f], "vpermilps xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x0c, 0x0f], "vpermilps ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0c, 0xcd], "vpermilps xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0c, 0xcd], "vpermilps ymm9, ymm1, ymm13"); test_instr(&[0xc4, 0x02, 0x71, 0x0d, 0x0f], "vpermilpd xmm9, xmm1, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x75, 0x0d, 0x0f], "vpermilpd ymm9, ymm1, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x71, 0x0d, 0xcd], "vpermilpd xmm9, xmm1, xmm13"); test_instr(&[0xc4, 0x02, 0x75, 0x0d, 0xcd], "vpermilpd ymm9, ymm1, ymm13"); test_instr_invalid(&[0xc4, 0x02, 0x71, 0x0e, 0x00]); test_instr(&[0xc4, 0x02, 0x79, 0x0e, 0x0f], "vtestps xmm9, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x7d, 0x0e, 0x0f], "vtestps ymm9, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x79, 0x0e, 0xcd], "vtestps xmm9, xmm13"); test_instr(&[0xc4, 0x02, 0x7d, 0x0e, 0xcd], "vtestps ymm9, ymm13"); test_instr_invalid(&[0xc4, 0x02, 0x71, 0x0f, 0x00]); test_instr(&[0xc4, 0x02, 0x79, 0x0f, 0x0f], "vtestpd xmm9, xmmword [r15]"); test_instr(&[0xc4, 0x02, 0x7d, 0x0f, 0x0f], "vtestpd ymm9, ymmword [r15]"); test_instr(&[0xc4, 0x02, 0x79, 0x0f, 0xcd], "vtestpd xmm9, xmm13"); test_instr(&[0xc4, 0x02, 0x7d, 0x0f, 0xcd], "vtestpd ymm9, ymm13"); test_instr(&[0xc4, 0xe2, 0x65, 0x90, 0x04, 0x51], "vpgatherdd ymm0, dword [rcx + ymm2 * 2], ymm3"); test_instr(&[0xc4, 0xe2, 0xe5, 0x90, 0x04, 0x51], "vpgatherdq ymm0, qword [rcx + xmm2 * 2], ymm3"); test_instr(&[0xc4, 0xe2, 0x65, 0x91, 0x04, 0x51], "vpgatherqd xmm0, dword [rcx + ymm2 * 2], xmm3"); test_instr(&[0xc4, 0xe2, 0xe5, 0x91, 0x04, 0x51], "vpgatherqq ymm0, qword [rcx + ymm2 * 2], ymm3"); test_instr(&[0xc4, 0x02, 0x09, 0x9d, 0xcd], "vfnmadd132ss xmm9, xmm14, xmm13"); test_instr(&[0xc4, 0x02, 0x89, 0x9d, 0xcd], "vfnmadd132sd xmm9, xmm14, xmm13"); // ... test_instr(&[0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x0a], "vpextrb eax, xmm2, 0xa"); test_instr(&[0xc4, 0xe3, 0x79, 0x14, 0x10, 0x0a], "vpextrb byte [rax], xmm2, 0xa"); test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0xd0]); test_instr_invalid(&[0xc4, 0xe3, 0xf9, 0x14, 0x00, 0x0a]); test_instr(&[0xc5, 0xed, 0x71, 0xd0, 0x04], "vpsrlw ymm2, ymm0, 0x4"); test_instr(&[0xc5, 0xed, 0x73, 0xd4, 0x20], "vpsrlq ymm2, ymm4, 0x20"); test_instr(&[0xc4, 0xe3, 0xfd, 0x00, 0xc1, 0xa8], "vpermq ymm0, ymm1, 0xa8"); test_instr(&[0xc5, 0xfd, 0xea, 0xd1], "vpminsw ymm2, ymm0, ymm1"); test_instr(&[0xc5, 0xfd, 0xee, 0xd9], "vpmaxsw ymm3, ymm0, ymm1"); test_instr(&[0xc4, 0xe3, 0x7d, 0x19, 0xd1, 0x01], "vextractf128 xmm1, ymm2, 0x1"); test_instr(&[0xc4, 0xc3, 0x75, 0x38, 0x7c, 0x12, 0x05, 0x01], "vinserti128 ymm7, ymm1, xmmword [r10 + rdx * 1 + 0x5], 0x1"); test_instr(&[0xc4, 0xc3, 0x75, 0x42, 0x7c, 0x12, 0x05, 0x61], "vmpsadbw ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], 0x61"); test_instr(&[0xc4, 0xc3, 0x75, 0x46, 0x7c, 0x12, 0x05, 0x61], "vperm2i128 ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], 0x61"); test_instr(&[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], "vblendvps xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4a, 0xdc, 0x61], "vblendvps xmm3, xmm1, xmm12, xmm6"); test_instr(&[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd ymm7, ymm1, ymmword [r10 + rdx * 1 + 0x5], ymm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], "vblendvpd xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4b, 0xdc, 0x61], "vblendvpd xmm3, xmm1, xmm12, xmm6"); test_instr(&[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], "vpblendvb xmm7, xmm1, xmmword [r10 + rdx * 1 + 0x5], xmm6"); test_instr(&[0xc5, 0xc9, 0xf1, 0x0f], "vpsllw xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf1, 0xcf], "vpsllw xmm1, xmm6, xmm7"); test_instr(&[0xc5, 0xcd, 0xf1, 0x0f], "vpsllw ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf1, 0xcf], "vpsllw ymm1, ymm6, xmm7"); test_instr(&[0xc5, 0xc9, 0xf2, 0x0f], "vpslld xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf2, 0xcf], "vpslld xmm1, xmm6, xmm7"); test_instr(&[0xc5, 0xcd, 0xf2, 0x0f], "vpslld ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf2, 0xcf], "vpslld ymm1, ymm6, xmm7"); test_instr(&[0xc5, 0xc9, 0xf3, 0x0f], "vpsllq xmm1, xmm6, xmmword [rdi]"); test_instr(&[0xc5, 0xc9, 0xf3, 0xcf], "vpsllq xmm1, xmm6, xmm7"); test_instr(&[0xc5, 0xcd, 0xf3, 0x0f], "vpsllq ymm1, ymm6, xmmword [rdi]"); test_instr(&[0xc5, 0xcd, 0xf3, 0xcf], "vpsllq ymm1, ymm6, xmm7"); test_instr(&[0xc5, 0xf1, 0xc4, 0xd8, 0x78], "vpinsrw xmm3, xmm1, eax, 0x78"); test_instr(&[0xc5, 0xf1, 0xc4, 0x18, 0x78], "vpinsrw xmm3, xmm1, word [rax], 0x78"); test_instr(&[0xc5, 0xe0, 0x54, 0x03], "vandps xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc5, 0xe1, 0x54, 0x03], "vandpd xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc5, 0xe0, 0x55, 0x03], "vandnps xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc5, 0xe1, 0x55, 0x03], "vandnpd xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc5, 0xe0, 0x56, 0x03], "vorps xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc5, 0xe1, 0x56, 0x03], "vorpd xmm0, xmm3, xmmword [rbx]"); test_instr(&[0xc4, 0xa2, 0x15, 0x3e, 0x14, 0xb9], "vpmaxuw ymm2, ymm13, ymmword [rcx + r15 * 4]"); } #[test] fn strange_prefixing() { test_display(&[0x45, 0x66, 0x0f, 0x21, 0xc8], "mov rax, dr1"); test_display(&[0x45, 0xf2, 0x0f, 0x21, 0xc8], "mov rax, dr1"); test_display(&[0x45, 0xf3, 0x0f, 0x21, 0xc8], "mov rax, dr1"); } #[test] fn prefixed_0f() { test_display(&[0x0f, 0x02, 0x01], "lar eax, word [rcx]"); test_display(&[0x0f, 0x02, 0xc1], "lar eax, ecx"); test_display(&[0x4f, 0x0f, 0x02, 0x01], "lar r8, word [r9]"); test_display(&[0x4f, 0x0f, 0x02, 0xc1], "lar r8, r9"); test_display(&[0x66, 0x0f, 0x02, 0x01], "lar ax, word [rcx]"); test_display(&[0x66, 0x0f, 0x02, 0xc1], "lar ax, cx"); test_display(&[0x0f, 0x03, 0x01], "lsl eax, word [rcx]"); test_display(&[0x0f, 0x03, 0xc1], "lsl eax, ecx"); test_display(&[0x48, 0x0f, 0x03, 0x01], "lsl rax, word [rcx]"); // capstone says `lsl rax, rcx`, but xed says `rax, ecx`. intel docs also say second reg should // be dword. test_display(&[0x48, 0x0f, 0x03, 0xc1], "lsl rax, ecx"); test_display(&[0x66, 0x0f, 0x03, 0x01], "lsl ax, word [rcx]"); test_display(&[0x66, 0x0f, 0x03, 0xc1], "lsl ax, cx"); test_display(&[0x0f, 0x05], "syscall"); test_display(&[0x48, 0x0f, 0x05], "syscall"); test_display(&[0x66, 0x0f, 0x05], "syscall"); test_display(&[0x0f, 0x06], "clts"); test_display(&[0xf2, 0x0f, 0x06], "clts"); test_display(&[0x0f, 0x07], "sysret"); test_display(&[0xf2, 0x0f, 0x07], "sysret"); test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, qword [rdi]"); test_display(&[0x0f, 0x12, 0xcf], "movhlps xmm1, xmm7"); test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [rdi]"); test_display(&[0x0f, 0x16, 0xcf], "movlhps xmm1, xmm7"); test_display(&[0x0f, 0x12, 0xc0], "movhlps xmm0, xmm0"); test_invalid(&[0x0f, 0x13, 0xc0]); test_display(&[0x0f, 0x13, 0x00], "movlps qword [rax], xmm0"); test_display(&[0x0f, 0x14, 0x08], "unpcklps xmm1, xmmword [rax]"); test_display(&[0x0f, 0x15, 0x08], "unpckhps xmm1, xmmword [rax]"); test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [rdi]"); test_display(&[0x0f, 0x16, 0xc0], "movlhps xmm0, xmm0"); test_invalid(&[0x0f, 0x17, 0xc0]); test_display(&[0x0f, 0x17, 0x00], "movhps qword [rax], xmm0"); test_display(&[0x0f, 0x18, 0xc0], "nop eax"); // capstone says invalid, xed says nop test_display(&[0x0f, 0x18, 0x00], "prefetchnta zmmword [rax]"); test_display(&[0x0f, 0x18, 0x08], "prefetch0 zmmword [rax]"); test_display(&[0x0f, 0x18, 0x10], "prefetch1 zmmword [rax]"); test_display(&[0x0f, 0x18, 0x18], "prefetch2 zmmword [rax]"); test_display(&[0x0f, 0x18, 0x20], "nop zmmword [rax]"); test_display(&[0x4f, 0x0f, 0x18, 0x20], "nop zmmword [r8]"); test_display(&[0x0f, 0x18, 0xcc], "nop esp"); test_display(&[0x0f, 0x19, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1a, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1b, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1c, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1d, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1e, 0x20], "nop dword [rax]"); test_display(&[0x0f, 0x1f, 0x20], "nop dword [rax]"); test_invalid(&[0x45, 0x0f, 0x20, 0xc8]); test_display(&[0x45, 0x0f, 0x20, 0xc0], "mov r8, cr8"); test_invalid(&[0x0f, 0x20, 0xc8]); test_invalid(&[0x45, 0x0f, 0x21, 0xc8]); test_display(&[0x0f, 0x21, 0xc8], "mov rax, dr1"); test_invalid(&[0x45, 0x0f, 0x22, 0xc8]); test_display(&[0x45, 0x0f, 0x22, 0xc0], "mov cr8, r8"); test_invalid(&[0x40, 0x0f, 0x22, 0xc8]); test_invalid(&[0x0f, 0x22, 0xc8]); test_display(&[0x0f, 0x22, 0xc0], "mov cr0, rax"); test_invalid(&[0x44, 0x0f, 0x22, 0xcf]); test_display(&[0x0f, 0x22, 0xc7], "mov cr0, rdi"); test_invalid(&[0x0f, 0x22, 0xcf]); test_invalid(&[0x45, 0x0f, 0x23, 0xc8]); test_display(&[0x40, 0x0f, 0x23, 0xc8], "mov dr1, rax"); test_display(&[0x0f, 0x23, 0xc8], "mov dr1, rax"); test_invalid(&[0x44, 0x0f, 0x23, 0xcf]); test_display(&[0x0f, 0x23, 0xcf], "mov dr1, rdi"); test_display(&[0x0f, 0x30], "wrmsr"); test_display(&[0x0f, 0x31], "rdtsc"); test_display(&[0x0f, 0x32], "rdmsr"); test_display(&[0x0f, 0x33], "rdpmc"); test_display(&[0x0f, 0x34], "sysenter"); test_display(&[0x0f, 0x35], "sysexit"); test_invalid(&[0x0f, 0x36]); test_display(&[0x0f, 0x37], "getsec"); test_invalid(&[0x66, 0x0f, 0x37]); test_invalid(&[0xf2, 0x0f, 0x37]); test_invalid(&[0xf3, 0x0f, 0x37]); test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, dword [rax]"); test_display(&[0x0f, 0x60, 0xc2], "punpcklbw mm0, mm2"); test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, dword [rax]"); test_display(&[0x0f, 0x61, 0xc2], "punpcklwd mm0, mm2"); test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, dword [rax]"); test_display(&[0x0f, 0x62, 0xc2], "punpckldq mm0, mm2"); test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, qword [rax]"); test_display(&[0x0f, 0x63, 0xc2], "packsswb mm0, mm2"); test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, qword [rax]"); test_display(&[0x0f, 0x64, 0xc2], "pcmpgtb mm0, mm2"); test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, qword [rax]"); test_display(&[0x0f, 0x65, 0xc2], "pcmpgtw mm0, mm2"); test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, qword [rax]"); test_display(&[0x0f, 0x66, 0xc2], "pcmpgtd mm0, mm2"); test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, qword [rax]"); test_display(&[0x0f, 0x67, 0xc2], "packuswb mm0, mm2"); test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, qword [rax]"); test_display(&[0x0f, 0x68, 0xc2], "punpckhbw mm0, mm2"); test_display(&[0x0f, 0x69, 0x00], "punpckhwd mm0, qword [rax]"); test_display(&[0x0f, 0x69, 0xc2], "punpckhwd mm0, mm2"); test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, qword [rax]"); test_display(&[0x0f, 0x6a, 0xc2], "punpckhdq mm0, mm2"); test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, qword [rax]"); test_display(&[0x0f, 0x6b, 0xc2], "packssdw mm0, mm2"); test_invalid(&[0x0f, 0x6c]); test_invalid(&[0x0f, 0x6d]); test_display(&[0x0f, 0x6e, 0x00], "movd mm0, dword [rax]"); test_display(&[0x0f, 0x6e, 0xc2], "movd mm0, edx"); test_display(&[0x0f, 0x6f, 0x00], "movq mm0, qword [rax]"); test_display(&[0x0f, 0x6f, 0xc2], "movq mm0, mm2"); test_display(&[0x0f, 0x6f, 0xfb], "movq mm7, mm3"); test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [rax], 0x7f"); test_display(&[0x4f, 0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [r8], 0x7f"); test_invalid(&[0x0f, 0x71, 0x00, 0x7f]); test_invalid(&[0x0f, 0x71, 0xc0, 0x7f]); test_display(&[0x0f, 0x71, 0xd0, 0x7f], "psrlw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xe0, 0x7f], "psraw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xf0, 0x7f], "psllw mm0, 0x7f"); test_invalid(&[0x0f, 0x72, 0x00, 0x7f]); test_invalid(&[0x0f, 0x72, 0xc0, 0x7f]); test_display(&[0x0f, 0x72, 0xd0, 0x7f], "psrld mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xe0, 0x7f], "psrad mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xf0, 0x7f], "pslld mm0, 0x7f"); test_invalid(&[0x0f, 0x73, 0x00, 0x7f]); test_invalid(&[0x0f, 0x73, 0xc0, 0x7f]); test_display(&[0x0f, 0x73, 0xd0, 0x7f], "psrlq mm0, 0x7f"); test_invalid(&[0x0f, 0x73, 0xe0, 0x7f]); test_display(&[0x0f, 0x73, 0xf0, 0x7f], "psllq mm0, 0x7f"); test_display(&[0x0f, 0xa0], "push fs"); test_display(&[0x0f, 0xa1], "pop fs"); test_display(&[0x0f, 0xa2], "cpuid"); test_display(&[0x0f, 0xa4, 0xc0, 0x11], "shld eax, eax, 0x11"); test_display(&[0x66, 0x0f, 0xa4, 0xcf, 0x11], "shld di, cx, 0x11"); test_display(&[0x66, 0x45, 0x0f, 0xa4, 0xcf, 0x11], "shld r15w, r9w, 0x11"); test_display(&[0x0f, 0xa5, 0xc0], "shld eax, eax, cl"); test_display(&[0x0f, 0xa5, 0xc9], "shld ecx, ecx, cl"); test_display(&[0x0f, 0xac, 0xc0, 0x11], "shrd eax, eax, 0x11"); test_display(&[0x66, 0x0f, 0xac, 0xcf, 0x11], "shrd di, cx, 0x11"); test_display(&[0x66, 0x45, 0x0f, 0xac, 0xcf, 0x11], "shrd r15w, r9w, 0x11"); test_display(&[0x0f, 0xad, 0xc9], "shrd ecx, ecx, cl"); } #[test] fn prefixed_660f() { test_display(&[0x66, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0"); test_display(&[0x66, 0x48, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0"); test_display(&[0x66, 0x4a, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0"); test_display(&[0x66, 0x4b, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm8"); test_display(&[0x66, 0x4c, 0x0f, 0x10, 0xc0], "movupd xmm8, xmm0"); test_display(&[0x66, 0x4d, 0x0f, 0x10, 0xc0], "movupd xmm8, xmm8"); test_display(&[0xf2, 0x66, 0x66, 0x4d, 0x0f, 0x10, 0xc0], "movsd xmm8, xmm8"); } #[test] fn prefixed_f20f() { test_invalid(&[0xf2, 0x0f, 0x16, 0xcf]); test_invalid(&[0xf2, 0x4d, 0x0f, 0x16, 0xcf]); test_invalid(&[0x40, 0x66, 0xf2, 0x66, 0x4d, 0x0f, 0x16, 0xcf]); } #[test] fn prefixed_f30f() { test_display(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_display(&[0xf3, 0x4d, 0x0f, 0x16, 0xcf], "movshdup xmm9, xmm15"); test_display(&[0xf3, 0x0f, 0x1e, 0xfa], "endbr64"); test_display(&[0xf3, 0x0f, 0x1e, 0xfb], "endbr32"); test_display(&[0xf3, 0x0f, 0x1e, 0xfc], "nop esp, edi"); } #[test] fn only_64bit() { test_display(&[0xae], "scas byte es:[rdi], al"); test_display(&[0xaf], "scas dword es:[rdi], eax"); test_display(&[0x67, 0xaf], "scas dword es:[edi], eax"); test_display(&[0x67, 0xac], "lods al, byte ds:[esi]"); test_display(&[0x67, 0xaa], "stos byte es:[edi], al"); // note that rax.b does *not* change the register test_display(&[0x4f, 0xa0, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34], "mov al, byte [0x3412341234123412]"); test_display(&[0x4f, 0xa1, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34], "mov rax, qword [0x3412341234123412]"); test_display(&[0x4f, 0xa2, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34], "mov byte [0x3412341234123412], al"); test_display(&[0x4f, 0xa3, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34, 0x12, 0x34], "mov qword [0x3412341234123412], rax"); } #[test] fn test_adx() { test_display(&[0x66, 0x0f, 0x38, 0xf6, 0xc1], "adcx eax, ecx"); test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, dword [rcx]"); test_display(&[0x66, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adcx r8, qword [r9]"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0xc1], "adox eax, ecx"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, dword [rcx]"); test_display(&[0xf3, 0x4f, 0x0f, 0x38, 0xf6, 0x01], "adox r8, qword [r9]"); } #[test] fn test_prefetchw() { test_display(&[0x0f, 0x0d, 0x08], "prefetchw zmmword [rax]"); } #[test] fn test_lzcnt() { test_display(&[0x66, 0xf3, 0x0f, 0xbd, 0xc1], "lzcnt ax, cx"); test_display(&[0xf3, 0x0f, 0xbd, 0xc1], "lzcnt eax, ecx"); test_display(&[0xf3, 0x48, 0x0f, 0xbd, 0xc1], "lzcnt rax, rcx"); } #[test] fn test_svm() { test_display(&[0x0f, 0x01, 0xdf], "invlpga rax, ecx"); test_display(&[0x0f, 0x01, 0xde], "skinit eax"); test_display(&[0x0f, 0x01, 0xdd], "clgi"); test_display(&[0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x0f, 0x01, 0xdb], "vmsave rax"); test_display(&[0x0f, 0x01, 0xda], "vmload rax"); test_display(&[0x0f, 0x01, 0xd9], "vmmcall"); test_display(&[0x0f, 0x01, 0xd8], "vmrun rax"); test_display(&[0x0f, 0x78, 0xc4], "vmread rsp, rax"); test_display(&[0x0f, 0x79, 0xc5], "vmwrite rax, rbp"); test_display(&[0x0f, 0x78, 0x0b], "vmread qword [rbx], rcx"); test_invalid(&[0x66, 0x0f, 0x78, 0x03]); test_display(&[0x0f, 0x79, 0x0b], "vmwrite rcx, qword [rbx]"); test_invalid(&[0x66, 0x0f, 0x79, 0x03]); } #[test] fn test_movbe() { test_display(&[0x0f, 0x38, 0xf0, 0x06], "movbe eax, dword [rsi]"); test_display(&[0x4f, 0x0f, 0x38, 0xf0, 0x06], "movbe r8, qword [r14]"); test_invalid(&[0x4f, 0x0f, 0x38, 0xf0, 0xc6]); test_display(&[0x0f, 0x38, 0xf1, 0x06], "movbe dword [rsi], eax"); test_display(&[0x4f, 0x0f, 0x38, 0xf1, 0x06], "movbe qword [r14], r8"); test_display(&[0x66, 0x0f, 0x38, 0xf1, 0x06], "movbe word [rsi], ax"); test_invalid(&[0x66, 0x0f, 0x38, 0xf1, 0xc6]); } #[test] fn test_tsx() { test_display(&[0xc6, 0xf8, 0x10], "xabort 0x10"); test_display(&[0xc7, 0xf8, 0x10, 0x12, 0x34, 0x56], "xbegin $+0x56341210"); test_display(&[0x66, 0xc7, 0xf8, 0x10, 0x12], "xbegin $+0x1210"); test_display(&[0x0f, 0x01, 0xd5], "xend"); test_display(&[0x0f, 0x01, 0xd6], "xtest"); } #[test] fn test_rand() { test_display(&[0x0f, 0xc7, 0xfd], "rdseed ebp"); test_display(&[0x66, 0x0f, 0xc7, 0xfd], "rdseed bp"); test_display(&[0x48, 0x0f, 0xc7, 0xfd], "rdseed rbp"); test_display(&[0x0f, 0xc7, 0xf5], "rdrand ebp"); test_display(&[0x66, 0x0f, 0xc7, 0xf5], "rdrand bp"); test_display(&[0x48, 0x0f, 0xc7, 0xf5], "rdrand rbp"); } #[test] fn test_sha() { test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, xmmword [rdx], 0x40"); test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0xff], "sha1rnds4 xmm2, xmmword [rdx], 0xff"); test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, xmmword [rdx]"); test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, xmmword [rdx]"); test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, xmmword [rdx]"); test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, xmmword [rdx]"); test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, xmmword [rdx]"); test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, xmmword [rdx]"); } #[test] fn test_vmx() { test_display(&[0x0f, 0xc7, 0x3f], "vmptrst qword [rdi]"); test_display(&[0x0f, 0xc7, 0x37], "vmptrld qword [rdi]"); test_display(&[0xf3, 0x0f, 0xc7, 0x37], "vmxon qword [rdi]"); test_display(&[0x66, 0x0f, 0xc7, 0xf7], "rdrand di"); test_display(&[0x66, 0x0f, 0xc7, 0x37], "vmclear qword [rdi]"); // this is actually vmx // test_invalid(&[0x66, 0x0f, 0xc7, 0x03]); test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x33], "vmclear qword [r11]"); test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear qword [rbx]"); test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x33], "vmxon qword [r11]"); test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon qword [rbx]"); } #[test] fn test_rdpid() { test_display(&[0xf3, 0x0f, 0xc7, 0xfd], "rdpid ebp"); } #[test] fn test_cmpxchg8b() { test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); test_display(&[0xf2, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); test_display(&[0xf3, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); test_display(&[0x66, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); test_display(&[0xf2, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); test_display(&[0xf3, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); test_display(&[0x66, 0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); } #[test] fn test_x87() { // test_display(&[0xd8, 0x03], "fadd st, dword ptr [rbx]"); test_display(&[0xd8, 0x03], "fadd st(0), dword [rbx]"); // test_display(&[0xd8, 0x0b], "fmul st, dword ptr [rbx]"); test_display(&[0xd8, 0x0b], "fmul st(0), dword [rbx]"); // test_display(&[0xd8, 0x13], "fcom st, dword ptr [rbx]"); test_display(&[0xd8, 0x13], "fcom st(0), dword [rbx]"); // test_display(&[0xd8, 0x1b], "fcomp st, dword ptr [rbx]"); test_display(&[0xd8, 0x1b], "fcomp st(0), dword [rbx]"); // test_display(&[0xd8, 0x23], "fsub st, dword ptr [rbx]"); test_display(&[0xd8, 0x23], "fsub st(0), dword [rbx]"); // test_display(&[0xd8, 0x2b], "fsubr st, dword ptr [rbx]"); test_display(&[0xd8, 0x2b], "fsubr st(0), dword [rbx]"); // test_display(&[0xd8, 0x33], "fdiv st, dword ptr [rbx]"); test_display(&[0xd8, 0x33], "fdiv st(0), dword [rbx]"); // test_display(&[0xd8, 0x3b], "fdivr st, dword ptr [rbx]"); test_display(&[0xd8, 0x3b], "fdivr st(0), dword [rbx]"); // test_display(&[0xd8, 0xc3], "fadd st, st(3)"); test_display(&[0xd8, 0xc3], "fadd st(0), st(3)"); // test_display(&[0xd8, 0xcb], "fmul st, st(3)"); test_display(&[0xd8, 0xcb], "fmul st(0), st(3)"); // test_display(&[0xd8, 0xd3], "fcom st, st(3)"); test_display(&[0xd8, 0xd3], "fcom st(0), st(3)"); // test_display(&[0xd8, 0xdb], "fcomp st, st(3)"); test_display(&[0xd8, 0xdb], "fcomp st(0), st(3)"); // test_display(&[0xd8, 0xe3], "fsub st, st(3)"); test_display(&[0xd8, 0xe3], "fsub st(0), st(3)"); // test_display(&[0xd8, 0xeb], "fsubr st, st(3)"); test_display(&[0xd8, 0xeb], "fsubr st(0), st(3)"); // test_display(&[0xd8, 0xf3], "fdiv st, st(3)"); test_display(&[0xd8, 0xf3], "fdiv st(0), st(3)"); // test_display(&[0xd8, 0xfb], "fdivr st, st(3)"); test_display(&[0xd8, 0xfb], "fdivr st(0), st(3)"); // test_display(&[0xd9, 0x03], "fld st, dword ptr [rbx]"); test_display(&[0xd9, 0x03], "fld st(0), dword [rbx]"); test_invalid(&[0xd9, 0x08]); test_invalid(&[0xd9, 0x09]); test_invalid(&[0xd9, 0x0a]); test_invalid(&[0xd9, 0x0b]); test_invalid(&[0xd9, 0x0c]); test_invalid(&[0xd9, 0x0d]); test_invalid(&[0xd9, 0x0e]); test_invalid(&[0xd9, 0x0f]); // test_display(&[0xd9, 0x13], "fst dword ptr [rbx], st"); test_display(&[0xd9, 0x13], "fst dword [rbx], st(0)"); // test_display(&[0xd9, 0x1b], "fstp dword ptr [rbx], st"); test_display(&[0xd9, 0x1b], "fstp dword [rbx], st(0)"); // test_display(&[0xd9, 0x23], "fldenv ptr [rbx]"); test_display(&[0xd9, 0x23], "fldenv ptr [rbx]"); // test_display(&[0xd9, 0x2b], "fldcw word ptr [rbx]"); test_display(&[0xd9, 0x2b], "fldcw word [rbx]"); // test_display(&[0xd9, 0x33], "fnstenv ptr [rbx]"); test_display(&[0xd9, 0x33], "fnstenv ptr [rbx]"); // test_display(&[0xd9, 0x3b], "fnstcw word ptr [rbx]"); test_display(&[0xd9, 0x3b], "fnstcw word [rbx]"); // test_display(&[0xd9, 0xc3], "fld st, st(3)"); test_display(&[0xd9, 0xc3], "fld st(0), st(3)"); // test_display(&[0xd9, 0xcb], "fxch st, st(3)"); test_display(&[0xd9, 0xcb], "fxch st(0), st(3)"); test_display(&[0xd9, 0xd0], "fnop"); test_invalid(&[0xd9, 0xd1]); test_invalid(&[0xd9, 0xd2]); test_invalid(&[0xd9, 0xd3]); test_invalid(&[0xd9, 0xd4]); test_invalid(&[0xd9, 0xd5]); test_invalid(&[0xd9, 0xd6]); test_invalid(&[0xd9, 0xd7]); // undocumented save for intel xed // test_display(&[0xd9, 0xdb], "fstpnce st(3), st"); test_display(&[0xd9, 0xdb], "fstpnce st(3), st(0)"); test_display(&[0xd9, 0xe0], "fchs"); test_display(&[0xd9, 0xe1], "fabs"); test_invalid(&[0xd9, 0xe2]); test_invalid(&[0xd9, 0xe3]); test_display(&[0xd9, 0xe4], "ftst"); test_display(&[0xd9, 0xe5], "fxam"); test_invalid(&[0xd9, 0xe6]); test_invalid(&[0xd9, 0xe7]); test_display(&[0xd9, 0xe8], "fld1"); test_display(&[0xd9, 0xe9], "fldl2t"); test_display(&[0xd9, 0xea], "fldl2e"); test_display(&[0xd9, 0xeb], "fldpi"); test_display(&[0xd9, 0xec], "fldlg2"); test_display(&[0xd9, 0xed], "fldln2"); test_display(&[0xd9, 0xee], "fldz"); test_invalid(&[0xd9, 0xef]); test_display(&[0xd9, 0xf0], "f2xm1"); test_display(&[0xd9, 0xf1], "fyl2x"); test_display(&[0xd9, 0xf2], "fptan"); test_display(&[0xd9, 0xf3], "fpatan"); test_display(&[0xd9, 0xf4], "fxtract"); test_display(&[0xd9, 0xf5], "fprem1"); test_display(&[0xd9, 0xf6], "fdecstp"); test_display(&[0xd9, 0xf7], "fincstp"); test_display(&[0xd9, 0xf8], "fprem"); test_display(&[0xd9, 0xf9], "fyl2xp1"); test_display(&[0xd9, 0xfa], "fsqrt"); test_display(&[0xd9, 0xfb], "fsincos"); test_display(&[0xd9, 0xfc], "frndint"); test_display(&[0xd9, 0xfd], "fscale"); test_display(&[0xd9, 0xfe], "fsin"); test_display(&[0xd9, 0xff], "fcos"); // test_display(&[0xda, 0x03], "fiadd st, dword ptr [rbx]"); test_display(&[0xda, 0x03], "fiadd st(0), dword [rbx]"); // test_display(&[0xda, 0x0b], "fimul st, dword ptr [rbx]"); test_display(&[0xda, 0x0b], "fimul st(0), dword [rbx]"); // test_display(&[0xda, 0x13], "ficom st, dword ptr [rbx]"); test_display(&[0xda, 0x13], "ficom st(0), dword [rbx]"); // test_display(&[0xda, 0x1b], "ficomp st, dword ptr [rbx]"); test_display(&[0xda, 0x1b], "ficomp st(0), dword [rbx]"); // test_display(&[0xda, 0x23], "fisub st, dword ptr [rbx]"); test_display(&[0xda, 0x23], "fisub st(0), dword [rbx]"); // test_display(&[0xda, 0x2b], "fisubr st, dword ptr [rbx]"); test_display(&[0xda, 0x2b], "fisubr st(0), dword [rbx]"); // test_display(&[0xda, 0x33], "fidiv st, dword ptr [rbx]"); test_display(&[0xda, 0x33], "fidiv st(0), dword [rbx]"); // test_display(&[0xda, 0x3b], "fidivr st, dword ptr [rbx]"); test_display(&[0xda, 0x3b], "fidivr st(0), dword [rbx]"); // test_display(&[0xda, 0xc3], "fcmovb st, st(3)"); test_display(&[0xda, 0xc3], "fcmovb st(0), st(3)"); // test_display(&[0xda, 0xcb], "fcmove st, st(3)"); test_display(&[0xda, 0xcb], "fcmove st(0), st(3)"); // test_display(&[0xda, 0xd3], "fcmovbe st, st(3)"); test_display(&[0xda, 0xd3], "fcmovbe st(0), st(3)"); // test_display(&[0xda, 0xdb], "fcmovu st, st(3)"); test_display(&[0xda, 0xdb], "fcmovu st(0), st(3)"); test_invalid(&[0xda, 0xe0]); test_invalid(&[0xda, 0xe1]); test_invalid(&[0xda, 0xe2]); test_invalid(&[0xda, 0xe3]); test_invalid(&[0xda, 0xe4]); test_invalid(&[0xda, 0xe5]); test_invalid(&[0xda, 0xe6]); test_invalid(&[0xda, 0xe7]); test_invalid(&[0xda, 0xe8]); test_display(&[0xda, 0xe9], "fucompp"); test_invalid(&[0xda, 0xea]); test_invalid(&[0xda, 0xeb]); test_invalid(&[0xda, 0xec]); test_invalid(&[0xda, 0xed]); test_invalid(&[0xda, 0xee]); test_invalid(&[0xda, 0xef]); test_invalid(&[0xda, 0xf0]); test_invalid(&[0xda, 0xf1]); test_invalid(&[0xda, 0xf2]); test_invalid(&[0xda, 0xf3]); test_invalid(&[0xda, 0xf4]); test_invalid(&[0xda, 0xf5]); test_invalid(&[0xda, 0xf6]); test_invalid(&[0xda, 0xf7]); test_invalid(&[0xda, 0xf8]); test_invalid(&[0xda, 0xf9]); test_invalid(&[0xda, 0xfa]); test_invalid(&[0xda, 0xfb]); test_invalid(&[0xda, 0xfc]); test_invalid(&[0xda, 0xfd]); test_invalid(&[0xda, 0xfe]); test_invalid(&[0xda, 0xff]); // test_display(&[0xdb, 0x03], "fild st, dword ptr [rbx]"); test_display(&[0xdb, 0x03], "fild st(0), dword [rbx]"); // test_display(&[0xdb, 0x0b], "fisttp dword ptr [rbx], st"); test_display(&[0xdb, 0x0b], "fisttp dword [rbx], st(0)"); // test_display(&[0xdb, 0x13], "fist dword ptr [rbx], st"); test_display(&[0xdb, 0x13], "fist dword [rbx], st(0)"); // test_display(&[0xdb, 0x1b], "fistp dword ptr [rbx], st"); test_display(&[0xdb, 0x1b], "fistp dword [rbx], st(0)"); test_invalid(&[0xdb, 0x20]); test_invalid(&[0xdb, 0x21]); test_invalid(&[0xdb, 0x22]); test_invalid(&[0xdb, 0x23]); test_invalid(&[0xdb, 0x24]); test_invalid(&[0xdb, 0x25]); test_invalid(&[0xdb, 0x26]); test_invalid(&[0xdb, 0x27]); // test_display(&[0xdb, 0x2b], "fld st, ptr [rbx]"); test_display(&[0xdb, 0x2b], "fld st(0), mword [rbx]"); test_invalid(&[0xdb, 0x30]); test_invalid(&[0xdb, 0x31]); test_invalid(&[0xdb, 0x32]); test_invalid(&[0xdb, 0x33]); test_invalid(&[0xdb, 0x34]); test_invalid(&[0xdb, 0x35]); test_invalid(&[0xdb, 0x36]); test_invalid(&[0xdb, 0x37]); // test_display(&[0xdb, 0x3b], "fstp ptr [rbx], st"); test_display(&[0xdb, 0x3b], "fstp mword [rbx], st(0)"); // test_display(&[0xdb, 0xc3], "fcmovnb st, st(3)"); test_display(&[0xdb, 0xc3], "fcmovnb st(0), st(3)"); // test_display(&[0xdb, 0xcb], "fcmovne st, st(3)"); test_display(&[0xdb, 0xcb], "fcmovne st(0), st(3)"); // test_display(&[0xdb, 0xd3], "fcmovnbe st, st(3)"); test_display(&[0xdb, 0xd3], "fcmovnbe st(0), st(3)"); // test_display(&[0xdb, 0xdb], "fcmovnu st, st(3)"); test_display(&[0xdb, 0xdb], "fcmovnu st(0), st(3)"); test_display(&[0xdb, 0xe0], "feni8087_nop"); test_display(&[0xdb, 0xe1], "fdisi8087_nop"); test_display(&[0xdb, 0xe2], "fnclex"); test_display(&[0xdb, 0xe3], "fninit"); test_display(&[0xdb, 0xe4], "fsetpm287_nop"); test_invalid(&[0xdb, 0xe5]); test_invalid(&[0xdb, 0xe6]); test_invalid(&[0xdb, 0xe7]); // test_display(&[0xdb, 0xeb], "fucomi st, st(3)"); test_display(&[0xdb, 0xeb], "fucomi st(0), st(3)"); // test_display(&[0xdb, 0xf3], "fcomi st, st(3)"); test_display(&[0xdb, 0xf3], "fcomi st(0), st(3)"); test_invalid(&[0xdb, 0xf8]); test_invalid(&[0xdb, 0xf9]); test_invalid(&[0xdb, 0xfa]); test_invalid(&[0xdb, 0xfb]); test_invalid(&[0xdb, 0xfc]); test_invalid(&[0xdb, 0xfd]); test_invalid(&[0xdb, 0xfe]); test_invalid(&[0xdb, 0xff]); // test_display(&[0xdc, 0x03], "fadd st, qword ptr [rbx]"); test_display(&[0xdc, 0x03], "fadd st(0), qword [rbx]"); // test_display(&[0xdc, 0x0b], "fmul st, qword ptr [rbx]"); test_display(&[0xdc, 0x0b], "fmul st(0), qword [rbx]"); // test_display(&[0xdc, 0x13], "fcom st, qword ptr [rbx]"); test_display(&[0xdc, 0x13], "fcom st(0), qword [rbx]"); // test_display(&[0xdc, 0x1b], "fcomp st, qword ptr [rbx]"); test_display(&[0xdc, 0x1b], "fcomp st(0), qword [rbx]"); // test_display(&[0xdc, 0x23], "fsub st, qword ptr [rbx]"); test_display(&[0xdc, 0x23], "fsub st(0), qword [rbx]"); // test_display(&[0xdc, 0x2b], "fsubr st, qword ptr [rbx]"); test_display(&[0xdc, 0x2b], "fsubr st(0), qword [rbx]"); // test_display(&[0xdc, 0x33], "fdiv st, qword ptr [rbx]"); test_display(&[0xdc, 0x33], "fdiv st(0), qword [rbx]"); // test_display(&[0xdc, 0x3b], "fdivr st, qword ptr [rbx]"); test_display(&[0xdc, 0x3b], "fdivr st(0), qword [rbx]"); // test_display(&[0xdc, 0xc3], "fadd st(3), st"); test_display(&[0xdc, 0xc3], "fadd st(3), st(0)"); // test_display(&[0xdc, 0xcb], "fmul st(3), st"); test_display(&[0xdc, 0xcb], "fmul st(3), st(0)"); // test_display(&[0xdc, 0xd3], "fcom st, st(3)"); test_display(&[0xdc, 0xd3], "fcom st(0), st(3)"); // test_display(&[0xdc, 0xdb], "fcomp st, st(3)"); test_display(&[0xdc, 0xdb], "fcomp st(0), st(3)"); // test_display(&[0xdc, 0xe3], "fsubr st(3), st"); test_display(&[0xdc, 0xe3], "fsubr st(3), st(0)"); // test_display(&[0xdc, 0xeb], "fsub st(3), st"); test_display(&[0xdc, 0xeb], "fsub st(3), st(0)"); // test_display(&[0xdc, 0xf3], "fdivr st(3), st"); test_display(&[0xdc, 0xf3], "fdivr st(3), st(0)"); // test_display(&[0xdc, 0xfb], "fdiv st(3), st"); test_display(&[0xdc, 0xfb], "fdiv st(3), st(0)"); // test_display(&[0xdd, 0x03], "fld st, qword ptr [rbx]"); test_display(&[0xdd, 0x03], "fld st(0), qword [rbx]"); // test_display(&[0xdd, 0x0b], "fisttp qword ptr [rbx], st"); test_display(&[0xdd, 0x0b], "fisttp qword [rbx], st(0)"); // test_display(&[0xdd, 0x13], "fst qword ptr [rbx], st"); test_display(&[0xdd, 0x13], "fst qword [rbx], st(0)"); // test_display(&[0xdd, 0x1b], "fstp qword ptr [rbx], st"); test_display(&[0xdd, 0x1b], "fstp qword [rbx], st(0)"); // test_display(&[0xdd, 0x23], "frstor ptr [rbx]"); test_display(&[0xdd, 0x23], "frstor ptr [rbx]"); test_invalid(&[0xdd, 0x28]); test_invalid(&[0xdd, 0x29]); test_invalid(&[0xdd, 0x2a]); test_invalid(&[0xdd, 0x2b]); test_invalid(&[0xdd, 0x2c]); test_invalid(&[0xdd, 0x2d]); test_invalid(&[0xdd, 0x2e]); test_invalid(&[0xdd, 0x2f]); // test_display(&[0xdd, 0x33], "fnsave ptr [rbx]"); test_display(&[0xdd, 0x33], "fnsave ptr [rbx]"); // test_display(&[0xdd, 0x3b], "fnstsw word ptr [rbx]"); test_display(&[0xdd, 0x3b], "fnstsw word [rbx]"); test_display(&[0xdd, 0xc3], "ffree st(3)"); // test_display(&[0xdd, 0xcb], "fxch st, st(3)"); test_display(&[0xdd, 0xcb], "fxch st(0), st(3)"); // test_display(&[0xdd, 0xd3], "fst st(3), st"); test_display(&[0xdd, 0xd3], "fst st(3), st(0)"); // test_display(&[0xdd, 0xdb], "fstp st(3), st"); test_display(&[0xdd, 0xdb], "fstp st(3), st(0)"); // test_display(&[0xdd, 0xe3], "fucom st, st(3)"); test_display(&[0xdd, 0xe3], "fucom st(0), st(3)"); // test_display(&[0xdd, 0xeb], "fucomp st, st(3)"); test_display(&[0xdd, 0xeb], "fucomp st(0), st(3)"); test_invalid(&[0xdd, 0xf0]); test_invalid(&[0xdd, 0xf1]); test_invalid(&[0xdd, 0xf2]); test_invalid(&[0xdd, 0xf3]); test_invalid(&[0xdd, 0xf4]); test_invalid(&[0xdd, 0xf5]); test_invalid(&[0xdd, 0xf6]); test_invalid(&[0xdd, 0xf7]); test_invalid(&[0xdd, 0xf8]); test_invalid(&[0xdd, 0xf9]); test_invalid(&[0xdd, 0xfa]); test_invalid(&[0xdd, 0xfb]); test_invalid(&[0xdd, 0xfc]); test_invalid(&[0xdd, 0xfd]); test_invalid(&[0xdd, 0xfe]); test_invalid(&[0xdd, 0xff]); // test_display(&[0xde, 0x03], "fiadd st, word ptr [rbx]"); test_display(&[0xde, 0x03], "fiadd st(0), word [rbx]"); // test_display(&[0xde, 0x0b], "fimul st, word ptr [rbx]"); test_display(&[0xde, 0x0b], "fimul st(0), word [rbx]"); // test_display(&[0xde, 0x13], "ficom st, word ptr [rbx]"); test_display(&[0xde, 0x13], "ficom st(0), word [rbx]"); // test_display(&[0xde, 0x1b], "ficomp st, word ptr [rbx]"); test_display(&[0xde, 0x1b], "ficomp st(0), word [rbx]"); // test_display(&[0xde, 0x23], "fisub st, word ptr [rbx]"); test_display(&[0xde, 0x23], "fisub st(0), word [rbx]"); // test_display(&[0xde, 0x2b], "fisubr st, word ptr [rbx]"); test_display(&[0xde, 0x2b], "fisubr st(0), word [rbx]"); // test_display(&[0xde, 0x33], "fidiv st, word ptr [rbx]"); test_display(&[0xde, 0x33], "fidiv st(0), word [rbx]"); // test_display(&[0xde, 0x3b], "fidivr st, word ptr [rbx]"); test_display(&[0xde, 0x3b], "fidivr st(0), word [rbx]"); // test_display(&[0xde, 0xc3], "faddp st(3), st"); test_display(&[0xde, 0xc3], "faddp st(3), st(0)"); // test_display(&[0xde, 0xcb], "fmulp st(3), st"); test_display(&[0xde, 0xcb], "fmulp st(3), st(0)"); // test_display(&[0xde, 0xd3], "fcomp st, st(3)"); test_display(&[0xde, 0xd3], "fcomp st(0), st(3)"); test_invalid(&[0xde, 0xd8]); test_display(&[0xde, 0xd9], "fcompp"); test_invalid(&[0xde, 0xda]); test_invalid(&[0xde, 0xdb]); test_invalid(&[0xde, 0xdc]); test_invalid(&[0xde, 0xdd]); test_invalid(&[0xde, 0xde]); test_invalid(&[0xde, 0xdf]); // test_display(&[0xde, 0xe3], "fsubrp st(3), st"); test_display(&[0xde, 0xe3], "fsubrp st(3), st(0)"); // test_display(&[0xde, 0xeb], "fsubp st(3), st"); test_display(&[0xde, 0xeb], "fsubp st(3), st(0)"); // test_display(&[0xde, 0xf3], "fdivrp st(3), st"); test_display(&[0xde, 0xf3], "fdivrp st(3), st(0)"); // test_display(&[0xde, 0xfb], "fdivp st(3), st"); test_display(&[0xde, 0xfb], "fdivp st(3), st(0)"); // test_display(&[0xdf, 0x03], "fild st, word ptr [rbx]"); test_display(&[0xdf, 0x03], "fild st(0), word [rbx]"); // test_display(&[0xdf, 0x0b], "fisttp word ptr [rbx], st"); test_display(&[0xdf, 0x0b], "fisttp word [rbx], st(0)"); // test_display(&[0xdf, 0x13], "fist word ptr [rbx], st"); test_display(&[0xdf, 0x13], "fist word [rbx], st(0)"); // test_display(&[0xdf, 0x1b], "fistp word ptr [rbx], st"); test_display(&[0xdf, 0x1b], "fistp word [rbx], st(0)"); // test_display(&[0xdf, 0x23], "fbld st, ptr [rbx]"); test_display(&[0xdf, 0x23], "fbld st(0), mword [rbx]"); // test_display(&[0xdf, 0x2b], "fild st, qword ptr [rbx]"); test_display(&[0xdf, 0x2b], "fild st(0), qword [rbx]"); // test_display(&[0xdf, 0x33], "fbstp ptr [rbx], st"); test_display(&[0xdf, 0x33], "fbstp mword [rbx], st(0)"); // test_display(&[0xdf, 0x3b], "fistp qword ptr [rbx], st"); test_display(&[0xdf, 0x3b], "fistp qword [rbx], st(0)"); // test_display(&[0xdf, 0xc3], "ffreep st(3)"); test_display(&[0xdf, 0xc3], "ffreep st(3)"); // test_display(&[0xdf, 0xcb], "fxch st, st(3)"); test_display(&[0xdf, 0xcb], "fxch st(0), st(3)"); // test_display(&[0xdf, 0xd3], "fstp st(3), st"); test_display(&[0xdf, 0xd3], "fstp st(3), st(0)"); // test_display(&[0xdf, 0xdb], "fstp st(3), st"); test_display(&[0xdf, 0xdb], "fstp st(3), st(0)"); test_display(&[0xdf, 0xe0], "fnstsw ax"); test_invalid(&[0xdf, 0xe1]); test_invalid(&[0xdf, 0xe2]); test_invalid(&[0xdf, 0xe3]); test_invalid(&[0xdf, 0xe4]); test_invalid(&[0xdf, 0xe5]); test_invalid(&[0xdf, 0xe6]); test_invalid(&[0xdf, 0xe7]); // test_display(&[0xdf, 0xeb], "fucomip st, st(3)"); test_display(&[0xdf, 0xeb], "fucomip st(0), st(3)"); // test_display(&[0xdf, 0xf3], "fcomip st, st(3)"); test_display(&[0xdf, 0xf3], "fcomip st(0), st(3)"); test_invalid(&[0xdf, 0xf8]); test_invalid(&[0xdf, 0xf9]); test_invalid(&[0xdf, 0xfa]); test_invalid(&[0xdf, 0xfb]); test_invalid(&[0xdf, 0xfc]); test_invalid(&[0xdf, 0xfd]); test_invalid(&[0xdf, 0xfe]); test_invalid(&[0xdf, 0xff]); } #[test] fn test_mishegos_finds() { test_invalid(&[0xc5, 0x8c, 0x77]); test_display(&[0x0f, 0xfc, 0xaf, 0x40, 0x38, 0x25, 0xbf], "paddb mm5, qword [rdi - 0x40dac7c0]"); test_invalid(&[0xc5, 0x4d, 0x16, 0x0f]); test_invalid(&[0xf3, 0x67, 0x0f, 0x3a, 0xf0, 0xfb, 0xb4]); // XOP is still not supported // test_display(&[0xc4, 0x63, 0x91, 0x7f, 0x2f, 0x2e], "vfnmsubsd xmm13, xmm13, xmm2, qword ptr [rdi]"); test_invalid(&[0x62, 0xf1, 0x56, 0xfe, 0x58, 0x04, 0xca]); test_invalid(&[0x66, 0xf3, 0x36, 0x65, 0x0f, 0x3a, 0xf0, 0xee, 0x7a]); test_display(&[0x62, 0x42, 0xd5, 0x9d, 0x97, 0xf6], "vfmsubadd132pd zmm30{k5}{z}{rne-sae}, zmm5, zmm14"); test_invalid(&[0x67, 0x66, 0x42, 0x0f, 0x01, 0xfe]); test_display(&[0x62, 0x52, 0x05, 0xff, 0xad, 0xfd], "vfnmadd213ss xmm15{k7}{z}{rz-sae}, xmm15, xmm13"); test_invalid(&[0xf2, 0x67, 0x4a, 0x0f, 0x01, 0xd6]); test_invalid(&[0x36, 0x64, 0x62, 0x33, 0x39, 0xef, 0x55, 0xc2, 0x68]); test_invalid(&[0x36, 0x66, 0x67, 0xf3, 0x0f, 0x01, 0xce]); test_invalid(&[0x62, 0x0f, 0xc1, 0x35, 0x38, 0xf8, 0xc8]); test_invalid(&[0x66, 0x2e, 0x64, 0x26, 0x0f, 0x01, 0xc1]); test_invalid(&[0x2e, 0x2e, 0xf2, 0x36, 0x40, 0x0e, 0xb2, 0xdb, 0x42, 0xd6, 0xa3, 0x16]); test_invalid(&[0x2e, 0xf2, 0x36, 0x40, 0x0f, 0xb2, 0xdb, 0x42, 0xd6, 0xa3, 0x16]); test_invalid(&[0x3e, 0x3e, 0x3e, 0x66, 0x4b, 0x35, 0x58, 0x3e]); test_display(&[0xf2, 0xf3, 0x66, 0x65, 0x4f, 0x25, 0x9b, 0x5e, 0xda, 0x44], "and rax, 0x44da5e9b"); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x26, 0x66, 0x67, 0x41, 0x0f, 0x38, 0xdf, 0xe4], "aesdeclast xmm4, xmm12"); test_display(&[0x65, 0x66, 0x66, 0x64, 0x48, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[rdi]"); test_invalid(&[0xf3, 0xf2, 0x41, 0x0f, 0xae, 0x8f, 0x54, 0x3c, 0x58, 0xb7]); /* test_display(&[652e662e0f3814ff], "blendvps"); test_display(&[66666565450f3acf2b4b], "gf2 "); */ // might just be yax trying to do a f20f decode when it should not be f2 // impossible instruction if operands could be read: lock is illegal here. // test_display(&[f06565f2640f16], "???"); // test_display(&[0x0f, 0x38, 0xf6, 0x8c, 0x98, 0x4d, 0x33, 0xf5, 0xd3, ], "wrssd"); test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [rdi]"); test_display(&[0x4f, 0x0f, 0xc7, 0x0f], "cmpxchg16b xmmword [r15]"); test_display(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b, ], "movntdqa xmm5, xmmword [rbx]"); test_display(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c, 0xf0, 0x63, ], "blendpd xmm7, xmmword [eax - 0xf83d010], 0x63"); test_display(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d, ], "pmovsxwd xmm3, qword fs:[rbp + 0x2da80f69]"); test_display(&[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], "insertps xmm1, dword fs:[r11], -0x4f"); test_display(&[0x66, 0x26, 0x45, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm10, xmmword [r14 - 0x669d68c], 0x6a"); test_display(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03, 0xb3, 0xfa], "pmaxud xmm3, xmmword gs:[ebp - 0x54cfc34]"); test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword [rbp + 0x3e], edx"); test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, zmmword [rbp + 0x729080b]"); test_invalid(&[0x66, 0x2e, 0x64, 0x66, 0x46, 0x0f, 0x38, 0xf8, 0xe2]); test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword [ebp + 0x729080b]"); test_display(&[0x67, 0x66, 0x65, 0x3e, 0x0f, 0x6d, 0xd1], "punpckhqdq xmm2, xmm1"); test_display(&[0x2e, 0x66, 0x40, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, xmmword [rax + 0x2d], 0x57"); test_display(&[0xf2, 0x3e, 0x26, 0x67, 0x0f, 0xf0, 0xa0, 0x1b, 0x5f, 0xcd, 0xd7], "lddqu xmm4, xmmword [eax - 0x2832a0e5]"); test_display(&[0x2e, 0x3e, 0x66, 0x3e, 0x49, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, xmmword [r8], 0x48"); test_display(&[0x2e, 0x36, 0x47, 0x0f, 0x18, 0xe7], "nop r15d"); test_display(&[0x65, 0xf0, 0x87, 0x0f], "lock xchg dword gs:[rdi], ecx"); test_display(&[0x66, 0x4e, 0x0f, 0x3a, 0x44, 0x88, 0xb3, 0xad, 0x26, 0x35, 0x75], "pclmulqdq xmm9, xmmword [rax + 0x3526adb3], 0x75"); test_display(&[0x4c, 0x0f, 0xff, 0x6b, 0xac], "ud0 r13d, dword [rbx - 0x54]"); test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8, zmmword [r11 + 0x3f9d1c09]"); test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds rsi, zmmword fs:[rdx + 0x54]"); test_invalid(&[0xf3, 0x0f, 0x38, 0xf8, 0xf3]); test_display(&[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], "loadiwkey xmm5, xmm0"); test_invalid(&[0xf3, 0x2e, 0x0f, 0x6a, 0x18]); } #[test] fn test_cet() { // see // https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf // includes encodings: // wruss{d,q} 066 f 38 f5 // wrss{d,q} 0f 38 f6 // rstorssp f3 0f 01 /5 // saveprevssp f3 0f 01 ea // rdssp{d,q} f3 0f 1e // incssp{d,q} f3 0f ae /5 // test_display(&[0x0f, 0x38, 0xf6, 0x8c, 0x98, 0x4d, 0x33, 0xf5, 0xd3, ], "wrssd [rax + rbx * 4 - 0x2c0accb3], ecx"); // setssbsy f3 0f 01 e8 // clrssbsy f3 0f ae /6 // endbr64 f3 0f ae fa // endbr32 f3 0f ae fb test_display(&[0xf3, 0x4f, 0x0f, 0xae, 0xe9], "incssp r9"); test_display(&[0xf3, 0x0f, 0xae, 0xe9], "incssp ecx"); test_display(&[0x3e, 0x4f, 0x0f, 0x38, 0xf6, 0x23], "wrss qword [r11], r12"); test_display(&[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], "wruss dword [rdi - 0x17], eax"); test_invalid(&[0x0f, 0x38, 0xf5, 0x47, 0xe9]); test_invalid(&[0x66, 0x3e, 0x65, 0x3e, 0x0f, 0x38, 0xf5, 0xf0]); test_display(&[0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x0f, 0x01, 0x29], "rstorssp qword [rcx]"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0x29], "rstorssp qword [rcx]"); test_display(&[0xf3, 0x0f, 0xae, 0x30], "clrssbsy qword [rax]"); } #[test] fn test_sse4a() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4a(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } test_instr(&[0xf2, 0x0f, 0x2b, 0x06], "movntsd qword [rsi], xmm0"); test_invalid(&[0xf2, 0x0f, 0x2b, 0xc6]); test_instr(&[0xf3, 0x0f, 0x2b, 0x06], "movntss dword [rsi], xmm0"); test_invalid(&[0xf3, 0x0f, 0xba, 0xc6]); test_instr(&[0x66, 0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_invalid(&[0x66, 0xf2, 0x0f, 0x79, 0x0f]); test_instr(&[0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_instr(&[0xf2, 0x0f, 0x78, 0xf1, 0x4e, 0x76], "insertq xmm6, xmm1, 0x4e, 0x76"); test_invalid(&[0xf2, 0x0f, 0x79, 0x0f]); test_instr(&[0x66, 0x0f, 0x79, 0xcf], "extrq xmm1, xmm7"); test_invalid(&[0x66, 0x0f, 0x79, 0x0f]); test_instr(&[0x66, 0x0f, 0x78, 0xc1, 0x4e, 0x76], "extrq xmm1, 0x4e, 0x76"); test_invalid(&[0x66, 0x0f, 0x78, 0xc9, 0x4e, 0x76]); } #[test] fn test_3dnow() { test_display(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [rax]"); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, qword [rbx + rdx * 4 - 0x6d]"); test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword [rax - 0x5]"); test_display(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); test_display(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); } // first appeared in tremont #[test] fn test_direct_stores() { test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword [rbp + 0x3e], edx"); test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b rbp, zmmword [rbp + 0x729080b]"); test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword [ebp + 0x729080b]"); } #[test] fn test_key_locker() { test_display(&[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], "loadiwkey xmm5, xmm0"); test_display(&[0xf3, 0x0f, 0x38, 0xfa, 0xde], "encodekey128 ebx, esi"); test_display(&[0xf3, 0x0f, 0x38, 0xfb, 0xde], "encodekey256 ebx, esi"); } // these uinter test cases come from llvm: // https://reviews.llvm.org/differential/changeset/?ref=2226860 #[test] fn test_uintr() { test_display(&[0xf3, 0x0f, 0x01, 0xec], "uiret"); test_display(&[0xf3, 0x0f, 0x01, 0xed], "testui"); test_display(&[0xf3, 0x0f, 0x01, 0xee], "clui"); test_display(&[0xf3, 0x0f, 0x01, 0xef], "stui"); test_display(&[0xf3, 0x0f, 0xc7, 0xf0], "senduipi rax"); test_display(&[0xf3, 0x0f, 0xc7, 0xf2], "senduipi rdx"); test_display(&[0xf3, 0x41, 0x0f, 0xc7, 0xf0], "senduipi r8"); test_display(&[0xf3, 0x41, 0x0f, 0xc7, 0xf5], "senduipi r13"); } // started shipping in sapphire rapids #[test] fn test_enqcmd() { test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd r8, zmmword [r11 + 0x3f9d1c09]"); test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds rsi, zmmword fs:[rdx + 0x54]"); } #[test] fn test_gfni() { test_display(&[0x3e, 0x64, 0x64, 0x66, 0x4e, 0x0f, 0x3a, 0xcf, 0xba, 0x13, 0x23, 0x04, 0xba, 0x6b], "gf2p8affineinvqb xmm15, xmmword fs:[rdx - 0x45fbdced], 0x6b"); test_display(&[0x66, 0x36, 0x0f, 0x3a, 0xce, 0x8c, 0x56, 0x9e, 0x82, 0xd1, 0xbe, 0xad], "gf2p8affineqb xmm1, xmmword [rsi + rdx * 2 - 0x412e7d62], 0xad"); test_display(&[0x66, 0x4e, 0x0f, 0x38, 0xcf, 0x1c, 0x54], "gf2p8mulb xmm11, xmmword [rsp + r10 * 2]"); } #[test] fn test_tdx() { test_display(&[0x66, 0x0f, 0x01, 0xcc], "tdcall"); test_display(&[0x66, 0x0f, 0x01, 0xcd], "seamret"); test_display(&[0x66, 0x0f, 0x01, 0xce], "seamops"); test_display(&[0x66, 0x0f, 0x01, 0xcf], "seamcall"); } #[test] fn test_tsxldtrk() { test_display(&[0xf2, 0x0f, 0x01, 0xe8], "xsusldtrk"); test_display(&[0xf2, 0x0f, 0x01, 0xe9], "xresldtrk"); } #[test] fn test_sevsnp() { test_display(&[0xf3, 0x0f, 0x01, 0xff], "psmash"); test_display(&[0xf2, 0x0f, 0x01, 0xff], "pvalidate"); test_display(&[0xf3, 0x0f, 0x01, 0xfe], "rmpadjust"); test_display(&[0xf2, 0x0f, 0x01, 0xfe], "rmpupdate"); } #[test] fn test_keylocker() { test_display(&[0xf3, 0x0f, 0x38, 0xdd, 0x03], "aesdec128kl xmm0, m384b [rbx]"); } // some test cases are best just lifted from llvm or gcc. #[test] fn from_llvm() { test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); assert_eq!(hreset.operand_count(), 1); } #[test] fn from_reports() { // negative compressed evex displacements should not overflow and panic test_display(&[0x62, 0xf2, 0x6d, 0xac, 0x00, 0x59, 0xa7], "vpshufb ymm3{k4}{z}, ymm2, ymmword [rcx - 0xb20]"); test_display(&[0x62, 0xf2, 0xfd, 0x0f, 0x8a, 0x62, 0xf2], "vcompresspd xmmword [rdx - 0x70]{k7}, xmm4"); test_display(&[0xf3, 0x0f, 0x1e, 0x0f], "nop dword [rdi], ecx"); } /// the first four single byte registers (`al`, `cl`, `dl`, `bl`) can be described as either the /// first four registers of the old `B` bank (`al..bh`) or the first four registers of the new `rB` /// bank, used when `rex.w` is present on the instruction. `RegSpec` relies on the bank matching to /// compare equality, as well as for `Hash` and `Ord` to work correctly, so having two spellings of /// the register `al` (and friends) can be a correctness issue for dependent code. #[test] fn register_synonyms_use_old_bank() { // a few instructions where adding a rex.w prefix would yield a synonymous byte-size register let cases: &'static [&'static [u8]] = &[ &[0x30, 0x00], &[0x30, 0xc1], &[0x0f, 0xb6, 0xc0], &[0x0f, 0xbe, 0xc0], &[0xb2, 0xff], // from `does_not_decode_invalid_registers` fuzz target 🎉 ]; for case in cases.iter() { let mut case_with_rexw: Vec = vec![0x48]; case_with_rexw.extend_from_slice(case); let mut reader = yaxpeax_arch::U8Reader::new(case); let no_rexw = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); let mut reader = yaxpeax_arch::U8Reader::new(case); let with_rexw = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); assert_eq!(no_rexw, with_rexw); } } mod reg_specs { use yaxpeax_x86::long_mode::RegSpec; #[test] fn reg_specs_are_correct() { #[cfg(feature = "fmt")] { let cases: Vec<(RegSpec, &'static str)> = vec![ (RegSpec::q(0), "rax"), (RegSpec::rax(), "rax"), (RegSpec::q(1), "rcx"), (RegSpec::rcx(), "rcx"), (RegSpec::q(2), "rdx"), (RegSpec::rdx(), "rdx"), (RegSpec::q(3), "rbx"), (RegSpec::rbx(), "rbx"), (RegSpec::q(4), "rsp"), (RegSpec::rsp(), "rsp"), (RegSpec::q(5), "rbp"), (RegSpec::rbp(), "rbp"), (RegSpec::q(6), "rsi"), (RegSpec::rsi(), "rsi"), (RegSpec::q(7), "rdi"), (RegSpec::rdi(), "rdi"), (RegSpec::q(8), "r8"), (RegSpec::r8(), "r8"), (RegSpec::q(9), "r9"), (RegSpec::r9(), "r9"), (RegSpec::q(10), "r10"), (RegSpec::r10(), "r10"), (RegSpec::q(11), "r11"), (RegSpec::r11(), "r11"), (RegSpec::q(12), "r12"), (RegSpec::r12(), "r12"), (RegSpec::q(13), "r13"), (RegSpec::r13(), "r13"), (RegSpec::q(14), "r14"), (RegSpec::r14(), "r14"), (RegSpec::q(15), "r15"), (RegSpec::r15(), "r15"), (RegSpec::d(0), "eax"), (RegSpec::eax(), "eax"), (RegSpec::d(1), "ecx"), (RegSpec::ecx(), "ecx"), (RegSpec::d(2), "edx"), (RegSpec::edx(), "edx"), (RegSpec::d(3), "ebx"), (RegSpec::ebx(), "ebx"), (RegSpec::d(4), "esp"), (RegSpec::esp(), "esp"), (RegSpec::d(5), "ebp"), (RegSpec::ebp(), "ebp"), (RegSpec::d(6), "esi"), (RegSpec::esi(), "esi"), (RegSpec::d(7), "edi"), (RegSpec::edi(), "edi"), (RegSpec::d(8), "r8d"), (RegSpec::r8d(), "r8d"), (RegSpec::d(9), "r9d"), (RegSpec::r9d(), "r9d"), (RegSpec::d(10), "r10d"), (RegSpec::r10d(), "r10d"), (RegSpec::d(11), "r11d"), (RegSpec::r11d(), "r11d"), (RegSpec::d(12), "r12d"), (RegSpec::r12d(), "r12d"), (RegSpec::d(13), "r13d"), (RegSpec::r13d(), "r13d"), (RegSpec::d(14), "r14d"), (RegSpec::r14d(), "r14d"), (RegSpec::d(15), "r15d"), (RegSpec::r15d(), "r15d"), (RegSpec::w(0), "ax"), (RegSpec::ax(), "ax"), (RegSpec::w(1), "cx"), (RegSpec::cx(), "cx"), (RegSpec::w(2), "dx"), (RegSpec::dx(), "dx"), (RegSpec::w(3), "bx"), (RegSpec::bx(), "bx"), (RegSpec::w(4), "sp"), (RegSpec::sp(), "sp"), (RegSpec::w(5), "bp"), (RegSpec::bp(), "bp"), (RegSpec::w(6), "si"), (RegSpec::si(), "si"), (RegSpec::w(7), "di"), (RegSpec::di(), "di"), (RegSpec::w(8), "r8w"), (RegSpec::r8w(), "r8w"), (RegSpec::w(9), "r9w"), (RegSpec::r9w(), "r9w"), (RegSpec::w(10), "r10w"), (RegSpec::r10w(), "r10w"), (RegSpec::w(11), "r11w"), (RegSpec::r11w(), "r11w"), (RegSpec::w(12), "r12w"), (RegSpec::r12w(), "r12w"), (RegSpec::w(13), "r13w"), (RegSpec::r13w(), "r13w"), (RegSpec::w(14), "r14w"), (RegSpec::r14w(), "r14w"), (RegSpec::w(15), "r15w"), (RegSpec::r15w(), "r15w"), (RegSpec::b(0), "al"), (RegSpec::al(), "al"), (RegSpec::b(1), "cl"), (RegSpec::cl(), "cl"), (RegSpec::b(2), "dl"), (RegSpec::dl(), "dl"), (RegSpec::b(3), "bl"), (RegSpec::bl(), "bl"), (RegSpec::b(4), "ah"), (RegSpec::ah(), "ah"), (RegSpec::b(5), "ch"), (RegSpec::ch(), "ch"), (RegSpec::b(6), "dh"), (RegSpec::dh(), "dh"), (RegSpec::b(7), "bh"), (RegSpec::bh(), "bh"), (RegSpec::rb(0), "al"), (RegSpec::al(), "al"), (RegSpec::rb(1), "cl"), (RegSpec::cl(), "cl"), (RegSpec::rb(2), "dl"), (RegSpec::dl(), "dl"), (RegSpec::rb(3), "bl"), (RegSpec::bl(), "bl"), (RegSpec::rb(4), "spl"), (RegSpec::spl(), "spl"), (RegSpec::rb(5), "bpl"), (RegSpec::bpl(), "bpl"), (RegSpec::rb(6), "sil"), (RegSpec::sil(), "sil"), (RegSpec::rb(7), "dil"), (RegSpec::dil(), "dil"), (RegSpec::rb(8), "r8b"), (RegSpec::r8b(), "r8b"), (RegSpec::rb(9), "r9b"), (RegSpec::r9b(), "r9b"), (RegSpec::rb(10), "r10b"), (RegSpec::r10b(), "r10b"), (RegSpec::rb(11), "r11b"), (RegSpec::r11b(), "r11b"), (RegSpec::rb(12), "r12b"), (RegSpec::r12b(), "r12b"), (RegSpec::rb(13), "r13b"), (RegSpec::r13b(), "r13b"), (RegSpec::rb(14), "r14b"), (RegSpec::r14b(), "r14b"), (RegSpec::rb(15), "r15b"), (RegSpec::r15b(), "r15b"), (RegSpec::rip(), "rip"), (RegSpec::eip(), "eip"), (RegSpec::rflags(), "rflags"), (RegSpec::eflags(), "eflags"), (RegSpec::es(), "es"), (RegSpec::cs(), "cs"), (RegSpec::ss(), "ss"), (RegSpec::ds(), "ds"), (RegSpec::fs(), "fs"), (RegSpec::gs(), "gs"), (RegSpec::mask(0), "k0"), (RegSpec::mask(1), "k1"), (RegSpec::mask(2), "k2"), (RegSpec::mask(3), "k3"), (RegSpec::mask(4), "k4"), (RegSpec::mask(5), "k5"), (RegSpec::mask(6), "k6"), (RegSpec::mask(7), "k7"), ]; for (reg, name) in cases.iter() { assert_eq!(reg.name(), *name); } } let cases: Vec<(RegSpec, RegSpec)> = vec![ (RegSpec::q(0), RegSpec::rax()), (RegSpec::q(1), RegSpec::rcx()), (RegSpec::q(2), RegSpec::rdx()), (RegSpec::q(3), RegSpec::rbx()), (RegSpec::q(4), RegSpec::rsp()), (RegSpec::q(5), RegSpec::rbp()), (RegSpec::q(6), RegSpec::rsi()), (RegSpec::q(7), RegSpec::rdi()), (RegSpec::q(8), RegSpec::r8()), (RegSpec::q(9), RegSpec::r9()), (RegSpec::q(10), RegSpec::r10()), (RegSpec::q(11), RegSpec::r11()), (RegSpec::q(12), RegSpec::r12()), (RegSpec::q(13), RegSpec::r13()), (RegSpec::q(14), RegSpec::r14()), (RegSpec::q(15), RegSpec::r15()), (RegSpec::d(0), RegSpec::eax()), (RegSpec::d(1), RegSpec::ecx()), (RegSpec::d(2), RegSpec::edx()), (RegSpec::d(3), RegSpec::ebx()), (RegSpec::d(4), RegSpec::esp()), (RegSpec::d(5), RegSpec::ebp()), (RegSpec::d(6), RegSpec::esi()), (RegSpec::d(7), RegSpec::edi()), (RegSpec::d(8), RegSpec::r8d()), (RegSpec::d(9), RegSpec::r9d()), (RegSpec::d(10), RegSpec::r10d()), (RegSpec::d(11), RegSpec::r11d()), (RegSpec::d(12), RegSpec::r12d()), (RegSpec::d(13), RegSpec::r13d()), (RegSpec::d(14), RegSpec::r14d()), (RegSpec::d(15), RegSpec::r15d()), (RegSpec::w(0), RegSpec::ax()), (RegSpec::w(1), RegSpec::cx()), (RegSpec::w(2), RegSpec::dx()), (RegSpec::w(3), RegSpec::bx()), (RegSpec::w(4), RegSpec::sp()), (RegSpec::w(5), RegSpec::bp()), (RegSpec::w(6), RegSpec::si()), (RegSpec::w(7), RegSpec::di()), (RegSpec::w(8), RegSpec::r8w()), (RegSpec::w(9), RegSpec::r9w()), (RegSpec::w(10), RegSpec::r10w()), (RegSpec::w(11), RegSpec::r11w()), (RegSpec::w(12), RegSpec::r12w()), (RegSpec::w(13), RegSpec::r13w()), (RegSpec::w(14), RegSpec::r14w()), (RegSpec::w(15), RegSpec::r15w()), (RegSpec::b(0), RegSpec::al()), (RegSpec::b(1), RegSpec::cl()), (RegSpec::b(2), RegSpec::dl()), (RegSpec::b(3), RegSpec::bl()), (RegSpec::b(4), RegSpec::ah()), (RegSpec::b(5), RegSpec::ch()), (RegSpec::b(6), RegSpec::dh()), (RegSpec::b(7), RegSpec::bh()), (RegSpec::rb(0), RegSpec::al()), (RegSpec::rb(1), RegSpec::cl()), (RegSpec::rb(2), RegSpec::dl()), (RegSpec::rb(3), RegSpec::bl()), (RegSpec::rb(4), RegSpec::spl()), (RegSpec::rb(5), RegSpec::bpl()), (RegSpec::rb(6), RegSpec::sil()), (RegSpec::rb(7), RegSpec::dil()), (RegSpec::rb(8), RegSpec::r8b()), (RegSpec::rb(9), RegSpec::r9b()), (RegSpec::rb(10), RegSpec::r10b()), (RegSpec::rb(11), RegSpec::r11b()), (RegSpec::rb(12), RegSpec::r12b()), (RegSpec::rb(13), RegSpec::r13b()), (RegSpec::rb(14), RegSpec::r14b()), (RegSpec::rb(15), RegSpec::r15b()), ]; for (reg1, reg2) in cases.iter() { assert_eq!(reg1, reg2); } } #[test] #[should_panic] fn invalid_mask_reg_panics() { RegSpec::mask(8); } #[test] #[should_panic] fn invalid_qword_reg_panics() { RegSpec::q(16); } #[test] #[should_panic] fn invalid_dword_reg_panics() { RegSpec::d(16); } #[test] #[should_panic] fn invalid_word_reg_panics() { RegSpec::w(16); } #[test] #[should_panic] fn invalid_byte_reg_panics() { RegSpec::b(8); } #[test] #[should_panic] fn invalid_rex_byte_reg_panics() { RegSpec::rb(16); } #[test] #[should_panic] fn invalid_x87_reg_panics() { RegSpec::st(8); } #[test] #[should_panic] fn invalid_xmm_reg_panics() { RegSpec::xmm(32); } #[test] #[should_panic] fn invalid_ymm_reg_panics() { RegSpec::ymm(32); } #[test] #[should_panic] fn invalid_zmm_reg_panics() { RegSpec::zmm(32); } } yaxpeax-x86-1.2.2/test/long_mode/opcode.rs000064400000000000000000000055621046102023000165010ustar 00000000000000use yaxpeax_x86::long_mode::{ConditionCode, Opcode}; #[test] fn conditional_instructions() { const JCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::JO, ConditionCode::O), (Opcode::JNO, ConditionCode::NO), (Opcode::JB, ConditionCode::B), (Opcode::JNB, ConditionCode::AE), (Opcode::JZ, ConditionCode::Z), (Opcode::JNZ, ConditionCode::NZ), (Opcode::JA, ConditionCode::A), (Opcode::JNA, ConditionCode::BE), (Opcode::JS, ConditionCode::S), (Opcode::JNS, ConditionCode::NS), (Opcode::JP, ConditionCode::P), (Opcode::JNP, ConditionCode::NP), (Opcode::JL, ConditionCode::L), (Opcode::JGE, ConditionCode::GE), (Opcode::JG, ConditionCode::G), (Opcode::JLE, ConditionCode::LE), ]; for (opc, cond) in JCC.iter() { assert!(opc.is_jcc()); assert!(!opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const SETCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::SETO, ConditionCode::O), (Opcode::SETNO, ConditionCode::NO), (Opcode::SETB, ConditionCode::B), (Opcode::SETAE, ConditionCode::AE), (Opcode::SETZ, ConditionCode::Z), (Opcode::SETNZ, ConditionCode::NZ), (Opcode::SETA, ConditionCode::A), (Opcode::SETBE, ConditionCode::BE), (Opcode::SETS, ConditionCode::S), (Opcode::SETNS, ConditionCode::NS), (Opcode::SETP, ConditionCode::P), (Opcode::SETNP, ConditionCode::NP), (Opcode::SETL, ConditionCode::L), (Opcode::SETGE, ConditionCode::GE), (Opcode::SETG, ConditionCode::G), (Opcode::SETLE, ConditionCode::LE), ]; for (opc, cond) in SETCC.iter() { assert!(!opc.is_jcc()); assert!(opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const CMOVCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::CMOVO, ConditionCode::O), (Opcode::CMOVNO, ConditionCode::NO), (Opcode::CMOVB, ConditionCode::B), (Opcode::CMOVNB, ConditionCode::AE), (Opcode::CMOVZ, ConditionCode::Z), (Opcode::CMOVNZ, ConditionCode::NZ), (Opcode::CMOVA, ConditionCode::A), (Opcode::CMOVNA, ConditionCode::BE), (Opcode::CMOVS, ConditionCode::S), (Opcode::CMOVNS, ConditionCode::NS), (Opcode::CMOVP, ConditionCode::P), (Opcode::CMOVNP, ConditionCode::NP), (Opcode::CMOVL, ConditionCode::L), (Opcode::CMOVGE, ConditionCode::GE), (Opcode::CMOVG, ConditionCode::G), (Opcode::CMOVLE, ConditionCode::LE), ]; for (opc, cond) in CMOVCC.iter() { assert!(!opc.is_jcc()); assert!(!opc.is_setcc()); assert!(opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } } yaxpeax-x86-1.2.2/test/long_mode/operand.rs000064400000000000000000000041541046102023000166540ustar 00000000000000use yaxpeax_x86::long_mode::{InstDecoder, Operand, RegSpec}; use yaxpeax_x86::MemoryAccessSize; #[test] fn register_widths() { assert_eq!(Operand::Register(RegSpec::rsp()).width(), Some(8)); assert_eq!(Operand::Register(RegSpec::esp()).width(), Some(4)); assert_eq!(Operand::Register(RegSpec::sp()).width(), Some(2)); assert_eq!(Operand::Register(RegSpec::cl()).width(), Some(1)); assert_eq!(Operand::Register(RegSpec::ch()).width(), Some(1)); assert_eq!(Operand::Register(RegSpec::gs()).width(), Some(2)); } #[test] fn memory_widths() { // the register operand directly doesn't report a size - it comes from the `Instruction` for // which this is an operand. assert_eq!(Operand::RegDeref(RegSpec::rsp()).width(), None); fn mem_size_of(data: &[u8]) -> MemoryAccessSize { let decoder = InstDecoder::default(); decoder.decode_slice(data).unwrap().mem_size().unwrap() } // and checking the memory size direcly reports correct names assert_eq!(mem_size_of(&[0x32, 0x00]).size_name(), "byte"); assert_eq!(mem_size_of(&[0x66, 0x33, 0x00]).size_name(), "word"); assert_eq!(mem_size_of(&[0x33, 0x00]).size_name(), "dword"); assert_eq!(mem_size_of(&[0x48, 0x33, 0x00]).size_name(), "qword"); } #[test] fn test_implied_memory_width() { fn mem_size_of(data: &[u8]) -> Option { let decoder = InstDecoder::default(); decoder.decode_slice(data).unwrap().mem_size().unwrap().bytes_size() } // test push, pop, call, and ret assert_eq!(mem_size_of(&[0xc3]), Some(8)); assert_eq!(mem_size_of(&[0xe8, 0x11, 0x22, 0x33, 0x44]), Some(8)); assert_eq!(mem_size_of(&[0x50]), Some(8)); assert_eq!(mem_size_of(&[0x58]), Some(8)); assert_eq!(mem_size_of(&[0x66, 0x50]), Some(8)); assert_eq!(mem_size_of(&[0x66, 0x58]), Some(8)); assert_eq!(mem_size_of(&[0xff, 0xf0]), Some(8)); assert_eq!(mem_size_of(&[0x66, 0xff, 0xf0]), Some(2)); // operand-size prefixed call and jump still reads 8 bytes (prefix ignored) assert_eq!(mem_size_of(&[0x66, 0xff, 0x10]), Some(8)); assert_eq!(mem_size_of(&[0x66, 0xff, 0x20]), Some(8)); } yaxpeax-x86-1.2.2/test/long_mode/regspec.rs000064400000000000000000000035071046102023000166550ustar 00000000000000use yaxpeax_x86::long_mode::{register_class, RegSpec}; use std::collections::{BTreeMap, HashMap}; #[test] fn test_ord() { let _: BTreeMap = BTreeMap::new(); } #[test] fn test_hash() { let _: HashMap = HashMap::new(); } #[cfg(features="fmt")] #[test] fn test_labels() { assert_eq!(RegSpec::rip().name(), "rip"); assert_eq!(RegSpec::eip().name(), "eip"); assert_eq!(RegSpec::rflags().name(), "rflags"); assert_eq!(RegSpec::rbp().name(), "rbp"); assert_eq!(RegSpec::gs().name(), "gs"); assert_eq!(RegSpec::al().name(), "al"); } #[cfg(features="fmt")] #[test] fn test_bank_names() { assert_eq!(RegSpec::al().class().name(), "byte"); assert_eq!(RegSpec::r8b().class().name(), "rex-byte"); assert_eq!(RegSpec::ax().class().name(), "word"); assert_eq!(RegSpec::eax().class().name(), "dword"); assert_eq!(RegSpec::rax().class().name(), "qword"); assert_eq!(RegSpec::fs().class().name(), "segment"); assert_eq!(RegSpec::eflags().class().name(), "eflags"); assert_eq!(RegSpec::rflags().class().name(), "rflags"); assert_eq!(RegSpec::eip().class().name(), "eip"); assert_eq!(RegSpec::rip().class().name(), "rip"); assert_eq!(RegSpec::st0().class().name(), "x87-stack"); assert_eq!(RegSpec::mm0().class().name(), "mmx"); assert_eq!(RegSpec::xmm0().class().name(), "xmm"); assert_eq!(RegSpec::ymm0().class().name(), "ymm"); assert_eq!(RegSpec::zmm0().class().name(), "zmm"); } // this should compile. #[test] fn match_bank_kind() { match RegSpec::al().class() { register_class::X => { panic!("al is an xmm register? don't think so"); } register_class::B => { println!("al is a byte register"); } other => { panic!("unknown register kind: {:?}", other); } } } yaxpeax-x86-1.2.2/test/long_mode/reuse_test.rs000064400000000000000000002403721046102023000174120ustar 00000000000000use yaxpeax_arch::Decoder; use yaxpeax_x86::long_mode::InstDecoder; const INSTRUCTIONS: [&'static [u8]; 1975] = [ &[0xc4, 0b000_00001, 0b0_0111_101, 0x60, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x61, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x62, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x64, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x65, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x66, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x67, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x68, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x69, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x6a, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x6b, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xd5, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xda, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xde, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xea, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xeb, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xec, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xed, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xee, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xef, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0xd7, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x74, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x75, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x76, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xdb, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xdc, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xdd, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xdf, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe5, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xe9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xf9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xfa, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xfb, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xfc, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xfd, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xfe, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x6c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x6d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_100_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x71, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_011_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0x73, 0b11_111_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0xf5, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0xf6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_111, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00010, 0b0_0111_101, 0x28, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x29, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x2b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x36, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x37, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x38, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x39, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3a, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x3f, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x40, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x45, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x46, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x47, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x8c, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x8e, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x90, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_001, 0x91, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_001, 0x92, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_001, 0x93, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_101, 0x00, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x01, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x02, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x03, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x04, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x05, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x06, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x07, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x08, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x09, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x0a, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x0b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x1c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x1d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x1e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x20, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x21, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x22, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x23, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x24, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x25, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x2a, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x45, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x46, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x47, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x8c, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x8e, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x90, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_101, 0x91, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_101, 0x92, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b0_1111_101, 0x93, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x45, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x47, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x8c, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x8e, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_001, 0x90, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_001, 0x91, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_001, 0x92, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_001, 0x93, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x45, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x47, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x8c, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x8e, 0b00_001_010], &[0xc4, 0b000_00010, 0b1_1111_101, 0x90, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_101, 0x91, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_101, 0x92, 0b00_000_100, 0xa1], &[0xc4, 0b000_00010, 0b1_1111_101, 0x93, 0b00_000_100, 0xa1], &[0xc4, 0b000_00011, 0b0_0111_101, 0x38, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x42, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x4c, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x02, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x02, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x39, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x46, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_1111_101, 0x00, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_1111_101, 0x01, 0b11_001_010, 0x77], &[0x0f, 0x01, 0x38], &[0x0f, 0x01, 0x3f], &[0x0f, 0x01, 0x40, 0xff], &[0x0f, 0x01, 0x41, 0xff], &[0x0f, 0x01, 0x49, 0xff], &[0x0f, 0x01, 0x51, 0xff], &[0x0f, 0x01, 0x59, 0xff], &[0x0f, 0x01, 0x61, 0xff], &[0x0f, 0x01, 0x71, 0xff], &[0x0f, 0x01, 0x79, 0xff], &[0x0f, 0x01, 0xc0], &[0x0f, 0x01, 0xc1], &[0x0f, 0x01, 0xc2], &[0x0f, 0x01, 0xc3], &[0x0f, 0x01, 0xc4], &[0x0f, 0x01, 0xc8], &[0x0f, 0x01, 0xc9], &[0x0f, 0x01, 0xca], &[0x0f, 0x01, 0xcb], &[0x0f, 0x01, 0xcf], &[0x0f, 0x01, 0xd0], &[0x0f, 0x01, 0xd1], &[0x0f, 0x01, 0xd4], &[0x0f, 0x01, 0xd5], &[0x0f, 0x01, 0xd5], &[0x0f, 0x01, 0xd6], &[0x0f, 0x01, 0xd6], &[0x0f, 0x01, 0xd7], &[0x0f, 0x01, 0xd8], &[0x0f, 0x01, 0xd8], &[0x0f, 0x01, 0xd9], &[0x0f, 0x01, 0xd9], &[0x0f, 0x01, 0xda], &[0x0f, 0x01, 0xda], &[0x0f, 0x01, 0xdb], &[0x0f, 0x01, 0xdb], &[0x0f, 0x01, 0xdc], &[0x0f, 0x01, 0xdc], &[0x0f, 0x01, 0xdd], &[0x0f, 0x01, 0xdd], &[0x0f, 0x01, 0xde], &[0x0f, 0x01, 0xde], &[0x0f, 0x01, 0xdf], &[0x0f, 0x01, 0xdf], &[0x0f, 0x01, 0xe0], &[0x0f, 0x01, 0xe1], &[0x0f, 0x01, 0xe2], &[0x0f, 0x01, 0xe3], &[0x0f, 0x01, 0xe4], &[0x0f, 0x01, 0xe5], &[0x0f, 0x01, 0xe6], &[0x0f, 0x01, 0xe7], &[0x0f, 0x01, 0xee], &[0x0f, 0x01, 0xef], &[0x0f, 0x01, 0xf0], &[0x0f, 0x01, 0xf1], &[0x0f, 0x01, 0xf2], &[0x0f, 0x01, 0xf3], &[0x0f, 0x01, 0xf4], &[0x0f, 0x01, 0xf5], &[0x0f, 0x01, 0xf6], &[0x0f, 0x01, 0xf7], &[0x0f, 0x01, 0xf8], &[0x0f, 0x01, 0xf9], &[0x0f, 0x01, 0xfa], &[0x0f, 0x01, 0xfb], &[0x0f, 0x01, 0xfc], &[0x0f, 0x01, 0xfd], &[0x0f, 0x01, 0xfe], &[0x0f, 0x01, 0xff], &[0x0f, 0x02, 0xc0], &[0x0f, 0x03, 0xc0], &[0x0f, 0x05], &[0x0f, 0x06], &[0x0f, 0x06], &[0x0f, 0x07], &[0x0f, 0x0d, 0x08], &[0x0f, 0x0f, 0x38, 0x8e], &[0x0f, 0x0f, 0xc6, 0xb7], &[0x0f, 0x0f, 0xe0, 0x8a], &[0x0f, 0x12, 0x0f], &[0x0f, 0x12, 0xc0], &[0x0f, 0x12, 0xcf], &[0x0f, 0x13, 0x00], &[0x0f, 0x14, 0x08], &[0x0f, 0x15, 0x08], &[0x0f, 0x16, 0x0f], &[0x0f, 0x16, 0x0f], &[0x0f, 0x16, 0xc0], &[0x0f, 0x16, 0xcf], &[0x0f, 0x17, 0x00], &[0x0f, 0x18, 0x00], &[0x0f, 0x18, 0x08], &[0x0f, 0x18, 0x10], &[0x0f, 0x18, 0x18], &[0x0f, 0x18, 0x20], &[0x0f, 0x18, 0xc0], &[0x0f, 0x18, 0xcc], &[0x0f, 0x19, 0x20], &[0x0f, 0x1a, 0x20], &[0x0f, 0x1b, 0x20], &[0x0f, 0x1c, 0x20], &[0x0f, 0x1d, 0x20], &[0x0f, 0x1e, 0x20], &[0x0f, 0x1f, 0x20], &[0x0f, 0x20, 0xd0], &[0x0f, 0x21, 0xc8], &[0x0f, 0x21, 0xc8], &[0x0f, 0x22, 0xc0], &[0x0f, 0x22, 0xc7], &[0x0f, 0x22, 0xd0], &[0x0f, 0x22, 0xd7], &[0x0f, 0x23, 0xc8], &[0x0f, 0x23, 0xc8], &[0x0f, 0x23, 0xcf], &[0x0f, 0x28, 0xd0], &[0x0f, 0x2c, 0xcf], &[0x0f, 0x30], &[0x0f, 0x31], &[0x0f, 0x32], &[0x0f, 0x33], &[0x0f, 0x34], &[0x0f, 0x35], &[0x0f, 0x37], &[0x0f, 0x38, 0x00, 0xda], &[0x0f, 0x38, 0xc8, 0x12], &[0x0f, 0x38, 0xc9, 0x12], &[0x0f, 0x38, 0xca, 0x12], &[0x0f, 0x38, 0xcb, 0x12], &[0x0f, 0x38, 0xcc, 0x12], &[0x0f, 0x38, 0xcd, 0x12], &[0x0f, 0x38, 0xf0, 0x06], &[0x0f, 0x38, 0xf1, 0x06], &[0x0f, 0x3a, 0x0f, 0xc1, 0x23], &[0x0f, 0x3a, 0xcc, 0x12, 0x40], &[0x0f, 0x3a, 0xcc, 0x12, 0xff], &[0x0f, 0x60, 0x00], &[0x0f, 0x60, 0xc2], &[0x0f, 0x61, 0x00], &[0x0f, 0x61, 0xc2], &[0x0f, 0x62, 0x00], &[0x0f, 0x62, 0xc2], &[0x0f, 0x63, 0x00], &[0x0f, 0x63, 0xc2], &[0x0f, 0x64, 0x00], &[0x0f, 0x64, 0xc2], &[0x0f, 0x65, 0x00], &[0x0f, 0x65, 0xc2], &[0x0f, 0x66, 0x00], &[0x0f, 0x66, 0xc2], &[0x0f, 0x67, 0x00], &[0x0f, 0x67, 0xc2], &[0x0f, 0x68, 0x00], &[0x0f, 0x68, 0xc2], &[0x0f, 0x69, 0x00], &[0x0f, 0x69, 0xc2], &[0x0f, 0x6a, 0x00], &[0x0f, 0x6a, 0xc2], &[0x0f, 0x6b, 0x00], &[0x0f, 0x6b, 0xc2], &[0x0f, 0x6e, 0x00], &[0x0f, 0x6e, 0xc2], &[0x0f, 0x6f, 0x00], &[0x0f, 0x6f, 0xc2], &[0x0f, 0x6f, 0xe9], &[0x0f, 0x6f, 0xfb], &[0x0f, 0x70, 0x00, 0x7f], &[0x0f, 0x70, 0x00, 0x7f], &[0x0f, 0x71, 0xd0, 0x7f], &[0x0f, 0x71, 0xe0, 0x7f], &[0x0f, 0x71, 0xf0, 0x7f], &[0x0f, 0x72, 0xd0, 0x7f], &[0x0f, 0x72, 0xe0, 0x7f], &[0x0f, 0x72, 0xf0, 0x7f], &[0x0f, 0x73, 0xd0, 0x7f], &[0x0f, 0x73, 0xf0, 0x7f], &[0x0f, 0x74, 0xc2], &[0x0f, 0x75, 0xc2], &[0x0f, 0x76, 0xc2], &[0x0f, 0x78, 0x0b], &[0x0f, 0x78, 0xc4], &[0x0f, 0x79, 0x0b], &[0x0f, 0x79, 0xc5], &[0x0f, 0x86, 0x8b, 0x01, 0x00, 0x00], &[0x0f, 0x97, 0x00], &[0x0f, 0x97, 0x08], &[0x0f, 0x97, 0xc0], &[0x0f, 0x97, 0xc8], &[0x0f, 0xa0], &[0x0f, 0xa1], &[0x0f, 0xa2], &[0x0f, 0xa4, 0xc0, 0x11], &[0x0f, 0xa5, 0xc0], &[0x0f, 0xa5, 0xc9], &[0x0f, 0xac, 0xc0, 0x11], &[0x0f, 0xad, 0xc9], &[0x0f, 0xae, 0x04, 0x4f], &[0x0f, 0xae, 0x04, 0x4f], &[0x0f, 0xae, 0x0c, 0x4f], &[0x0f, 0xae, 0x14, 0x4f], &[0x0f, 0xae, 0x1c, 0x4f], &[0x0f, 0xae, 0x24, 0x4f], &[0x0f, 0xae, 0x2c, 0x4f], &[0x0f, 0xae, 0x34, 0x4f], &[0x0f, 0xae, 0x3c, 0x4f], &[0x0f, 0xae, 0x3f], &[0x0f, 0xaf, 0xc2], &[0x0f, 0xb2, 0x00], &[0x0f, 0xb3, 0xd0], &[0x0f, 0xb6, 0x06], &[0x0f, 0xb7, 0x06], &[0x0f, 0xbe, 0x83, 0xb4, 0x00, 0x00, 0x00], &[0x0f, 0xc0, 0xcc], &[0x0f, 0xc1, 0xcc], &[0x0f, 0xc3, 0x03], &[0x0f, 0xc4, 0xc0, 0x14], &[0x0f, 0xc5, 0xd1, 0x00], &[0x0f, 0xc7, 0x0f], &[0x0f, 0xc7, 0x0f], &[0x0f, 0xc7, 0x37], &[0x0f, 0xc7, 0x3f], &[0x0f, 0xc7, 0x5c, 0x24, 0x40], &[0x0f, 0xc7, 0x64, 0x24, 0x40], &[0x0f, 0xc7, 0x6c, 0x24, 0x40], &[0x0f, 0xc7, 0x74, 0x24, 0x40], &[0x0f, 0xc7, 0x7c, 0x24, 0x40], &[0x0f, 0xc7, 0xf5], &[0x0f, 0xc7, 0xfd], &[0x0f, 0xd8, 0xc2], &[0x0f, 0xd9, 0xc2], &[0x0f, 0xda, 0xc2], &[0x0f, 0xdb, 0xc2], &[0x0f, 0xdc, 0xc2], &[0x0f, 0xdd, 0xc2], &[0x0f, 0xde, 0xc2], &[0x0f, 0xdf, 0xc2], &[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], &[0x0f, 0xe7, 0x03], &[0x0f, 0xe8, 0xc2], &[0x0f, 0xe9, 0xc2], &[0x0f, 0xea, 0xc2], &[0x0f, 0xeb, 0xc2], &[0x0f, 0xec, 0xc2], &[0x0f, 0xed, 0xc2], &[0x0f, 0xee, 0xc2], &[0x0f, 0xef, 0xc2], &[0x0f, 0xf1, 0xc2], &[0x0f, 0xf2, 0xc2], &[0x0f, 0xf3, 0xc2], &[0x0f, 0xf4, 0xc2], &[0x0f, 0xf5, 0xc2], &[0x0f, 0xf6, 0xc2], &[0x0f, 0xf7, 0xc1], &[0x0f, 0xf8, 0xc2], &[0x0f, 0xf9, 0xc2], &[0x0f, 0xf9, 0xc2], &[0x0f, 0xfa, 0xc2], &[0x0f, 0xfb, 0xc2], &[0x0f, 0xfc, 0xc2], &[0x0f, 0xfd, 0xc2], &[0x0f, 0xfd, 0xd2], &[0x0f, 0xfe, 0xc2], &[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], &[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], &[0x26, 0x66, 0x67, 0x41, 0x0f, 0x38, 0xdf, 0xe4], &[0x2e, 0x36, 0x47, 0x0f, 0x18, 0xe7], &[0x2e, 0x3e, 0x66, 0x3e, 0x49, 0x0f, 0x3a, 0x41, 0x30, 0x48], &[0x2e, 0x66, 0x26, 0x64, 0x49, 0x0f, 0x3a, 0x21, 0x0b, 0xb1, ], &[0x2e, 0x66, 0x40, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], &[0x2e, 0x67, 0x65, 0x2e, 0x46, 0x0f, 0x01, 0xff], &[0x31, 0xc9], &[0x33, 0x04, 0x0a], &[0x33, 0x04, 0x20], &[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], &[0x33, 0x04, 0x4a], &[0x33, 0x04, 0x60], &[0x33, 0x04, 0x8a], &[0x33, 0x04, 0xa0], &[0x33, 0x04, 0xca], &[0x33, 0x04, 0xe0], &[0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], &[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], &[0x33, 0x08], &[0x33, 0x20], &[0x33, 0x41, 0x23], &[0x33, 0x44, 0x65, 0x11], &[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], &[0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], &[0x33, 0xc0], &[0x33, 0xc1], &[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], &[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], &[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], &[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], &[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], &[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], &[0x3d, 0x01, 0xf0, 0xff, 0xff], &[0x3e, 0x4f, 0x0f, 0x38, 0xf6, 0x23], &[0x3e, 0x64, 0x64, 0x66, 0x4e, 0x0f, 0x3a, 0xcf, 0xba, 0x13, 0x23, 0x04, 0xba, 0x6b], &[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], &[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], &[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], &[0x40, 0x0f, 0x22, 0xd0], &[0x40, 0x0f, 0x23, 0xc8], &[0x40, 0x0f, 0x23, 0xc8], &[0x40, 0x32, 0xc5], &[0x41, 0x0f, 0x7e, 0xcf], &[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], &[0x41, 0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], &[0x41, 0x33, 0x44, 0x65, 0x11], &[0x41, 0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], &[0x41, 0x5e], &[0x42, 0x33, 0x04, 0x20], &[0x42, 0x33, 0x04, 0x60], &[0x42, 0x33, 0x04, 0xa0], &[0x42, 0x33, 0x04, 0xe0], &[0x42, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], &[0x42, 0x33, 0x74, 0x25, 0x20], &[0x42, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], &[0x43, 0x33, 0x04, 0x20], &[0x43, 0x33, 0x04, 0x60], &[0x43, 0x33, 0x04, 0xa0], &[0x43, 0x33, 0x04, 0xe0], &[0x43, 0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], &[0x43, 0x33, 0x74, 0x25, 0x20], &[0x43, 0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], &[0x44, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], &[0x44, 0x33, 0x08], &[0x44, 0x33, 0x20], &[0x44, 0x33, 0x41, 0x23], &[0x44, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], &[0x44, 0x33, 0xc1], &[0x45, 0x0f, 0x20, 0xc0], &[0x45, 0x0f, 0x22, 0xc0], &[0x45, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], &[0x45, 0x33, 0x08], &[0x45, 0x33, 0x20], &[0x45, 0x33, 0x41, 0x23], &[0x45, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], &[0x45, 0x33, 0xc1], &[0x45, 0x66, 0x0f, 0x21, 0xc8], &[0x45, 0xf2, 0x0f, 0x21, 0xc8], &[0x45, 0xf3, 0x0f, 0x21, 0xc8], &[0x46, 0x63, 0xc1], &[0x48, 0x03, 0x0b], &[0x48, 0x0f, 0x02, 0xc0], &[0x48, 0x0f, 0x03, 0xc0], &[0x48, 0x0f, 0x05], &[0x48, 0x0f, 0x2c, 0xcf], &[0x48, 0x0f, 0xa3, 0xd0], &[0x48, 0x0f, 0xab, 0xd0], &[0x48, 0x0f, 0xb3, 0xd0], &[0x48, 0x0f, 0xc7, 0xf5], &[0x48, 0x0f, 0xc7, 0xfd], &[0x48, 0x29, 0xc8], &[0x48, 0x33, 0x05, 0x78, 0x56, 0x34, 0x12], &[0x48, 0x33, 0x08], &[0x48, 0x33, 0x20], &[0x48, 0x33, 0x41, 0x23], &[0x48, 0x33, 0x81, 0x23, 0x01, 0x65, 0x43], &[0x48, 0x33, 0xc1], &[0x48, 0x39, 0xc6], &[0x48, 0x3d, 0x01, 0xf0, 0xff, 0xff], &[0x48, 0x63, 0x04, 0xba], &[0x48, 0x83, 0xf8, 0xff], &[0x48, 0x89, 0x43, 0x18], &[0x48, 0x89, 0x44, 0x24, 0x08], &[0x48, 0x8b, 0x32], &[0x48, 0x8d, 0x0c, 0x12], &[0x48, 0x8d, 0x53, 0x08], &[0x48, 0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12], &[0x48, 0x8f, 0x00], &[0x48, 0x98], &[0x48, 0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00], &[0x48, 0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00], &[0x48, 0xcf], &[0x48, 0xff, 0x00], &[0x49, 0x89, 0x46, 0x10], &[0x49, 0x89, 0x4e, 0x08], &[0x4b, 0x69, 0x43, 0x6f, 0x6d, 0x70, 0x6c, 0x65], &[0x4b, 0x6b, 0x43, 0x6f, 0x6d], &[0x4c, 0x0f, 0xff, 0x6b, 0xac], &[0x4d, 0x0f, 0x43, 0xec], &[0x4d, 0x8b, 0x4c, 0x10, 0xf8], &[0x4f, 0x0f, 0x01, 0xe0], &[0x4f, 0x0f, 0x01, 0xf0], &[0x4f, 0x0f, 0x18, 0x20], &[0x4f, 0x0f, 0x28, 0x00], &[0x4f, 0x0f, 0x29, 0x00], &[0x4f, 0x0f, 0x2a, 0x00], &[0x4f, 0x0f, 0x2a, 0xcf], &[0x4f, 0x0f, 0x2b, 0x00], &[0x4f, 0x0f, 0x2c, 0xcf], &[0x4f, 0x0f, 0x2e, 0x00], &[0x4f, 0x0f, 0x2f, 0x00], &[0x4f, 0x0f, 0x38, 0xf0, 0x06], &[0x4f, 0x0f, 0x38, 0xf1, 0x06], &[0x4f, 0x0f, 0x50, 0xc1], &[0x4f, 0x0f, 0x51, 0x01], &[0x4f, 0x0f, 0x52, 0x01], &[0x4f, 0x0f, 0x53, 0x01], &[0x4f, 0x0f, 0x54, 0x01], &[0x4f, 0x0f, 0x55, 0x01], &[0x4f, 0x0f, 0x56, 0x01], &[0x4f, 0x0f, 0x57, 0x01], &[0x4f, 0x0f, 0x58, 0x01], &[0x4f, 0x0f, 0x59, 0x01], &[0x4f, 0x0f, 0x5a, 0x01], &[0x4f, 0x0f, 0x5b, 0x01], &[0x4f, 0x0f, 0x5c, 0x01], &[0x4f, 0x0f, 0x5d, 0x01], &[0x4f, 0x0f, 0x5e, 0x01], &[0x4f, 0x0f, 0x5f, 0x01], &[0x4f, 0x0f, 0x70, 0x00, 0x7f], &[0x4f, 0x0f, 0x70, 0x00, 0x7f], &[0x4f, 0x0f, 0x7e, 0xcf], &[0x4f, 0x0f, 0x7f, 0x0f], &[0x4f, 0x0f, 0x7f, 0xcf], &[0x4f, 0x0f, 0xb2, 0x00], &[0x4f, 0x0f, 0xc3, 0x03], &[0x4f, 0x0f, 0xc4, 0x00, 0x14], &[0x4f, 0x0f, 0xc4, 0xc0, 0x14], &[0x4f, 0x0f, 0xc7, 0x0f], &[0x4f, 0x0f, 0xc7, 0x0f], &[0x4f, 0x0f, 0xc7, 0x5c, 0x24, 0x40], &[0x4f, 0x0f, 0xc7, 0x64, 0x24, 0x40], &[0x4f, 0x0f, 0xc7, 0x6c, 0x24, 0x40], &[0x4f, 0x0f, 0xd1, 0x00], &[0x4f, 0x0f, 0xd1, 0xcf], &[0x4f, 0x0f, 0xd7, 0xcf], &[0x4f, 0x0f, 0xe7, 0x03], &[0x4f, 0x0f, 0xf7, 0xc1], &[0x4f, 0x4e, 0x00, 0xcc], &[0x4f, 0x66, 0x0f, 0x28, 0x00], &[0x4f, 0x66, 0x0f, 0x2a, 0x00], &[0x4f, 0x66, 0x0f, 0x2a, 0xcf], &[0x4f, 0x91], &[0x4f, 0xe5, 0x99], &[0x4f, 0xe7, 0x99], &[0x4f, 0xf2, 0x0f, 0x2a, 0x00], &[0x4f, 0xf2, 0x0f, 0x2a, 0xcf], &[0x4f, 0xf3, 0x0f, 0x2a, 0x00], &[0x4f, 0xf3, 0x0f, 0x2a, 0xcf], &[0x5b], &[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x44, 0x40, 0x01], &[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x44, 0x40, 0x01], &[0x65, 0x4c, 0x89, 0x04, 0x25, 0xa8, 0x01, 0x00, 0x00], &[0x65, 0x66, 0x66, 0x64, 0x48, 0x0f, 0x38, 0xdb, 0x0f], &[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], &[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], &[0x65, 0xf0, 0x87, 0x0f], &[0x66, 0x0f, 0x01, 0xcc], &[0x66, 0x0f, 0x01, 0xcd], &[0x66, 0x0f, 0x01, 0xce], &[0x66, 0x0f, 0x01, 0xcf], &[0x66, 0x0f, 0x05], &[0x66, 0x0f, 0x0f, 0xc6, 0xb7], &[0x66, 0x0f, 0x10, 0xc0], &[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00], &[0x66, 0x0f, 0x28, 0x00], &[0x66, 0x0f, 0x28, 0xd0], &[0x66, 0x0f, 0x29, 0x00], &[0x66, 0x0f, 0x38, 0x80, 0x2f], &[0x66, 0x0f, 0x38, 0x81, 0x2f], &[0x66, 0x0f, 0x38, 0x82, 0x2f], &[0x66, 0x0f, 0x38, 0xf1, 0x06], &[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], &[0x66, 0x0f, 0x38, 0xf6, 0x01], &[0x66, 0x0f, 0x38, 0xf6, 0xc1], &[0x66, 0x0f, 0xa4, 0xcf, 0x11], &[0x66, 0x0f, 0xac, 0xcf, 0x11], &[0x66, 0x0f, 0xae, 0x37], &[0x66, 0x0f, 0xae, 0x3f], &[0x66, 0x0f, 0xae, 0xf1], &[0x66, 0x0f, 0xae, 0xf7], &[0x66, 0x0f, 0xaf, 0xd1], &[0x66, 0x0f, 0xc0, 0xcc], &[0x66, 0x0f, 0xc1, 0xcc], &[0x66, 0x0f, 0xc5, 0xd8, 0xff], &[0x66, 0x0f, 0xc7, 0x0f], &[0x66, 0x0f, 0xc7, 0x33], &[0x66, 0x0f, 0xc7, 0x37], &[0x66, 0x0f, 0xc7, 0xf5], &[0x66, 0x0f, 0xc7, 0xf7], &[0x66, 0x0f, 0xc7, 0xfd], &[0x66, 0x0f, 0xef, 0xc0], &[0x66, 0x26, 0x45, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], &[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00], &[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c, 0xf0, 0x63, ], &[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], &[0x66, 0x36, 0x0f, 0x3a, 0xce, 0x8c, 0x56, 0x9e, 0x82, 0xd1, 0xbe, 0xad], &[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b, ], &[0x66, 0x41, 0x0f, 0xb3, 0xc0], &[0x66, 0x41, 0x31, 0xc0], &[0x66, 0x41, 0x32, 0xc0], &[0x66, 0x41, 0x50], &[0x66, 0x45, 0x0f, 0xa4, 0xcf, 0x11], &[0x66, 0x45, 0x0f, 0xac, 0xcf, 0x11], &[0x66, 0x48, 0x0f, 0x10, 0xc0], &[0x66, 0x49, 0x0f, 0x38, 0x80, 0x2f], &[0x66, 0x49, 0x0f, 0x38, 0x81, 0x2f], &[0x66, 0x49, 0x0f, 0x38, 0x82, 0x2f], &[0x66, 0x4a, 0x0f, 0x10, 0xc0], &[0x66, 0x4b, 0x0f, 0x10, 0xc0], &[0x66, 0x4c, 0x0f, 0x10, 0xc0], &[0x66, 0x4d, 0x0f, 0x10, 0xc0], &[0x66, 0x4e, 0x0f, 0x38, 0xcf, 0x1c, 0x54], &[0x66, 0x4e, 0x0f, 0x3a, 0x44, 0x88, 0xb3, 0xad, 0x26, 0x35, 0x75], &[0x66, 0x4f, 0x0f, 0x28, 0x00], &[0x66, 0x4f, 0x0f, 0x28, 0x00], &[0x66, 0x4f, 0x0f, 0x2a, 0x00], &[0x66, 0x4f, 0x0f, 0x2a, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xf6, 0x01], &[0x66, 0x4f, 0x0f, 0xae, 0xf1], &[0x66, 0x4f, 0x0f, 0xb2, 0x00], &[0x66, 0x4f, 0x0f, 0xc7, 0x0f], &[0x66, 0x4f, 0x0f, 0xc7, 0x33], &[0x66, 0x4f, 0x0f, 0xef, 0xc0], &[0x66, 0x4f, 0xcf], &[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d, ], &[0x66, 0x8f, 0x00], &[0x66, 0x91], &[0x66, 0x99], &[0x66, 0xc7, 0xf8, 0x10, 0x12], &[0x66, 0xcf], &[0x66, 0xf3, 0x0f, 0x01, 0xe8], &[0x66, 0xf3, 0x0f, 0x01, 0xea], &[0x66, 0xf3, 0x0f, 0xbd, 0xc1], &[0x66, 0xff, 0xe0], &[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03, 0xb3, 0xfa], &[0x67, 0x4f, 0x0f, 0x5b, 0x01], &[0x67, 0x4f, 0x0f, 0xb2, 0x00], &[0x67, 0x4f, 0x66, 0x0f, 0x28, 0x00], &[0x67, 0x66, 0x4f, 0x0f, 0x28, 0x00], &[0x67, 0x66, 0x65, 0x3e, 0x0f, 0x6d, 0xd1], &[0x67, 0xa0, 0x93, 0x62, 0xc4, 0x00], &[0x67, 0xa1, 0x93, 0x62, 0xc4, 0x00], &[0x67, 0xa2, 0x93, 0x62, 0xc4, 0x00], &[0x67, 0xa3, 0x93, 0x62, 0xc4, 0x00], &[0x67, 0xe5, 0x99], &[0x67, 0xff, 0xe0], &[0x68, 0x7f, 0x63, 0xc4, 0x00], &[0x72, 0x5a], &[0x73, 0x31], &[0x74, 0x47], &[0x81, 0xec, 0x10, 0x03, 0x00, 0x00], &[0x89, 0x55, 0x94], &[0x8e, 0x00], &[0x8e, 0x10], &[0x8e, 0x18], &[0x8e, 0x20], &[0x8e, 0x28], &[0x8f, 0x00], &[0x90], &[0x91], &[0x98], &[0x9c], &[0xa0, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], &[0xa1, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], &[0xa2, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], &[0xa3, 0x93, 0x62, 0xc4, 0x00, 0x12, 0x34, 0x12, 0x34], &[0xba, 0x01, 0x00, 0x00, 0x00], &[0xc3], &[0xc6, 0xf8, 0x10], &[0xc7, 0xf8, 0x10, 0x12, 0x34, 0x56], &[0xc8, 0x01, 0x02, 0x03], &[0xc9], &[0xca, 0x12, 0x34], &[0xcb], &[0xcd, 0x00], &[0xcd, 0xff], &[0xcf], &[0xd2, 0xe0], &[0xd8, 0x03], &[0xd8, 0x0b], &[0xd8, 0x13], &[0xd8, 0x1b], &[0xd8, 0x23], &[0xd8, 0x2b], &[0xd8, 0x33], &[0xd8, 0x3b], &[0xd8, 0xc3], &[0xd8, 0xcb], &[0xd8, 0xd3], &[0xd8, 0xdb], &[0xd8, 0xe3], &[0xd8, 0xeb], &[0xd8, 0xf3], &[0xd8, 0xfb], &[0xd9, 0x03], &[0xd9, 0x13], &[0xd9, 0x1b], &[0xd9, 0x23], &[0xd9, 0x2b], &[0xd9, 0x33], &[0xd9, 0x3b], &[0xd9, 0xc3], &[0xd9, 0xcb], &[0xd9, 0xd0], &[0xd9, 0xdb], &[0xd9, 0xe0], &[0xd9, 0xe1], &[0xd9, 0xe4], &[0xd9, 0xe5], &[0xd9, 0xe8], &[0xd9, 0xe9], &[0xd9, 0xea], &[0xd9, 0xeb], &[0xd9, 0xec], &[0xd9, 0xed], &[0xd9, 0xee], &[0xd9, 0xf0], &[0xd9, 0xf1], &[0xd9, 0xf2], &[0xd9, 0xf3], &[0xd9, 0xf4], &[0xd9, 0xf5], &[0xd9, 0xf6], &[0xd9, 0xf7], &[0xd9, 0xf8], &[0xd9, 0xf9], &[0xd9, 0xfa], &[0xd9, 0xfb], &[0xd9, 0xfc], &[0xd9, 0xfd], &[0xd9, 0xfe], &[0xd9, 0xff], &[0xda, 0x03], &[0xda, 0x0b], &[0xda, 0x13], &[0xda, 0x1b], &[0xda, 0x23], &[0xda, 0x2b], &[0xda, 0x33], &[0xda, 0x3b], &[0xda, 0xc3], &[0xda, 0xcb], &[0xda, 0xd3], &[0xda, 0xdb], &[0xda, 0xe9], &[0xdb, 0x03], &[0xdb, 0x0b], &[0xdb, 0x13], &[0xdb, 0x1b], &[0xdb, 0x2b], &[0xdb, 0x3b], &[0xdb, 0xc3], &[0xdb, 0xcb], &[0xdb, 0xd3], &[0xdb, 0xdb], &[0xdb, 0xe0], &[0xdb, 0xe1], &[0xdb, 0xe2], &[0xdb, 0xe3], &[0xdb, 0xe4], &[0xdb, 0xeb], &[0xdb, 0xf3], &[0xdc, 0x03], &[0xdc, 0x0b], &[0xdc, 0x13], &[0xdc, 0x1b], &[0xdc, 0x23], &[0xdc, 0x2b], &[0xdc, 0x33], &[0xdc, 0x3b], &[0xdc, 0xc3], &[0xdc, 0xcb], &[0xdc, 0xd3], &[0xdc, 0xdb], &[0xdc, 0xe3], &[0xdc, 0xeb], &[0xdc, 0xf3], &[0xdc, 0xfb], &[0xdd, 0x03], &[0xdd, 0x0b], &[0xdd, 0x13], &[0xdd, 0x1b], &[0xdd, 0x23], &[0xdd, 0x33], &[0xdd, 0x3b], &[0xdd, 0xc3], &[0xdd, 0xcb], &[0xdd, 0xd3], &[0xdd, 0xdb], &[0xdd, 0xe3], &[0xdd, 0xeb], &[0xde, 0x03], &[0xde, 0x0b], &[0xde, 0x13], &[0xde, 0x1b], &[0xde, 0x23], &[0xde, 0x2b], &[0xde, 0x33], &[0xde, 0x3b], &[0xde, 0xc3], &[0xde, 0xcb], &[0xde, 0xd3], &[0xde, 0xd9], &[0xde, 0xe3], &[0xde, 0xeb], &[0xde, 0xf3], &[0xde, 0xfb], &[0xdf, 0x03], &[0xdf, 0x0b], &[0xdf, 0x13], &[0xdf, 0x1b], &[0xdf, 0x23], &[0xdf, 0x2b], &[0xdf, 0x33], &[0xdf, 0x3b], &[0xdf, 0xc3], &[0xdf, 0xcb], &[0xdf, 0xd3], &[0xdf, 0xdb], &[0xdf, 0xe0], &[0xdf, 0xeb], &[0xdf, 0xf3], &[0xe0, 0x12], &[0xe1, 0x12], &[0xe2, 0x12], &[0xe3, 0x12], &[0xe4, 0x99], &[0xe5, 0x99], &[0xe6, 0x99], &[0xec], &[0xed], &[0xee], &[0xef], &[0xf0, 0x0f, 0xbb, 0x17], &[0xf0, 0x31, 0x00], &[0xf0, 0x80, 0x30, 0x00], &[0xf1], &[0xf2, 0x0f, 0x01, 0xe8], &[0xf2, 0x0f, 0x01, 0xe9], &[0xf2, 0x0f, 0x06], &[0xf2, 0x0f, 0x07], &[0xf2, 0x0f, 0x10, 0x0c, 0xc6], &[0xf2, 0x0f, 0x38, 0xf0, 0xc1], &[0xf2, 0x0f, 0x38, 0xf1, 0xc1], &[0xf2, 0x0f, 0x59, 0xc8], &[0xf2, 0x0f, 0xae, 0xf1], &[0xf2, 0x0f, 0xc0, 0xcc], &[0xf2, 0x0f, 0xc1, 0xcc], &[0xf2, 0x0f, 0xc7, 0x0f], &[0xf2, 0x3e, 0x26, 0x67, 0x0f, 0xf0, 0xa0, 0x1b, 0x5f, 0xcd, 0xd7], &[0xf2, 0x4f, 0x0f, 0x2a, 0x00], &[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], &[0xf2, 0x4f, 0x0f, 0x59, 0xc8], &[0xf2, 0x4f, 0x0f, 0xae, 0xf1], &[0xf2, 0x4f, 0x0f, 0xc7, 0x0f], &[0xf2, 0x66, 0x66, 0x4d, 0x0f, 0x10, 0xc0], &[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], &[0xf2, 0xf2, 0x2e, 0x36, 0x47, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], &[0xf3, 0x0f, 0x01, 0x29], &[0xf3, 0x0f, 0x01, 0xe8], &[0xf3, 0x0f, 0x01, 0xea], &[0xf3, 0x0f, 0x01, 0xec], &[0xf3, 0x0f, 0x01, 0xed], &[0xf3, 0x0f, 0x01, 0xee], &[0xf3, 0x0f, 0x01, 0xef], &[0xf3, 0x0f, 0x10, 0x04, 0x86], &[0xf3, 0x0f, 0x10, 0x0c, 0xc7], &[0xf3, 0x0f, 0x11, 0x0c, 0xc7], &[0xf3, 0x0f, 0x16, 0xcf], &[0xf3, 0x0f, 0x38, 0xf6, 0x01], &[0xf3, 0x0f, 0x38, 0xf6, 0xc1], &[0xf3, 0x0f, 0x38, 0xfa, 0xde], &[0xf3, 0x0f, 0x38, 0xfb, 0xde], &[0xf3, 0x0f, 0x59, 0xc8], &[0xf3, 0x0f, 0x6f, 0x07], &[0xf3, 0x0f, 0x70, 0xc0, 0x4e], &[0xf3, 0x0f, 0x7e, 0xc1], &[0xf3, 0x0f, 0x7f, 0x45, 0x00], &[0xf3, 0x0f, 0xae, 0x26], &[0xf3, 0x0f, 0xae, 0x30], &[0xf3, 0x0f, 0xae, 0xc4], &[0xf3, 0x0f, 0xae, 0xcc], &[0xf3, 0x0f, 0xae, 0xd4], &[0xf3, 0x0f, 0xae, 0xdc], &[0xf3, 0x0f, 0xae, 0xe6], &[0xf3, 0x0f, 0xae, 0xe9], &[0xf3, 0x0f, 0xae, 0xf1], &[0xf3, 0x0f, 0xbd, 0xc1], &[0xf3, 0x0f, 0xc0, 0xcc], &[0xf3, 0x0f, 0xc1, 0xcc], &[0xf3, 0x0f, 0xc2, 0xc3, 0x08], &[0xf3, 0x0f, 0xc7, 0x0f], &[0xf3, 0x0f, 0xc7, 0x33], &[0xf3, 0x0f, 0xc7, 0x37], &[0xf3, 0x0f, 0xc7, 0xf0], &[0xf3, 0x0f, 0xc7, 0xf2], &[0xf3, 0x0f, 0xc7, 0xfd], &[0xf3, 0x40, 0x0f, 0x7e, 0xc1], &[0xf3, 0x41, 0x0f, 0x7e, 0xc1], &[0xf3, 0x41, 0x0f, 0xc7, 0xf0], &[0xf3, 0x41, 0x0f, 0xc7, 0xf5], &[0xf3, 0x42, 0x0f, 0x7e, 0xc1], &[0xf3, 0x44, 0x0f, 0x7e, 0xc1], &[0xf3, 0x45, 0x0f, 0xbc, 0xd7], &[0xf3, 0x48, 0x0f, 0x7e, 0xc1], &[0xf3, 0x48, 0x0f, 0xbd, 0xc1], &[0xf3, 0x48, 0xa5], &[0xf3, 0x48, 0xab], &[0xf3, 0x49, 0x0f, 0xae, 0x26], &[0xf3, 0x4d, 0x0f, 0x16, 0xcf], &[0xf3, 0x4f, 0x0f, 0x2a, 0x00], &[0xf3, 0x4f, 0x0f, 0x2a, 0x01], &[0xf3, 0x4f, 0x0f, 0x2a, 0xc1], &[0xf3, 0x4f, 0x0f, 0x2a, 0xcf], &[0xf3, 0x4f, 0x0f, 0x2c, 0x01], &[0xf3, 0x4f, 0x0f, 0x2c, 0xc1], &[0xf3, 0x4f, 0x0f, 0x2d, 0x01], &[0xf3, 0x4f, 0x0f, 0x2d, 0xc1], &[0xf3, 0x4f, 0x0f, 0x38, 0xf6, 0x01], &[0xf3, 0x4f, 0x0f, 0x51, 0x01], &[0xf3, 0x4f, 0x0f, 0x52, 0x01], &[0xf3, 0x4f, 0x0f, 0x53, 0x01], &[0xf3, 0x4f, 0x0f, 0x53, 0xc1], &[0xf3, 0x4f, 0x0f, 0x58, 0x01], &[0xf3, 0x4f, 0x0f, 0x59, 0x01], &[0xf3, 0x4f, 0x0f, 0x5a, 0x01], &[0xf3, 0x4f, 0x0f, 0x5b, 0x01], &[0xf3, 0x4f, 0x0f, 0x5c, 0x01], &[0xf3, 0x4f, 0x0f, 0x5d, 0x01], &[0xf3, 0x4f, 0x0f, 0x5e, 0x01], &[0xf3, 0x4f, 0x0f, 0x5f, 0x01], &[0xf3, 0x4f, 0x0f, 0x7e, 0xc1], &[0xf3, 0x4f, 0x0f, 0xae, 0xc4], &[0xf3, 0x4f, 0x0f, 0xae, 0xcc], &[0xf3, 0x4f, 0x0f, 0xae, 0xd4], &[0xf3, 0x4f, 0x0f, 0xae, 0xdc], &[0xf3, 0x4f, 0x0f, 0xae, 0xe9], &[0xf3, 0x4f, 0x0f, 0xc2, 0x03, 0x08], &[0xf3, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], &[0xf3, 0x4f, 0x0f, 0xc7, 0x0f], &[0xf3, 0x4f, 0x0f, 0xc7, 0x33], &[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], &[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], &[0xf3, 0x66, 0x0f, 0x01, 0x29], &[0xf3, 0x66, 0x0f, 0x01, 0xe8], &[0xf3, 0x66, 0x0f, 0x01, 0xea], &[0xf5], &[0xf6, 0x05, 0x2c, 0x9b, 0xff, 0xff, 0x01], &[0xf6, 0x28], &[0xf6, 0xc2, 0x18], &[0xf6, 0xe8], &[0xfe, 0x00], &[0xfe, 0x08], &[0xff, 0x00], &[0xff, 0x15, 0x7e, 0x72, 0x24, 0x00], &[0xff, 0x18], &[0xff, 0x24, 0xcd, 0x70, 0xa0, 0xbc, 0x01], &[0xff, 0x75, 0x08], &[0xff, 0x75, 0xb8], &[0xff, 0xe0], &[0x0f, 0xbb, 0x17], &[0x41, 0x0f, 0xbc, 0xd3], &[0xf0, 0x0f, 0xbb, 0x17], &[0x41, 0x0f, 0xbc, 0xd3], &[0xc4, 0xc2, 0x60, 0xf2, 0x01], &[0xc4, 0xc2, 0x60, 0xf7, 0x01], &[0xc4, 0xc2, 0x78, 0xf3, 0x09], &[0xc4, 0xc2, 0x78, 0xf3, 0x11], &[0xc4, 0xc2, 0x78, 0xf3, 0x19], &[0xc4, 0xc2, 0xe0, 0xf2, 0x01], &[0xc4, 0xc2, 0xe0, 0xf7, 0x01], &[0xc4, 0xc2, 0xf8, 0xf3, 0x09], &[0xc4, 0xc2, 0xf8, 0xf3, 0x11], &[0xc4, 0xc2, 0xf8, 0xf3, 0x19], &[0xf2, 0x41, 0x0f, 0xbc, 0xd3], &[0xf3, 0x41, 0x0f, 0xbc, 0xd3], &[0xc4, 0xc2, 0x61, 0xf7, 0x01], &[0xc4, 0xc2, 0x62, 0xf7, 0x01], &[0xc4, 0xc2, 0x63, 0xf7, 0x01], &[0xc4, 0xc2, 0xe1, 0xf7, 0x01], &[0xc4, 0xc2, 0xe2, 0xf7, 0x01], &[0xc4, 0xc2, 0xe3, 0xf7, 0x01], &[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], &[0xc4, 0xc3, 0xfb, 0xf0, 0x01, 0x05], &[0xc4, 0xe2, 0x60, 0xf5, 0x07], &[0xc4, 0xe2, 0x62, 0xf5, 0x07], &[0xc4, 0xe2, 0x63, 0xf5, 0x07], &[0xc4, 0xe2, 0x63, 0xf6, 0x07], &[0xc4, 0xe2, 0xe0, 0xf5, 0x07], &[0xc4, 0xe2, 0xe2, 0xf5, 0x07], &[0xc4, 0xe2, 0xe3, 0xf5, 0x07], &[0xc4, 0xe2, 0xe3, 0xf6, 0x07], &[0xf3, 0x0f, 0xb8, 0xc1], &[0xf3, 0x4f, 0x0f, 0xb8, 0xc1], &[0xf3, 0x41, 0x0f, 0xbc, 0xd3], &[0xf3, 0x0f, 0xb8, 0xc1], &[0xf3, 0x4f, 0x0f, 0xb8, 0xc1], &[0x0f, 0x01, 0xc8], &[0x0f, 0x01, 0xc9], &[0x0f, 0x38, 0x00, 0x06], &[0x0f, 0x38, 0x01, 0x06], &[0x0f, 0x38, 0x02, 0x06], &[0x0f, 0x38, 0x03, 0x06], &[0x0f, 0x38, 0x04, 0x06], &[0x0f, 0x38, 0x05, 0x06], &[0x0f, 0x38, 0x06, 0x06], &[0x0f, 0x38, 0x07, 0x06], &[0x0f, 0x38, 0x08, 0x06], &[0x0f, 0x38, 0x09, 0x06], &[0x0f, 0x38, 0x0a, 0x06], &[0x0f, 0x38, 0x0b, 0x06], &[0x0f, 0x38, 0x1c, 0x06], &[0x0f, 0x38, 0x1d, 0x06], &[0x0f, 0x38, 0x1e, 0x06], &[0x0f, 0x3a, 0x0f, 0x06, 0x30], &[0x66, 0x0f, 0x11, 0x0c, 0xc7], &[0x66, 0x0f, 0x38, 0x00, 0x06], &[0x66, 0x0f, 0x38, 0x00, 0xda], &[0x66, 0x0f, 0x38, 0x01, 0x06], &[0x66, 0x0f, 0x38, 0x02, 0x06], &[0x66, 0x0f, 0x38, 0x03, 0x06], &[0x66, 0x0f, 0x38, 0x04, 0x06], &[0x66, 0x0f, 0x38, 0x05, 0x06], &[0x66, 0x0f, 0x38, 0x06, 0x06], &[0x66, 0x0f, 0x38, 0x07, 0x06], &[0x66, 0x0f, 0x38, 0x08, 0x06], &[0x66, 0x0f, 0x38, 0x09, 0x06], &[0x66, 0x0f, 0x38, 0x0a, 0x06], &[0x66, 0x0f, 0x38, 0x0b, 0x06], &[0x66, 0x0f, 0x38, 0x10, 0x06], &[0x66, 0x0f, 0x38, 0x14, 0x06], &[0x66, 0x0f, 0x38, 0x15, 0x06], &[0x66, 0x0f, 0x38, 0x17, 0x06], &[0x66, 0x0f, 0x38, 0x1c, 0x06], &[0x66, 0x0f, 0x38, 0x1d, 0x06], &[0x66, 0x0f, 0x38, 0x1e, 0x06], &[0x66, 0x0f, 0x38, 0x20, 0x06], &[0x66, 0x0f, 0x38, 0x21, 0x06], &[0x66, 0x0f, 0x38, 0x22, 0x06], &[0x66, 0x0f, 0x38, 0x23, 0x06], &[0x66, 0x0f, 0x38, 0x24, 0x06], &[0x66, 0x0f, 0x38, 0x25, 0x06], &[0x66, 0x0f, 0x38, 0x28, 0x06], &[0x66, 0x0f, 0x38, 0x29, 0x06], &[0x66, 0x0f, 0x38, 0x2a, 0x06], &[0x66, 0x0f, 0x38, 0x2b, 0x06], &[0x66, 0x0f, 0x38, 0x30, 0x06], &[0x66, 0x0f, 0x38, 0x31, 0x06], &[0x66, 0x0f, 0x38, 0x32, 0x06], &[0x66, 0x0f, 0x38, 0x33, 0x06], &[0x66, 0x0f, 0x38, 0x34, 0x06], &[0x66, 0x0f, 0x38, 0x35, 0x06], &[0x66, 0x0f, 0x38, 0x37, 0x03], &[0x66, 0x0f, 0x38, 0x37, 0xc3], &[0x66, 0x0f, 0x38, 0x38, 0x06], &[0x66, 0x0f, 0x38, 0x39, 0x06], &[0x66, 0x0f, 0x38, 0x3a, 0x06], &[0x66, 0x0f, 0x38, 0x3b, 0x06], &[0x66, 0x0f, 0x38, 0x3c, 0x06], &[0x66, 0x0f, 0x38, 0x3d, 0x06], &[0x66, 0x0f, 0x38, 0x3e, 0x06], &[0x66, 0x0f, 0x38, 0x3f, 0x06], &[0x66, 0x0f, 0x38, 0x40, 0x06], &[0x66, 0x0f, 0x38, 0x41, 0x06], &[0x66, 0x0f, 0x38, 0xdb, 0x0f], &[0x66, 0x0f, 0x38, 0xdc, 0x0f], &[0x66, 0x0f, 0x38, 0xdd, 0x0f], &[0x66, 0x0f, 0x38, 0xde, 0x0f], &[0x66, 0x0f, 0x38, 0xdf, 0x0f], &[0x66, 0x0f, 0x3a, 0x08, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x09, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x0a, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x0b, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], &[0x66, 0x0f, 0x3a, 0x0c, 0xc1, 0x22], &[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], &[0x66, 0x0f, 0x3a, 0x0d, 0xc1, 0x22], &[0x66, 0x0f, 0x3a, 0x0e, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x0f, 0x06, 0x30], &[0x66, 0x0f, 0x3a, 0x14, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x15, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x16, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x17, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x20, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x21, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x22, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x40, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x41, 0x06, 0x31], &[0x66, 0x0f, 0x3a, 0x42, 0x06, 0x44], &[0x66, 0x0f, 0x3a, 0x60, 0x06, 0x54], &[0x66, 0x0f, 0x3a, 0x60, 0xc6, 0x54], &[0x66, 0x0f, 0x3a, 0x61, 0x06, 0x54], &[0x66, 0x0f, 0x3a, 0x61, 0xc6, 0x54], &[0x66, 0x0f, 0x3a, 0x62, 0x06, 0x54], &[0x66, 0x0f, 0x3a, 0x62, 0xc6, 0x54], &[0x66, 0x0f, 0x3a, 0x63, 0x06, 0x54], &[0x66, 0x0f, 0x3a, 0x63, 0xc6, 0x54], &[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], &[0x66, 0x0f, 0x70, 0xc0, 0x4e], &[0x66, 0x0f, 0x74, 0x12], &[0x66, 0x0f, 0x74, 0xc1], &[0x66, 0x0f, 0x78, 0xc1, 0x4e, 0x76], &[0x66, 0x0f, 0x79, 0xcf], &[0x66, 0x0f, 0x7c, 0x0f], &[0x66, 0x0f, 0x7c, 0xcf], &[0x66, 0x0f, 0x7d, 0x0f], &[0x66, 0x0f, 0x7d, 0xcf], &[0x66, 0x0f, 0x7e, 0xc1], &[0x66, 0x0f, 0xc2, 0xc3, 0x08], &[0x66, 0x0f, 0xc4, 0x03, 0x08], &[0x66, 0x0f, 0xc4, 0xc3, 0x08], &[0x66, 0x0f, 0xc6, 0x03, 0x08], &[0x66, 0x0f, 0xc6, 0xc3, 0x08], &[0x66, 0x0f, 0xd0, 0x0f], &[0x66, 0x0f, 0xd0, 0xcf], &[0x66, 0x0f, 0xd1, 0x01], &[0x66, 0x0f, 0xd1, 0xc1], &[0x66, 0x0f, 0xd2, 0x01], &[0x66, 0x0f, 0xd2, 0xc1], &[0x66, 0x0f, 0xd3, 0x01], &[0x66, 0x0f, 0xd3, 0xc1], &[0x66, 0x0f, 0xd4, 0x01], &[0x66, 0x0f, 0xd4, 0xc1], &[0x66, 0x0f, 0xd5, 0x01], &[0x66, 0x0f, 0xd5, 0xc1], &[0x66, 0x0f, 0xd6, 0x01], &[0x66, 0x0f, 0xd6, 0xc1], &[0x66, 0x0f, 0xd7, 0xc1], &[0x66, 0x0f, 0xd8, 0x01], &[0x66, 0x0f, 0xd8, 0xc1], &[0x66, 0x0f, 0xd9, 0x01], &[0x66, 0x0f, 0xd9, 0xc1], &[0x66, 0x0f, 0xda, 0x01], &[0x66, 0x0f, 0xda, 0xc1], &[0x66, 0x0f, 0xdb, 0x01], &[0x66, 0x0f, 0xdb, 0xc1], &[0x66, 0x0f, 0xdc, 0x01], &[0x66, 0x0f, 0xdc, 0xc1], &[0x66, 0x0f, 0xdd, 0x01], &[0x66, 0x0f, 0xdd, 0xc1], &[0x66, 0x0f, 0xde, 0x01], &[0x66, 0x0f, 0xde, 0xc1], &[0x66, 0x0f, 0xdf, 0x01], &[0x66, 0x0f, 0xdf, 0xc1], &[0x66, 0x0f, 0xe0, 0x01], &[0x66, 0x0f, 0xe0, 0xc1], &[0x66, 0x0f, 0xe1, 0x01], &[0x66, 0x0f, 0xe1, 0xc1], &[0x66, 0x0f, 0xe2, 0x01], &[0x66, 0x0f, 0xe2, 0xc1], &[0x66, 0x0f, 0xe3, 0x01], &[0x66, 0x0f, 0xe3, 0xc1], &[0x66, 0x0f, 0xe4, 0x01], &[0x66, 0x0f, 0xe4, 0xc1], &[0x66, 0x0f, 0xe5, 0x01], &[0x66, 0x0f, 0xe5, 0xc1], &[0x66, 0x0f, 0xe6, 0x01], &[0x66, 0x0f, 0xe6, 0xc1], &[0x66, 0x0f, 0xe7, 0x01], &[0x66, 0x0f, 0xe8, 0x01], &[0x66, 0x0f, 0xe8, 0xc1], &[0x66, 0x0f, 0xe9, 0x01], &[0x66, 0x0f, 0xe9, 0xc1], &[0x66, 0x0f, 0xea, 0x01], &[0x66, 0x0f, 0xea, 0xc1], &[0x66, 0x0f, 0xeb, 0x01], &[0x66, 0x0f, 0xeb, 0x12], &[0x66, 0x0f, 0xeb, 0xc1], &[0x66, 0x0f, 0xeb, 0xc3], &[0x66, 0x0f, 0xeb, 0xc4], &[0x66, 0x0f, 0xeb, 0xd3], &[0x66, 0x0f, 0xec, 0x01], &[0x66, 0x0f, 0xec, 0xc1], &[0x66, 0x0f, 0xed, 0x01], &[0x66, 0x0f, 0xed, 0xc1], &[0x66, 0x0f, 0xee, 0x01], &[0x66, 0x0f, 0xee, 0xc1], &[0x66, 0x0f, 0xef, 0x01], &[0x66, 0x0f, 0xef, 0xc1], &[0x66, 0x0f, 0xf1, 0x01], &[0x66, 0x0f, 0xf1, 0xc1], &[0x66, 0x0f, 0xf2, 0x01], &[0x66, 0x0f, 0xf2, 0xc1], &[0x66, 0x0f, 0xf3, 0x01], &[0x66, 0x0f, 0xf3, 0xc1], &[0x66, 0x0f, 0xf4, 0x01], &[0x66, 0x0f, 0xf4, 0xc1], &[0x66, 0x0f, 0xf5, 0x01], &[0x66, 0x0f, 0xf5, 0xc1], &[0x66, 0x0f, 0xf6, 0x01], &[0x66, 0x0f, 0xf6, 0xc1], &[0x66, 0x0f, 0xf7, 0xc1], &[0x66, 0x0f, 0xf8, 0x01], &[0x66, 0x0f, 0xf8, 0x12], &[0x66, 0x0f, 0xf8, 0xc1], &[0x66, 0x0f, 0xf8, 0xc8], &[0x66, 0x0f, 0xf8, 0xd0], &[0x66, 0x0f, 0xf9, 0x01], &[0x66, 0x0f, 0xf9, 0xc1], &[0x66, 0x0f, 0xfa, 0x01], &[0x66, 0x0f, 0xfa, 0xc1], &[0x66, 0x0f, 0xfb, 0x01], &[0x66, 0x0f, 0xfb, 0xc1], &[0x66, 0x0f, 0xfc, 0x01], &[0x66, 0x0f, 0xfc, 0xc1], &[0x66, 0x0f, 0xfd, 0x01], &[0x66, 0x0f, 0xfd, 0xc1], &[0x66, 0x0f, 0xfe, 0x01], &[0x66, 0x0f, 0xfe, 0xc1], &[0x66, 0x0f, 0xff, 0x01], &[0x66, 0x0f, 0xff, 0xc1], &[0x66, 0x48, 0x0f, 0x3a, 0x16, 0x06, 0x31], &[0x66, 0x48, 0x0f, 0x3a, 0x22, 0x06, 0x31], &[0x66, 0x48, 0x0f, 0x6e, 0xc0], &[0x66, 0x48, 0x0f, 0x7e, 0x01], &[0x66, 0x48, 0x0f, 0x7e, 0xc1], &[0x66, 0x4f, 0x0f, 0x12, 0x03], &[0x66, 0x4f, 0x0f, 0x13, 0x03], &[0x66, 0x4f, 0x0f, 0x14, 0x03], &[0x66, 0x4f, 0x0f, 0x14, 0xc3], &[0x66, 0x4f, 0x0f, 0x15, 0x03], &[0x66, 0x4f, 0x0f, 0x15, 0xc3], &[0x66, 0x4f, 0x0f, 0x16, 0x03], &[0x66, 0x4f, 0x0f, 0x17, 0x03], &[0x66, 0x4f, 0x0f, 0x28, 0x00], &[0x66, 0x4f, 0x0f, 0x28, 0xd0], &[0x66, 0x4f, 0x0f, 0x2a, 0x0f], &[0x66, 0x4f, 0x0f, 0x2a, 0xcf], &[0x66, 0x4f, 0x0f, 0x2b, 0x0f], &[0x66, 0x4f, 0x0f, 0x2c, 0x0f], &[0x66, 0x4f, 0x0f, 0x2c, 0xcf], &[0x66, 0x4f, 0x0f, 0x2d, 0x0f], &[0x66, 0x4f, 0x0f, 0x2d, 0xcf], &[0x66, 0x4f, 0x0f, 0x2e, 0x0f], &[0x66, 0x4f, 0x0f, 0x2e, 0xcf], &[0x66, 0x4f, 0x0f, 0x2f, 0x0f], &[0x66, 0x4f, 0x0f, 0x2f, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xdb, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xdc, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xdd, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xde, 0xcf], &[0x66, 0x4f, 0x0f, 0x38, 0xdf, 0xcf], &[0x66, 0x4f, 0x0f, 0x3a, 0xdf, 0xcf, 0xaa], &[0x66, 0x4f, 0x0f, 0x50, 0xc1], &[0x66, 0x4f, 0x0f, 0x51, 0x01], &[0x66, 0x4f, 0x0f, 0x54, 0x01], &[0x66, 0x4f, 0x0f, 0x55, 0x01], &[0x66, 0x4f, 0x0f, 0x56, 0x01], &[0x66, 0x4f, 0x0f, 0x57, 0x01], &[0x66, 0x4f, 0x0f, 0x58, 0x01], &[0x66, 0x4f, 0x0f, 0x59, 0x01], &[0x66, 0x4f, 0x0f, 0x5a, 0x01], &[0x66, 0x4f, 0x0f, 0x5b, 0x01], &[0x66, 0x4f, 0x0f, 0x5c, 0x01], &[0x66, 0x4f, 0x0f, 0x5d, 0x01], &[0x66, 0x4f, 0x0f, 0x5e, 0x01], &[0x66, 0x4f, 0x0f, 0x5f, 0x01], &[0x66, 0x4f, 0x0f, 0x71, 0xd0, 0x8f], &[0x66, 0x4f, 0x0f, 0x71, 0xe0, 0x8f], &[0x66, 0x4f, 0x0f, 0x71, 0xf0, 0x8f], &[0x66, 0x4f, 0x0f, 0x72, 0xd0, 0x8f], &[0x66, 0x4f, 0x0f, 0x72, 0xe0, 0x8f], &[0x66, 0x4f, 0x0f, 0x72, 0xf0, 0x8f], &[0x66, 0x4f, 0x0f, 0x73, 0xd0, 0x8f], &[0x66, 0x4f, 0x0f, 0x73, 0xd8, 0x8f], &[0x66, 0x4f, 0x0f, 0x73, 0xf0, 0x8f], &[0x66, 0x4f, 0x0f, 0x73, 0xf8, 0x8f], &[0x66, 0x4f, 0x0f, 0x7c, 0xcf], &[0x66, 0x4f, 0x0f, 0x7d, 0xcf], &[0x66, 0x4f, 0x0f, 0x7e, 0xc1], &[0x66, 0x4f, 0x0f, 0xc2, 0x03, 0x08], &[0x66, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], &[0x66, 0x4f, 0x0f, 0xc4, 0x03, 0x08], &[0x66, 0x4f, 0x0f, 0xc4, 0xc3, 0x08], &[0x66, 0x4f, 0x0f, 0xc6, 0x03, 0x08], &[0x66, 0x4f, 0x0f, 0xd0, 0xcf], &[0x66, 0x4f, 0x0f, 0xd7, 0xc1], &[0x66, 0x4f, 0x0f, 0xff, 0xc1], &[0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc6], &[0x66, 0xf2, 0x0f, 0x79, 0xcf], &[0x66, 0xf2, 0x48, 0x0f, 0x38, 0xf1, 0xc6], &[0xc4, 0b000_00001, 0b0_0111_000, 0x14, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_000, 0x15, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_000, 0xc6, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b0_0111_001, 0x14, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x15, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x60, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x61, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x62, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x63, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x64, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x65, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x66, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x67, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x68, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x69, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x6a, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0x6b, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xc6, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b0_0111_001, 0xd5, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xda, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xde, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xea, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xeb, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xec, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xed, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xee, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_001, 0xef, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_010, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_011, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_011, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_100, 0x14, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_100, 0x15, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_100, 0xc6, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b0_0111_101, 0x14, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x15, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0x63, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_0111_101, 0xc6, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b0_0111_110, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_111, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_0111_111, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_000, 0x28, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_000, 0x29, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_000, 0x2b, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_000, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_010_001], &[0xc4, 0b000_00001, 0b0_1111_000, 0xae, 0b00_011_001], &[0xc4, 0b000_00001, 0b0_1111_001, 0x28, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x29, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x2b, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x2e, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x2f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x6f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x7e, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0x7f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_001, 0xc5, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b0_1111_001, 0xd7, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x2d, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x6f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_010, 0x7f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_011, 0x2d, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_100, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x2e, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x2f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x5c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x6f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_101, 0x7f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x2d, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x6f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_110, 0x7f, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b00_001_010], &[0xc4, 0b000_00001, 0b0_1111_111, 0x2d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x12, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x54, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x55, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x56, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x57, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x58, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_000, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_001, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x54, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x55, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x56, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x57, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x71, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_001, 0x74, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x75, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x76, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x7c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0x7d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_001, 0xc4, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xd9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xdb, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xdc, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xdd, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xdf, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe5, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xe9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf1, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf2, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf3, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf4, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf8, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xf9, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xfa, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xfb, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xfc, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xfd, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_001, 0xfe, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x58, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_010, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x11, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x7c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0x7d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_011, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_011, 0xd0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x54, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x55, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x56, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x57, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x58, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_100, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_101, 0x54, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x55, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x56, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x57, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x7c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0x7d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_101, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_101, 0xd0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x58, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_110, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x11, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x58, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x59, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x5d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x5e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x5f, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x7c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0x7d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_0111_111, 0xc2, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_0111_111, 0xd0, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x17, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x52, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x53, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_000, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x13, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x17, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x6c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x6d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x6e, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_100_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x71, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_100_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x72, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_010_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_011_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_110_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x73, 0b11_111_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_001, 0x7e, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0xe7, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0xf5, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0xf6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_001, 0xf7, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x52, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x53, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_010, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_010, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x2a, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x2d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0x70, 0b11_001_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_011, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_011, 0xf0, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x28, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x29, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x2b, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x52, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x53, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_100, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x28, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x29, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x2b, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x50, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0x72, 0b11_100_010, 0x77], &[0xc4, 0b000_00001, 0b1_1111_101, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_101, 0xe7, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x12, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x2d, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x51, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x52, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x53, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0x5b, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_110, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x10, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x11, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x2a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b00_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x2c, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x2d, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0x5a, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0xe6, 0b11_001_010], &[0xc4, 0b000_00001, 0b1_1111_111, 0xf0, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x0c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x0d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x28, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x29, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x2b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x37, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x38, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x39, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3a, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x3f, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_001, 0x40, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x0c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_0111_101, 0x0d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x00, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x01, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x02, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x03, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x04, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x05, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x06, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x07, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x08, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x09, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x0a, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x0b, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x0e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x0f, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x17, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x18, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x1c, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x1d, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x1e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x20, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x21, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x22, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x23, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x24, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x25, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x2a, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x30, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x31, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x32, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x33, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x34, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x35, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_001, 0x41, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x0e, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x0f, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x16, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x17, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x18, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x19, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x1a, 0b00_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x30, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x31, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x32, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x33, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x34, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x35, 0b11_001_010], &[0xc4, 0b000_00010, 0b0_1111_101, 0x5a, 0b00_001_010], &[0xc4, 0b000_00011, 0b0_0111_001, 0x0a, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x0b, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x0c, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x0d, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x0e, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x20, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x21, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x22, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x40, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x41, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x42, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_001, 0x4c, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x0a, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x0b, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x0c, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x0d, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x0e, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x18, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_0111_101, 0x40, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x04, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x05, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x08, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x09, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x14, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x15, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x16, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x17, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x60, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x61, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x62, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_001, 0x63, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x04, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x05, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x06, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x08, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x09, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b0_1111_101, 0x19, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_0111_001, 0x0f, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b00_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_0111_001, 0x22, 0b11_001_010, 0x77], &[0xc4, 0b000_00011, 0b1_0111_101, 0x0f, 0b11_001_010, 0x77], &[0xc4, 0x02, 0x09, 0x9d, 0xcd], &[0xc4, 0x02, 0x71, 0x00, 0x0f], &[0xc4, 0x02, 0x71, 0x00, 0xcd], &[0xc4, 0x02, 0x71, 0x01, 0x0f], &[0xc4, 0x02, 0x71, 0x01, 0xcd], &[0xc4, 0x02, 0x71, 0x02, 0x0f], &[0xc4, 0x02, 0x71, 0x02, 0xcd], &[0xc4, 0x02, 0x71, 0x03, 0x0f], &[0xc4, 0x02, 0x71, 0x03, 0xcd], &[0xc4, 0x02, 0x71, 0x04, 0x0f], &[0xc4, 0x02, 0x71, 0x04, 0xcd], &[0xc4, 0x02, 0x71, 0x05, 0x0f], &[0xc4, 0x02, 0x71, 0x05, 0xcd], &[0xc4, 0x02, 0x71, 0x06, 0x0f], &[0xc4, 0x02, 0x71, 0x06, 0xcd], &[0xc4, 0x02, 0x71, 0x07, 0x0f], &[0xc4, 0x02, 0x71, 0x07, 0xcd], &[0xc4, 0x02, 0x71, 0x08, 0x0f], &[0xc4, 0x02, 0x71, 0x08, 0xcd], &[0xc4, 0x02, 0x71, 0x09, 0x0f], &[0xc4, 0x02, 0x71, 0x09, 0xcd], &[0xc4, 0x02, 0x71, 0x0a, 0x0f], &[0xc4, 0x02, 0x71, 0x0a, 0xcd], &[0xc4, 0x02, 0x71, 0x0b, 0x0f], &[0xc4, 0x02, 0x71, 0x0b, 0xcd], &[0xc4, 0x02, 0x71, 0x0c, 0x0f], &[0xc4, 0x02, 0x71, 0x0c, 0xcd], &[0xc4, 0x02, 0x71, 0x0d, 0x0f], &[0xc4, 0x02, 0x71, 0x0d, 0xcd], &[0xc4, 0x02, 0x75, 0x00, 0x0f], &[0xc4, 0x02, 0x75, 0x00, 0xcd], &[0xc4, 0x02, 0x75, 0x01, 0x0f], &[0xc4, 0x02, 0x75, 0x01, 0xcd], &[0xc4, 0x02, 0x75, 0x02, 0x0f], &[0xc4, 0x02, 0x75, 0x02, 0xcd], &[0xc4, 0x02, 0x75, 0x03, 0x0f], &[0xc4, 0x02, 0x75, 0x03, 0xcd], &[0xc4, 0x02, 0x75, 0x04, 0x0f], &[0xc4, 0x02, 0x75, 0x04, 0xcd], &[0xc4, 0x02, 0x75, 0x05, 0x0f], &[0xc4, 0x02, 0x75, 0x05, 0xcd], &[0xc4, 0x02, 0x75, 0x06, 0x0f], &[0xc4, 0x02, 0x75, 0x06, 0xcd], &[0xc4, 0x02, 0x75, 0x07, 0x0f], &[0xc4, 0x02, 0x75, 0x07, 0xcd], &[0xc4, 0x02, 0x75, 0x08, 0x0f], &[0xc4, 0x02, 0x75, 0x08, 0xcd], &[0xc4, 0x02, 0x75, 0x09, 0x0f], &[0xc4, 0x02, 0x75, 0x09, 0xcd], &[0xc4, 0x02, 0x75, 0x0a, 0x0f], &[0xc4, 0x02, 0x75, 0x0a, 0xcd], &[0xc4, 0x02, 0x75, 0x0b, 0x0f], &[0xc4, 0x02, 0x75, 0x0b, 0xcd], &[0xc4, 0x02, 0x75, 0x0c, 0x0f], &[0xc4, 0x02, 0x75, 0x0c, 0xcd], &[0xc4, 0x02, 0x75, 0x0d, 0x0f], &[0xc4, 0x02, 0x75, 0x0d, 0xcd], &[0xc4, 0x02, 0x79, 0x0e, 0x0f], &[0xc4, 0x02, 0x79, 0x0e, 0xcd], &[0xc4, 0x02, 0x79, 0x0f, 0x0f], &[0xc4, 0x02, 0x79, 0x0f, 0xcd], &[0xc4, 0x02, 0x7d, 0x0e, 0x0f], &[0xc4, 0x02, 0x7d, 0x0e, 0xcd], &[0xc4, 0x02, 0x7d, 0x0f, 0x0f], &[0xc4, 0x02, 0x7d, 0x0f, 0xcd], &[0xc4, 0x02, 0x89, 0x9d, 0xcd], &[0xc4, 0xa2, 0x15, 0x3e, 0x14, 0xb9], &[0xc4, 0xc3, 0x71, 0x4a, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x71, 0x4a, 0xdc, 0x61], &[0xc4, 0xc3, 0x71, 0x4b, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x71, 0x4b, 0xdc, 0x61], &[0xc4, 0xc3, 0x71, 0x4c, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x75, 0x38, 0x7c, 0x12, 0x05, 0x01], &[0xc4, 0xc3, 0x75, 0x42, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x75, 0x46, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x75, 0x4a, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xc3, 0x75, 0x4b, 0x7c, 0x12, 0x05, 0x61], &[0xc4, 0xe2, 0x65, 0x90, 0x04, 0x51], &[0xc4, 0xe2, 0x65, 0x91, 0x04, 0x51], &[0xc4, 0xe2, 0xe5, 0x90, 0x04, 0x51], &[0xc4, 0xe2, 0xe5, 0x91, 0x04, 0x51], &[0xc4, 0xe3, 0x79, 0x14, 0x10, 0x0a], &[0xc4, 0xe3, 0x79, 0x14, 0xd0, 0x0a], &[0xc4, 0xe3, 0x7d, 0x19, 0xd1, 0x01], &[0xc4, 0xe3, 0xfd, 0x00, 0xc1, 0xa8], &[0xc5, 0b0_1111_000, 0x2e, 0b11_001_010], &[0xc5, 0b0_1111_000, 0x2f, 0b11_001_010], &[0xc5, 0b0_1111_010, 0x2c, 0b00_001_010], &[0xc5, 0b0_1111_010, 0x2c, 0b11_001_010], &[0xc5, 0b0_1111_010, 0x2d, 0b11_001_010], &[0xc5, 0b0_1111_011, 0x2a, 0b11_001_010], &[0xc5, 0b0_1111_011, 0x2c, 0b11_001_010], &[0xc5, 0b0_1111_011, 0x2d, 0b11_001_010], &[0xc5, 0b0_1111_100, 0x2e, 0b00_001_010], &[0xc5, 0b0_1111_100, 0x2f, 0b00_001_010], &[0xc5, 0b0_1111_110, 0x2c, 0b11_001_010], &[0xc5, 0b0_1111_110, 0x2d, 0b11_001_010], &[0xc5, 0b0_1111_111, 0x2a, 0b11_001_010], &[0xc5, 0b0_1111_111, 0x2c, 0b00_001_010], &[0xc5, 0b0_1111_111, 0x2c, 0b11_001_010], &[0xc5, 0b0_1111_111, 0x2d, 0b11_001_010], &[0xc5, 0x78, 0x10, 0x0f], &[0xc5, 0xc9, 0xf1, 0x0f], &[0xc5, 0xc9, 0xf1, 0xcf], &[0xc5, 0xc9, 0xf2, 0x0f], &[0xc5, 0xc9, 0xf2, 0xcf], &[0xc5, 0xc9, 0xf3, 0x0f], &[0xc5, 0xc9, 0xf3, 0xcf], &[0xc5, 0xcd, 0xf1, 0x0f], &[0xc5, 0xcd, 0xf1, 0xcf], &[0xc5, 0xcd, 0xf2, 0x0f], &[0xc5, 0xcd, 0xf2, 0xcf], &[0xc5, 0xcd, 0xf3, 0x0f], &[0xc5, 0xcd, 0xf3, 0xcf], &[0xc5, 0xe0, 0x54, 0x03], &[0xc5, 0xe0, 0x55, 0x03], &[0xc5, 0xe0, 0x56, 0x03], &[0xc5, 0xe1, 0x54, 0x03], &[0xc5, 0xe1, 0x55, 0x03], &[0xc5, 0xe1, 0x56, 0x03], &[0xc5, 0xed, 0x71, 0xd0, 0x04], &[0xc5, 0xed, 0x73, 0xd4, 0x20], &[0xc5, 0xf1, 0xc4, 0x18, 0x78], &[0xc5, 0xf1, 0xc4, 0xd8, 0x78], &[0xc5, 0xf8, 0x10, 0x00], &[0xc5, 0xf8, 0x10, 0x01], &[0xc5, 0xf8, 0x10, 0xcf], &[0xc5, 0xf9, 0x10, 0x0f], &[0xc5, 0xf9, 0x6e, 0x13], &[0xc5, 0xf9, 0x6e, 0xc6], &[0xc5, 0xf9, 0x7e, 0x13], &[0xc5, 0xf9, 0x7e, 0xc6], &[0xc5, 0xfa, 0x7e, 0x10], &[0xc5, 0xfc, 0x10, 0x0f], &[0xc5, 0xfd, 0x10, 0x0f], &[0xc5, 0xfd, 0xea, 0xd1], &[0xc5, 0xfd, 0xee, 0xd9], &[0xc5, 0xfe, 0x10, 0x0f], &[0xc5, 0xff, 0x10, 0x01], &[0xc5, 0xff, 0x10, 0xcf], &[0xf2, 0x0f, 0x10, 0x0c, 0xc7], &[0xf2, 0x0f, 0x11, 0x0c, 0xc7], &[0xf2, 0x0f, 0x12, 0x0f], &[0xf2, 0x0f, 0x12, 0xcf], &[0xf2, 0x0f, 0x2b, 0x06], &[0xf2, 0x0f, 0x38, 0xf0, 0x06], &[0xf2, 0x0f, 0x38, 0xf0, 0xc6], &[0xf2, 0x0f, 0x38, 0xf1, 0x06], &[0xf2, 0x0f, 0x38, 0xf1, 0xc6], &[0xf2, 0x0f, 0x70, 0xc0, 0x4e], &[0xf2, 0x0f, 0x78, 0xf1, 0x4e, 0x76], &[0xf2, 0x0f, 0x79, 0xcf], &[0xf2, 0x0f, 0x7c, 0x0f], &[0xf2, 0x0f, 0x7c, 0xcf], &[0xf2, 0x0f, 0x7d, 0x0f], &[0xf2, 0x0f, 0x7d, 0xcf], &[0xf2, 0x0f, 0xc2, 0xc3, 0x08], &[0xf2, 0x0f, 0xd0, 0x0f], &[0xf2, 0x0f, 0xd0, 0xcf], &[0xf2, 0x0f, 0xf0, 0x0f], &[0xf2, 0x0f, 0xff, 0xc1], &[0xf2, 0x4f, 0x0f, 0x12, 0xcf], &[0xf2, 0x4f, 0x0f, 0x2a, 0x0f], &[0xf2, 0x4f, 0x0f, 0x2a, 0xcf], &[0xf2, 0x4f, 0x0f, 0x2c, 0x0f], &[0xf2, 0x4f, 0x0f, 0x2c, 0xcf], &[0xf2, 0x4f, 0x0f, 0x2d, 0x0f], &[0xf2, 0x4f, 0x0f, 0x2d, 0xcf], &[0xf2, 0x4f, 0x0f, 0x51, 0x01], &[0xf2, 0x4f, 0x0f, 0x58, 0x01], &[0xf2, 0x4f, 0x0f, 0x59, 0x01], &[0xf2, 0x4f, 0x0f, 0x5a, 0x01], &[0xf2, 0x4f, 0x0f, 0x5c, 0x01], &[0xf2, 0x4f, 0x0f, 0x5d, 0x01], &[0xf2, 0x4f, 0x0f, 0x5e, 0x01], &[0xf2, 0x4f, 0x0f, 0x5f, 0x01], &[0xf2, 0x4f, 0x0f, 0x7c, 0xcf], &[0xf2, 0x4f, 0x0f, 0x7d, 0xcf], &[0xf2, 0x4f, 0x0f, 0xc2, 0x03, 0x08], &[0xf2, 0x4f, 0x0f, 0xc2, 0xc3, 0x08], &[0xf2, 0x4f, 0x0f, 0xd0, 0xcf], &[0xf2, 0x4f, 0x0f, 0xd6, 0xc3], &[0xf3, 0x0f, 0x12, 0x0f], &[0xf3, 0x0f, 0x12, 0xcf], &[0xf3, 0x0f, 0x16, 0x0f], &[0xf3, 0x0f, 0x16, 0xcf], &[0xf3, 0x0f, 0x2b, 0x06], &[0xf3, 0x0f, 0x70, 0xc0, 0x4e], &[0xf3, 0x0f, 0xff, 0xc1], &[0xf3, 0x4f, 0x0f, 0x12, 0xcf], &[0xf3, 0x4f, 0x0f, 0x16, 0xcf], &[0xf3, 0x4f, 0x0f, 0xd6, 0xc3], &[0xc4, 0b000_00010, 0b0_1111_001, 0xdb, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_001, 0xdc, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_001, 0xdd, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_001, 0xde, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_001, 0xdf, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_101, 0xdc, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_101, 0xdd, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_101, 0xde, 0b11_001_010], &[0xc4, 0b000_00010, 0b1_0111_101, 0xdf, 0b11_001_010], &[0xc4, 0b000_00011, 0b1_1111_001, 0xdf, 0b11_001_010, 0x77], ]; #[test] fn test_against_leftover_data() { use super::rand::{thread_rng, Rng}; use yaxpeax_arch::U8Reader; let mut rng = thread_rng(); let decoder = InstDecoder::default(); for _ in 0..100000 { let first_vec = INSTRUCTIONS[rng.gen_range(0..INSTRUCTIONS.len())]; let mut first_reader = U8Reader::new(first_vec); let first_decode = decoder.decode(&mut first_reader).unwrap(); let second_vec = INSTRUCTIONS[rng.gen_range(0..INSTRUCTIONS.len())]; let mut second_reader = U8Reader::new(second_vec); let mut reused_decode = decoder.decode(&mut second_reader).unwrap(); let mut first_reader = U8Reader::new(first_vec); decoder.decode_into(&mut reused_decode, &mut first_reader).unwrap(); assert_eq!(first_decode, reused_decode); } } yaxpeax-x86-1.2.2/test/protected_mode/display.rs000064400000000000000000000144101046102023000177170ustar 00000000000000use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, LengthedInstruction}; use yaxpeax_x86::protected_mode::{DisplayStyle, InstDecoder}; fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), DisplayStyle::Intel, data, expected); } fn test_c_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), DisplayStyle::C, data, expected); } fn test_display_under(decoder: &InstDecoder, style: DisplayStyle, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { let text = format!("{}", instr.display_with(style)); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u32.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } } } // decided i do not like at&t syntax much at all. not going to write a formatter for it. some test // cases will live on in case someone else feels like adding one, or i get mad enough to do it. #[allow(unreachable_code)] #[ignore] #[test] fn test_instructions_atnt() { // `ignore` is now used to avoid running (slow!) exhaustive tests in a default `cargo test`. // running exhaustive tests now runs these tests, which fail. so instead, return early. return; // just modrm test_display(&[0x33, 0x08], "xor (%eax), %ecx"); test_display(&[0x33, 0x20], "xor (%eax), %esp"); test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor (0x12345678), %eax"); test_display(&[0x33, 0x41, 0x23], "xor 0x23(%ecx), %eax"); test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor %0x43650123, %eax"); test_display(&[0x33, 0xc1], "xor %ecx, %eax"); // sib test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor (0x44332211), %eax"); test_display(&[0x41, 0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor (0x44332211), %eax"); test_display(&[0x33, 0x44, 0x65, 0x11], "xor 0x11(%r13), %eax"); test_display(&[0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor 0x50403020, %esi"); test_display(&[0x0f, 0xe7, 0x03], "movntq %mm0, (%ebx)"); test_display(&[0x0f, 0x7f, 0x0f], "movq %mm1, (%edi)"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw $0x14, %eax, %mm0"); test_display(&[0x0f, 0xd1, 0x00], "psrlw (%eax), %mm0"); test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw 0x77ccbbaa, %mm7"); } #[test] fn test_instructions_c() { // just modrm test_c_display(&[0x33, 0x08], "ecx ^= [eax]"); test_c_display(&[0x33, 0x20], "esp ^= [eax]"); test_c_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "eax ^= [0x12345678]"); test_c_display(&[0x33, 0x41, 0x23], "eax ^= [ecx + 0x23]"); test_c_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "eax ^= [ecx + 0x43650123]"); test_c_display(&[0x33, 0xc1], "eax ^= ecx"); // sib test_c_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "eax ^= [0x44332211]"); test_c_display(&[0x33, 0x44, 0x65, 0x11], "eax ^= [ebp + 0x11]"); test_c_display(&[0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "esi ^= [0x50403020]"); test_c_display(&[0x0f, 0xe7, 0x03], "[ebx] = movntq(mm0)"); test_c_display(&[0x0f, 0x7f, 0x0f], "[edi] = movq(mm1)"); test_c_display(&[0x0f, 0xc4, 0xc0, 0x14], "mm0 = pinsrw(mm0, eax, 0x14)"); test_c_display(&[0x0f, 0xd1, 0x00], "mm0 = psrlw(mm0, [eax])"); test_c_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "mm7 = pmulhw(mm7, [0x77ccbbaa])"); test_c_display(&[0xf3, 0xa5], "rep dword { es:[edi++] = ds:[esi++] }"); test_c_display(&[0xf3, 0x66, 0xa5], "rep word { es:[edi++] = ds:[esi++] }"); test_c_display(&[0xf3, 0xa4], "rep byte { es:[edi++] = ds:[esi++] }"); test_c_display(&[0xf6, 0xc2, 0x18], "eflags = flags(dl & 0x18)"); test_c_display(&[0xf6, 0xc2, 0x18], "eflags = flags(dl & 0x18)"); test_c_display(&[0x84, 0xc0], "eflags = flags(al & al)"); test_c_display(&[0x85, 0xc0], "eflags = flags(eax & eax)"); test_c_display(&[0x3a, 0xc0], "eflags = flags(al - al)"); test_c_display(&[0x3b, 0xc0], "eflags = flags(eax - eax)"); test_c_display(&[0x0f, 0xbc, 0xd3], "edx = lsb(ebx) (x86 bsf)"); test_c_display(&[0xf3, 0x0f, 0xbc, 0xd3], "edx = lsb(ebx)"); // test_c_display(&[0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(ebx) (x86 bsf"); // for non-bm1 test_c_display(&[0x0f, 0xbd, 0xd3], "edx = msb(ebx)"); // test_c_display(&[0x41, 0x0f, 0xbc, 0xd3], "edx = lsb(ebx) (x86 bsr"); // for non-bm1 test_c_display(&[0xd2, 0xc0], "al = al rol cl"); test_c_display(&[0xd2, 0xc8], "al = al ror cl"); test_c_display(&[0xd2, 0xd0], "al = al rcl cl"); test_c_display(&[0xd2, 0xd8], "al = al rcr cl"); test_c_display(&[0xd2, 0xe0], "al = al << cl"); test_c_display(&[0xd2, 0xe8], "al = al >> cl"); test_c_display(&[0xd2, 0xf0], "al = al <<< cl"); test_c_display(&[0xd2, 0xf8], "al = al >>> cl"); test_c_display(&[0xc4, 0xc3, 0x7b, 0xf0, 0x01, 0x05], "eax = [ecx] ror 0x5 (x86 rorx)"); test_c_display(&[0xc4, 0xc2, 0xe3, 0xf7, 0x01], "eax = [ecx] >> ebx (x86 shrx)"); test_c_display(&[0xc4, 0xc2, 0xe1, 0xf7, 0x01], "eax = [ecx] << ebx (x86 shlx)"); test_c_display(&[0xd2, 0xe0], "al = al << cl"); test_c_display(&[0x66, 0x0f, 0xac, 0xcf, 0x11], "di = shrd(di, cx, 0x11)"); test_c_display(&[0x0f, 0xa5, 0xc9], "ecx = shld(ecx, ecx, cl)"); test_c_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "eax += [ecx] + eflags.cf"); test_c_display(&[0xfe, 0x00], "byte [eax]++"); test_c_display(&[0x66, 0xff, 0x08], "word [eax]--"); test_c_display(&[0xff, 0x00], "dword [eax]++"); test_c_display(&[0xff, 0xe0], "jmp eax"); } yaxpeax-x86-1.2.2/test/protected_mode/evex_generated.rs000064400000000000000000063250521046102023000212540ustar 00000000000000use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, U8Reader, LengthedInstruction}; use yaxpeax_x86::protected_mode::InstDecoder; #[allow(dead_code)] fn test_invalid(data: &[u8]) { test_invalid_under(&InstDecoder::default(), data); } fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) { let mut reader = U8Reader::new(data); if let Ok(inst) = decoder.decode(&mut reader) { // realistically, the chances an error only shows up under non-fmt builds seems unlikely, // but try to report *something* in such cases. cfg_if::cfg_if! { if #[cfg(feature="fmt")] { panic!("decoded {:?} from {:02x?} under decoder {}", inst.opcode(), data, decoder); } else { // don't warn about the unused inst here let _ = inst; panic!("decoded instruction from {:02x?} under decoder ", data); } } } else { // this is fine } } #[allow(dead_code)] fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), data, expected); } fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { let text = format!("{}", instr); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); } else { eprintln!("non-fmt build cannot compare text equality") } } // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u32.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } fn test_avx_full(bytes: &[u8], text: &'static str) { // test with a hypothetical CPU that supports all of AVX512. at time of writing, no such CPU // exists. test_display_under(&InstDecoder::minimal().with_avx512(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } #[allow(non_snake_case)] #[test] fn tests_None_0f() { test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0xca], "vmovups ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0x0a], "vmovups ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0x4a, 0x01], "vmovups ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0xca], "vmovups ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0xca], "vmovups ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0x0a], "vmovups ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0x0a], "vmovups ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0x4a, 0x01], "vmovups ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0x4a, 0x01], "vmovups ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0xca], "vmovups zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0x0a], "vmovups zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0x4a, 0x01], "vmovups zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0xca], "vmovups zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0xca], "vmovups zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0x0a], "vmovups zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0x0a], "vmovups zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0x4a, 0x01], "vmovups zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0x4a, 0x01], "vmovups zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0xca], "vmovups xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0x0a], "vmovups xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0x4a, 0x01], "vmovups xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0xca], "vmovups xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0xca], "vmovups xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0x0a], "vmovups xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0x0a], "vmovups xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0x4a, 0x01], "vmovups xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0x4a, 0x01], "vmovups xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x11, 0xca], "vmovups ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0xca], "vmovups ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0xca], "vmovups ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0x0a], "vmovups ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0x0a], "vmovups ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0x4a, 0x01], "vmovups ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0x4a, 0x01], "vmovups ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x11, 0xca], "vmovups zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0xca], "vmovups zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0xca], "vmovups zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0x0a], "vmovups zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0x0a], "vmovups zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0x4a, 0x01], "vmovups zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0x4a, 0x01], "vmovups zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0xca], "vmovups xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0xca], "vmovups xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0xca], "vmovups xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x0a], "vmovups xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x4a, 0x01], "vmovups xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x4a, 0x01], "vmovups xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x4a, 0x01], "vmovlps xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x4a, 0x01], "vmovlps qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x14, 0x0a], "vunpcklps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x14, 0x4a, 0x01], "vunpcklps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0xca], "vunpcklps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0xca], "vunpcklps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0xca], "vunpcklps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0x0a], "vunpcklps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0x4a, 0x01], "vunpcklps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x14, 0x0a], "vunpcklps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x14, 0x4a, 0x01], "vunpcklps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x14, 0x0a], "vunpcklps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x14, 0x4a, 0x01], "vunpcklps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0xca], "vunpcklps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0xca], "vunpcklps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0xca], "vunpcklps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0x0a], "vunpcklps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0x4a, 0x01], "vunpcklps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0xca], "vunpcklps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0xca], "vunpcklps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0xca], "vunpcklps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0x0a], "vunpcklps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0x4a, 0x01], "vunpcklps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x15, 0x0a], "vunpckhps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x15, 0x4a, 0x01], "vunpckhps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0xca], "vunpckhps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0xca], "vunpckhps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0xca], "vunpckhps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0x0a], "vunpckhps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0x4a, 0x01], "vunpckhps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x15, 0x0a], "vunpckhps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x15, 0x4a, 0x01], "vunpckhps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x15, 0x0a], "vunpckhps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x15, 0x4a, 0x01], "vunpckhps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0xca], "vunpckhps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0xca], "vunpckhps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0xca], "vunpckhps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0x0a], "vunpckhps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0x4a, 0x01], "vunpckhps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0xca], "vunpckhps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0xca], "vunpckhps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0xca], "vunpckhps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x4a, 0x01], "vunpckhps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x4a, 0x01], "vmovhps xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x4a, 0x01], "vmovhps qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x4a, 0x01], "vmovaps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x0a], "vmovaps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0x0a], "vmovaps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x4a, 0x01], "vmovaps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0x4a, 0x01], "vmovaps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0xca], "vmovaps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0x0a], "vmovaps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0x4a, 0x01], "vmovaps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0xca], "vmovaps zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0xca], "vmovaps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0x0a], "vmovaps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x0a], "vmovaps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0x4a, 0x01], "vmovaps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x4a, 0x01], "vmovaps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0xca], "vmovaps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x0a], "vmovaps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x4a, 0x01], "vmovaps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0xca], "vmovaps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0xca], "vmovaps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0x0a], "vmovaps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0x0a], "vmovaps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0x4a, 0x01], "vmovaps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0x4a, 0x01], "vmovaps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x29, 0xca], "vmovaps ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0xca], "vmovaps ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0xca], "vmovaps ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0x0a], "vmovaps ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0x0a], "vmovaps ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0x4a, 0x01], "vmovaps ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0x4a, 0x01], "vmovaps ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x29, 0xca], "vmovaps zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0xca], "vmovaps zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0xca], "vmovaps zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x0a], "vmovaps zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x0a], "vmovaps zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x4a, 0x01], "vmovaps zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x4a, 0x01], "vmovaps zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x29, 0xca], "vmovaps xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0xca], "vmovaps xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0xca], "vmovaps xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x0a], "vmovaps xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0x0a], "vmovaps xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x4a, 0x01], "vmovaps xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0x4a, 0x01], "vmovaps xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x0a], "vmovntps ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x4a, 0x01], "vmovntps ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x0a], "vmovntps zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x4a, 0x01], "vmovntps zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x4a, 0x01], "vmovntps xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x4a, 0x01], "vucomiss xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x4a, 0x01], "vcomiss xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0xca], "vsqrtps zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0xca], "vsqrtps zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0x0a], "vsqrtps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0x0a], "vsqrtps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0x4a, 0x01], "vsqrtps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0xca], "vsqrtps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0xca], "vsqrtps ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0xca], "vsqrtps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0x0a], "vsqrtps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0x0a], "vsqrtps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0x4a, 0x01], "vsqrtps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0xca], "vsqrtps zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0xca], "vsqrtps zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0x0a], "vsqrtps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0x0a], "vsqrtps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0x4a, 0x01], "vsqrtps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0xca], "vsqrtps zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0xca], "vsqrtps zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0x0a], "vsqrtps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0x0a], "vsqrtps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0x4a, 0x01], "vsqrtps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0xca], "vsqrtps zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0xca], "vsqrtps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0x0a], "vsqrtps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0x0a], "vsqrtps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0x4a, 0x01], "vsqrtps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0xca], "vsqrtps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0xca], "vsqrtps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0xca], "vsqrtps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0x0a], "vsqrtps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0x0a], "vsqrtps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0x4a, 0x01], "vsqrtps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x54, 0x4a, 0x01], "vandps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x54, 0x0a], "vandps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x54, 0x4a, 0x01], "vandps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x54, 0x4a, 0x01], "vandps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0xca], "vandps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0x4a, 0x01], "vandps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0xca], "vandps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0xca], "vandps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0x0a], "vandps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0x4a, 0x01], "vandps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0x4a, 0x01], "vandps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x54, 0x4a, 0x01], "vandps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x54, 0x0a], "vandps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x54, 0x4a, 0x01], "vandps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x54, 0x4a, 0x01], "vandps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x54, 0x0a], "vandps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x54, 0x4a, 0x01], "vandps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0xca], "vandps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0x4a, 0x01], "vandps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0xca], "vandps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0xca], "vandps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0x0a], "vandps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0x4a, 0x01], "vandps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0x4a, 0x01], "vandps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0xca], "vandps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0xca], "vandps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0xca], "vandps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0x0a], "vandps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0x4a, 0x01], "vandps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x55, 0x0a], "vandnps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x55, 0x4a, 0x01], "vandnps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0xca], "vandnps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0xca], "vandnps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0xca], "vandnps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0x0a], "vandnps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0x4a, 0x01], "vandnps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x55, 0x0a], "vandnps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x55, 0x4a, 0x01], "vandnps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x55, 0x0a], "vandnps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x55, 0x4a, 0x01], "vandnps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0xca], "vandnps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0xca], "vandnps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0xca], "vandnps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0x0a], "vandnps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0x4a, 0x01], "vandnps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0xca], "vandnps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0xca], "vandnps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0xca], "vandnps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0x0a], "vandnps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0x4a, 0x01], "vandnps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x56, 0x4a, 0x01], "vorps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x56, 0x0a], "vorps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x56, 0x4a, 0x01], "vorps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x56, 0x4a, 0x01], "vorps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0xca], "vorps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0x4a, 0x01], "vorps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0xca], "vorps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0xca], "vorps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0x0a], "vorps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0x4a, 0x01], "vorps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0x4a, 0x01], "vorps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x56, 0x4a, 0x01], "vorps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x56, 0x0a], "vorps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x56, 0x4a, 0x01], "vorps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x56, 0x4a, 0x01], "vorps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x56, 0x0a], "vorps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x56, 0x4a, 0x01], "vorps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0xca], "vorps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0x4a, 0x01], "vorps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0xca], "vorps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0xca], "vorps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0x0a], "vorps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0x4a, 0x01], "vorps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0x4a, 0x01], "vorps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0xca], "vorps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0xca], "vorps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0xca], "vorps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0x0a], "vorps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0x4a, 0x01], "vorps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x57, 0x0a], "vxorps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x57, 0x4a, 0x01], "vxorps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0xca], "vxorps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0xca], "vxorps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0xca], "vxorps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0x0a], "vxorps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0x4a, 0x01], "vxorps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x57, 0x0a], "vxorps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x57, 0x4a, 0x01], "vxorps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x57, 0x0a], "vxorps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x57, 0x4a, 0x01], "vxorps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0xca], "vxorps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0xca], "vxorps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0xca], "vxorps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0x0a], "vxorps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0x4a, 0x01], "vxorps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0xca], "vxorps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0xca], "vxorps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0xca], "vxorps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0x0a], "vxorps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0x4a, 0x01], "vxorps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x58, 0xca], "vaddps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x58, 0xca], "vaddps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0xca], "vaddps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0xca], "vaddps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0x0a], "vaddps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0x4a, 0x01], "vaddps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0xca], "vaddps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0xca], "vaddps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0xca], "vaddps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0x0a], "vaddps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0x4a, 0x01], "vaddps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0xca], "vaddps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0xca], "vaddps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0xca], "vaddps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0x0a], "vaddps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0x4a, 0x01], "vaddps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0xca], "vaddps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0xca], "vaddps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0xca], "vaddps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0x0a], "vaddps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0x4a, 0x01], "vaddps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0xca], "vaddps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0xca], "vaddps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0xca], "vaddps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0x0a], "vaddps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0x4a, 0x01], "vaddps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0xca], "vaddps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0xca], "vaddps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0xca], "vaddps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0x0a], "vaddps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0x4a, 0x01], "vaddps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x59, 0xca], "vmulps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x59, 0xca], "vmulps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0xca], "vmulps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0xca], "vmulps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0x0a], "vmulps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0x4a, 0x01], "vmulps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0xca], "vmulps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0xca], "vmulps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0xca], "vmulps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0x0a], "vmulps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0x4a, 0x01], "vmulps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0xca], "vmulps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0xca], "vmulps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0xca], "vmulps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0x0a], "vmulps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0x4a, 0x01], "vmulps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0xca], "vmulps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0xca], "vmulps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0xca], "vmulps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0x0a], "vmulps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0x4a, 0x01], "vmulps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0xca], "vmulps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0xca], "vmulps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0xca], "vmulps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0x0a], "vmulps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0x4a, 0x01], "vmulps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0xca], "vmulps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0xca], "vmulps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0xca], "vmulps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0x0a], "vmulps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0x4a, 0x01], "vmulps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x0a], "vcvtps2pd ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0xca], "vcvtps2pd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0xca], "vcvtps2pd ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0xca], "vcvtps2pd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0x0a], "vcvtps2pd ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5a, 0x0a], "vcvtps2pd zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5a, 0x0a], "vcvtps2pd xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0xca], "vcvtps2pd zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0x0a], "vcvtps2pd zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0xca], "vcvtps2pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0x0a], "vcvtps2pd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x5b, 0xca], "vcvtqq2ps ymm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0xca], "vcvtqq2ps ymm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0xca], "vcvtqq2ps xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0x0a], "vcvtqq2ps xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5b, 0xca], "vcvtdq2ps zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0xca], "vcvtdq2ps zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0x0a], "vcvtdq2ps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0xca], "vcvtdq2ps ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0x0a], "vcvtdq2ps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0xca], "vcvtqq2ps ymm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0x0a], "vcvtqq2ps ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0xca], "vcvtqq2ps ymm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0xca], "vcvtqq2ps ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0x0a], "vcvtqq2ps ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0xca], "vcvtqq2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0x0a], "vcvtqq2ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0xca], "vcvtdq2ps zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0x0a], "vcvtdq2ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0xca], "vcvtdq2ps zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0x0a], "vcvtdq2ps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0xca], "vcvtdq2ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0x0a], "vcvtdq2ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0xca], "vcvtdq2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0x0a], "vcvtdq2ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5c, 0xca], "vsubps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5c, 0xca], "vsubps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0xca], "vsubps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0xca], "vsubps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0x0a], "vsubps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0x4a, 0x01], "vsubps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0xca], "vsubps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0xca], "vsubps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0xca], "vsubps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0x0a], "vsubps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0x4a, 0x01], "vsubps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0xca], "vsubps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0xca], "vsubps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0x0a], "vsubps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0x4a, 0x01], "vsubps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0xca], "vsubps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0xca], "vsubps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0x0a], "vsubps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0x4a, 0x01], "vsubps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0xca], "vsubps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0xca], "vsubps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0xca], "vsubps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0x0a], "vsubps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0x4a, 0x01], "vsubps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0xca], "vsubps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0xca], "vsubps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0xca], "vsubps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0x0a], "vsubps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0x4a, 0x01], "vsubps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5d, 0xca], "vminps zmm1{k5}{z}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5d, 0xca], "vminps zmm1{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5d, 0xca], "vminps zmm1{k5}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5d, 0x0a], "vminps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5d, 0x4a, 0x01], "vminps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0xca], "vminps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0xca], "vminps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0xca], "vminps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0x0a], "vminps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0x4a, 0x01], "vminps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5d, 0x0a], "vminps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5d, 0x4a, 0x01], "vminps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5d, 0x0a], "vminps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5d, 0x4a, 0x01], "vminps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0xca], "vminps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0xca], "vminps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0xca], "vminps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0x0a], "vminps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0x4a, 0x01], "vminps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0xca], "vminps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0xca], "vminps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0xca], "vminps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0x0a], "vminps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0x4a, 0x01], "vminps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5e, 0xca], "vdivps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5e, 0xca], "vdivps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0xca], "vdivps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0xca], "vdivps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0x0a], "vdivps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0x4a, 0x01], "vdivps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0xca], "vdivps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0xca], "vdivps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0xca], "vdivps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0x0a], "vdivps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0x4a, 0x01], "vdivps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0xca], "vdivps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0xca], "vdivps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0x0a], "vdivps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0x4a, 0x01], "vdivps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0xca], "vdivps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0xca], "vdivps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0x0a], "vdivps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0x4a, 0x01], "vdivps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0xca], "vdivps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0xca], "vdivps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0xca], "vdivps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0x0a], "vdivps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0x4a, 0x01], "vdivps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0xca], "vdivps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0xca], "vdivps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0xca], "vdivps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0x0a], "vdivps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0x4a, 0x01], "vdivps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x5f, 0xca], "vmaxps zmm1{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x5f, 0xca], "vmaxps zmm1{k5}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5f, 0x0a], "vmaxps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x5f, 0x4a, 0x01], "vmaxps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0xca], "vmaxps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0xca], "vmaxps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0xca], "vmaxps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0x0a], "vmaxps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0x4a, 0x01], "vmaxps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5f, 0x0a], "vmaxps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x5f, 0x4a, 0x01], "vmaxps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5f, 0x0a], "vmaxps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x5f, 0x4a, 0x01], "vmaxps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0xca], "vmaxps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0xca], "vmaxps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0x0a], "vmaxps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0x4a, 0x01], "vmaxps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0xca], "vmaxps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0xca], "vmaxps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0xca], "vmaxps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0x0a], "vmaxps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0x4a, 0x01], "vmaxps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x78, 0xca], "vcvttpd2udq ymm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0xca], "vcvttpd2udq xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0x0a], "vcvttpd2udq xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x78, 0xca], "vcvttps2udq zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x78, 0xca], "vcvttps2udq zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x78, 0x0a], "vcvttps2udq ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0xca], "vcvttps2udq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0xca], "vcvttps2udq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0xca], "vcvttps2udq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0x0a], "vcvttps2udq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x78, 0x0a], "vcvttpd2udq ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0xca], "vcvttpd2udq ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0x0a], "vcvttpd2udq ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0xca], "vcvttpd2udq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0x0a], "vcvttpd2udq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x78, 0x0a], "vcvttps2udq zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x78, 0x0a], "vcvttps2udq xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0xca], "vcvttps2udq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0xca], "vcvttps2udq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0x0a], "vcvttps2udq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0xca], "vcvttps2udq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0xca], "vcvttps2udq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0xca], "vcvttps2udq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0x0a], "vcvttps2udq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xfd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x78, 0x79, 0xca], "vcvtpd2udq ymm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x7d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0xca], "vcvtpd2udq ymm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0xca], "vcvtpd2udq xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0x0a], "vcvtpd2udq xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xfd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0x79, 0xca], "vcvtps2udq zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0xca], "vcvtps2udq zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0x0a], "vcvtps2udq ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0xca], "vcvtps2udq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0xca], "vcvtps2udq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0xca], "vcvtps2udq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0x0a], "vcvtps2udq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0xca], "vcvtpd2udq ymm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0x0a], "vcvtpd2udq ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0xca], "vcvtpd2udq ymm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0xca], "vcvtpd2udq ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0x0a], "vcvtpd2udq ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0xca], "vcvtpd2udq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0x0a], "vcvtpd2udq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0xca], "vcvtps2udq zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0x0a], "vcvtps2udq zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0xca], "vcvtps2udq zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0x0a], "vcvtps2udq xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0xca], "vcvtps2udq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0xca], "vcvtps2udq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0x0a], "vcvtps2udq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0xca], "vcvtps2udq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0xca], "vcvtps2udq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0xca], "vcvtps2udq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0x0a], "vcvtps2udq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0xca, 0xcc], "vcmpps k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0xca, 0xcc], "vcmpps k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0xca, 0xcc], "vcmpps k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0xca, 0xcc], "vshufps ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xdd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x58, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x5d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x9d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x18, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x1d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0xca, 0xcc], "vshufps zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0xca, 0xcc], "vshufps xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); } #[test] fn tests_66_0f() { test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0xca], "vmovupd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0x0a], "vmovupd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0x4a, 0x01], "vmovupd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0xca], "vmovupd ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0xca], "vmovupd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0x0a], "vmovupd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x0a], "vmovupd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0x4a, 0x01], "vmovupd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x4a, 0x01], "vmovupd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0xca], "vmovupd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x0a], "vmovupd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x4a, 0x01], "vmovupd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0xca], "vmovupd zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0xca], "vmovupd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x0a], "vmovupd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0x0a], "vmovupd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x4a, 0x01], "vmovupd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0x4a, 0x01], "vmovupd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0xca], "vmovupd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0x0a], "vmovupd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0x4a, 0x01], "vmovupd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0xca], "vmovupd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0xca], "vmovupd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0x0a], "vmovupd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0x0a], "vmovupd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0x4a, 0x01], "vmovupd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0x4a, 0x01], "vmovupd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x11, 0xca], "vmovupd ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0xca], "vmovupd ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0xca], "vmovupd ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0x0a], "vmovupd ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0x0a], "vmovupd ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0x4a, 0x01], "vmovupd ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0x4a, 0x01], "vmovupd ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x11, 0xca], "vmovupd zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0xca], "vmovupd zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0xca], "vmovupd zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0x0a], "vmovupd zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0x0a], "vmovupd zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0x4a, 0x01], "vmovupd zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0x4a, 0x01], "vmovupd zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x11, 0xca], "vmovupd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0xca], "vmovupd xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0xca], "vmovupd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0x0a], "vmovupd xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0x0a], "vmovupd xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0x4a, 0x01], "vmovupd xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0x4a, 0x01], "vmovupd xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x12, 0x0a], "vmovlpd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x12, 0x4a, 0x01], "vmovlpd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x13, 0x0a], "vmovlpd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x13, 0x4a, 0x01], "vmovlpd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x4a, 0x01], "vunpcklpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0xca], "vunpcklpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0xca], "vunpcklpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0xca], "vunpcklpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0x4a, 0x01], "vunpcklpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x14, 0x4a, 0x01], "vunpcklpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x14, 0x4a, 0x01], "vunpcklpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0xca], "vunpcklpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0xca], "vunpcklpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0xca], "vunpcklpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0x4a, 0x01], "vunpcklpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0xca], "vunpcklpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0xca], "vunpcklpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0xca], "vunpcklpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0x4a, 0x01], "vunpcklpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x4a, 0x01], "vunpckhpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0xca], "vunpckhpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0xca], "vunpckhpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0xca], "vunpckhpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0x4a, 0x01], "vunpckhpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x15, 0x4a, 0x01], "vunpckhpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x15, 0x4a, 0x01], "vunpckhpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0xca], "vunpckhpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0xca], "vunpckhpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0xca], "vunpckhpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0x4a, 0x01], "vunpckhpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0xca], "vunpckhpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0xca], "vunpckhpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0xca], "vunpckhpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0x4a, 0x01], "vunpckhpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x16, 0x0a], "vmovhpd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x16, 0x4a, 0x01], "vmovhpd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x17, 0x0a], "vmovhpd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x17, 0x4a, 0x01], "vmovhpd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0xca], "vmovapd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0x0a], "vmovapd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0x4a, 0x01], "vmovapd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0xca], "vmovapd ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0xca], "vmovapd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x0a], "vmovapd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x0a], "vmovapd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x4a, 0x01], "vmovapd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x4a, 0x01], "vmovapd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0xca], "vmovapd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x0a], "vmovapd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x4a, 0x01], "vmovapd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0xca], "vmovapd zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0xca], "vmovapd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0x0a], "vmovapd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0x0a], "vmovapd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0x4a, 0x01], "vmovapd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0x4a, 0x01], "vmovapd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0xca], "vmovapd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0x0a], "vmovapd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0x4a, 0x01], "vmovapd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0xca], "vmovapd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0xca], "vmovapd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0x0a], "vmovapd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0x0a], "vmovapd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0x4a, 0x01], "vmovapd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0x4a, 0x01], "vmovapd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x29, 0xca], "vmovapd ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0xca], "vmovapd ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0xca], "vmovapd ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0x0a], "vmovapd ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0x0a], "vmovapd ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0x4a, 0x01], "vmovapd ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0x4a, 0x01], "vmovapd ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x29, 0xca], "vmovapd zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0xca], "vmovapd zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0xca], "vmovapd zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0x0a], "vmovapd zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0x0a], "vmovapd zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0x4a, 0x01], "vmovapd zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0x4a, 0x01], "vmovapd zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x29, 0xca], "vmovapd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0xca], "vmovapd xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0xca], "vmovapd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0x0a], "vmovapd xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0x0a], "vmovapd xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0x4a, 0x01], "vmovapd xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0x4a, 0x01], "vmovapd xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x0a], "vmovntpd ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x4a, 0x01], "vmovntpd ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x4a, 0x01], "vmovntpd zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x4a, 0x01], "vmovntpd xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x4a, 0x01], "vucomisd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0xca], "vcomisd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x0a], "vcomisd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x4a, 0x01], "vcomisd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x51, 0xca], "vsqrtpd zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0xca], "vsqrtpd zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0x0a], "vsqrtpd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0x4a, 0x01], "vsqrtpd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0xca], "vsqrtpd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0xca], "vsqrtpd ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0xca], "vsqrtpd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0x0a], "vsqrtpd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0x4a, 0x01], "vsqrtpd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0xca], "vsqrtpd zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0xca], "vsqrtpd zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0x0a], "vsqrtpd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0x4a, 0x01], "vsqrtpd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0xca], "vsqrtpd zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0x0a], "vsqrtpd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0x4a, 0x01], "vsqrtpd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0xca], "vsqrtpd zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0xca], "vsqrtpd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0x0a], "vsqrtpd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0x4a, 0x01], "vsqrtpd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0xca], "vsqrtpd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0xca], "vsqrtpd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0xca], "vsqrtpd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0x0a], "vsqrtpd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0x4a, 0x01], "vsqrtpd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x54, 0x0a], "vandpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x54, 0x4a, 0x01], "vandpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0xca], "vandpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0xca], "vandpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0xca], "vandpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0x0a], "vandpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0x4a, 0x01], "vandpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x54, 0x0a], "vandpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x54, 0x4a, 0x01], "vandpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x54, 0x0a], "vandpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x54, 0x4a, 0x01], "vandpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0xca], "vandpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0xca], "vandpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0xca], "vandpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0x0a], "vandpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0x4a, 0x01], "vandpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0xca], "vandpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0xca], "vandpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0xca], "vandpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0x0a], "vandpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0x4a, 0x01], "vandpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x55, 0x0a], "vandnpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x55, 0x4a, 0x01], "vandnpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0xca], "vandnpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0xca], "vandnpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0xca], "vandnpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0x0a], "vandnpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0x4a, 0x01], "vandnpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x55, 0x0a], "vandnpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x55, 0x4a, 0x01], "vandnpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x55, 0x0a], "vandnpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x55, 0x4a, 0x01], "vandnpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0xca], "vandnpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0xca], "vandnpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0xca], "vandnpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0x0a], "vandnpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0x4a, 0x01], "vandnpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0xca], "vandnpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0xca], "vandnpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0xca], "vandnpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0x0a], "vandnpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0x4a, 0x01], "vandnpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x56, 0x0a], "vorpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x56, 0x4a, 0x01], "vorpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0xca], "vorpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0xca], "vorpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0xca], "vorpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0x0a], "vorpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0x4a, 0x01], "vorpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x56, 0x0a], "vorpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x56, 0x4a, 0x01], "vorpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x56, 0x0a], "vorpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x56, 0x4a, 0x01], "vorpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0xca], "vorpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0xca], "vorpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0xca], "vorpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0x0a], "vorpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0x4a, 0x01], "vorpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0xca], "vorpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0xca], "vorpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0xca], "vorpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0x0a], "vorpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0x4a, 0x01], "vorpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x57, 0x0a], "vxorpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x57, 0x4a, 0x01], "vxorpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0xca], "vxorpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0xca], "vxorpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0xca], "vxorpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0x0a], "vxorpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0x4a, 0x01], "vxorpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x57, 0x0a], "vxorpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x57, 0x4a, 0x01], "vxorpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x57, 0x0a], "vxorpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x57, 0x4a, 0x01], "vxorpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0xca], "vxorpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0xca], "vxorpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0xca], "vxorpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0x0a], "vxorpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0x4a, 0x01], "vxorpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0xca], "vxorpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0xca], "vxorpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0xca], "vxorpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0x0a], "vxorpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0x4a, 0x01], "vxorpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x58, 0xca], "vaddpd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x58, 0xca], "vaddpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0xca], "vaddpd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0xca], "vaddpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0x0a], "vaddpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0x4a, 0x01], "vaddpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0xca], "vaddpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0xca], "vaddpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0xca], "vaddpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0x0a], "vaddpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0x4a, 0x01], "vaddpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0xca], "vaddpd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0xca], "vaddpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0x0a], "vaddpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0x4a, 0x01], "vaddpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0xca], "vaddpd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0xca], "vaddpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0x0a], "vaddpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0x4a, 0x01], "vaddpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0xca], "vaddpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0xca], "vaddpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0xca], "vaddpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0x0a], "vaddpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0x4a, 0x01], "vaddpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0xca], "vaddpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0xca], "vaddpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0xca], "vaddpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0x0a], "vaddpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0x4a, 0x01], "vaddpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x59, 0xca], "vmulpd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x59, 0xca], "vmulpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0xca], "vmulpd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0xca], "vmulpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0x0a], "vmulpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0x4a, 0x01], "vmulpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0xca], "vmulpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0xca], "vmulpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0xca], "vmulpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0x0a], "vmulpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0x4a, 0x01], "vmulpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0xca], "vmulpd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0xca], "vmulpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0x0a], "vmulpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0x4a, 0x01], "vmulpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0xca], "vmulpd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0xca], "vmulpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0x0a], "vmulpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0x4a, 0x01], "vmulpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0xca], "vmulpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0xca], "vmulpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0xca], "vmulpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0x0a], "vmulpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0x4a, 0x01], "vmulpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0xca], "vmulpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0xca], "vmulpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0xca], "vmulpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0x0a], "vmulpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0x4a, 0x01], "vmulpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5a, 0xca], "vcvtpd2ps ymm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0xca], "vcvtpd2ps ymm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0xca], "vcvtpd2ps xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0x0a], "vcvtpd2ps xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0xca], "vcvtpd2ps ymm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0x0a], "vcvtpd2ps ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0xca], "vcvtpd2ps ymm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0xca], "vcvtpd2ps ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0x0a], "vcvtpd2ps ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0xca], "vcvtpd2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0x0a], "vcvtpd2ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x5b, 0xca], "vcvtps2dq zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0xca], "vcvtps2dq zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0x0a], "vcvtps2dq ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0xca], "vcvtps2dq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0xca], "vcvtps2dq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x0a], "vcvtps2dq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0xca], "vcvtps2dq zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0x0a], "vcvtps2dq zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0xca], "vcvtps2dq zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0x0a], "vcvtps2dq xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0xca], "vcvtps2dq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0x0a], "vcvtps2dq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0xca], "vcvtps2dq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0x0a], "vcvtps2dq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5c, 0xca], "vsubpd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5c, 0xca], "vsubpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0xca], "vsubpd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0xca], "vsubpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0x0a], "vsubpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0x4a, 0x01], "vsubpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0xca], "vsubpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0xca], "vsubpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0xca], "vsubpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0x0a], "vsubpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0x4a, 0x01], "vsubpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0xca], "vsubpd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0xca], "vsubpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0x0a], "vsubpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0x4a, 0x01], "vsubpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0xca], "vsubpd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0xca], "vsubpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0x0a], "vsubpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0x4a, 0x01], "vsubpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0xca], "vsubpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0xca], "vsubpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0x0a], "vsubpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0x4a, 0x01], "vsubpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0xca], "vsubpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0xca], "vsubpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0xca], "vsubpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0x0a], "vsubpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0x4a, 0x01], "vsubpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5d, 0xca], "vminpd zmm1{k5}{z}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5d, 0xca], "vminpd zmm1{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5d, 0xca], "vminpd zmm1{k5}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5d, 0x0a], "vminpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5d, 0x4a, 0x01], "vminpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0xca], "vminpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0xca], "vminpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0xca], "vminpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0x0a], "vminpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0x4a, 0x01], "vminpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5d, 0x0a], "vminpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5d, 0x4a, 0x01], "vminpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5d, 0x0a], "vminpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5d, 0x4a, 0x01], "vminpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0xca], "vminpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0xca], "vminpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0xca], "vminpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0x0a], "vminpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0x4a, 0x01], "vminpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0xca], "vminpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0xca], "vminpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0xca], "vminpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0x0a], "vminpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0x4a, 0x01], "vminpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5e, 0xca], "vdivpd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5e, 0xca], "vdivpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0xca], "vdivpd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0xca], "vdivpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0x0a], "vdivpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0x4a, 0x01], "vdivpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0xca], "vdivpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0xca], "vdivpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0xca], "vdivpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0x0a], "vdivpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0x4a, 0x01], "vdivpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0xca], "vdivpd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0xca], "vdivpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0x0a], "vdivpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0x4a, 0x01], "vdivpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0xca], "vdivpd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0xca], "vdivpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0x0a], "vdivpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0x4a, 0x01], "vdivpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0xca], "vdivpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0xca], "vdivpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0x0a], "vdivpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0x4a, 0x01], "vdivpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0xca], "vdivpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0xca], "vdivpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0xca], "vdivpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0x0a], "vdivpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0x4a, 0x01], "vdivpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x5f, 0xca], "vmaxpd zmm1{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x5f, 0xca], "vmaxpd zmm1{k5}{sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x5f, 0x4a, 0x01], "vmaxpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0xca], "vmaxpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0xca], "vmaxpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0xca], "vmaxpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0x4a, 0x01], "vmaxpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x5f, 0x4a, 0x01], "vmaxpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x5f, 0x4a, 0x01], "vmaxpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0xca], "vmaxpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0xca], "vmaxpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0x4a, 0x01], "vmaxpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0xca], "vmaxpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0xca], "vmaxpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0xca], "vmaxpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0x4a, 0x01], "vmaxpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0xca], "vpunpcklbw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0x0a], "vpunpcklbw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0xca], "vpunpcklbw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0xca], "vpunpcklbw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0x0a], "vpunpcklbw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0x0a], "vpunpcklbw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0xca], "vpunpcklbw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0x0a], "vpunpcklbw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0xca], "vpunpcklbw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0xca], "vpunpcklbw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0x0a], "vpunpcklbw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0x0a], "vpunpcklbw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0xca], "vpunpcklbw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0xca], "vpunpcklbw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0xca], "vpunpcklbw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0x0a], "vpunpcklbw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0xca], "vpunpcklwd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0x0a], "vpunpcklwd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0xca], "vpunpcklwd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0xca], "vpunpcklwd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0x0a], "vpunpcklwd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0x0a], "vpunpcklwd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0xca], "vpunpcklwd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0x0a], "vpunpcklwd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0xca], "vpunpcklwd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0xca], "vpunpcklwd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0x0a], "vpunpcklwd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0x0a], "vpunpcklwd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0xca], "vpunpcklwd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0xca], "vpunpcklwd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0xca], "vpunpcklwd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0x0a], "vpunpcklwd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x62, 0x4a, 0x01], "vpunpckldq ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0xca], "vpunpckldq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0xca], "vpunpckldq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0xca], "vpunpckldq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0x4a, 0x01], "vpunpckldq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x62, 0x4a, 0x01], "vpunpckldq zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x62, 0x4a, 0x01], "vpunpckldq xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0xca], "vpunpckldq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0xca], "vpunpckldq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0xca], "vpunpckldq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0x4a, 0x01], "vpunpckldq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0xca], "vpunpckldq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0xca], "vpunpckldq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0xca], "vpunpckldq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0x4a, 0x01], "vpunpckldq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0xca], "vpacksswb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0x0a], "vpacksswb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0x4a, 0x01], "vpacksswb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0xca], "vpacksswb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0xca], "vpacksswb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0x0a], "vpacksswb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0x0a], "vpacksswb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0x4a, 0x01], "vpacksswb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0x4a, 0x01], "vpacksswb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0xca], "vpacksswb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0x0a], "vpacksswb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0x4a, 0x01], "vpacksswb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0xca], "vpacksswb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0xca], "vpacksswb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0x0a], "vpacksswb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0x0a], "vpacksswb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0x4a, 0x01], "vpacksswb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0x4a, 0x01], "vpacksswb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0xca], "vpacksswb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0x0a], "vpacksswb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0x4a, 0x01], "vpacksswb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0xca], "vpacksswb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0xca], "vpacksswb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0x0a], "vpacksswb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0x0a], "vpacksswb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0x4a, 0x01], "vpacksswb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0x4a, 0x01], "vpacksswb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0xca], "vpcmpgtb k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0xca], "vpcmpgtb k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0x0a], "vpcmpgtb k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0x0a], "vpcmpgtb k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0x4a, 0x01], "vpcmpgtb k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0xca], "vpcmpgtb k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0xca], "vpcmpgtb k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0x0a], "vpcmpgtb k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0x0a], "vpcmpgtb k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0x4a, 0x01], "vpcmpgtb k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0xca], "vpcmpgtb k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0xca], "vpcmpgtb k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0x0a], "vpcmpgtb k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0x0a], "vpcmpgtb k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0x4a, 0x01], "vpcmpgtb k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0xca], "vpcmpgtw k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0xca], "vpcmpgtw k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0x0a], "vpcmpgtw k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0x0a], "vpcmpgtw k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0x4a, 0x01], "vpcmpgtw k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0xca], "vpcmpgtw k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0xca], "vpcmpgtw k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0x0a], "vpcmpgtw k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0x0a], "vpcmpgtw k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0x4a, 0x01], "vpcmpgtw k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0xca], "vpcmpgtw k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0xca], "vpcmpgtw k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0x0a], "vpcmpgtw k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0x0a], "vpcmpgtw k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0x4a, 0x01], "vpcmpgtw k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x66, 0x0a], "vpcmpgtd k1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x66, 0x4a, 0x01], "vpcmpgtd k1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0xca], "vpcmpgtd k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0xca], "vpcmpgtd k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x0a], "vpcmpgtd k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x4a, 0x01], "vpcmpgtd k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x0a], "vpcmpgtd k1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x4a, 0x01], "vpcmpgtd k1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x66, 0x0a], "vpcmpgtd k1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x66, 0x4a, 0x01], "vpcmpgtd k1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0xca], "vpcmpgtd k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0xca], "vpcmpgtd k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0x0a], "vpcmpgtd k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0x4a, 0x01], "vpcmpgtd k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0xca], "vpcmpgtd k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0xca], "vpcmpgtd k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0x0a], "vpcmpgtd k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0x4a, 0x01], "vpcmpgtd k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0xca], "vpackuswb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0x0a], "vpackuswb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0x4a, 0x01], "vpackuswb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0xca], "vpackuswb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0xca], "vpackuswb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0x0a], "vpackuswb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0x0a], "vpackuswb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0x4a, 0x01], "vpackuswb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0x4a, 0x01], "vpackuswb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0xca], "vpackuswb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0x0a], "vpackuswb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0x4a, 0x01], "vpackuswb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0xca], "vpackuswb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0xca], "vpackuswb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0x0a], "vpackuswb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0x0a], "vpackuswb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0x4a, 0x01], "vpackuswb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0x4a, 0x01], "vpackuswb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0xca], "vpackuswb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0x0a], "vpackuswb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0x4a, 0x01], "vpackuswb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0xca], "vpackuswb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0xca], "vpackuswb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0x0a], "vpackuswb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0x0a], "vpackuswb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0x4a, 0x01], "vpackuswb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0x4a, 0x01], "vpackuswb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0xca], "vpunpckhbw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0x0a], "vpunpckhbw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0xca], "vpunpckhbw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0xca], "vpunpckhbw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0x0a], "vpunpckhbw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0x0a], "vpunpckhbw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0xca], "vpunpckhbw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0x0a], "vpunpckhbw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0xca], "vpunpckhbw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0xca], "vpunpckhbw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0x0a], "vpunpckhbw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0x0a], "vpunpckhbw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0xca], "vpunpckhbw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0xca], "vpunpckhbw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0xca], "vpunpckhbw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0x0a], "vpunpckhbw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0xca], "vpunpckhwd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0x0a], "vpunpckhwd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0xca], "vpunpckhwd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0xca], "vpunpckhwd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0x0a], "vpunpckhwd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0x0a], "vpunpckhwd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0xca], "vpunpckhwd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0x0a], "vpunpckhwd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0xca], "vpunpckhwd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0xca], "vpunpckhwd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0x0a], "vpunpckhwd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0x0a], "vpunpckhwd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0xca], "vpunpckhwd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0xca], "vpunpckhwd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0xca], "vpunpckhwd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0x0a], "vpunpckhwd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0xca], "vpunpckhdq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0xca], "vpunpckhdq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0xca], "vpunpckhdq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0xca], "vpunpckhdq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0xca], "vpunpckhdq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0xca], "vpunpckhdq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0xca], "vpunpckhdq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x6b, 0x4a, 0x01], "vpackssdw ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0xca], "vpackssdw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0xca], "vpackssdw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0xca], "vpackssdw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0x4a, 0x01], "vpackssdw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x6b, 0x4a, 0x01], "vpackssdw zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x6b, 0x4a, 0x01], "vpackssdw xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0xca], "vpackssdw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0xca], "vpackssdw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0xca], "vpackssdw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0x4a, 0x01], "vpackssdw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0xca], "vpackssdw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0xca], "vpackssdw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0xca], "vpackssdw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0x4a, 0x01], "vpackssdw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0xca], "vpunpcklqdq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0xca], "vpunpcklqdq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0xca], "vpunpcklqdq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0xca], "vpunpckhqdq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0xca], "vpunpckhqdq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0xca], "vpunpckhqdq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0xca], "vmovd xmm1, edx"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x0a], "vmovd xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x4a, 0x01], "vmovd xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0xca], "vmovdqa64 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0xca], "vmovdqa64 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0xca], "vmovdqa64 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0x0a], "vmovdqa64 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0xca], "vmovdqa32 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0xca], "vmovdqa32 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0xca], "vmovdqa32 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0x0a], "vmovdqa32 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0xca], "vmovdqa64 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0xca], "vmovdqa64 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0xca], "vmovdqa64 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0x0a], "vmovdqa64 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0xca], "vmovdqa64 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0x0a], "vmovdqa64 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0xca], "vmovdqa32 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0xca], "vmovdqa32 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0xca], "vmovdqa32 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0x0a], "vmovdqa32 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0xca], "vmovdqa32 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0x0a], "vmovdqa32 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x70, 0x0a, 0xcc], "vpshufd ymm1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0xca, 0xcc], "vpshufd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0x0a, 0xcc], "vpshufd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x70, 0x0a, 0xcc], "vpshufd zmm1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x70, 0x0a, 0xcc], "vpshufd xmm1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0xca, 0xcc], "vpshufd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0x0a, 0xcc], "vpshufd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0xca, 0xcc], "vpshufd xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0x0a, 0xcc], "vpshufd xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x72, 0x0a, 0xcc], "vprolq ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vprolq ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vprolq ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x72, 0x0a, 0xcc], "vprold ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0xca, 0xcc], "vprold ymm0{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0xca, 0xcc], "vprold ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0xca, 0xcc], "vprold ymm0{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0x0a, 0xcc], "vprold ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x72, 0x0a, 0xcc], "vprolq zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}{z}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x72, 0x0a, 0xcc], "vprolq xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vprolq zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vprolq zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vprolq xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vprolq xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x72, 0x0a, 0xcc], "vprold zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x72, 0x0a, 0xcc], "vprold xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0xca, 0xcc], "vprold zmm0{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0xca, 0xcc], "vprold zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0xca, 0xcc], "vprold zmm0{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0x0a, 0xcc], "vprold zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0xca, 0xcc], "vprold xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0x0a, 0xcc], "vprold xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0xca], "vpcmpeqb k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0xca], "vpcmpeqb k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0x0a], "vpcmpeqb k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0x0a], "vpcmpeqb k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0x4a, 0x01], "vpcmpeqb k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0xca], "vpcmpeqb k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0xca], "vpcmpeqb k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0x0a], "vpcmpeqb k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0x0a], "vpcmpeqb k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0x4a, 0x01], "vpcmpeqb k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0xca], "vpcmpeqb k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0xca], "vpcmpeqb k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0x0a], "vpcmpeqb k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0x0a], "vpcmpeqb k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0x4a, 0x01], "vpcmpeqb k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0xca], "vpcmpeqw k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0xca], "vpcmpeqw k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0x0a], "vpcmpeqw k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0x0a], "vpcmpeqw k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0x4a, 0x01], "vpcmpeqw k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0xca], "vpcmpeqw k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0xca], "vpcmpeqw k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0x0a], "vpcmpeqw k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0x0a], "vpcmpeqw k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0x4a, 0x01], "vpcmpeqw k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0xca], "vpcmpeqw k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0xca], "vpcmpeqw k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0x0a], "vpcmpeqw k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0x0a], "vpcmpeqw k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0x4a, 0x01], "vpcmpeqw k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x76, 0x0a], "vpcmpeqd k1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x76, 0x4a, 0x01], "vpcmpeqd k1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0xca], "vpcmpeqd k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0xca], "vpcmpeqd k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0x0a], "vpcmpeqd k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0x4a, 0x01], "vpcmpeqd k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x76, 0x0a], "vpcmpeqd k1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x76, 0x4a, 0x01], "vpcmpeqd k1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x76, 0x0a], "vpcmpeqd k1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x76, 0x4a, 0x01], "vpcmpeqd k1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0xca], "vpcmpeqd k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0xca], "vpcmpeqd k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0x0a], "vpcmpeqd k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0x4a, 0x01], "vpcmpeqd k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0xca], "vpcmpeqd k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0xca], "vpcmpeqd k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0x0a], "vpcmpeqd k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0x4a, 0x01], "vpcmpeqd k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x78, 0xca], "vcvttpd2uqq zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x78, 0x0a], "vcvttpd2uqq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0xca], "vcvttpd2uqq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0x0a], "vcvttpd2uqq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x78, 0xca], "vcvttps2uqq zmm1{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x78, 0x0a], "vcvttps2uqq ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0xca], "vcvttps2uqq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0xca], "vcvttps2uqq ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0xca], "vcvttps2uqq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0x0a], "vcvttps2uqq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x78, 0x0a], "vcvttpd2uqq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x78, 0x0a], "vcvttpd2uqq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0xca], "vcvttpd2uqq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0x0a], "vcvttpd2uqq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0xca], "vcvttpd2uqq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0x0a], "vcvttpd2uqq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x78, 0x0a], "vcvttps2uqq zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x78, 0x0a], "vcvttps2uqq xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0xca], "vcvttps2uqq zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0x0a], "vcvttps2uqq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0xca], "vcvttps2uqq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0x0a], "vcvttps2uqq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x79, 0xca], "vcvtpd2uqq zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0xca], "vcvtpd2uqq zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0x0a], "vcvtpd2uqq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0xca], "vcvtpd2uqq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0x0a], "vcvtpd2uqq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x79, 0xca], "vcvtps2uqq zmm1{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0xca], "vcvtps2uqq zmm1{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0x0a], "vcvtps2uqq ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0xca], "vcvtps2uqq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0xca], "vcvtps2uqq ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0xca], "vcvtps2uqq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0x0a], "vcvtps2uqq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0xca], "vcvtpd2uqq zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0x0a], "vcvtpd2uqq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0xca], "vcvtpd2uqq zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0x0a], "vcvtpd2uqq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0xca], "vcvtpd2uqq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0x0a], "vcvtpd2uqq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0xca], "vcvtpd2uqq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0x0a], "vcvtpd2uqq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0xca], "vcvtps2uqq zmm1{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0x0a], "vcvtps2uqq zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0xca], "vcvtps2uqq zmm1{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0x0a], "vcvtps2uqq xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0xca], "vcvtps2uqq zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0x0a], "vcvtps2uqq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0xca], "vcvtps2uqq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0x0a], "vcvtps2uqq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x7a, 0xca], "vcvttpd2qq zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7a, 0x0a], "vcvttpd2qq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0xca], "vcvttpd2qq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0x0a], "vcvttpd2qq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x7a, 0xca], "vcvttps2qq zmm1{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7a, 0x0a], "vcvttps2qq ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0xca], "vcvttps2qq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0xca], "vcvttps2qq ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0xca], "vcvttps2qq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0x0a], "vcvttps2qq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7a, 0x0a], "vcvttpd2qq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7a, 0x0a], "vcvttpd2qq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0xca], "vcvttpd2qq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0x0a], "vcvttpd2qq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0xca], "vcvttpd2qq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0x0a], "vcvttpd2qq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7a, 0x0a], "vcvttps2qq zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7a, 0x0a], "vcvttps2qq xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0xca], "vcvttps2qq zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0x0a], "vcvttps2qq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0xca], "vcvttps2qq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0x0a], "vcvttps2qq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0x7b, 0xca], "vcvtpd2qq zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0xca], "vcvtpd2qq zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0x0a], "vcvtpd2qq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0xca], "vcvtpd2qq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0x0a], "vcvtpd2qq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xfd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x78, 0x7b, 0xca], "vcvtps2qq zmm1{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x7d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rz-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0xca], "vcvtps2qq zmm1{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rd-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0x0a], "vcvtps2qq ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0xca], "vcvtps2qq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0xca], "vcvtps2qq ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0xca], "vcvtps2qq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0x0a], "vcvtps2qq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0xca], "vcvtpd2qq zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0x0a], "vcvtpd2qq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0xca], "vcvtpd2qq zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0x0a], "vcvtpd2qq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0xca], "vcvtpd2qq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0x0a], "vcvtpd2qq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0xca], "vcvtpd2qq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0x0a], "vcvtpd2qq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0xca], "vcvtps2qq zmm1{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{ru-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0x0a], "vcvtps2qq zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0xca], "vcvtps2qq zmm1{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rne-sae}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0x0a], "vcvtps2qq xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0xca], "vcvtps2qq zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0x0a], "vcvtps2qq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0xca], "vcvtps2qq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0x0a], "vcvtps2qq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0xca], "vmovd edx, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x0a], "vmovd dword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x4a, 0x01], "vmovd dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0x7f, 0xca], "vmovdqa64 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0xca], "vmovdqa64 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0xca], "vmovdqa64 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0x0a], "vmovdqa64 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0x0a], "vmovdqa64 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0x4a, 0x01], "vmovdqa64 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqa64 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0x7f, 0xca], "vmovdqa32 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0xca], "vmovdqa32 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0xca], "vmovdqa32 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0x0a], "vmovdqa32 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0x0a], "vmovdqa32 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0x4a, 0x01], "vmovdqa32 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqa32 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0x7f, 0xca], "vmovdqa64 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0xca], "vmovdqa64 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0xca], "vmovdqa64 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0x0a], "vmovdqa64 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0x0a], "vmovdqa64 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0x4a, 0x01], "vmovdqa64 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqa64 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0xca], "vmovdqa64 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0x0a], "vmovdqa64 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0x0a], "vmovdqa64 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0x4a, 0x01], "vmovdqa64 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqa64 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0x7f, 0xca], "vmovdqa32 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0xca], "vmovdqa32 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0xca], "vmovdqa32 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0x0a], "vmovdqa32 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0x0a], "vmovdqa32 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0x4a, 0x01], "vmovdqa32 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqa32 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0xca], "vmovdqa32 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x0a], "vmovdqa32 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0x0a], "vmovdqa32 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x4a, 0x01], "vmovdqa32 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqa32 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xc2, 0xca, 0xcc], "vcmppd k1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0xca, 0xcc], "vcmppd k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0xca, 0xcc], "vcmppd k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0xca, 0xcc], "vcmppd k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0xca, 0xcc], "vpinsrw xmm1, xmm0, edx, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0x0a, 0xcc], "vpinsrw xmm1, xmm0, word [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0x4a, 0x01, 0xcc], "vpinsrw xmm1, xmm0, word [edx + 0x2], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc5, 0xca, 0xcc], "vpextrw ecx, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0xca, 0xcc], "vshufpd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0xca, 0xcc], "vshufpd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0xca, 0xcc], "vshufpd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0xca], "vpsrlw ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0x0a], "vpsrlw ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0x4a, 0x01], "vpsrlw ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0xca], "vpsrlw ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0xca], "vpsrlw ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0x0a], "vpsrlw ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0x0a], "vpsrlw ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0x4a, 0x01], "vpsrlw ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0x4a, 0x01], "vpsrlw ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0xca], "vpsrlw zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0x0a], "vpsrlw zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0x4a, 0x01], "vpsrlw zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0xca], "vpsrlw zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0xca], "vpsrlw zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0x0a], "vpsrlw zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0x0a], "vpsrlw zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0x4a, 0x01], "vpsrlw zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0x4a, 0x01], "vpsrlw zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0xca], "vpsrlw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0x0a], "vpsrlw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0x4a, 0x01], "vpsrlw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0xca], "vpsrlw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0xca], "vpsrlw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0x0a], "vpsrlw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0x0a], "vpsrlw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0x4a, 0x01], "vpsrlw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0x4a, 0x01], "vpsrlw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0xca], "vpsrld ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0x0a], "vpsrld ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0x4a, 0x01], "vpsrld ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0xca], "vpsrld ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0xca], "vpsrld ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0x0a], "vpsrld ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0x0a], "vpsrld ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0x4a, 0x01], "vpsrld ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0x4a, 0x01], "vpsrld ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0xca], "vpsrld zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0x0a], "vpsrld zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0x4a, 0x01], "vpsrld zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0xca], "vpsrld zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0xca], "vpsrld zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0x0a], "vpsrld zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0x0a], "vpsrld zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0x4a, 0x01], "vpsrld zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0x4a, 0x01], "vpsrld zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0xca], "vpsrld xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0x0a], "vpsrld xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0x4a, 0x01], "vpsrld xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0xca], "vpsrld xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0xca], "vpsrld xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0x0a], "vpsrld xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0x0a], "vpsrld xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0x4a, 0x01], "vpsrld xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0x4a, 0x01], "vpsrld xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0xca], "vpsrlq ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0x0a], "vpsrlq ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0x4a, 0x01], "vpsrlq ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0xca], "vpsrlq ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0xca], "vpsrlq ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0x0a], "vpsrlq ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0x0a], "vpsrlq ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0x4a, 0x01], "vpsrlq ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0x4a, 0x01], "vpsrlq ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0xca], "vpsrlq zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0x0a], "vpsrlq zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0x4a, 0x01], "vpsrlq zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0xca], "vpsrlq zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0xca], "vpsrlq zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0x0a], "vpsrlq zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0x0a], "vpsrlq zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0x4a, 0x01], "vpsrlq zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0x4a, 0x01], "vpsrlq zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0xca], "vpsrlq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0x0a], "vpsrlq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0x4a, 0x01], "vpsrlq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0xca], "vpsrlq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0xca], "vpsrlq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0x0a], "vpsrlq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0x0a], "vpsrlq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0x4a, 0x01], "vpsrlq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0x4a, 0x01], "vpsrlq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xd4, 0x0a], "vpaddq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xd4, 0x4a, 0x01], "vpaddq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0xca], "vpaddq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0xca], "vpaddq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0xca], "vpaddq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0x0a], "vpaddq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0x4a, 0x01], "vpaddq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xd4, 0x0a], "vpaddq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xd4, 0x4a, 0x01], "vpaddq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xd4, 0x0a], "vpaddq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xd4, 0x4a, 0x01], "vpaddq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0xca], "vpaddq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0xca], "vpaddq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0xca], "vpaddq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0x0a], "vpaddq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0x4a, 0x01], "vpaddq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0xca], "vpaddq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0xca], "vpaddq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0xca], "vpaddq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0x0a], "vpaddq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0x4a, 0x01], "vpaddq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0xca], "vpmullw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0x0a], "vpmullw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0x4a, 0x01], "vpmullw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0xca], "vpmullw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0xca], "vpmullw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0x0a], "vpmullw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0x0a], "vpmullw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0x4a, 0x01], "vpmullw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0x4a, 0x01], "vpmullw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0xca], "vpmullw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0x0a], "vpmullw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0x4a, 0x01], "vpmullw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0xca], "vpmullw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0xca], "vpmullw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0x0a], "vpmullw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0x0a], "vpmullw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0x4a, 0x01], "vpmullw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0x4a, 0x01], "vpmullw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0xca], "vpmullw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0x0a], "vpmullw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0x4a, 0x01], "vpmullw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0xca], "vpmullw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0xca], "vpmullw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0x0a], "vpmullw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0x0a], "vpmullw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0x4a, 0x01], "vpmullw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0x4a, 0x01], "vpmullw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0xca], "vmovq xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0x0a], "vmovq qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0x4a, 0x01], "vmovq qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0xca], "vpsubusb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0x0a], "vpsubusb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0x4a, 0x01], "vpsubusb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0xca], "vpsubusb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0xca], "vpsubusb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0x0a], "vpsubusb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0x0a], "vpsubusb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0x4a, 0x01], "vpsubusb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0x4a, 0x01], "vpsubusb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0xca], "vpsubusb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0x0a], "vpsubusb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0x4a, 0x01], "vpsubusb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0xca], "vpsubusb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0xca], "vpsubusb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0x0a], "vpsubusb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0x0a], "vpsubusb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0x4a, 0x01], "vpsubusb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0x4a, 0x01], "vpsubusb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0xca], "vpsubusb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0x0a], "vpsubusb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0x4a, 0x01], "vpsubusb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0xca], "vpsubusb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0xca], "vpsubusb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0x0a], "vpsubusb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0x0a], "vpsubusb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0x4a, 0x01], "vpsubusb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0x4a, 0x01], "vpsubusb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0xca], "vpsubusw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0x0a], "vpsubusw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0x4a, 0x01], "vpsubusw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0xca], "vpsubusw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0xca], "vpsubusw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0x0a], "vpsubusw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0x0a], "vpsubusw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0x4a, 0x01], "vpsubusw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0x4a, 0x01], "vpsubusw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0xca], "vpsubusw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0x0a], "vpsubusw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0x4a, 0x01], "vpsubusw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0xca], "vpsubusw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0xca], "vpsubusw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0x0a], "vpsubusw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0x0a], "vpsubusw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0x4a, 0x01], "vpsubusw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0x4a, 0x01], "vpsubusw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0xca], "vpsubusw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0x0a], "vpsubusw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0x4a, 0x01], "vpsubusw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0xca], "vpsubusw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0xca], "vpsubusw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0x0a], "vpsubusw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0x0a], "vpsubusw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0x4a, 0x01], "vpsubusw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0x4a, 0x01], "vpsubusw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0xca], "vpminub ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0x0a], "vpminub ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0x4a, 0x01], "vpminub ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0xca], "vpminub ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0xca], "vpminub ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0x0a], "vpminub ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0x0a], "vpminub ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0x4a, 0x01], "vpminub ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0x4a, 0x01], "vpminub ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0xca], "vpminub zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0x0a], "vpminub zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0x4a, 0x01], "vpminub zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0xca], "vpminub zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0xca], "vpminub zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0x0a], "vpminub zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0x0a], "vpminub zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0x4a, 0x01], "vpminub zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0x4a, 0x01], "vpminub zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0xca], "vpminub xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0x0a], "vpminub xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0x4a, 0x01], "vpminub xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0xca], "vpminub xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0xca], "vpminub xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0x0a], "vpminub xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0x0a], "vpminub xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0x4a, 0x01], "vpminub xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0x4a, 0x01], "vpminub xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdb, 0x0a], "vpandq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdb, 0x4a, 0x01], "vpandq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0xca], "vpandq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0xca], "vpandq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0xca], "vpandq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0x0a], "vpandq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0x4a, 0x01], "vpandq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdb, 0x0a], "vpandd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdb, 0x4a, 0x01], "vpandd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0xca], "vpandd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0xca], "vpandd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0xca], "vpandd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0x0a], "vpandd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0x4a, 0x01], "vpandd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdb, 0x0a], "vpandq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdb, 0x4a, 0x01], "vpandq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdb, 0x0a], "vpandq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdb, 0x4a, 0x01], "vpandq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0xca], "vpandq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0xca], "vpandq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0xca], "vpandq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0x0a], "vpandq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0x4a, 0x01], "vpandq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0xca], "vpandq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0xca], "vpandq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0xca], "vpandq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0x0a], "vpandq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0x4a, 0x01], "vpandq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdb, 0x0a], "vpandd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdb, 0x4a, 0x01], "vpandd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdb, 0x0a], "vpandd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdb, 0x4a, 0x01], "vpandd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0xca], "vpandd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0xca], "vpandd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0xca], "vpandd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0x0a], "vpandd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0x4a, 0x01], "vpandd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0xca], "vpandd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0xca], "vpandd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0xca], "vpandd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0x0a], "vpandd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0x4a, 0x01], "vpandd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0xca], "vpaddusb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0x0a], "vpaddusb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0x4a, 0x01], "vpaddusb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0xca], "vpaddusb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0xca], "vpaddusb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0x0a], "vpaddusb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0x0a], "vpaddusb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0x4a, 0x01], "vpaddusb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0x4a, 0x01], "vpaddusb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0xca], "vpaddusb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0x0a], "vpaddusb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0x4a, 0x01], "vpaddusb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0xca], "vpaddusb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0xca], "vpaddusb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0x0a], "vpaddusb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0x0a], "vpaddusb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0x4a, 0x01], "vpaddusb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0x4a, 0x01], "vpaddusb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0xca], "vpaddusb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0x0a], "vpaddusb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0x4a, 0x01], "vpaddusb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0xca], "vpaddusb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0xca], "vpaddusb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0x0a], "vpaddusb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0x0a], "vpaddusb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0x4a, 0x01], "vpaddusb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0x4a, 0x01], "vpaddusb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0xca], "vpaddusw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0x0a], "vpaddusw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0x4a, 0x01], "vpaddusw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0xca], "vpaddusw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0xca], "vpaddusw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0x0a], "vpaddusw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0x0a], "vpaddusw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0x4a, 0x01], "vpaddusw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0x4a, 0x01], "vpaddusw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0xca], "vpaddusw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0x0a], "vpaddusw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0x4a, 0x01], "vpaddusw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0xca], "vpaddusw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0xca], "vpaddusw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0x0a], "vpaddusw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0x0a], "vpaddusw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0x4a, 0x01], "vpaddusw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0x4a, 0x01], "vpaddusw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0xca], "vpaddusw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0x0a], "vpaddusw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0x4a, 0x01], "vpaddusw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0xca], "vpaddusw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0xca], "vpaddusw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0x0a], "vpaddusw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0x0a], "vpaddusw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0x4a, 0x01], "vpaddusw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0x4a, 0x01], "vpaddusw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0xca], "vpmaxub ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0x0a], "vpmaxub ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0x4a, 0x01], "vpmaxub ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0xca], "vpmaxub ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0xca], "vpmaxub ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0x0a], "vpmaxub ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0x0a], "vpmaxub ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0x4a, 0x01], "vpmaxub ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0x4a, 0x01], "vpmaxub ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0xca], "vpmaxub zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0x0a], "vpmaxub zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0x4a, 0x01], "vpmaxub zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0xca], "vpmaxub zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0xca], "vpmaxub zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0x0a], "vpmaxub zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0x0a], "vpmaxub zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0x4a, 0x01], "vpmaxub zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0x4a, 0x01], "vpmaxub zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0xca], "vpmaxub xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0x0a], "vpmaxub xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0x4a, 0x01], "vpmaxub xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0xca], "vpmaxub xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0xca], "vpmaxub xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0x0a], "vpmaxub xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0x0a], "vpmaxub xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0x4a, 0x01], "vpmaxub xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0x4a, 0x01], "vpmaxub xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdf, 0x0a], "vpandnq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xdf, 0x4a, 0x01], "vpandnq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0xca], "vpandnq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0xca], "vpandnq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0xca], "vpandnq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0x0a], "vpandnq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0x4a, 0x01], "vpandnq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdf, 0x0a], "vpandnd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xdf, 0x4a, 0x01], "vpandnd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0xca], "vpandnd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0xca], "vpandnd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0xca], "vpandnd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0x0a], "vpandnd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0x4a, 0x01], "vpandnd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdf, 0x0a], "vpandnq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xdf, 0x4a, 0x01], "vpandnq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdf, 0x0a], "vpandnq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xdf, 0x4a, 0x01], "vpandnq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0xca], "vpandnq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0xca], "vpandnq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0xca], "vpandnq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0x0a], "vpandnq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0x4a, 0x01], "vpandnq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0xca], "vpandnq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0xca], "vpandnq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0xca], "vpandnq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0x0a], "vpandnq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0x4a, 0x01], "vpandnq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdf, 0x0a], "vpandnd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xdf, 0x4a, 0x01], "vpandnd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdf, 0x0a], "vpandnd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xdf, 0x4a, 0x01], "vpandnd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0xca], "vpandnd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0xca], "vpandnd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0xca], "vpandnd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0x0a], "vpandnd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0x4a, 0x01], "vpandnd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0xca], "vpandnd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0xca], "vpandnd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0xca], "vpandnd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0x0a], "vpandnd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0x4a, 0x01], "vpandnd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0xca], "vpavgb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0x0a], "vpavgb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0x4a, 0x01], "vpavgb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0xca], "vpavgb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0xca], "vpavgb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0x0a], "vpavgb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0x0a], "vpavgb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0x4a, 0x01], "vpavgb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0x4a, 0x01], "vpavgb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0xca], "vpavgb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0x0a], "vpavgb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0x4a, 0x01], "vpavgb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0xca], "vpavgb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0xca], "vpavgb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0x0a], "vpavgb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0x0a], "vpavgb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0x4a, 0x01], "vpavgb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0x4a, 0x01], "vpavgb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0xca], "vpavgb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0x0a], "vpavgb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0x4a, 0x01], "vpavgb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0xca], "vpavgb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0xca], "vpavgb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0x0a], "vpavgb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0x0a], "vpavgb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0x4a, 0x01], "vpavgb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0x4a, 0x01], "vpavgb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0xca], "vpsraw ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0x0a], "vpsraw ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0x4a, 0x01], "vpsraw ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0xca], "vpsraw ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0xca], "vpsraw ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0x0a], "vpsraw ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0x0a], "vpsraw ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0x4a, 0x01], "vpsraw ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0x4a, 0x01], "vpsraw ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0xca], "vpsraw zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0x0a], "vpsraw zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0x4a, 0x01], "vpsraw zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0xca], "vpsraw zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0xca], "vpsraw zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0x0a], "vpsraw zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0x0a], "vpsraw zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0x4a, 0x01], "vpsraw zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0x4a, 0x01], "vpsraw zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0xca], "vpsraw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0x0a], "vpsraw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0x4a, 0x01], "vpsraw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0xca], "vpsraw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0xca], "vpsraw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0x0a], "vpsraw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0x0a], "vpsraw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0x4a, 0x01], "vpsraw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0x4a, 0x01], "vpsraw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0xca], "vpsraq ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0x0a], "vpsraq ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0x4a, 0x01], "vpsraq ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0xca], "vpsraq ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0xca], "vpsraq ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0x0a], "vpsraq ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0x0a], "vpsraq ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0x4a, 0x01], "vpsraq ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0x4a, 0x01], "vpsraq ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0xca], "vpsrad ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0x0a], "vpsrad ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0x4a, 0x01], "vpsrad ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0xca], "vpsrad ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0xca], "vpsrad ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0x0a], "vpsrad ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0x0a], "vpsrad ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0x4a, 0x01], "vpsrad ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0x4a, 0x01], "vpsrad ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0xca], "vpsraq zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0x0a], "vpsraq zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0x4a, 0x01], "vpsraq zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0xca], "vpsraq zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0xca], "vpsraq zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0x0a], "vpsraq zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0x0a], "vpsraq zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0x4a, 0x01], "vpsraq zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0x4a, 0x01], "vpsraq zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0xca], "vpsraq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0x0a], "vpsraq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0x4a, 0x01], "vpsraq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0xca], "vpsraq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0xca], "vpsraq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0x0a], "vpsraq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0x0a], "vpsraq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0x4a, 0x01], "vpsraq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0x4a, 0x01], "vpsraq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0xca], "vpsrad zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0x0a], "vpsrad zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0x4a, 0x01], "vpsrad zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0xca], "vpsrad zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0xca], "vpsrad zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0x0a], "vpsrad zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0x0a], "vpsrad zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0x4a, 0x01], "vpsrad zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0x4a, 0x01], "vpsrad zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0xca], "vpsrad xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0x0a], "vpsrad xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0x4a, 0x01], "vpsrad xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0xca], "vpsrad xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0xca], "vpsrad xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0x0a], "vpsrad xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0x0a], "vpsrad xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0x4a, 0x01], "vpsrad xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0x4a, 0x01], "vpsrad xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0xca], "vpavgw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0x0a], "vpavgw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0x4a, 0x01], "vpavgw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0xca], "vpavgw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0xca], "vpavgw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0x0a], "vpavgw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0x0a], "vpavgw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0x4a, 0x01], "vpavgw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0x4a, 0x01], "vpavgw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0xca], "vpavgw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0x0a], "vpavgw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0x4a, 0x01], "vpavgw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0xca], "vpavgw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0xca], "vpavgw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0x0a], "vpavgw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0x0a], "vpavgw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0x4a, 0x01], "vpavgw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0x4a, 0x01], "vpavgw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0xca], "vpavgw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0x0a], "vpavgw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0x4a, 0x01], "vpavgw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0xca], "vpavgw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0xca], "vpavgw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0x0a], "vpavgw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0x0a], "vpavgw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0x4a, 0x01], "vpavgw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0x4a, 0x01], "vpavgw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0xca], "vpmulhuw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0x0a], "vpmulhuw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0xca], "vpmulhuw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0xca], "vpmulhuw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0x0a], "vpmulhuw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0x0a], "vpmulhuw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0xca], "vpmulhuw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0x0a], "vpmulhuw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0xca], "vpmulhuw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0xca], "vpmulhuw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0x0a], "vpmulhuw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0x0a], "vpmulhuw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0xca], "vpmulhuw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0xca], "vpmulhuw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0xca], "vpmulhuw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0x0a], "vpmulhuw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0xca], "vpmulhw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0x0a], "vpmulhw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0x4a, 0x01], "vpmulhw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0xca], "vpmulhw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0xca], "vpmulhw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0x0a], "vpmulhw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0x0a], "vpmulhw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0x4a, 0x01], "vpmulhw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0x4a, 0x01], "vpmulhw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0xca], "vpmulhw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0x0a], "vpmulhw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0x4a, 0x01], "vpmulhw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0xca], "vpmulhw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0xca], "vpmulhw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0x0a], "vpmulhw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0x0a], "vpmulhw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0x4a, 0x01], "vpmulhw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0x4a, 0x01], "vpmulhw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0xca], "vpmulhw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0x0a], "vpmulhw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0x4a, 0x01], "vpmulhw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0xca], "vpmulhw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0xca], "vpmulhw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0x0a], "vpmulhw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x0a], "vpmulhw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0x4a, 0x01], "vpmulhw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x4a, 0x01], "vpmulhw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xfd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x78, 0xe6, 0xca], "vcvttpd2dq ymm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x7d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0xca], "vcvttpd2dq xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0x0a], "vcvttpd2dq xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xe6, 0x0a], "vcvttpd2dq ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0xca], "vcvttpd2dq ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0x0a], "vcvttpd2dq ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0xca], "vcvttpd2dq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0x0a], "vcvttpd2dq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x0a], "vmovntdq ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x4a, 0x01], "vmovntdq ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x0a], "vmovntdq zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x4a, 0x01], "vmovntdq zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x0a], "vmovntdq xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x4a, 0x01], "vmovntdq xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0xca], "vpsubsb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x0a], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x4a, 0x01], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0xca], "vpsubsb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0x0a], "vpsubsb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0x0a], "vpsubsb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0x4a, 0x01], "vpsubsb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0x4a, 0x01], "vpsubsb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0xca], "vpsubsb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0x0a], "vpsubsb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0x4a, 0x01], "vpsubsb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0xca], "vpsubsb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0xca], "vpsubsb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0x0a], "vpsubsb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0x0a], "vpsubsb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0x4a, 0x01], "vpsubsb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0x4a, 0x01], "vpsubsb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0xca], "vpsubsb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0x0a], "vpsubsb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0x4a, 0x01], "vpsubsb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0xca], "vpsubsb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0xca], "vpsubsb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0x0a], "vpsubsb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0x0a], "vpsubsb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0x4a, 0x01], "vpsubsb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0x4a, 0x01], "vpsubsb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0xca], "vpsubsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0x0a], "vpsubsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0x4a, 0x01], "vpsubsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0xca], "vpsubsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0xca], "vpsubsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0x0a], "vpsubsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0x0a], "vpsubsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0x4a, 0x01], "vpsubsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0x4a, 0x01], "vpsubsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0xca], "vpsubsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0x0a], "vpsubsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0x4a, 0x01], "vpsubsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0xca], "vpsubsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0xca], "vpsubsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0x0a], "vpsubsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0x0a], "vpsubsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0x4a, 0x01], "vpsubsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0x4a, 0x01], "vpsubsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0xca], "vpsubsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0x0a], "vpsubsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0x4a, 0x01], "vpsubsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0xca], "vpsubsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0xca], "vpsubsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0x0a], "vpsubsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0x0a], "vpsubsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0x4a, 0x01], "vpsubsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0x4a, 0x01], "vpsubsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0xca], "vpminsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0x0a], "vpminsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0x4a, 0x01], "vpminsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0xca], "vpminsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0xca], "vpminsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0x0a], "vpminsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0x0a], "vpminsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0x4a, 0x01], "vpminsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0x4a, 0x01], "vpminsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0xca], "vpminsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0x0a], "vpminsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0x4a, 0x01], "vpminsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0xca], "vpminsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0xca], "vpminsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0x0a], "vpminsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0x0a], "vpminsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0x4a, 0x01], "vpminsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0x4a, 0x01], "vpminsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0xca], "vpminsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0x0a], "vpminsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0x4a, 0x01], "vpminsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0xca], "vpminsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0xca], "vpminsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0x0a], "vpminsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0x0a], "vpminsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0x4a, 0x01], "vpminsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0x4a, 0x01], "vpminsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xeb, 0x0a], "vporq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xeb, 0x4a, 0x01], "vporq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0xca], "vporq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0xca], "vporq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0xca], "vporq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0x0a], "vporq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0x4a, 0x01], "vporq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xeb, 0x0a], "vpord ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xeb, 0x4a, 0x01], "vpord ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0xca], "vpord ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0xca], "vpord ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0xca], "vpord ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0x0a], "vpord ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0x4a, 0x01], "vpord ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xeb, 0x0a], "vporq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xeb, 0x4a, 0x01], "vporq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xeb, 0x0a], "vporq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xeb, 0x4a, 0x01], "vporq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0xca], "vporq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0xca], "vporq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0xca], "vporq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0x0a], "vporq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0x4a, 0x01], "vporq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0xca], "vporq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0xca], "vporq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0xca], "vporq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0x0a], "vporq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0x4a, 0x01], "vporq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xeb, 0x0a], "vpord zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xeb, 0x4a, 0x01], "vpord zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xeb, 0x0a], "vpord xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xeb, 0x4a, 0x01], "vpord xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0xca], "vpord zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0xca], "vpord zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0xca], "vpord zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0x0a], "vpord zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0x4a, 0x01], "vpord zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0xca], "vpord xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0xca], "vpord xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0xca], "vpord xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0x0a], "vpord xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0x4a, 0x01], "vpord xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0xca], "vpaddsb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0x0a], "vpaddsb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0x4a, 0x01], "vpaddsb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0xca], "vpaddsb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0xca], "vpaddsb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0x0a], "vpaddsb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0x0a], "vpaddsb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0x4a, 0x01], "vpaddsb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0x4a, 0x01], "vpaddsb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0xca], "vpaddsb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0x0a], "vpaddsb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0x4a, 0x01], "vpaddsb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0xca], "vpaddsb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0xca], "vpaddsb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0x0a], "vpaddsb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0x0a], "vpaddsb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0x4a, 0x01], "vpaddsb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0x4a, 0x01], "vpaddsb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0xca], "vpaddsb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0x0a], "vpaddsb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0x4a, 0x01], "vpaddsb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0xca], "vpaddsb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0xca], "vpaddsb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0x0a], "vpaddsb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0x0a], "vpaddsb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0x4a, 0x01], "vpaddsb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0x4a, 0x01], "vpaddsb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0xca], "vpaddsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0x0a], "vpaddsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0x4a, 0x01], "vpaddsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0xca], "vpaddsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0xca], "vpaddsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0x0a], "vpaddsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0x0a], "vpaddsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0x4a, 0x01], "vpaddsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0x4a, 0x01], "vpaddsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0xca], "vpaddsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0x0a], "vpaddsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0x4a, 0x01], "vpaddsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0xca], "vpaddsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0xca], "vpaddsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0x0a], "vpaddsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0x0a], "vpaddsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0x4a, 0x01], "vpaddsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0x4a, 0x01], "vpaddsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0xca], "vpaddsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0x0a], "vpaddsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0x4a, 0x01], "vpaddsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0xca], "vpaddsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0xca], "vpaddsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0x0a], "vpaddsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0x0a], "vpaddsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0x4a, 0x01], "vpaddsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0x4a, 0x01], "vpaddsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0xca], "vpmaxsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0x0a], "vpmaxsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0x4a, 0x01], "vpmaxsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0xca], "vpmaxsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0xca], "vpmaxsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0x0a], "vpmaxsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0x0a], "vpmaxsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0x4a, 0x01], "vpmaxsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0x4a, 0x01], "vpmaxsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0xca], "vpmaxsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0x0a], "vpmaxsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0x4a, 0x01], "vpmaxsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0xca], "vpmaxsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0xca], "vpmaxsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0x0a], "vpmaxsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0x0a], "vpmaxsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0x4a, 0x01], "vpmaxsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0x4a, 0x01], "vpmaxsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0xca], "vpmaxsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0x0a], "vpmaxsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0x4a, 0x01], "vpmaxsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0xca], "vpmaxsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0xca], "vpmaxsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0x0a], "vpmaxsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0x0a], "vpmaxsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0x4a, 0x01], "vpmaxsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0x4a, 0x01], "vpmaxsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xef, 0x0a], "vpxorq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xef, 0x4a, 0x01], "vpxorq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0xca], "vpxorq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0xca], "vpxorq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0xca], "vpxorq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0x0a], "vpxorq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0x4a, 0x01], "vpxorq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xef, 0x0a], "vpxord ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xef, 0x4a, 0x01], "vpxord ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0xca], "vpxord ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0xca], "vpxord ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0xca], "vpxord ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0x0a], "vpxord ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0x4a, 0x01], "vpxord ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xef, 0x0a], "vpxorq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xef, 0x4a, 0x01], "vpxorq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xef, 0x0a], "vpxorq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xef, 0x4a, 0x01], "vpxorq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0xca], "vpxorq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0xca], "vpxorq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0xca], "vpxorq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0x0a], "vpxorq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0x4a, 0x01], "vpxorq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0xca], "vpxorq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0xca], "vpxorq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0xca], "vpxorq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0x0a], "vpxorq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0x4a, 0x01], "vpxorq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xef, 0x0a], "vpxord zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xef, 0x4a, 0x01], "vpxord zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xef, 0x0a], "vpxord xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xef, 0x4a, 0x01], "vpxord xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0xca], "vpxord zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0xca], "vpxord zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0xca], "vpxord zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0x0a], "vpxord zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0x4a, 0x01], "vpxord zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0xca], "vpxord xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0xca], "vpxord xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0xca], "vpxord xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0x0a], "vpxord xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0x4a, 0x01], "vpxord xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0xca], "vpsllw ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0x0a], "vpsllw ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0x4a, 0x01], "vpsllw ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0xca], "vpsllw ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0xca], "vpsllw ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0x0a], "vpsllw ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0x0a], "vpsllw ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0x4a, 0x01], "vpsllw ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0x4a, 0x01], "vpsllw ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0xca], "vpsllw zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0x0a], "vpsllw zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0x4a, 0x01], "vpsllw zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0xca], "vpsllw zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0xca], "vpsllw zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0x0a], "vpsllw zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0x0a], "vpsllw zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0x4a, 0x01], "vpsllw zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0x4a, 0x01], "vpsllw zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0xca], "vpsllw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0x0a], "vpsllw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0x4a, 0x01], "vpsllw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0xca], "vpsllw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0xca], "vpsllw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0x0a], "vpsllw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0x0a], "vpsllw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0x4a, 0x01], "vpsllw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0x4a, 0x01], "vpsllw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0xca], "vpslld ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0x0a], "vpslld ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0x4a, 0x01], "vpslld ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0xca], "vpslld ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0xca], "vpslld ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0x0a], "vpslld ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0x0a], "vpslld ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0x4a, 0x01], "vpslld ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0x4a, 0x01], "vpslld ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0xca], "vpslld zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0x0a], "vpslld zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0x4a, 0x01], "vpslld zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0xca], "vpslld zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0xca], "vpslld zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0x0a], "vpslld zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0x0a], "vpslld zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0x4a, 0x01], "vpslld zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0x4a, 0x01], "vpslld zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0xca], "vpslld xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0x0a], "vpslld xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0x4a, 0x01], "vpslld xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0xca], "vpslld xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0xca], "vpslld xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0x0a], "vpslld xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0x0a], "vpslld xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0x4a, 0x01], "vpslld xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0x4a, 0x01], "vpslld xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0xca], "vpsllq ymm1{k5}{z}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0x0a], "vpsllq ymm1{k5}{z}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0x4a, 0x01], "vpsllq ymm1{k5}{z}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0xca], "vpsllq ymm1, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0xca], "vpsllq ymm1{k5}, ymm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0x0a], "vpsllq ymm1, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0x0a], "vpsllq ymm1{k5}, ymm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0x4a, 0x01], "vpsllq ymm1, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0x4a, 0x01], "vpsllq ymm1{k5}, ymm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0xca], "vpsllq zmm1{k5}{z}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0x0a], "vpsllq zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0x4a, 0x01], "vpsllq zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0xca], "vpsllq zmm1, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0xca], "vpsllq zmm1{k5}, zmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0x0a], "vpsllq zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0x0a], "vpsllq zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0x4a, 0x01], "vpsllq zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0x4a, 0x01], "vpsllq zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0xca], "vpsllq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0x0a], "vpsllq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0x4a, 0x01], "vpsllq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0xca], "vpsllq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0xca], "vpsllq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0x0a], "vpsllq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0x0a], "vpsllq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0x4a, 0x01], "vpsllq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0x4a, 0x01], "vpsllq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xf4, 0x4a, 0x01], "vpmuludq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0xca], "vpmuludq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0xca], "vpmuludq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0xca], "vpmuludq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0x4a, 0x01], "vpmuludq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xf4, 0x4a, 0x01], "vpmuludq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xf4, 0x4a, 0x01], "vpmuludq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0xca], "vpmuludq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0xca], "vpmuludq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0xca], "vpmuludq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0x4a, 0x01], "vpmuludq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0xca], "vpmuludq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0xca], "vpmuludq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0xca], "vpmuludq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0x4a, 0x01], "vpmuludq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0xca], "vpmaddwd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0x0a], "vpmaddwd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0xca], "vpmaddwd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0xca], "vpmaddwd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0x0a], "vpmaddwd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0x0a], "vpmaddwd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0xca], "vpmaddwd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0x0a], "vpmaddwd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0xca], "vpmaddwd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0xca], "vpmaddwd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0x0a], "vpmaddwd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0x0a], "vpmaddwd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0xca], "vpmaddwd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0xca], "vpmaddwd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0xca], "vpmaddwd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0x0a], "vpmaddwd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x0a], "vpsadbw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x4a, 0x01], "vpsadbw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0xca], "vpsadbw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x0a], "vpsadbw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x4a, 0x01], "vpsadbw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0x0a], "vpsadbw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0x4a, 0x01], "vpsadbw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0xca], "vpsubb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0x0a], "vpsubb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0x4a, 0x01], "vpsubb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0xca], "vpsubb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0xca], "vpsubb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0x0a], "vpsubb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0x0a], "vpsubb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0x4a, 0x01], "vpsubb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0x4a, 0x01], "vpsubb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0xca], "vpsubb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0x0a], "vpsubb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0x4a, 0x01], "vpsubb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0xca], "vpsubb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0xca], "vpsubb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0x0a], "vpsubb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0x0a], "vpsubb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0x4a, 0x01], "vpsubb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0x4a, 0x01], "vpsubb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0xca], "vpsubb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0x0a], "vpsubb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0x4a, 0x01], "vpsubb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0xca], "vpsubb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0xca], "vpsubb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0x0a], "vpsubb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0x0a], "vpsubb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0x4a, 0x01], "vpsubb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0x4a, 0x01], "vpsubb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0xca], "vpsubw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0x0a], "vpsubw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0x4a, 0x01], "vpsubw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0xca], "vpsubw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0xca], "vpsubw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0x0a], "vpsubw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0x0a], "vpsubw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0x4a, 0x01], "vpsubw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0x4a, 0x01], "vpsubw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0xca], "vpsubw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0x0a], "vpsubw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0x4a, 0x01], "vpsubw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0xca], "vpsubw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0xca], "vpsubw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0x0a], "vpsubw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0x0a], "vpsubw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0x4a, 0x01], "vpsubw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0x4a, 0x01], "vpsubw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0xca], "vpsubw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0x0a], "vpsubw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0x4a, 0x01], "vpsubw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0xca], "vpsubw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0xca], "vpsubw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0x0a], "vpsubw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0x0a], "vpsubw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0x4a, 0x01], "vpsubw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0x4a, 0x01], "vpsubw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfa, 0x0a], "vpsubd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfa, 0x4a, 0x01], "vpsubd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0xca], "vpsubd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0xca], "vpsubd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0xca], "vpsubd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0x0a], "vpsubd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0x4a, 0x01], "vpsubd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfa, 0x0a], "vpsubd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfa, 0x4a, 0x01], "vpsubd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfa, 0x0a], "vpsubd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfa, 0x4a, 0x01], "vpsubd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0xca], "vpsubd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0xca], "vpsubd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0xca], "vpsubd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0x0a], "vpsubd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0x4a, 0x01], "vpsubd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0xca], "vpsubd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0xca], "vpsubd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0xca], "vpsubd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0x0a], "vpsubd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0x4a, 0x01], "vpsubd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xbd, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xfb, 0x0a], "vpsubq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x38, 0xfb, 0x4a, 0x01], "vpsubq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x3d, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0xca], "vpsubq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0xca], "vpsubq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0xca], "vpsubq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0x0a], "vpsubq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0x4a, 0x01], "vpsubq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xdd, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xfb, 0x0a], "vpsubq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x58, 0xfb, 0x4a, 0x01], "vpsubq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x5d, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x9d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xfb, 0x0a], "vpsubq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x18, 0xfb, 0x4a, 0x01], "vpsubq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x1d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0xca], "vpsubq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0xca], "vpsubq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0xca], "vpsubq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0x0a], "vpsubq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0x4a, 0x01], "vpsubq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0xca], "vpsubq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0xca], "vpsubq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0xca], "vpsubq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0x0a], "vpsubq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0x4a, 0x01], "vpsubq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0xca], "vpaddb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0x0a], "vpaddb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0x4a, 0x01], "vpaddb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0xca], "vpaddb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0xca], "vpaddb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0x0a], "vpaddb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0x0a], "vpaddb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0x4a, 0x01], "vpaddb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0x4a, 0x01], "vpaddb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0xca], "vpaddb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0x0a], "vpaddb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0x4a, 0x01], "vpaddb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0xca], "vpaddb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0xca], "vpaddb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0x0a], "vpaddb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0x0a], "vpaddb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0x4a, 0x01], "vpaddb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0x4a, 0x01], "vpaddb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0xca], "vpaddb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0x0a], "vpaddb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0x4a, 0x01], "vpaddb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0xca], "vpaddb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0xca], "vpaddb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0x0a], "vpaddb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0x0a], "vpaddb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0x4a, 0x01], "vpaddb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0x4a, 0x01], "vpaddb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0xca], "vpaddw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0x0a], "vpaddw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0x4a, 0x01], "vpaddw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0xca], "vpaddw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0xca], "vpaddw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0x0a], "vpaddw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0x0a], "vpaddw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0x4a, 0x01], "vpaddw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0x4a, 0x01], "vpaddw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0xca], "vpaddw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0x0a], "vpaddw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0x4a, 0x01], "vpaddw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0xca], "vpaddw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0xca], "vpaddw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0x0a], "vpaddw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0x0a], "vpaddw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0x4a, 0x01], "vpaddw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0x4a, 0x01], "vpaddw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0xca], "vpaddw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0x0a], "vpaddw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0x4a, 0x01], "vpaddw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0xca], "vpaddw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0xca], "vpaddw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0x0a], "vpaddw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0x0a], "vpaddw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0x4a, 0x01], "vpaddw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0x4a, 0x01], "vpaddw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xbd, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfe, 0x0a], "vpaddd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x38, 0xfe, 0x4a, 0x01], "vpaddd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x3d, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0xca], "vpaddd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0xca], "vpaddd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0xca], "vpaddd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0x0a], "vpaddd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0x4a, 0x01], "vpaddd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xdd, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfe, 0x0a], "vpaddd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x58, 0xfe, 0x4a, 0x01], "vpaddd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x5d, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x9d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfe, 0x0a], "vpaddd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x18, 0xfe, 0x4a, 0x01], "vpaddd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x1d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0xca], "vpaddd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0xca], "vpaddd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0xca], "vpaddd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x0a], "vpaddd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x4a, 0x01], "vpaddd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0xca], "vpaddd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0xca], "vpaddd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0xca], "vpaddd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0x0a], "vpaddd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0x4a, 0x01], "vpaddd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); } #[test] fn tests_66_0f38() { test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0xca], "vpshufb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0x0a], "vpshufb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0x4a, 0x01], "vpshufb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0xca], "vpshufb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0xca], "vpshufb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0x0a], "vpshufb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0x0a], "vpshufb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0x4a, 0x01], "vpshufb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0x4a, 0x01], "vpshufb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0xca], "vpshufb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0x0a], "vpshufb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0x4a, 0x01], "vpshufb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0xca], "vpshufb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0xca], "vpshufb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0x0a], "vpshufb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0x0a], "vpshufb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0x4a, 0x01], "vpshufb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0x4a, 0x01], "vpshufb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0xca], "vpshufb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0x0a], "vpshufb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0x4a, 0x01], "vpshufb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0xca], "vpshufb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0xca], "vpshufb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0x0a], "vpshufb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0x0a], "vpshufb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0x4a, 0x01], "vpshufb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0x4a, 0x01], "vpshufb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0xca], "vpmaddubsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0x0a], "vpmaddubsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0xca], "vpmaddubsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0xca], "vpmaddubsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0x0a], "vpmaddubsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0x0a], "vpmaddubsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0xca], "vpmaddubsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0x0a], "vpmaddubsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0xca], "vpmaddubsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0xca], "vpmaddubsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0x0a], "vpmaddubsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0x0a], "vpmaddubsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0xca], "vpmaddubsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0xca], "vpmaddubsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0xca], "vpmaddubsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0x0a], "vpmaddubsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0xca], "vpmulhrsw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0xca], "vpmulhrsw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0xca], "vpmulhrsw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0x0a], "vpmulhrsw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0xca], "vpmulhrsw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0xca], "vpmulhrsw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0xca], "vpmulhrsw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0x0a], "vpmulhrsw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0xca], "vpmulhrsw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0x0a], "vpmulhrsw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x0c, 0x0a], "vpermilps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x0c, 0x4a, 0x01], "vpermilps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0xca], "vpermilps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0xca], "vpermilps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0xca], "vpermilps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0x0a], "vpermilps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0x4a, 0x01], "vpermilps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x0c, 0x0a], "vpermilps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x0c, 0x4a, 0x01], "vpermilps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x0c, 0x0a], "vpermilps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x0c, 0x4a, 0x01], "vpermilps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0xca], "vpermilps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0xca], "vpermilps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0xca], "vpermilps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0x0a], "vpermilps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0x4a, 0x01], "vpermilps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0xca], "vpermilps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0xca], "vpermilps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0xca], "vpermilps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0x0a], "vpermilps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0x4a, 0x01], "vpermilps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x0d, 0x4a, 0x01], "vpermilpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0xca], "vpermilpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0xca], "vpermilpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0xca], "vpermilpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0x4a, 0x01], "vpermilpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x0d, 0x4a, 0x01], "vpermilpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x0d, 0x4a, 0x01], "vpermilpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0xca], "vpermilpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0xca], "vpermilpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0xca], "vpermilpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0x4a, 0x01], "vpermilpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0xca], "vpermilpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0xca], "vpermilpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0xca], "vpermilpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0x4a, 0x01], "vpermilpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0xca], "vpsrlvw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0x0a], "vpsrlvw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0x4a, 0x01], "vpsrlvw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0xca], "vpsrlvw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0xca], "vpsrlvw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0x0a], "vpsrlvw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0x0a], "vpsrlvw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0x4a, 0x01], "vpsrlvw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0x4a, 0x01], "vpsrlvw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0xca], "vpsrlvw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0x0a], "vpsrlvw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0x4a, 0x01], "vpsrlvw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0xca], "vpsrlvw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0xca], "vpsrlvw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0x0a], "vpsrlvw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0x0a], "vpsrlvw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0x4a, 0x01], "vpsrlvw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0x4a, 0x01], "vpsrlvw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0xca], "vpsrlvw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0x0a], "vpsrlvw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0x4a, 0x01], "vpsrlvw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0xca], "vpsrlvw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0xca], "vpsrlvw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0x0a], "vpsrlvw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0x0a], "vpsrlvw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0x4a, 0x01], "vpsrlvw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0x4a, 0x01], "vpsrlvw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0xca], "vpsravw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0x0a], "vpsravw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0x4a, 0x01], "vpsravw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0xca], "vpsravw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0xca], "vpsravw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0x0a], "vpsravw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0x0a], "vpsravw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0x4a, 0x01], "vpsravw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0x4a, 0x01], "vpsravw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0xca], "vpsravw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0x0a], "vpsravw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0x4a, 0x01], "vpsravw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0xca], "vpsravw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0xca], "vpsravw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0x0a], "vpsravw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0x0a], "vpsravw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0x4a, 0x01], "vpsravw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0x4a, 0x01], "vpsravw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0xca], "vpsravw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0x0a], "vpsravw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0x4a, 0x01], "vpsravw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0xca], "vpsravw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0xca], "vpsravw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0x0a], "vpsravw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0x0a], "vpsravw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0x4a, 0x01], "vpsravw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0x4a, 0x01], "vpsravw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0xca], "vpsllvw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0x0a], "vpsllvw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0x4a, 0x01], "vpsllvw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0xca], "vpsllvw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0xca], "vpsllvw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0x0a], "vpsllvw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0x0a], "vpsllvw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0x4a, 0x01], "vpsllvw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0x4a, 0x01], "vpsllvw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0xca], "vpsllvw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0x0a], "vpsllvw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0x4a, 0x01], "vpsllvw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0xca], "vpsllvw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0xca], "vpsllvw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0x0a], "vpsllvw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0x0a], "vpsllvw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0x4a, 0x01], "vpsllvw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0x4a, 0x01], "vpsllvw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0xca], "vpsllvw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0x0a], "vpsllvw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0x4a, 0x01], "vpsllvw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0xca], "vpsllvw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0xca], "vpsllvw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0x0a], "vpsllvw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x0a], "vpsllvw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0x4a, 0x01], "vpsllvw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x4a, 0x01], "vpsllvw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}{sae}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x13, 0xca], "vcvtph2ps zmm1{sae}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x13, 0xca], "vcvtph2ps zmm1{k5}{sae}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0xca], "vcvtph2ps ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x0a], "vcvtph2ps ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0xca], "vcvtph2ps ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0xca], "vcvtph2ps ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0x0a], "vcvtph2ps ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0x0a], "vcvtph2ps ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0x0a], "vcvtph2ps zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0xca], "vcvtph2ps zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0xca], "vcvtph2ps zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0x0a], "vcvtph2ps zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0x0a], "vcvtph2ps zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0xca], "vcvtph2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0xca], "vcvtph2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0xca], "vcvtph2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0x0a], "vcvtph2ps xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x14, 0x0a], "vprorvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x14, 0x4a, 0x01], "vprorvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0xca], "vprorvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0xca], "vprorvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0xca], "vprorvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0x0a], "vprorvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0x4a, 0x01], "vprorvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x0a], "vprorvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x4a, 0x01], "vprorvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0xca], "vprorvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0xca], "vprorvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0xca], "vprorvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0x0a], "vprorvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0x4a, 0x01], "vprorvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x14, 0x0a], "vprorvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x14, 0x4a, 0x01], "vprorvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x14, 0x0a], "vprorvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x14, 0x4a, 0x01], "vprorvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0xca], "vprorvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0xca], "vprorvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0xca], "vprorvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0x0a], "vprorvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0x4a, 0x01], "vprorvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0xca], "vprorvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0xca], "vprorvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0xca], "vprorvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0x0a], "vprorvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0x4a, 0x01], "vprorvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x14, 0x0a], "vprorvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x14, 0x4a, 0x01], "vprorvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x14, 0x0a], "vprorvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x14, 0x4a, 0x01], "vprorvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0xca], "vprorvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0xca], "vprorvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0xca], "vprorvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0x0a], "vprorvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0x4a, 0x01], "vprorvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0xca], "vprorvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0xca], "vprorvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0xca], "vprorvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0x0a], "vprorvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0x4a, 0x01], "vprorvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x15, 0x0a], "vprolvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x15, 0x4a, 0x01], "vprolvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0xca], "vprolvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0xca], "vprolvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0xca], "vprolvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0x0a], "vprolvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0x4a, 0x01], "vprolvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x15, 0x0a], "vprolvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x15, 0x4a, 0x01], "vprolvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0xca], "vprolvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0xca], "vprolvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0xca], "vprolvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0x0a], "vprolvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0x4a, 0x01], "vprolvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x15, 0x0a], "vprolvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x15, 0x4a, 0x01], "vprolvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x15, 0x0a], "vprolvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x15, 0x4a, 0x01], "vprolvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0xca], "vprolvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0xca], "vprolvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0xca], "vprolvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0x0a], "vprolvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0x4a, 0x01], "vprolvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0xca], "vprolvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0xca], "vprolvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0xca], "vprolvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0x0a], "vprolvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0x4a, 0x01], "vprolvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x15, 0x0a], "vprolvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x15, 0x4a, 0x01], "vprolvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x15, 0x0a], "vprolvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x15, 0x4a, 0x01], "vprolvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0xca], "vprolvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0xca], "vprolvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0xca], "vprolvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0x0a], "vprolvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0x4a, 0x01], "vprolvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0xca], "vprolvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0xca], "vprolvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0xca], "vprolvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0x0a], "vprolvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0x4a, 0x01], "vprolvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x16, 0x0a], "vpermpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x16, 0x4a, 0x01], "vpermpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0xca], "vpermpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0xca], "vpermpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0xca], "vpermpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0x0a], "vpermpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0x4a, 0x01], "vpermpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x16, 0x0a], "vpermps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x16, 0x4a, 0x01], "vpermps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0xca], "vpermps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0xca], "vpermps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0xca], "vpermps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0x0a], "vpermps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0x4a, 0x01], "vpermps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x16, 0x0a], "vpermpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x16, 0x4a, 0x01], "vpermpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0xca], "vpermpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0xca], "vpermpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0xca], "vpermpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0x0a], "vpermpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0x4a, 0x01], "vpermpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x16, 0x0a], "vpermps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x16, 0x4a, 0x01], "vpermps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0xca], "vpermps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0xca], "vpermps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0xca], "vpermps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0x0a], "vpermps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0x4a, 0x01], "vpermps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0xca], "vbroadcastss ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0x0a], "vbroadcastss ymm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0x4a, 0x01], "vbroadcastss ymm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0xca], "vbroadcastss ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0xca], "vbroadcastss ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0x0a], "vbroadcastss ymm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0x0a], "vbroadcastss ymm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0x4a, 0x01], "vbroadcastss ymm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0x4a, 0x01], "vbroadcastss ymm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0xca], "vbroadcastss zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0x0a], "vbroadcastss zmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0x4a, 0x01], "vbroadcastss zmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0xca], "vbroadcastss zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0xca], "vbroadcastss zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0x0a], "vbroadcastss zmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0x0a], "vbroadcastss zmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0x4a, 0x01], "vbroadcastss zmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0x4a, 0x01], "vbroadcastss zmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0xca], "vbroadcastss xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0x0a], "vbroadcastss xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0x4a, 0x01], "vbroadcastss xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0xca], "vbroadcastss xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0xca], "vbroadcastss xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0x0a], "vbroadcastss xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0x0a], "vbroadcastss xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0x4a, 0x01], "vbroadcastss xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0x4a, 0x01], "vbroadcastss xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0xca], "vbroadcastsd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0x0a], "vbroadcastsd ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0xca], "vbroadcastsd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0xca], "vbroadcastsd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0x0a], "vbroadcastsd ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0x0a], "vbroadcastsd ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0xca], "vbroadcastf32x2 ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0x0a], "vbroadcastf32x2 ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0xca], "vbroadcastsd zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0x0a], "vbroadcastsd zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0xca], "vbroadcastsd zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0xca], "vbroadcastsd zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0x0a], "vbroadcastsd zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0x0a], "vbroadcastsd zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0xca], "vbroadcastf32x2 zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0x0a], "vbroadcastf32x2 zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1a, 0x0a], "vbroadcastf64x2 ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1a, 0x0a], "vbroadcastf32x4 ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x0a], "vbroadcastf64x2 zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x0a], "vbroadcastf32x4 zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x0a], "vbroadcastf64x4 zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x0a], "vbroadcastf32x8 zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0xca], "vpabsb ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0x0a], "vpabsb ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0x4a, 0x01], "vpabsb ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0xca], "vpabsb ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0xca], "vpabsb ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0x0a], "vpabsb ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0x0a], "vpabsb ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0x4a, 0x01], "vpabsb ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0x4a, 0x01], "vpabsb ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0xca], "vpabsb zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0x0a], "vpabsb zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0x4a, 0x01], "vpabsb zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0xca], "vpabsb zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0xca], "vpabsb zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0x0a], "vpabsb zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0x0a], "vpabsb zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0x4a, 0x01], "vpabsb zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0x4a, 0x01], "vpabsb zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0xca], "vpabsb xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0x0a], "vpabsb xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0x4a, 0x01], "vpabsb xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0xca], "vpabsb xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0xca], "vpabsb xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0x0a], "vpabsb xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0x0a], "vpabsb xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0x4a, 0x01], "vpabsb xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0x4a, 0x01], "vpabsb xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0xca], "vpabsw ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0x0a], "vpabsw ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0x4a, 0x01], "vpabsw ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0xca], "vpabsw ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0xca], "vpabsw ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0x0a], "vpabsw ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0x0a], "vpabsw ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0x4a, 0x01], "vpabsw ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0x4a, 0x01], "vpabsw ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0xca], "vpabsw zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0x0a], "vpabsw zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0x4a, 0x01], "vpabsw zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0xca], "vpabsw zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0xca], "vpabsw zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0x0a], "vpabsw zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0x0a], "vpabsw zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0x4a, 0x01], "vpabsw zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0x4a, 0x01], "vpabsw zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0xca], "vpabsw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0x0a], "vpabsw xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0x4a, 0x01], "vpabsw xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0xca], "vpabsw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0xca], "vpabsw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0x0a], "vpabsw xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0x0a], "vpabsw xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0x4a, 0x01], "vpabsw xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0x4a, 0x01], "vpabsw xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x1e, 0x0a], "vpabsd ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x1e, 0x0a], "vpabsd ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x1e, 0x4a, 0x01], "vpabsd ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0xca], "vpabsd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0xca], "vpabsd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0xca], "vpabsd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0x0a], "vpabsd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0x0a], "vpabsd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0x4a, 0x01], "vpabsd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x1e, 0x0a], "vpabsd zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x1e, 0x0a], "vpabsd zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x1e, 0x4a, 0x01], "vpabsd zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x1e, 0x0a], "vpabsd xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x1e, 0x0a], "vpabsd xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x1e, 0x4a, 0x01], "vpabsd xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0xca], "vpabsd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0xca], "vpabsd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0xca], "vpabsd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0x0a], "vpabsd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0x0a], "vpabsd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0x4a, 0x01], "vpabsd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0xca], "vpabsd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0xca], "vpabsd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0xca], "vpabsd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0x0a], "vpabsd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0x0a], "vpabsd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0x4a, 0x01], "vpabsd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x1f, 0x0a], "vpabsq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x1f, 0x0a], "vpabsq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x1f, 0x4a, 0x01], "vpabsq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0xca], "vpabsq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0xca], "vpabsq ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0xca], "vpabsq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0x0a], "vpabsq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0x0a], "vpabsq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0x4a, 0x01], "vpabsq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x1f, 0x0a], "vpabsq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x1f, 0x0a], "vpabsq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x1f, 0x4a, 0x01], "vpabsq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x1f, 0x0a], "vpabsq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x1f, 0x0a], "vpabsq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x1f, 0x4a, 0x01], "vpabsq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0xca], "vpabsq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0xca], "vpabsq zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0xca], "vpabsq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0x0a], "vpabsq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0x0a], "vpabsq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0x4a, 0x01], "vpabsq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0xca], "vpabsq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0xca], "vpabsq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0xca], "vpabsq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0x0a], "vpabsq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0x0a], "vpabsq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0x4a, 0x01], "vpabsq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0xca], "vpmovsxbw ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0x0a], "vpmovsxbw ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0xca], "vpmovsxbw ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0xca], "vpmovsxbw ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0x0a], "vpmovsxbw ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0x0a], "vpmovsxbw ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0xca], "vpmovsxbw zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0x0a], "vpmovsxbw zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0xca], "vpmovsxbw zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0xca], "vpmovsxbw zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0x0a], "vpmovsxbw zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0x0a], "vpmovsxbw zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0xca], "vpmovsxbw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0xca], "vpmovsxbw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0xca], "vpmovsxbw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0x0a], "vpmovsxbw xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0xca], "vpmovsxbd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0x0a], "vpmovsxbd ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0xca], "vpmovsxbd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0xca], "vpmovsxbd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0x0a], "vpmovsxbd ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0x0a], "vpmovsxbd ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0xca], "vpmovsxbd zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0x0a], "vpmovsxbd zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0xca], "vpmovsxbd zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0xca], "vpmovsxbd zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0x0a], "vpmovsxbd zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0x0a], "vpmovsxbd zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0xca], "vpmovsxbd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0xca], "vpmovsxbd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0xca], "vpmovsxbd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0x0a], "vpmovsxbd xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0xca], "vpmovsxbq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0x0a], "vpmovsxbq ymm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0xca], "vpmovsxbq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0xca], "vpmovsxbq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0x0a], "vpmovsxbq ymm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0x0a], "vpmovsxbq ymm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0xca], "vpmovsxbq zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0x0a], "vpmovsxbq zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0xca], "vpmovsxbq zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0xca], "vpmovsxbq zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0x0a], "vpmovsxbq zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0x0a], "vpmovsxbq zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0xca], "vpmovsxbq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}{z}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1{k5}{z}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0xca], "vpmovsxbq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0xca], "vpmovsxbq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0x0a], "vpmovsxbq xmm1, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1{k5}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0xca], "vpmovsxwd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0x0a], "vpmovsxwd ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0xca], "vpmovsxwd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0xca], "vpmovsxwd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0x0a], "vpmovsxwd ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0x0a], "vpmovsxwd ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0xca], "vpmovsxwd zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0x0a], "vpmovsxwd zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0xca], "vpmovsxwd zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0xca], "vpmovsxwd zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0x0a], "vpmovsxwd zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0x0a], "vpmovsxwd zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0xca], "vpmovsxwd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0xca], "vpmovsxwd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0xca], "vpmovsxwd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0x0a], "vpmovsxwd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0xca], "vpmovsxwq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0x0a], "vpmovsxwq ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0xca], "vpmovsxwq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0xca], "vpmovsxwq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0x0a], "vpmovsxwq ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0x0a], "vpmovsxwq ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0xca], "vpmovsxwq zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0x0a], "vpmovsxwq zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0xca], "vpmovsxwq zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0xca], "vpmovsxwq zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0x0a], "vpmovsxwq zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0x0a], "vpmovsxwq zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0xca], "vpmovsxwq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0xca], "vpmovsxwq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0xca], "vpmovsxwq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x0a], "vpmovsxwq xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0xca], "vpmovsxdq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x0a], "vpmovsxdq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0xca], "vpmovsxdq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x0a], "vpmovsxdq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x0a], "vpmovsxdq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0xca], "vpmovsxdq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x0a], "vpmovsxdq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0xca], "vpmovsxdq zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0xca], "vpmovsxdq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0x0a], "vpmovsxdq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0x0a], "vpmovsxdq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0xca], "vpmovsxdq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0xca], "vpmovsxdq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0xca], "vpmovsxdq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0x0a], "vpmovsxdq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0xca], "vptestmw k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0xca], "vptestmw k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x0a], "vptestmw k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x0a], "vptestmw k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x4a, 0x01], "vptestmw k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0xca], "vptestmb k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0xca], "vptestmb k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x0a], "vptestmb k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x0a], "vptestmb k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x4a, 0x01], "vptestmb k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0xca], "vptestmw k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0xca], "vptestmw k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x0a], "vptestmw k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0x0a], "vptestmw k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x4a, 0x01], "vptestmw k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0xca], "vptestmw k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0xca], "vptestmw k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0x0a], "vptestmw k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0x0a], "vptestmw k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0x4a, 0x01], "vptestmw k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0xca], "vptestmb k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0xca], "vptestmb k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0x0a], "vptestmb k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0x0a], "vptestmb k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0x4a, 0x01], "vptestmb k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0xca], "vptestmb k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0xca], "vptestmb k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0x0a], "vptestmb k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0x0a], "vptestmb k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0x4a, 0x01], "vptestmb k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x27, 0x0a], "vptestmq k1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x27, 0x4a, 0x01], "vptestmq k1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0xca], "vptestmq k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0xca], "vptestmq k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0x0a], "vptestmq k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0x4a, 0x01], "vptestmq k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x0a], "vptestmd k1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x4a, 0x01], "vptestmd k1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0xca], "vptestmd k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0xca], "vptestmd k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x0a], "vptestmd k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x4a, 0x01], "vptestmd k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x0a], "vptestmq k1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x4a, 0x01], "vptestmq k1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x0a], "vptestmq k1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x4a, 0x01], "vptestmq k1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0xca], "vptestmq k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0xca], "vptestmq k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0x0a], "vptestmq k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0x4a, 0x01], "vptestmq k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0xca], "vptestmq k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0xca], "vptestmq k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0x0a], "vptestmq k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0x4a, 0x01], "vptestmq k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x27, 0x0a], "vptestmd k1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x27, 0x4a, 0x01], "vptestmd k1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x27, 0x0a], "vptestmd k1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x27, 0x4a, 0x01], "vptestmd k1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0xca], "vptestmd k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0xca], "vptestmd k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0x0a], "vptestmd k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0x4a, 0x01], "vptestmd k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0xca], "vptestmd k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0xca], "vptestmd k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0x0a], "vptestmd k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0x4a, 0x01], "vptestmd k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x0a], "vpmuldq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x4a, 0x01], "vpmuldq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0xca], "vpmuldq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0xca], "vpmuldq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0x0a], "vpmuldq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0x4a, 0x01], "vpmuldq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x28, 0x0a], "vpmuldq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x28, 0x4a, 0x01], "vpmuldq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x28, 0x0a], "vpmuldq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x28, 0x4a, 0x01], "vpmuldq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0xca], "vpmuldq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0xca], "vpmuldq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0xca], "vpmuldq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0x0a], "vpmuldq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0x4a, 0x01], "vpmuldq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0xca], "vpmuldq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0xca], "vpmuldq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0xca], "vpmuldq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0x0a], "vpmuldq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0x4a, 0x01], "vpmuldq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x29, 0x0a], "vpcmpeqq k1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x29, 0x4a, 0x01], "vpcmpeqq k1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0xca], "vpcmpeqq k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0xca], "vpcmpeqq k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x0a], "vpcmpeqq k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x4a, 0x01], "vpcmpeqq k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x0a], "vpcmpeqq k1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x4a, 0x01], "vpcmpeqq k1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x29, 0x0a], "vpcmpeqq k1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x29, 0x4a, 0x01], "vpcmpeqq k1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0xca], "vpcmpeqq k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0xca], "vpcmpeqq k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0x0a], "vpcmpeqq k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0x4a, 0x01], "vpcmpeqq k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0xca], "vpcmpeqq k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0xca], "vpcmpeqq k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x0a], "vpcmpeqq k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x4a, 0x01], "vpcmpeqq k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x4a, 0x01], "vmovntdqa ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x0a], "vmovntdqa zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x4a, 0x01], "vmovntdqa zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x4a, 0x01], "vmovntdqa xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2b, 0x4a, 0x01], "vpackusdw ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0xca], "vpackusdw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0xca], "vpackusdw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0xca], "vpackusdw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0x4a, 0x01], "vpackusdw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2b, 0x4a, 0x01], "vpackusdw zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2b, 0x4a, 0x01], "vpackusdw xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0xca], "vpackusdw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0xca], "vpackusdw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0xca], "vpackusdw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0x4a, 0x01], "vpackusdw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0xca], "vpackusdw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0xca], "vpackusdw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0xca], "vpackusdw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0x4a, 0x01], "vpackusdw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x2c, 0xca], "vscalefpd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0xca], "vscalefpd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0x4a, 0x01], "vscalefpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0xca], "vscalefpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0xca], "vscalefpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0xca], "vscalefpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0x4a, 0x01], "vscalefpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2c, 0xca], "vscalefps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2c, 0xca], "vscalefps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0xca], "vscalefps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0xca], "vscalefps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0x0a], "vscalefps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0x4a, 0x01], "vscalefps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0xca], "vscalefps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0xca], "vscalefps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0xca], "vscalefps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0x0a], "vscalefps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0x4a, 0x01], "vscalefps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0xca], "vscalefpd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0xca], "vscalefpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0x4a, 0x01], "vscalefpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0xca], "vscalefpd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0x4a, 0x01], "vscalefpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0xca], "vscalefpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0xca], "vscalefpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0x4a, 0x01], "vscalefpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0xca], "vscalefpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0xca], "vscalefpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0xca], "vscalefpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0x4a, 0x01], "vscalefpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0xca], "vscalefps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0xca], "vscalefps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0x0a], "vscalefps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0x4a, 0x01], "vscalefps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0xca], "vscalefps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0xca], "vscalefps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0x0a], "vscalefps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0x4a, 0x01], "vscalefps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0xca], "vscalefps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0xca], "vscalefps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0x0a], "vscalefps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0x4a, 0x01], "vscalefps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0xca], "vscalefps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0xca], "vscalefps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0xca], "vscalefps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0x0a], "vscalefps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0x4a, 0x01], "vscalefps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x2d, 0xca], "vscalefsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x2d, 0xca], "vscalefsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0x0a], "vscalefsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0x4a, 0x01], "vscalefsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0xca], "vscalefsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0xca], "vscalefsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x0a], "vscalefsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x0a], "vscalefsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x4a, 0x01], "vscalefsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x4a, 0x01], "vscalefsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x2d, 0xca], "vscalefss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x2d, 0xca], "vscalefss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x2d, 0xca], "vscalefss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x2d, 0xca], "vscalefss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0xca], "vscalefss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0x0a], "vscalefss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0x4a, 0x01], "vscalefss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0xca], "vscalefss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0xca], "vscalefss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0x0a], "vscalefss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0x0a], "vscalefss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0x4a, 0x01], "vscalefss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0x4a, 0x01], "vscalefss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x2d, 0xca], "vscalefsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x2d, 0xca], "vscalefsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x2d, 0xca], "vscalefsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x2d, 0xca], "vscalefss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x2d, 0xca], "vscalefss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x2d, 0xca], "vscalefss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x2d, 0xca], "vscalefss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0xca], "vpmovzxbw ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0x0a], "vpmovzxbw ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0xca], "vpmovzxbw ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0xca], "vpmovzxbw ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0x0a], "vpmovzxbw ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0x0a], "vpmovzxbw ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0xca], "vpmovzxbw zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0x0a], "vpmovzxbw zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0xca], "vpmovzxbw zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0xca], "vpmovzxbw zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0x0a], "vpmovzxbw zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0x0a], "vpmovzxbw zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0xca], "vpmovzxbw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0xca], "vpmovzxbw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0xca], "vpmovzxbw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0x0a], "vpmovzxbw xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0xca], "vpmovzxbd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0x0a], "vpmovzxbd ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0xca], "vpmovzxbd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0xca], "vpmovzxbd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0x0a], "vpmovzxbd ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0x0a], "vpmovzxbd ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0xca], "vpmovzxbd zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0x0a], "vpmovzxbd zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0xca], "vpmovzxbd zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0xca], "vpmovzxbd zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0x0a], "vpmovzxbd zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0x0a], "vpmovzxbd zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0xca], "vpmovzxbd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0xca], "vpmovzxbd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0xca], "vpmovzxbd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0x0a], "vpmovzxbd xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0xca], "vpmovzxbq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0x0a], "vpmovzxbq ymm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0xca], "vpmovzxbq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0xca], "vpmovzxbq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0x0a], "vpmovzxbq ymm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0x0a], "vpmovzxbq ymm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0xca], "vpmovzxbq zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0x0a], "vpmovzxbq zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0xca], "vpmovzxbq zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0xca], "vpmovzxbq zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0x0a], "vpmovzxbq zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0x0a], "vpmovzxbq zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0xca], "vpmovzxbq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}{z}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1{k5}{z}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0xca], "vpmovzxbq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0xca], "vpmovzxbq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0x0a], "vpmovzxbq xmm1, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1{k5}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0xca], "vpmovzxwd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0x0a], "vpmovzxwd ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0xca], "vpmovzxwd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0xca], "vpmovzxwd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0x0a], "vpmovzxwd ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0x0a], "vpmovzxwd ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0xca], "vpmovzxwd zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0x0a], "vpmovzxwd zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0xca], "vpmovzxwd zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0xca], "vpmovzxwd zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0x0a], "vpmovzxwd zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0x0a], "vpmovzxwd zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0xca], "vpmovzxwd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0xca], "vpmovzxwd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0xca], "vpmovzxwd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0x0a], "vpmovzxwd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0xca], "vpmovzxwq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0x0a], "vpmovzxwq ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0xca], "vpmovzxwq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0xca], "vpmovzxwq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0x0a], "vpmovzxwq ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0x0a], "vpmovzxwq ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0xca], "vpmovzxwq zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0x0a], "vpmovzxwq zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0xca], "vpmovzxwq zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0xca], "vpmovzxwq zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0x0a], "vpmovzxwq zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0x0a], "vpmovzxwq zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0xca], "vpmovzxwq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0xca], "vpmovzxwq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0xca], "vpmovzxwq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0x0a], "vpmovzxwq xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0xca], "vpmovzxdq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0x0a], "vpmovzxdq ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0xca], "vpmovzxdq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0xca], "vpmovzxdq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0x0a], "vpmovzxdq ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0x0a], "vpmovzxdq ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0xca], "vpmovzxdq zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0x0a], "vpmovzxdq zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0xca], "vpmovzxdq zmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0xca], "vpmovzxdq zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0x0a], "vpmovzxdq zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0x0a], "vpmovzxdq zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0xca], "vpmovzxdq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0xca], "vpmovzxdq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0xca], "vpmovzxdq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0x0a], "vpmovzxdq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x36, 0x0a], "vpermq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x36, 0x4a, 0x01], "vpermq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0xca], "vpermq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0xca], "vpermq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0xca], "vpermq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0x0a], "vpermq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0x4a, 0x01], "vpermq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x36, 0x0a], "vpermd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x36, 0x4a, 0x01], "vpermd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0xca], "vpermd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0xca], "vpermd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0xca], "vpermd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0x0a], "vpermd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0x4a, 0x01], "vpermd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x36, 0x0a], "vpermq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x36, 0x4a, 0x01], "vpermq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0xca], "vpermq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0xca], "vpermq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0xca], "vpermq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0x0a], "vpermq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0x4a, 0x01], "vpermq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x36, 0x0a], "vpermd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x36, 0x4a, 0x01], "vpermd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0xca], "vpermd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0xca], "vpermd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0xca], "vpermd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0x0a], "vpermd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0x4a, 0x01], "vpermd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x37, 0x0a], "vpcmpgtq k1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x37, 0x4a, 0x01], "vpcmpgtq k1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0xca], "vpcmpgtq k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0xca], "vpcmpgtq k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0x0a], "vpcmpgtq k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0x4a, 0x01], "vpcmpgtq k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x37, 0x0a], "vpcmpgtq k1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x37, 0x4a, 0x01], "vpcmpgtq k1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x37, 0x0a], "vpcmpgtq k1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x37, 0x4a, 0x01], "vpcmpgtq k1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0xca], "vpcmpgtq k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0xca], "vpcmpgtq k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0x0a], "vpcmpgtq k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0x4a, 0x01], "vpcmpgtq k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0xca], "vpcmpgtq k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0xca], "vpcmpgtq k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0x0a], "vpcmpgtq k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0x4a, 0x01], "vpcmpgtq k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0xca], "vpminsb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0x0a], "vpminsb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0x4a, 0x01], "vpminsb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0xca], "vpminsb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0xca], "vpminsb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0x0a], "vpminsb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0x0a], "vpminsb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0x4a, 0x01], "vpminsb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0x4a, 0x01], "vpminsb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0xca], "vpminsb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0x0a], "vpminsb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0x4a, 0x01], "vpminsb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0xca], "vpminsb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0xca], "vpminsb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0x0a], "vpminsb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0x0a], "vpminsb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0x4a, 0x01], "vpminsb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0x4a, 0x01], "vpminsb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0xca], "vpminsb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0x0a], "vpminsb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0x4a, 0x01], "vpminsb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0xca], "vpminsb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0xca], "vpminsb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0x0a], "vpminsb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0x0a], "vpminsb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0x4a, 0x01], "vpminsb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0x4a, 0x01], "vpminsb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x39, 0x0a], "vpminsq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x39, 0x4a, 0x01], "vpminsq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0xca], "vpminsq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0xca], "vpminsq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0xca], "vpminsq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0x0a], "vpminsq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0x4a, 0x01], "vpminsq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x39, 0x0a], "vpminsd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x39, 0x4a, 0x01], "vpminsd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0xca], "vpminsd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0xca], "vpminsd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0xca], "vpminsd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0x0a], "vpminsd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0x4a, 0x01], "vpminsd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x39, 0x0a], "vpminsq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x39, 0x4a, 0x01], "vpminsq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x39, 0x0a], "vpminsq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x39, 0x4a, 0x01], "vpminsq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0xca], "vpminsq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0xca], "vpminsq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0xca], "vpminsq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0x0a], "vpminsq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0x4a, 0x01], "vpminsq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0xca], "vpminsq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0xca], "vpminsq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0xca], "vpminsq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0x0a], "vpminsq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0x4a, 0x01], "vpminsq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x39, 0x0a], "vpminsd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x39, 0x4a, 0x01], "vpminsd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x39, 0x0a], "vpminsd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x39, 0x4a, 0x01], "vpminsd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0xca], "vpminsd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0xca], "vpminsd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0xca], "vpminsd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0x0a], "vpminsd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0x4a, 0x01], "vpminsd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0xca], "vpminsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0xca], "vpminsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0xca], "vpminsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0x0a], "vpminsd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0x4a, 0x01], "vpminsd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0xca], "vpminuw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0x0a], "vpminuw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0x4a, 0x01], "vpminuw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0xca], "vpminuw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0xca], "vpminuw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0x0a], "vpminuw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0x0a], "vpminuw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0x4a, 0x01], "vpminuw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0x4a, 0x01], "vpminuw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0xca], "vpminuw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0x0a], "vpminuw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0x4a, 0x01], "vpminuw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0xca], "vpminuw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0xca], "vpminuw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0x0a], "vpminuw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0x0a], "vpminuw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0x4a, 0x01], "vpminuw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0x4a, 0x01], "vpminuw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0xca], "vpminuw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0x0a], "vpminuw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0x4a, 0x01], "vpminuw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0xca], "vpminuw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0xca], "vpminuw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0x0a], "vpminuw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0x0a], "vpminuw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0x4a, 0x01], "vpminuw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0x4a, 0x01], "vpminuw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3b, 0x0a], "vpminuq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3b, 0x4a, 0x01], "vpminuq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0xca], "vpminuq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0xca], "vpminuq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0xca], "vpminuq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0x0a], "vpminuq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0x4a, 0x01], "vpminuq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3b, 0x0a], "vpminud ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3b, 0x4a, 0x01], "vpminud ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0xca], "vpminud ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0xca], "vpminud ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0xca], "vpminud ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0x0a], "vpminud ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0x4a, 0x01], "vpminud ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3b, 0x0a], "vpminuq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3b, 0x4a, 0x01], "vpminuq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3b, 0x0a], "vpminuq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3b, 0x4a, 0x01], "vpminuq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0xca], "vpminuq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0xca], "vpminuq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0xca], "vpminuq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0x0a], "vpminuq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0x4a, 0x01], "vpminuq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0xca], "vpminuq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0xca], "vpminuq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0xca], "vpminuq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0x0a], "vpminuq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0x4a, 0x01], "vpminuq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3b, 0x0a], "vpminud zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3b, 0x4a, 0x01], "vpminud zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3b, 0x0a], "vpminud xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3b, 0x4a, 0x01], "vpminud xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0xca], "vpminud zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0xca], "vpminud zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0xca], "vpminud zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0x0a], "vpminud zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0x4a, 0x01], "vpminud zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0xca], "vpminud xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0xca], "vpminud xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0xca], "vpminud xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0x0a], "vpminud xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0x4a, 0x01], "vpminud xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0xca], "vpmaxsb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0x0a], "vpmaxsb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0xca], "vpmaxsb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0xca], "vpmaxsb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0x0a], "vpmaxsb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0x0a], "vpmaxsb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0xca], "vpmaxsb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0x0a], "vpmaxsb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0xca], "vpmaxsb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0xca], "vpmaxsb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0x0a], "vpmaxsb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0x0a], "vpmaxsb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0xca], "vpmaxsb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0xca], "vpmaxsb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0xca], "vpmaxsb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0x0a], "vpmaxsb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0xca], "vpmaxsq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0xca], "vpmaxsq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0xca], "vpmaxsq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0xca], "vpmaxsd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0xca], "vpmaxsd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0xca], "vpmaxsd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0xca], "vpmaxsq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0xca], "vpmaxsq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0xca], "vpmaxsq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0xca], "vpmaxsq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0xca], "vpmaxsq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0xca], "vpmaxsq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0xca], "vpmaxsd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0xca], "vpmaxsd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0xca], "vpmaxsd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0xca], "vpmaxsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0xca], "vpmaxsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0xca], "vpmaxsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0xca], "vpmaxuw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0x0a], "vpmaxuw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0xca], "vpmaxuw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0xca], "vpmaxuw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0x0a], "vpmaxuw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0x0a], "vpmaxuw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0xca], "vpmaxuw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0x0a], "vpmaxuw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0xca], "vpmaxuw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0xca], "vpmaxuw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0x0a], "vpmaxuw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0x0a], "vpmaxuw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0xca], "vpmaxuw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0xca], "vpmaxuw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0xca], "vpmaxuw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0x0a], "vpmaxuw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0xca], "vpmaxuq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0xca], "vpmaxuq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0xca], "vpmaxuq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x3f, 0x4a, 0x01], "vpmaxud ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0xca], "vpmaxud ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0xca], "vpmaxud ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0xca], "vpmaxud ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0x4a, 0x01], "vpmaxud ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0xca], "vpmaxuq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0xca], "vpmaxuq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0xca], "vpmaxuq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0xca], "vpmaxuq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0xca], "vpmaxuq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0xca], "vpmaxuq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x3f, 0x4a, 0x01], "vpmaxud zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x3f, 0x4a, 0x01], "vpmaxud xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0xca], "vpmaxud zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0xca], "vpmaxud zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0xca], "vpmaxud zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0x4a, 0x01], "vpmaxud zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0xca], "vpmaxud xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0xca], "vpmaxud xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0xca], "vpmaxud xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0x4a, 0x01], "vpmaxud xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x40, 0x0a], "vpmullq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x40, 0x4a, 0x01], "vpmullq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0xca], "vpmullq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0xca], "vpmullq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0xca], "vpmullq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0x0a], "vpmullq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0x4a, 0x01], "vpmullq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x40, 0x0a], "vpmulld ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x40, 0x4a, 0x01], "vpmulld ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0xca], "vpmulld ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0xca], "vpmulld ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0xca], "vpmulld ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0x0a], "vpmulld ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0x4a, 0x01], "vpmulld ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x40, 0x0a], "vpmullq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x40, 0x4a, 0x01], "vpmullq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x40, 0x0a], "vpmullq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x40, 0x4a, 0x01], "vpmullq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0xca], "vpmullq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0xca], "vpmullq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0xca], "vpmullq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0x0a], "vpmullq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0x4a, 0x01], "vpmullq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0xca], "vpmullq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0xca], "vpmullq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0xca], "vpmullq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0x0a], "vpmullq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0x4a, 0x01], "vpmullq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x40, 0x0a], "vpmulld zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x40, 0x4a, 0x01], "vpmulld zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x40, 0x0a], "vpmulld xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x40, 0x4a, 0x01], "vpmulld xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0xca], "vpmulld zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0xca], "vpmulld zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0xca], "vpmulld zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0x0a], "vpmulld zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0x4a, 0x01], "vpmulld zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0xca], "vpmulld xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0xca], "vpmulld xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0xca], "vpmulld xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0x0a], "vpmulld xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0x4a, 0x01], "vpmulld xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x42, 0xca], "vgetexppd zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x42, 0xca], "vgetexppd zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x42, 0x0a], "vgetexppd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x42, 0x0a], "vgetexppd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x42, 0x4a, 0x01], "vgetexppd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0xca], "vgetexppd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0xca], "vgetexppd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0xca], "vgetexppd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0x0a], "vgetexppd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0x0a], "vgetexppd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0x4a, 0x01], "vgetexppd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x42, 0xca], "vgetexpps zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x42, 0xca], "vgetexpps zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x42, 0x0a], "vgetexpps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x42, 0x0a], "vgetexpps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x42, 0x4a, 0x01], "vgetexpps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0xca], "vgetexpps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0xca], "vgetexpps ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0xca], "vgetexpps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0x0a], "vgetexpps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0x0a], "vgetexpps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0x4a, 0x01], "vgetexpps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x42, 0x0a], "vgetexppd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x42, 0x0a], "vgetexppd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x42, 0x4a, 0x01], "vgetexppd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x42, 0x0a], "vgetexppd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x42, 0x0a], "vgetexppd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x42, 0x4a, 0x01], "vgetexppd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0xca], "vgetexppd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0xca], "vgetexppd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0x0a], "vgetexppd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0x0a], "vgetexppd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0x4a, 0x01], "vgetexppd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0xca], "vgetexppd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0xca], "vgetexppd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0xca], "vgetexppd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0x0a], "vgetexppd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0x0a], "vgetexppd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0x4a, 0x01], "vgetexppd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x42, 0x0a], "vgetexpps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x42, 0x0a], "vgetexpps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x42, 0x4a, 0x01], "vgetexpps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x42, 0x0a], "vgetexpps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x42, 0x0a], "vgetexpps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x42, 0x4a, 0x01], "vgetexpps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0xca], "vgetexpps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0xca], "vgetexpps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0x0a], "vgetexpps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0x0a], "vgetexpps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0x4a, 0x01], "vgetexpps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0xca], "vgetexpps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0xca], "vgetexpps xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0xca], "vgetexpps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0x0a], "vgetexpps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0x0a], "vgetexpps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0x4a, 0x01], "vgetexpps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x43, 0xca], "vgetexpsd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x43, 0xca], "vgetexpsd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0x0a], "vgetexpsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0x4a, 0x01], "vgetexpsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0xca], "vgetexpsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0xca], "vgetexpsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0x0a], "vgetexpsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0x0a], "vgetexpsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0x4a, 0x01], "vgetexpsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0x4a, 0x01], "vgetexpsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x43, 0xca], "vgetexpss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x43, 0xca], "vgetexpss xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x43, 0xca], "vgetexpss xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0xca], "vgetexpss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x0a], "vgetexpss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x4a, 0x01], "vgetexpss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0xca], "vgetexpss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0xca], "vgetexpss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x0a], "vgetexpss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0x0a], "vgetexpss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x4a, 0x01], "vgetexpss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0x4a, 0x01], "vgetexpss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x44, 0x0a], "vplzcntq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x44, 0x0a], "vplzcntq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x44, 0x4a, 0x01], "vplzcntq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0xca], "vplzcntq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0xca], "vplzcntq ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0xca], "vplzcntq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0x0a], "vplzcntq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0x0a], "vplzcntq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0x4a, 0x01], "vplzcntq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x44, 0x0a], "vplzcntd ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x44, 0x0a], "vplzcntd ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x44, 0x4a, 0x01], "vplzcntd ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0xca], "vplzcntd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0xca], "vplzcntd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0xca], "vplzcntd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0x0a], "vplzcntd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0x0a], "vplzcntd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0x4a, 0x01], "vplzcntd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x44, 0x0a], "vplzcntq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x44, 0x0a], "vplzcntq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x44, 0x4a, 0x01], "vplzcntq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x44, 0x0a], "vplzcntq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x44, 0x0a], "vplzcntq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x44, 0x4a, 0x01], "vplzcntq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0xca], "vplzcntq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0xca], "vplzcntq zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0xca], "vplzcntq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0x0a], "vplzcntq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0x0a], "vplzcntq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0x4a, 0x01], "vplzcntq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0xca], "vplzcntq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0xca], "vplzcntq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0xca], "vplzcntq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0x0a], "vplzcntq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0x0a], "vplzcntq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0x4a, 0x01], "vplzcntq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x44, 0x0a], "vplzcntd zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x44, 0x0a], "vplzcntd zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x44, 0x4a, 0x01], "vplzcntd zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x44, 0x0a], "vplzcntd xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x44, 0x0a], "vplzcntd xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x44, 0x4a, 0x01], "vplzcntd xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0xca], "vplzcntd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0xca], "vplzcntd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0xca], "vplzcntd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0x0a], "vplzcntd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0x0a], "vplzcntd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0x4a, 0x01], "vplzcntd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0xca], "vplzcntd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0xca], "vplzcntd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0xca], "vplzcntd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0x0a], "vplzcntd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0x0a], "vplzcntd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0x4a, 0x01], "vplzcntd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x45, 0x4a, 0x01], "vpsrlvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0xca], "vpsrlvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0xca], "vpsrlvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0xca], "vpsrlvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0x4a, 0x01], "vpsrlvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x45, 0x4a, 0x01], "vpsrlvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0xca], "vpsrlvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0xca], "vpsrlvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0xca], "vpsrlvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0x4a, 0x01], "vpsrlvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x45, 0x4a, 0x01], "vpsrlvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x45, 0x4a, 0x01], "vpsrlvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0xca], "vpsrlvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0xca], "vpsrlvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0xca], "vpsrlvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0x4a, 0x01], "vpsrlvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0xca], "vpsrlvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0xca], "vpsrlvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0xca], "vpsrlvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0x4a, 0x01], "vpsrlvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x45, 0x4a, 0x01], "vpsrlvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x45, 0x4a, 0x01], "vpsrlvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0xca], "vpsrlvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0xca], "vpsrlvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0xca], "vpsrlvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0x4a, 0x01], "vpsrlvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0xca], "vpsrlvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0xca], "vpsrlvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0xca], "vpsrlvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0x4a, 0x01], "vpsrlvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x46, 0x0a], "vpsravq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x46, 0x4a, 0x01], "vpsravq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0xca], "vpsravq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0xca], "vpsravq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0xca], "vpsravq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0x0a], "vpsravq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0x4a, 0x01], "vpsravq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x46, 0x0a], "vpsravd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x46, 0x4a, 0x01], "vpsravd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0xca], "vpsravd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0xca], "vpsravd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0xca], "vpsravd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0x0a], "vpsravd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0x4a, 0x01], "vpsravd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x46, 0x0a], "vpsravq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x46, 0x4a, 0x01], "vpsravq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x46, 0x0a], "vpsravq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x46, 0x4a, 0x01], "vpsravq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0xca], "vpsravq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0xca], "vpsravq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0xca], "vpsravq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0x0a], "vpsravq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0x4a, 0x01], "vpsravq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0xca], "vpsravq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0xca], "vpsravq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0xca], "vpsravq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0x0a], "vpsravq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0x4a, 0x01], "vpsravq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x46, 0x0a], "vpsravd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x46, 0x4a, 0x01], "vpsravd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x46, 0x0a], "vpsravd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x46, 0x4a, 0x01], "vpsravd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0xca], "vpsravd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0xca], "vpsravd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0xca], "vpsravd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0x0a], "vpsravd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0x4a, 0x01], "vpsravd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0xca], "vpsravd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0xca], "vpsravd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0xca], "vpsravd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0x0a], "vpsravd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0x4a, 0x01], "vpsravd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x47, 0x0a], "vpsllvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x47, 0x4a, 0x01], "vpsllvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0xca], "vpsllvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0xca], "vpsllvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0xca], "vpsllvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0x0a], "vpsllvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0x4a, 0x01], "vpsllvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x47, 0x0a], "vpsllvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x47, 0x4a, 0x01], "vpsllvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0xca], "vpsllvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0xca], "vpsllvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0xca], "vpsllvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0x0a], "vpsllvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0x4a, 0x01], "vpsllvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x47, 0x0a], "vpsllvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x47, 0x4a, 0x01], "vpsllvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x47, 0x0a], "vpsllvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x47, 0x4a, 0x01], "vpsllvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0xca], "vpsllvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0xca], "vpsllvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0xca], "vpsllvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0x0a], "vpsllvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0x4a, 0x01], "vpsllvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0xca], "vpsllvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0xca], "vpsllvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0xca], "vpsllvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0x0a], "vpsllvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0x4a, 0x01], "vpsllvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x47, 0x0a], "vpsllvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x47, 0x4a, 0x01], "vpsllvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x47, 0x0a], "vpsllvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x47, 0x4a, 0x01], "vpsllvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0xca], "vpsllvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0xca], "vpsllvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0xca], "vpsllvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0x0a], "vpsllvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0x4a, 0x01], "vpsllvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0xca], "vpsllvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0xca], "vpsllvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0xca], "vpsllvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0x0a], "vpsllvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0x4a, 0x01], "vpsllvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4c, 0x0a], "vrcp14pd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0xca], "vrcp14pd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0xca], "vrcp14pd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0xca], "vrcp14pd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0x0a], "vrcp14pd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4c, 0x0a], "vrcp14ps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0xca], "vrcp14ps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0xca], "vrcp14ps ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0xca], "vrcp14ps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0x0a], "vrcp14ps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4c, 0x0a], "vrcp14pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4c, 0x0a], "vrcp14pd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0xca], "vrcp14pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0xca], "vrcp14pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0xca], "vrcp14pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0x0a], "vrcp14pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0xca], "vrcp14pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0xca], "vrcp14pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0xca], "vrcp14pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0x0a], "vrcp14pd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4c, 0x0a], "vrcp14ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4c, 0x0a], "vrcp14ps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0xca], "vrcp14ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0xca], "vrcp14ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0xca], "vrcp14ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0x0a], "vrcp14ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0xca], "vrcp14ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0xca], "vrcp14ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0xca], "vrcp14ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0x0a], "vrcp14ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0xca], "vrcp14sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0x0a], "vrcp14sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0xca], "vrcp14sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0xca], "vrcp14sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0x0a], "vrcp14sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0x0a], "vrcp14sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0xca], "vrcp14ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x0a], "vrcp14ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0xca], "vrcp14ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0xca], "vrcp14ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x0a], "vrcp14ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x0a], "vrcp14ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4e, 0x0a], "vrsqrt14pd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0xca], "vrsqrt14pd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0x0a], "vrsqrt14pd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4e, 0x0a], "vrsqrt14ps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0xca], "vrsqrt14ps ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x0a], "vrsqrt14ps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4e, 0x0a], "vrsqrt14pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4e, 0x0a], "vrsqrt14pd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0xca], "vrsqrt14pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0x0a], "vrsqrt14pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0xca], "vrsqrt14pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0x0a], "vrsqrt14pd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4e, 0x0a], "vrsqrt14ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4e, 0x0a], "vrsqrt14ps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0xca], "vrsqrt14ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0x0a], "vrsqrt14ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0xca], "vrsqrt14ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0x0a], "vrsqrt14ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0xca], "vrsqrt14sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0x0a], "vrsqrt14sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0xca], "vrsqrt14ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x0a], "vrsqrt14ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x50, 0x4a, 0x01], "vpdpbusd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0xca], "vpdpbusd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0xca], "vpdpbusd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0xca], "vpdpbusd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0x4a, 0x01], "vpdpbusd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x50, 0x4a, 0x01], "vpdpbusd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x50, 0x4a, 0x01], "vpdpbusd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0xca], "vpdpbusd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0xca], "vpdpbusd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0xca], "vpdpbusd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0x4a, 0x01], "vpdpbusd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0xca], "vpdpbusd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0xca], "vpdpbusd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0xca], "vpdpbusd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0x4a, 0x01], "vpdpbusd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x51, 0x4a, 0x01], "vpdpbusds ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0xca], "vpdpbusds ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0xca], "vpdpbusds ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0xca], "vpdpbusds ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0x4a, 0x01], "vpdpbusds ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x51, 0x4a, 0x01], "vpdpbusds zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x51, 0x4a, 0x01], "vpdpbusds xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0xca], "vpdpbusds zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0xca], "vpdpbusds zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0xca], "vpdpbusds zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0x4a, 0x01], "vpdpbusds zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0xca], "vpdpbusds xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0xca], "vpdpbusds xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0xca], "vpdpbusds xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0x4a, 0x01], "vpdpbusds xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x52, 0x4a, 0x01], "vpdpwssd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0xca], "vpdpwssd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0xca], "vpdpwssd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0xca], "vpdpwssd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0x4a, 0x01], "vpdpwssd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x52, 0x4a, 0x01], "vpdpwssd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x52, 0x4a, 0x01], "vpdpwssd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0xca], "vpdpwssd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0xca], "vpdpwssd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0xca], "vpdpwssd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0x4a, 0x01], "vpdpwssd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0xca], "vpdpwssd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0xca], "vpdpwssd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0xca], "vpdpwssd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0x4a, 0x01], "vpdpwssd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x53, 0x4a, 0x01], "vpdpwssds ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0xca], "vpdpwssds ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0xca], "vpdpwssds ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0xca], "vpdpwssds ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0x4a, 0x01], "vpdpwssds ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x53, 0x4a, 0x01], "vpdpwssds zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x53, 0x4a, 0x01], "vpdpwssds xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0xca], "vpdpwssds zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0xca], "vpdpwssds zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0xca], "vpdpwssds zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0x4a, 0x01], "vpdpwssds zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0xca], "vpdpwssds xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0xca], "vpdpwssds xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0xca], "vpdpwssds xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0x4a, 0x01], "vpdpwssds xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0xca], "vpopcntw ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0x0a], "vpopcntw ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0x4a, 0x01], "vpopcntw ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0xca], "vpopcntw ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0xca], "vpopcntw ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0x0a], "vpopcntw ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0x0a], "vpopcntw ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0x4a, 0x01], "vpopcntw ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0x4a, 0x01], "vpopcntw ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0xca], "vpopcntb ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0x0a], "vpopcntb ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0x4a, 0x01], "vpopcntb ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0xca], "vpopcntb ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0xca], "vpopcntb ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0x0a], "vpopcntb ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0x0a], "vpopcntb ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0x4a, 0x01], "vpopcntb ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0x4a, 0x01], "vpopcntb ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0xca], "vpopcntw zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0x0a], "vpopcntw zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0x4a, 0x01], "vpopcntw zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0xca], "vpopcntw zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0xca], "vpopcntw zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0x0a], "vpopcntw zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0x0a], "vpopcntw zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0x4a, 0x01], "vpopcntw zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0x4a, 0x01], "vpopcntw zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0xca], "vpopcntw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0x0a], "vpopcntw xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0x4a, 0x01], "vpopcntw xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0xca], "vpopcntw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0xca], "vpopcntw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0x0a], "vpopcntw xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0x0a], "vpopcntw xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0x4a, 0x01], "vpopcntw xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0x4a, 0x01], "vpopcntw xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0xca], "vpopcntb zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0x0a], "vpopcntb zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0x4a, 0x01], "vpopcntb zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0xca], "vpopcntb zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0xca], "vpopcntb zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0x0a], "vpopcntb zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0x0a], "vpopcntb zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0x4a, 0x01], "vpopcntb zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0x4a, 0x01], "vpopcntb zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0xca], "vpopcntb xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0x0a], "vpopcntb xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0x4a, 0x01], "vpopcntb xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0xca], "vpopcntb xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0xca], "vpopcntb xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0x0a], "vpopcntb xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0x0a], "vpopcntb xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0x4a, 0x01], "vpopcntb xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0x4a, 0x01], "vpopcntb xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x55, 0x0a], "vpopcntq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x55, 0x0a], "vpopcntq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x55, 0x4a, 0x01], "vpopcntq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0xca], "vpopcntq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0xca], "vpopcntq ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0xca], "vpopcntq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0x0a], "vpopcntq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0x0a], "vpopcntq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0x4a, 0x01], "vpopcntq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x55, 0x0a], "vpopcntd ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x55, 0x0a], "vpopcntd ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x55, 0x4a, 0x01], "vpopcntd ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0xca], "vpopcntd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0xca], "vpopcntd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0xca], "vpopcntd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0x0a], "vpopcntd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0x0a], "vpopcntd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0x4a, 0x01], "vpopcntd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x55, 0x0a], "vpopcntq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x55, 0x0a], "vpopcntq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x55, 0x4a, 0x01], "vpopcntq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x55, 0x0a], "vpopcntq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x55, 0x0a], "vpopcntq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x55, 0x4a, 0x01], "vpopcntq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0xca], "vpopcntq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0xca], "vpopcntq zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0xca], "vpopcntq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0x0a], "vpopcntq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0x0a], "vpopcntq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0x4a, 0x01], "vpopcntq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0xca], "vpopcntq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0xca], "vpopcntq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0xca], "vpopcntq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0x0a], "vpopcntq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0x0a], "vpopcntq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0x4a, 0x01], "vpopcntq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x55, 0x0a], "vpopcntd zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x55, 0x0a], "vpopcntd zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x55, 0x4a, 0x01], "vpopcntd zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x55, 0x0a], "vpopcntd xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x55, 0x0a], "vpopcntd xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x55, 0x4a, 0x01], "vpopcntd xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0xca], "vpopcntd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0xca], "vpopcntd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0xca], "vpopcntd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0x0a], "vpopcntd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0x0a], "vpopcntd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0x4a, 0x01], "vpopcntd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0xca], "vpopcntd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0xca], "vpopcntd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0xca], "vpopcntd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0x0a], "vpopcntd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0x0a], "vpopcntd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0x4a, 0x01], "vpopcntd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0xca], "vpbroadcastd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0x0a], "vpbroadcastd ymm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0xca], "vpbroadcastd ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0xca], "vpbroadcastd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0x0a], "vpbroadcastd ymm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0x0a], "vpbroadcastd ymm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0xca], "vpbroadcastd zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0x0a], "vpbroadcastd zmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0xca], "vpbroadcastd zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0xca], "vpbroadcastd zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0x0a], "vpbroadcastd zmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0x0a], "vpbroadcastd zmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0xca], "vpbroadcastd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0xca], "vpbroadcastd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0xca], "vpbroadcastd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0x0a], "vpbroadcastd xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0xca], "vpbroadcastq ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0x0a], "vpbroadcastq ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0xca], "vpbroadcastq ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0xca], "vpbroadcastq ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0x0a], "vpbroadcastq ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0x0a], "vpbroadcastq ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0xca], "vbroadcasti32x2 ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0x0a], "vbroadcasti32x2 ymm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0xca], "vpbroadcastq zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0x0a], "vpbroadcastq zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0xca], "vpbroadcastq zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0xca], "vpbroadcastq zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0x0a], "vpbroadcastq zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0x0a], "vpbroadcastq zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0xca], "vpbroadcastq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0xca], "vpbroadcastq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0xca], "vpbroadcastq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0x0a], "vpbroadcastq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0xca], "vbroadcasti32x2 zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0x0a], "vbroadcasti32x2 zmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0xca], "vbroadcasti32x2 xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0x0a], "vbroadcasti32x2 xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x5a, 0x0a], "vbroadcasti64x2 ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x5a, 0x0a], "vbroadcasti32x4 ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x0a], "vbroadcasti64x2 zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x0a], "vbroadcasti32x4 zmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x0a], "vbroadcasti64x4 zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x0a], "vbroadcasti32x8 zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0xca], "vpexpandw ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0x0a], "vpexpandw ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0x4a, 0x01], "vpexpandw ymm1{k5}{z}, ymmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0xca], "vpexpandw ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0xca], "vpexpandw ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0x0a], "vpexpandw ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0x0a], "vpexpandw ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0x4a, 0x01], "vpexpandw ymm1, ymmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0x4a, 0x01], "vpexpandw ymm1{k5}, ymmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0xca], "vpexpandb ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0x0a], "vpexpandb ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0x4a, 0x01], "vpexpandb ymm1{k5}{z}, ymmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0xca], "vpexpandb ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0xca], "vpexpandb ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0x0a], "vpexpandb ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0x0a], "vpexpandb ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0x4a, 0x01], "vpexpandb ymm1, ymmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0x4a, 0x01], "vpexpandb ymm1{k5}, ymmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0xca], "vpexpandw zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0x0a], "vpexpandw zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0x4a, 0x01], "vpexpandw zmm1{k5}{z}, zmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0xca], "vpexpandw zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0xca], "vpexpandw zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0x0a], "vpexpandw zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0x0a], "vpexpandw zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0x4a, 0x01], "vpexpandw zmm1, zmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0x4a, 0x01], "vpexpandw zmm1{k5}, zmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0xca], "vpexpandw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0x0a], "vpexpandw xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0x4a, 0x01], "vpexpandw xmm1{k5}{z}, xmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0xca], "vpexpandw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0xca], "vpexpandw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0x0a], "vpexpandw xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0x0a], "vpexpandw xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0x4a, 0x01], "vpexpandw xmm1, xmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0x4a, 0x01], "vpexpandw xmm1{k5}, xmmword [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0xca], "vpexpandb zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0x0a], "vpexpandb zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0x4a, 0x01], "vpexpandb zmm1{k5}{z}, zmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0xca], "vpexpandb zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0xca], "vpexpandb zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0x0a], "vpexpandb zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0x0a], "vpexpandb zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0x4a, 0x01], "vpexpandb zmm1, zmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0x4a, 0x01], "vpexpandb zmm1{k5}, zmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0xca], "vpexpandb xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0x0a], "vpexpandb xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0x4a, 0x01], "vpexpandb xmm1{k5}{z}, xmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0xca], "vpexpandb xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0xca], "vpexpandb xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0x0a], "vpexpandb xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0x0a], "vpexpandb xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0x4a, 0x01], "vpexpandb xmm1, xmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0x4a, 0x01], "vpexpandb xmm1{k5}, xmmword [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x63, 0xca], "vpcompressw ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca], "vpcompressw ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0xca], "vpcompressw ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0x0a], "vpcompressw ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0x0a], "vpcompressw ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0x4a, 0x01], "vpcompressw ymmword [edx + 0x2], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0x4a, 0x01], "vpcompressw ymmword [edx + 0x2]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0xca], "vpcompressb ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca], "vpcompressb ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0xca], "vpcompressb ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x0a], "vpcompressb ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x0a], "vpcompressb ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x4a, 0x01], "vpcompressb ymmword [edx + 0x1], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x4a, 0x01], "vpcompressb ymmword [edx + 0x1]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x63, 0xca], "vpcompressw zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca], "vpcompressw zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0xca], "vpcompressw zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0x0a], "vpcompressw zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0x0a], "vpcompressw zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0x4a, 0x01], "vpcompressw zmmword [edx + 0x2], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0x4a, 0x01], "vpcompressw zmmword [edx + 0x2]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x63, 0xca], "vpcompressw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca], "vpcompressw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0xca], "vpcompressw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0x0a], "vpcompressw xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0x0a], "vpcompressw xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0x4a, 0x01], "vpcompressw xmmword [edx + 0x2], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0x4a, 0x01], "vpcompressw xmmword [edx + 0x2]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x63, 0xca], "vpcompressb zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca], "vpcompressb zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0xca], "vpcompressb zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0x0a], "vpcompressb zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0x0a], "vpcompressb zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0x4a, 0x01], "vpcompressb zmmword [edx + 0x1], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0x4a, 0x01], "vpcompressb zmmword [edx + 0x1]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x63, 0xca], "vpcompressb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca], "vpcompressb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0xca], "vpcompressb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0x0a], "vpcompressb xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0x0a], "vpcompressb xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0x4a, 0x01], "vpcompressb xmmword [edx + 0x1], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0x4a, 0x01], "vpcompressb xmmword [edx + 0x1]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x64, 0x0a], "vpblendmq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x64, 0x4a, 0x01], "vpblendmq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0xca], "vpblendmq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0xca], "vpblendmq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0xca], "vpblendmq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0x0a], "vpblendmq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0x4a, 0x01], "vpblendmq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x64, 0x0a], "vpblendmd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x64, 0x4a, 0x01], "vpblendmd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0xca], "vpblendmd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0xca], "vpblendmd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0xca], "vpblendmd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0x0a], "vpblendmd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0x4a, 0x01], "vpblendmd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x64, 0x0a], "vpblendmq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x64, 0x4a, 0x01], "vpblendmq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x64, 0x0a], "vpblendmq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x64, 0x4a, 0x01], "vpblendmq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0xca], "vpblendmq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0xca], "vpblendmq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0xca], "vpblendmq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0x0a], "vpblendmq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0x4a, 0x01], "vpblendmq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0xca], "vpblendmq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0xca], "vpblendmq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0xca], "vpblendmq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0x0a], "vpblendmq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0x4a, 0x01], "vpblendmq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x64, 0x0a], "vpblendmd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x64, 0x4a, 0x01], "vpblendmd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x64, 0x0a], "vpblendmd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x64, 0x4a, 0x01], "vpblendmd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0xca], "vpblendmd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0xca], "vpblendmd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0xca], "vpblendmd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0x0a], "vpblendmd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0x4a, 0x01], "vpblendmd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0xca], "vpblendmd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0xca], "vpblendmd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0xca], "vpblendmd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0x0a], "vpblendmd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0x4a, 0x01], "vpblendmd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x65, 0x0a], "vblendmpd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x65, 0x4a, 0x01], "vblendmpd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0xca], "vblendmpd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0xca], "vblendmpd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0xca], "vblendmpd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0x0a], "vblendmpd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0x4a, 0x01], "vblendmpd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x65, 0x0a], "vblendmps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x65, 0x4a, 0x01], "vblendmps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0xca], "vblendmps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0xca], "vblendmps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0xca], "vblendmps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0x0a], "vblendmps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0x4a, 0x01], "vblendmps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x65, 0x0a], "vblendmpd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x65, 0x4a, 0x01], "vblendmpd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x65, 0x0a], "vblendmpd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x65, 0x4a, 0x01], "vblendmpd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0xca], "vblendmpd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0xca], "vblendmpd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0xca], "vblendmpd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0x0a], "vblendmpd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0x4a, 0x01], "vblendmpd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0xca], "vblendmpd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0xca], "vblendmpd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0xca], "vblendmpd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0x0a], "vblendmpd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0x4a, 0x01], "vblendmpd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x65, 0x0a], "vblendmps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x65, 0x4a, 0x01], "vblendmps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x65, 0x0a], "vblendmps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x65, 0x4a, 0x01], "vblendmps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0xca], "vblendmps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0xca], "vblendmps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0xca], "vblendmps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0x0a], "vblendmps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0x4a, 0x01], "vblendmps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0xca], "vblendmps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0xca], "vblendmps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0xca], "vblendmps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0x0a], "vblendmps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0x4a, 0x01], "vblendmps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0xca], "vpblendmw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0x0a], "vpblendmw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0x4a, 0x01], "vpblendmw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0xca], "vpblendmw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0xca], "vpblendmw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0x0a], "vpblendmw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0x0a], "vpblendmw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0x4a, 0x01], "vpblendmw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0x4a, 0x01], "vpblendmw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0xca], "vpblendmb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0x0a], "vpblendmb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0x4a, 0x01], "vpblendmb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0xca], "vpblendmb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0xca], "vpblendmb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0x0a], "vpblendmb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0x0a], "vpblendmb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0x4a, 0x01], "vpblendmb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0x4a, 0x01], "vpblendmb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0xca], "vpblendmw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0x0a], "vpblendmw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0x4a, 0x01], "vpblendmw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0xca], "vpblendmw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0xca], "vpblendmw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0x0a], "vpblendmw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0x0a], "vpblendmw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0x4a, 0x01], "vpblendmw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0x4a, 0x01], "vpblendmw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0xca], "vpblendmw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0x0a], "vpblendmw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0x4a, 0x01], "vpblendmw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0xca], "vpblendmw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0xca], "vpblendmw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0x0a], "vpblendmw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0x0a], "vpblendmw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0x4a, 0x01], "vpblendmw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0x4a, 0x01], "vpblendmw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0xca], "vpblendmb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0x0a], "vpblendmb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0x4a, 0x01], "vpblendmb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0xca], "vpblendmb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0xca], "vpblendmb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0x0a], "vpblendmb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0x0a], "vpblendmb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0x4a, 0x01], "vpblendmb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0x4a, 0x01], "vpblendmb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0xca], "vpblendmb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0x0a], "vpblendmb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0x4a, 0x01], "vpblendmb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0xca], "vpblendmb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0xca], "vpblendmb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0x0a], "vpblendmb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0x0a], "vpblendmb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0x4a, 0x01], "vpblendmb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0x4a, 0x01], "vpblendmb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0xca], "vpshldvw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0x0a], "vpshldvw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0x4a, 0x01], "vpshldvw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0xca], "vpshldvw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0xca], "vpshldvw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0x0a], "vpshldvw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0x0a], "vpshldvw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0x4a, 0x01], "vpshldvw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0x4a, 0x01], "vpshldvw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0xca], "vpshldvw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0x0a], "vpshldvw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0x4a, 0x01], "vpshldvw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0xca], "vpshldvw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0xca], "vpshldvw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0x0a], "vpshldvw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0x0a], "vpshldvw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0x4a, 0x01], "vpshldvw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0x4a, 0x01], "vpshldvw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0xca], "vpshldvw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0x0a], "vpshldvw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0x4a, 0x01], "vpshldvw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0xca], "vpshldvw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0xca], "vpshldvw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0x0a], "vpshldvw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0x0a], "vpshldvw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0x4a, 0x01], "vpshldvw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0x4a, 0x01], "vpshldvw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x71, 0x0a], "vpshldvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x71, 0x4a, 0x01], "vpshldvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0xca], "vpshldvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0xca], "vpshldvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0xca], "vpshldvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0x0a], "vpshldvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0x4a, 0x01], "vpshldvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x71, 0x0a], "vpshldvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x71, 0x4a, 0x01], "vpshldvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0xca], "vpshldvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0xca], "vpshldvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0xca], "vpshldvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0x0a], "vpshldvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0x4a, 0x01], "vpshldvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x71, 0x0a], "vpshldvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x71, 0x4a, 0x01], "vpshldvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x71, 0x0a], "vpshldvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x71, 0x4a, 0x01], "vpshldvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0xca], "vpshldvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0xca], "vpshldvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0xca], "vpshldvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0x0a], "vpshldvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0x4a, 0x01], "vpshldvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0xca], "vpshldvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0xca], "vpshldvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0xca], "vpshldvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0x0a], "vpshldvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0x4a, 0x01], "vpshldvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x71, 0x0a], "vpshldvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x71, 0x4a, 0x01], "vpshldvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x71, 0x0a], "vpshldvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x71, 0x4a, 0x01], "vpshldvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0xca], "vpshldvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0xca], "vpshldvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0xca], "vpshldvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0x0a], "vpshldvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0x4a, 0x01], "vpshldvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0xca], "vpshldvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0xca], "vpshldvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0xca], "vpshldvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0x0a], "vpshldvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0x4a, 0x01], "vpshldvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0xca], "vpshrdvw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0x0a], "vpshrdvw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0x4a, 0x01], "vpshrdvw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0xca], "vpshrdvw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0xca], "vpshrdvw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0x0a], "vpshrdvw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0x0a], "vpshrdvw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0x4a, 0x01], "vpshrdvw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0x4a, 0x01], "vpshrdvw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0xca], "vpshrdvw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0x0a], "vpshrdvw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0x4a, 0x01], "vpshrdvw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0xca], "vpshrdvw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0xca], "vpshrdvw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0x0a], "vpshrdvw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0x0a], "vpshrdvw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0x4a, 0x01], "vpshrdvw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0x4a, 0x01], "vpshrdvw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0xca], "vpshrdvw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0x0a], "vpshrdvw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0x4a, 0x01], "vpshrdvw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0xca], "vpshrdvw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0xca], "vpshrdvw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0x0a], "vpshrdvw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0x0a], "vpshrdvw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0x4a, 0x01], "vpshrdvw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0x4a, 0x01], "vpshrdvw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x73, 0x4a, 0x01], "vpshrdvq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0xca], "vpshrdvq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0xca], "vpshrdvq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0xca], "vpshrdvq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0x4a, 0x01], "vpshrdvq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x73, 0x4a, 0x01], "vpshrdvd ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0xca], "vpshrdvd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0xca], "vpshrdvd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0xca], "vpshrdvd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0x4a, 0x01], "vpshrdvd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x73, 0x4a, 0x01], "vpshrdvq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x73, 0x4a, 0x01], "vpshrdvq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0xca], "vpshrdvq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0xca], "vpshrdvq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0xca], "vpshrdvq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0x4a, 0x01], "vpshrdvq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0xca], "vpshrdvq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0xca], "vpshrdvq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0xca], "vpshrdvq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0x4a, 0x01], "vpshrdvq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x73, 0x4a, 0x01], "vpshrdvd zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x73, 0x4a, 0x01], "vpshrdvd xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0xca], "vpshrdvd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0xca], "vpshrdvd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0xca], "vpshrdvd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0x4a, 0x01], "vpshrdvd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0xca], "vpshrdvd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0xca], "vpshrdvd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0xca], "vpshrdvd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0x4a, 0x01], "vpshrdvd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0xca], "vpermi2w ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0x0a], "vpermi2w ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0x4a, 0x01], "vpermi2w ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0xca], "vpermi2w ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0xca], "vpermi2w ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0x0a], "vpermi2w ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0x0a], "vpermi2w ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0x4a, 0x01], "vpermi2w ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0x4a, 0x01], "vpermi2w ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0xca], "vpermi2b ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0x0a], "vpermi2b ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0x4a, 0x01], "vpermi2b ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0xca], "vpermi2b ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0xca], "vpermi2b ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0x0a], "vpermi2b ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0x0a], "vpermi2b ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0x4a, 0x01], "vpermi2b ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0x4a, 0x01], "vpermi2b ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0xca], "vpermi2w zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0x0a], "vpermi2w zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0x4a, 0x01], "vpermi2w zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0xca], "vpermi2w zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0xca], "vpermi2w zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0x0a], "vpermi2w zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0x0a], "vpermi2w zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0x4a, 0x01], "vpermi2w zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0x4a, 0x01], "vpermi2w zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0xca], "vpermi2w xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0x0a], "vpermi2w xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0x4a, 0x01], "vpermi2w xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0xca], "vpermi2w xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0xca], "vpermi2w xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0x0a], "vpermi2w xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0x0a], "vpermi2w xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0x4a, 0x01], "vpermi2w xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0x4a, 0x01], "vpermi2w xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0xca], "vpermi2b zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0x0a], "vpermi2b zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0x4a, 0x01], "vpermi2b zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0xca], "vpermi2b zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0xca], "vpermi2b zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0x0a], "vpermi2b zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0x0a], "vpermi2b zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0x4a, 0x01], "vpermi2b zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0x4a, 0x01], "vpermi2b zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0xca], "vpermi2b xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0x0a], "vpermi2b xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0x4a, 0x01], "vpermi2b xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0xca], "vpermi2b xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0xca], "vpermi2b xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0x0a], "vpermi2b xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0x0a], "vpermi2b xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0x4a, 0x01], "vpermi2b xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0x4a, 0x01], "vpermi2b xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x76, 0x0a], "vpermi2q ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x76, 0x4a, 0x01], "vpermi2q ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0xca], "vpermi2q ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0xca], "vpermi2q ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0xca], "vpermi2q ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0x0a], "vpermi2q ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0x4a, 0x01], "vpermi2q ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x76, 0x0a], "vpermi2d ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x76, 0x4a, 0x01], "vpermi2d ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0xca], "vpermi2d ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0xca], "vpermi2d ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0xca], "vpermi2d ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0x0a], "vpermi2d ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0x4a, 0x01], "vpermi2d ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x76, 0x0a], "vpermi2q zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x76, 0x4a, 0x01], "vpermi2q zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x76, 0x0a], "vpermi2q xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x76, 0x4a, 0x01], "vpermi2q xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0xca], "vpermi2q zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0xca], "vpermi2q zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0xca], "vpermi2q zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0x0a], "vpermi2q zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0x4a, 0x01], "vpermi2q zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0xca], "vpermi2q xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0xca], "vpermi2q xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0xca], "vpermi2q xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0x0a], "vpermi2q xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0x4a, 0x01], "vpermi2q xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x76, 0x0a], "vpermi2d zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x76, 0x4a, 0x01], "vpermi2d zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x76, 0x0a], "vpermi2d xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x76, 0x4a, 0x01], "vpermi2d xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0xca], "vpermi2d zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0xca], "vpermi2d zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0xca], "vpermi2d zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0x0a], "vpermi2d zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0x4a, 0x01], "vpermi2d zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0xca], "vpermi2d xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0xca], "vpermi2d xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0xca], "vpermi2d xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0x0a], "vpermi2d xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0x4a, 0x01], "vpermi2d xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x77, 0x4a, 0x01], "vpermi2pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0xca], "vpermi2pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0xca], "vpermi2pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0xca], "vpermi2pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0x4a, 0x01], "vpermi2pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x77, 0x4a, 0x01], "vpermi2ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0xca], "vpermi2ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0xca], "vpermi2ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0xca], "vpermi2ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0x4a, 0x01], "vpermi2ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x77, 0x4a, 0x01], "vpermi2pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x77, 0x4a, 0x01], "vpermi2pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0xca], "vpermi2pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0xca], "vpermi2pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0xca], "vpermi2pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0x4a, 0x01], "vpermi2pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0xca], "vpermi2pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0xca], "vpermi2pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0xca], "vpermi2pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0x4a, 0x01], "vpermi2pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x77, 0x4a, 0x01], "vpermi2ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x77, 0x4a, 0x01], "vpermi2ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0xca], "vpermi2ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0xca], "vpermi2ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0xca], "vpermi2ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0x4a, 0x01], "vpermi2ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0xca], "vpermi2ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0xca], "vpermi2ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0xca], "vpermi2ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0x4a, 0x01], "vpermi2ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0xca], "vpbroadcastb ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x0a], "vpbroadcastb ymm1{k5}{z}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1{k5}{z}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0xca], "vpbroadcastb ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0xca], "vpbroadcastb ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x0a], "vpbroadcastb ymm1, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x0a], "vpbroadcastb ymm1{k5}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1{k5}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0xca], "vpbroadcastb zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0x0a], "vpbroadcastb zmm1{k5}{z}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1{k5}{z}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0xca], "vpbroadcastb zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0xca], "vpbroadcastb zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0x0a], "vpbroadcastb zmm1, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0x0a], "vpbroadcastb zmm1{k5}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1{k5}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0xca], "vpbroadcastb xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}{z}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1{k5}{z}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0xca], "vpbroadcastb xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0xca], "vpbroadcastb xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0x0a], "vpbroadcastb xmm1, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}, byte [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1{k5}, byte [edx + 0x1]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0xca], "vpbroadcastw ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0x0a], "vpbroadcastw ymm1{k5}{z}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1{k5}{z}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0xca], "vpbroadcastw ymm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0xca], "vpbroadcastw ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0x0a], "vpbroadcastw ymm1, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0x0a], "vpbroadcastw ymm1{k5}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1{k5}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0xca], "vpbroadcastw zmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0x0a], "vpbroadcastw zmm1{k5}{z}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1{k5}{z}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0xca], "vpbroadcastw zmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0xca], "vpbroadcastw zmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0x0a], "vpbroadcastw zmm1, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0x0a], "vpbroadcastw zmm1{k5}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1{k5}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0xca], "vpbroadcastw xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}{z}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1{k5}{z}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0xca], "vpbroadcastw xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0xca], "vpbroadcastw xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0x0a], "vpbroadcastw xmm1, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}, word [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1{k5}, word [edx + 0x2]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7a, 0xca], "vpbroadcastb ymm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7a, 0xca], "vpbroadcastb ymm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7a, 0xca], "vpbroadcastb ymm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7a, 0xca], "vpbroadcastb zmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7a, 0xca], "vpbroadcastb zmm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7a, 0xca], "vpbroadcastb zmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7a, 0xca], "vpbroadcastb xmm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7b, 0xca], "vpbroadcastw ymm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7b, 0xca], "vpbroadcastw ymm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7b, 0xca], "vpbroadcastw ymm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7b, 0xca], "vpbroadcastw zmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7b, 0xca], "vpbroadcastw zmm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7b, 0xca], "vpbroadcastw zmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7b, 0xca], "vpbroadcastw xmm1, edx"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7c, 0xca], "vpbroadcastd ymm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7c, 0xca], "vpbroadcastd ymm1, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7c, 0xca], "vpbroadcastd ymm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7c, 0xca], "vpbroadcastd zmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7c, 0xca], "vpbroadcastd zmm1, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7c, 0xca], "vpbroadcastd zmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}{z}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7c, 0xca], "vpbroadcastd xmm1, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}, edx"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0xca], "vpermt2w ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0x0a], "vpermt2w ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0x4a, 0x01], "vpermt2w ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0xca], "vpermt2w ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0xca], "vpermt2w ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0x0a], "vpermt2w ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0x0a], "vpermt2w ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0x4a, 0x01], "vpermt2w ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0x4a, 0x01], "vpermt2w ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0xca], "vpermt2b ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0x0a], "vpermt2b ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0x4a, 0x01], "vpermt2b ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0xca], "vpermt2b ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0xca], "vpermt2b ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0x0a], "vpermt2b ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0x0a], "vpermt2b ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0x4a, 0x01], "vpermt2b ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0x4a, 0x01], "vpermt2b ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0xca], "vpermt2w zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0x0a], "vpermt2w zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0x4a, 0x01], "vpermt2w zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0xca], "vpermt2w zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0xca], "vpermt2w zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0x0a], "vpermt2w zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0x0a], "vpermt2w zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0x4a, 0x01], "vpermt2w zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0x4a, 0x01], "vpermt2w zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0xca], "vpermt2w xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0x0a], "vpermt2w xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0x4a, 0x01], "vpermt2w xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0xca], "vpermt2w xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0xca], "vpermt2w xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0x0a], "vpermt2w xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0x0a], "vpermt2w xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0x4a, 0x01], "vpermt2w xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0x4a, 0x01], "vpermt2w xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0xca], "vpermt2b zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0x0a], "vpermt2b zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0x4a, 0x01], "vpermt2b zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0xca], "vpermt2b zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0xca], "vpermt2b zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0x0a], "vpermt2b zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0x0a], "vpermt2b zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0x4a, 0x01], "vpermt2b zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0x4a, 0x01], "vpermt2b zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0xca], "vpermt2b xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0x0a], "vpermt2b xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0x4a, 0x01], "vpermt2b xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0xca], "vpermt2b xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0xca], "vpermt2b xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0x0a], "vpermt2b xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0x0a], "vpermt2b xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0x4a, 0x01], "vpermt2b xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0x4a, 0x01], "vpermt2b xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7e, 0x4a, 0x01], "vpermt2q ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0xca], "vpermt2q ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0xca], "vpermt2q ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0xca], "vpermt2q ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0x4a, 0x01], "vpermt2q ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7e, 0x4a, 0x01], "vpermt2d ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0xca], "vpermt2d ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0xca], "vpermt2d ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0xca], "vpermt2d ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0x4a, 0x01], "vpermt2d ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7e, 0x4a, 0x01], "vpermt2q zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7e, 0x4a, 0x01], "vpermt2q xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0xca], "vpermt2q zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0xca], "vpermt2q zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0xca], "vpermt2q zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0x4a, 0x01], "vpermt2q zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0xca], "vpermt2q xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0xca], "vpermt2q xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0xca], "vpermt2q xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0x4a, 0x01], "vpermt2q xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7e, 0x4a, 0x01], "vpermt2d zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7e, 0x4a, 0x01], "vpermt2d xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0xca], "vpermt2d zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0xca], "vpermt2d zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0xca], "vpermt2d zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0x4a, 0x01], "vpermt2d zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0xca], "vpermt2d xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0xca], "vpermt2d xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0xca], "vpermt2d xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0x4a, 0x01], "vpermt2d xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0xca], "vpermt2pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0xca], "vpermt2pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0xca], "vpermt2pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0xca], "vpermt2ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0xca], "vpermt2ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0xca], "vpermt2ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0xca], "vpermt2pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0xca], "vpermt2pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0xca], "vpermt2pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0xca], "vpermt2pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0xca], "vpermt2pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0xca], "vpermt2pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0xca], "vpermt2ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0xca], "vpermt2ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0xca], "vpermt2ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0xca], "vpermt2ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0xca], "vpermt2ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0xca], "vpermt2ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0xca], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0xca], "vpmultishiftqb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0xca], "vpmultishiftqb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0xca], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0xca], "vpmultishiftqb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0xca], "vpmultishiftqb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0xca], "vpmultishiftqb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0xca], "vexpandpd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0x0a], "vexpandpd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0x4a, 0x01], "vexpandpd ymm1{k5}{z}, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0xca], "vexpandpd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0xca], "vexpandpd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0x0a], "vexpandpd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0x0a], "vexpandpd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0x4a, 0x01], "vexpandpd ymm1, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0x4a, 0x01], "vexpandpd ymm1{k5}, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0xca], "vexpandps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0x0a], "vexpandps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0x4a, 0x01], "vexpandps ymm1{k5}{z}, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0xca], "vexpandps ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0xca], "vexpandps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0x0a], "vexpandps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0x0a], "vexpandps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0x4a, 0x01], "vexpandps ymm1, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0x4a, 0x01], "vexpandps ymm1{k5}, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0xca], "vexpandpd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0x0a], "vexpandpd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0x4a, 0x01], "vexpandpd zmm1{k5}{z}, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0xca], "vexpandpd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0xca], "vexpandpd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0x0a], "vexpandpd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0x0a], "vexpandpd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0x4a, 0x01], "vexpandpd zmm1, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0x4a, 0x01], "vexpandpd zmm1{k5}, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0xca], "vexpandpd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0x0a], "vexpandpd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0x4a, 0x01], "vexpandpd xmm1{k5}{z}, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0xca], "vexpandpd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0xca], "vexpandpd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0x0a], "vexpandpd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0x0a], "vexpandpd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0x4a, 0x01], "vexpandpd xmm1, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0x4a, 0x01], "vexpandpd xmm1{k5}, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0xca], "vexpandps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0x0a], "vexpandps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0x4a, 0x01], "vexpandps zmm1{k5}{z}, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0xca], "vexpandps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0xca], "vexpandps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0x0a], "vexpandps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0x0a], "vexpandps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0x4a, 0x01], "vexpandps zmm1, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0x4a, 0x01], "vexpandps zmm1{k5}, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0xca], "vexpandps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0x0a], "vexpandps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0x4a, 0x01], "vexpandps xmm1{k5}{z}, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0xca], "vexpandps xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0xca], "vexpandps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0x0a], "vexpandps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0x0a], "vexpandps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0x4a, 0x01], "vexpandps xmm1, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0x4a, 0x01], "vexpandps xmm1{k5}, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0xca], "vpexpandq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0x0a], "vpexpandq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0x4a, 0x01], "vpexpandq ymm1{k5}{z}, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0xca], "vpexpandq ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0xca], "vpexpandq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0x0a], "vpexpandq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0x0a], "vpexpandq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0x4a, 0x01], "vpexpandq ymm1, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0x4a, 0x01], "vpexpandq ymm1{k5}, ymmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0xca], "vpexpandd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0x0a], "vpexpandd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0x4a, 0x01], "vpexpandd ymm1{k5}{z}, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0xca], "vpexpandd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0xca], "vpexpandd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0x0a], "vpexpandd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0x0a], "vpexpandd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0x4a, 0x01], "vpexpandd ymm1, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0x4a, 0x01], "vpexpandd ymm1{k5}, ymmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0xca], "vpexpandq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0x0a], "vpexpandq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0x4a, 0x01], "vpexpandq zmm1{k5}{z}, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0xca], "vpexpandq zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0xca], "vpexpandq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0x0a], "vpexpandq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0x0a], "vpexpandq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0x4a, 0x01], "vpexpandq zmm1, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0x4a, 0x01], "vpexpandq zmm1{k5}, zmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0xca], "vpexpandq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0x0a], "vpexpandq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0x4a, 0x01], "vpexpandq xmm1{k5}{z}, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0xca], "vpexpandq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0xca], "vpexpandq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0x0a], "vpexpandq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0x0a], "vpexpandq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0x4a, 0x01], "vpexpandq xmm1, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0x4a, 0x01], "vpexpandq xmm1{k5}, xmmword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0xca], "vpexpandd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0x0a], "vpexpandd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0x4a, 0x01], "vpexpandd zmm1{k5}{z}, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0xca], "vpexpandd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0xca], "vpexpandd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0x0a], "vpexpandd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0x0a], "vpexpandd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0x4a, 0x01], "vpexpandd zmm1, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0x4a, 0x01], "vpexpandd zmm1{k5}, zmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0xca], "vpexpandd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0x0a], "vpexpandd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0x4a, 0x01], "vpexpandd xmm1{k5}{z}, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0xca], "vpexpandd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0xca], "vpexpandd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0x0a], "vpexpandd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0x0a], "vpexpandd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0x4a, 0x01], "vpexpandd xmm1, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0x4a, 0x01], "vpexpandd xmm1{k5}, xmmword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8a, 0xca], "vcompresspd ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0xca], "vcompresspd ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0xca], "vcompresspd ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0x0a], "vcompresspd ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0x0a], "vcompresspd ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0x4a, 0x01], "vcompresspd ymmword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0x4a, 0x01], "vcompresspd ymmword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8a, 0xca], "vcompressps ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0xca], "vcompressps ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0xca], "vcompressps ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0x0a], "vcompressps ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0x0a], "vcompressps ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0x4a, 0x01], "vcompressps ymmword [edx + 0x4], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0x4a, 0x01], "vcompressps ymmword [edx + 0x4]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8a, 0xca], "vcompresspd zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0xca], "vcompresspd zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0xca], "vcompresspd zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x0a], "vcompresspd zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0x0a], "vcompresspd zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x4a, 0x01], "vcompresspd zmmword [edx + 0x8], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0x4a, 0x01], "vcompresspd zmmword [edx + 0x8]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8a, 0xca], "vcompresspd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0xca], "vcompresspd xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0xca], "vcompresspd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0x0a], "vcompresspd xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0x0a], "vcompresspd xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0x4a, 0x01], "vcompresspd xmmword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0x4a, 0x01], "vcompresspd xmmword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8a, 0xca], "vcompressps zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0xca], "vcompressps zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0xca], "vcompressps zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x0a], "vcompressps zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0x0a], "vcompressps zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x4a, 0x01], "vcompressps zmmword [edx + 0x4], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0x4a, 0x01], "vcompressps zmmword [edx + 0x4]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8a, 0xca], "vcompressps xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0xca], "vcompressps xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0xca], "vcompressps xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0x0a], "vcompressps xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0x0a], "vcompressps xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0x4a, 0x01], "vcompressps xmmword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0x4a, 0x01], "vcompressps xmmword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8b, 0xca], "vpcompressq ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0xca], "vpcompressq ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0xca], "vpcompressq ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0x0a], "vpcompressq ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0x0a], "vpcompressq ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0x4a, 0x01], "vpcompressq ymmword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0x4a, 0x01], "vpcompressq ymmword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8b, 0xca], "vpcompressd ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0xca], "vpcompressd ymm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0xca], "vpcompressd ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0x0a], "vpcompressd ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0x0a], "vpcompressd ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0x4a, 0x01], "vpcompressd ymmword [edx + 0x4], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0x4a, 0x01], "vpcompressd ymmword [edx + 0x4]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8b, 0xca], "vpcompressq zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0xca], "vpcompressq zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0xca], "vpcompressq zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x0a], "vpcompressq zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0x0a], "vpcompressq zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x4a, 0x01], "vpcompressq zmmword [edx + 0x8], zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0x4a, 0x01], "vpcompressq zmmword [edx + 0x8]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8b, 0xca], "vpcompressq xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0xca], "vpcompressq xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0xca], "vpcompressq xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0x0a], "vpcompressq xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0x0a], "vpcompressq xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0x4a, 0x01], "vpcompressq xmmword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0x4a, 0x01], "vpcompressq xmmword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8b, 0xca], "vpcompressd zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0xca], "vpcompressd zmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0xca], "vpcompressd zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x0a], "vpcompressd zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0x0a], "vpcompressd zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x4a, 0x01], "vpcompressd zmmword [edx + 0x4], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0x4a, 0x01], "vpcompressd zmmword [edx + 0x4]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8b, 0xca], "vpcompressd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0xca], "vpcompressd xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0xca], "vpcompressd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0x0a], "vpcompressd xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0x0a], "vpcompressd xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0x4a, 0x01], "vpcompressd xmmword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0x4a, 0x01], "vpcompressd xmmword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0xca], "vpermw ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0x0a], "vpermw ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0x4a, 0x01], "vpermw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0xca], "vpermw ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0xca], "vpermw ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0x0a], "vpermw ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0x0a], "vpermw ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0x4a, 0x01], "vpermw ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0x4a, 0x01], "vpermw ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0xca], "vpermb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0x0a], "vpermb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0x4a, 0x01], "vpermb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0xca], "vpermb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0xca], "vpermb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0x0a], "vpermb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0x0a], "vpermb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0x4a, 0x01], "vpermb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0x4a, 0x01], "vpermb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0xca], "vpermw zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0x0a], "vpermw zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0x4a, 0x01], "vpermw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0xca], "vpermw zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0xca], "vpermw zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0x0a], "vpermw zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0x0a], "vpermw zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0x4a, 0x01], "vpermw zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0x4a, 0x01], "vpermw zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0xca], "vpermw xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0x0a], "vpermw xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0x4a, 0x01], "vpermw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0xca], "vpermw xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0xca], "vpermw xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0x0a], "vpermw xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0x0a], "vpermw xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0x4a, 0x01], "vpermw xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0x4a, 0x01], "vpermw xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0xca], "vpermb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0x0a], "vpermb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0x4a, 0x01], "vpermb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0xca], "vpermb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0xca], "vpermb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0x0a], "vpermb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0x0a], "vpermb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0x4a, 0x01], "vpermb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0x4a, 0x01], "vpermb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0xca], "vpermb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0x0a], "vpermb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0x4a, 0x01], "vpermb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0xca], "vpermb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0xca], "vpermb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0x0a], "vpermb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0x0a], "vpermb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0x4a, 0x01], "vpermb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0x4a, 0x01], "vpermb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0xca], "vpshufbitqmb k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0x0a], "vpshufbitqmb k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0xca], "vpshufbitqmb k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0x0a], "vpshufbitqmb k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0xca], "vpshufbitqmb k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0x0a], "vpshufbitqmb k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x96, 0xca], "vfmaddsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0xca], "vfmaddsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0xca], "vfmaddsub132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x96, 0xca], "vfmaddsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0xca], "vfmaddsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0xca], "vfmaddsub132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0xca], "vfmaddsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0xca], "vfmaddsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0xca], "vfmaddsub132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0xca], "vfmaddsub132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0xca], "vfmaddsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0xca], "vfmaddsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0xca], "vfmaddsub132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0xca], "vfmaddsub132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x97, 0xca], "vfmsubadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0xca], "vfmsubadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0xca], "vfmsubadd132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x97, 0xca], "vfmsubadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0xca], "vfmsubadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0xca], "vfmsubadd132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0xca], "vfmsubadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0xca], "vfmsubadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0xca], "vfmsubadd132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0xca], "vfmsubadd132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0xca], "vfmsubadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0xca], "vfmsubadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0xca], "vfmsubadd132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0xca], "vfmsubadd132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x98, 0xca], "vfmadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0xca], "vfmadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0xca], "vfmadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0xca], "vfmadd132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0xca], "vfmadd132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x98, 0xca], "vfmadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0xca], "vfmadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0xca], "vfmadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0xca], "vfmadd132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0xca], "vfmadd132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0xca], "vfmadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0xca], "vfmadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0xca], "vfmadd132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0xca], "vfmadd132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0xca], "vfmadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0xca], "vfmadd132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0xca], "vfmadd132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0xca], "vfmadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0xca], "vfmadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0xca], "vfmadd132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0xca], "vfmadd132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0xca], "vfmadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0xca], "vfmadd132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0xca], "vfmadd132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x99, 0xca], "vfmadd132sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x99, 0xca], "vfmadd132sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0x0a], "vfmadd132sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0xca], "vfmadd132sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0xca], "vfmadd132sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0x0a], "vfmadd132sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0x0a], "vfmadd132sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x99, 0xca], "vfmadd132ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x99, 0xca], "vfmadd132ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x0a], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0xca], "vfmadd132ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x0a], "vfmadd132ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x0a], "vfmadd132ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x99, 0xca], "vfmadd132sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x99, 0xca], "vfmadd132sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x99, 0xca], "vfmadd132ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x99, 0xca], "vfmadd132ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9a, 0xca], "vfmsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0xca], "vfmsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0xca], "vfmsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0xca], "vfmsub132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0xca], "vfmsub132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9a, 0xca], "vfmsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0xca], "vfmsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0xca], "vfmsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0xca], "vfmsub132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0xca], "vfmsub132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0xca], "vfmsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0xca], "vfmsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0xca], "vfmsub132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0xca], "vfmsub132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0xca], "vfmsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0xca], "vfmsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0xca], "vfmsub132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0xca], "vfmsub132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9b, 0xca], "vfmsub132sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9b, 0xca], "vfmsub132sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0xca], "vfmsub132sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0x0a], "vfmsub132sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9b, 0xca], "vfmsub132ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9b, 0xca], "vfmsub132ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0xca], "vfmsub132ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0x0a], "vfmsub132ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9b, 0xca], "vfmsub132sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9b, 0xca], "vfmsub132sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9b, 0xca], "vfmsub132ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9b, 0xca], "vfmsub132ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9c, 0xca], "vfnmadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0xca], "vfnmadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0xca], "vfnmadd132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9c, 0xca], "vfnmadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0xca], "vfnmadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0xca], "vfnmadd132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0xca], "vfnmadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0xca], "vfnmadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0xca], "vfnmadd132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0xca], "vfnmadd132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0xca], "vfnmadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0xca], "vfnmadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0xca], "vfnmadd132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0xca], "vfnmadd132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9d, 0xca], "vfnmadd132sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9d, 0xca], "vfnmadd132sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0xca], "vfnmadd132sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0x0a], "vfnmadd132sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9d, 0xca], "vfnmadd132ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9d, 0xca], "vfnmadd132ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0xca], "vfnmadd132ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0x0a], "vfnmadd132ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9d, 0xca], "vfnmadd132sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9d, 0xca], "vfnmadd132sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9d, 0xca], "vfnmadd132ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9d, 0xca], "vfnmadd132ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9e, 0xca], "vfnmsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0xca], "vfnmsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0xca], "vfnmsub132pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9e, 0xca], "vfnmsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0xca], "vfnmsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0xca], "vfnmsub132ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0xca], "vfnmsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0xca], "vfnmsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0xca], "vfnmsub132pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0xca], "vfnmsub132pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0xca], "vfnmsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0xca], "vfnmsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0xca], "vfnmsub132ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0xca], "vfnmsub132ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0x9f, 0xca], "vfnmsub132sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0x9f, 0xca], "vfnmsub132sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0xca], "vfnmsub132sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0x0a], "vfnmsub132sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0x9f, 0xca], "vfnmsub132ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0x9f, 0xca], "vfnmsub132ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0xca], "vfnmsub132ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0x0a], "vfnmsub132ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0x9f, 0xca], "vfnmsub132sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0x9f, 0xca], "vfnmsub132sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0x9f, 0xca], "vfnmsub132ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0x9f, 0xca], "vfnmsub132ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa6, 0xca], "vfmaddsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0xca], "vfmaddsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0xca], "vfmaddsub213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa6, 0xca], "vfmaddsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0xca], "vfmaddsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0xca], "vfmaddsub213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0xca], "vfmaddsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0xca], "vfmaddsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0xca], "vfmaddsub213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0xca], "vfmaddsub213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0xca], "vfmaddsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0xca], "vfmaddsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0xca], "vfmaddsub213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0xca], "vfmaddsub213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa7, 0xca], "vfmsubadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0xca], "vfmsubadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0xca], "vfmsubadd213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa7, 0xca], "vfmsubadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0xca], "vfmsubadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0xca], "vfmsubadd213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0xca], "vfmsubadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0xca], "vfmsubadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0xca], "vfmsubadd213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0xca], "vfmsubadd213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0xca], "vfmsubadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0xca], "vfmsubadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0xca], "vfmsubadd213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0xca], "vfmsubadd213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa8, 0xca], "vfmadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0xca], "vfmadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0xca], "vfmadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0xca], "vfmadd213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0xca], "vfmadd213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa8, 0xca], "vfmadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0xca], "vfmadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0xca], "vfmadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0xca], "vfmadd213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0xca], "vfmadd213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0xca], "vfmadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0xca], "vfmadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0xca], "vfmadd213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0xca], "vfmadd213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0xca], "vfmadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0xca], "vfmadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0xca], "vfmadd213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0xca], "vfmadd213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xa9, 0xca], "vfmadd213sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xa9, 0xca], "vfmadd213sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0xca], "vfmadd213sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0x0a], "vfmadd213sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xa9, 0xca], "vfmadd213ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xa9, 0xca], "vfmadd213ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0xca], "vfmadd213ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0x0a], "vfmadd213ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xa9, 0xca], "vfmadd213sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xa9, 0xca], "vfmadd213sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xa9, 0xca], "vfmadd213ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xa9, 0xca], "vfmadd213ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xaa, 0xca], "vfmsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0xca], "vfmsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0xca], "vfmsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0xca], "vfmsub213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0xca], "vfmsub213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xaa, 0xca], "vfmsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0xca], "vfmsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0xca], "vfmsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0xca], "vfmsub213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0xca], "vfmsub213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0xca], "vfmsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0xca], "vfmsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0xca], "vfmsub213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0xca], "vfmsub213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0xca], "vfmsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0xca], "vfmsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0xca], "vfmsub213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0xca], "vfmsub213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xab, 0xca], "vfmsub213sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xab, 0xca], "vfmsub213sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0x0a], "vfmsub213sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0xca], "vfmsub213sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0xca], "vfmsub213sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0x0a], "vfmsub213sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0x0a], "vfmsub213sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xab, 0xca], "vfmsub213ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xab, 0xca], "vfmsub213ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0x0a], "vfmsub213ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0xca], "vfmsub213ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0xca], "vfmsub213ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0x0a], "vfmsub213ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0x0a], "vfmsub213ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xab, 0xca], "vfmsub213sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xab, 0xca], "vfmsub213sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xab, 0xca], "vfmsub213ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xab, 0xca], "vfmsub213ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xac, 0xca], "vfnmadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0xca], "vfnmadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0xca], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0xca], "vfnmadd213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0xca], "vfnmadd213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xac, 0xca], "vfnmadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0xca], "vfnmadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0xca], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0xca], "vfnmadd213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0xca], "vfnmadd213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0xca], "vfnmadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0xca], "vfnmadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0xca], "vfnmadd213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0xca], "vfnmadd213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0xca], "vfnmadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0xca], "vfnmadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0xca], "vfnmadd213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0xca], "vfnmadd213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xad, 0xca], "vfnmadd213sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xad, 0xca], "vfnmadd213sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0xca], "vfnmadd213sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0x0a], "vfnmadd213sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xad, 0xca], "vfnmadd213ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xad, 0xca], "vfnmadd213ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0xca], "vfnmadd213ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0x0a], "vfnmadd213ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xad, 0xca], "vfnmadd213sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xad, 0xca], "vfnmadd213sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xad, 0xca], "vfnmadd213ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xad, 0xca], "vfnmadd213ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xae, 0xca], "vfnmsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0xca], "vfnmsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0xca], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0xca], "vfnmsub213pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0xca], "vfnmsub213pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xae, 0xca], "vfnmsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0xca], "vfnmsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0xca], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0xca], "vfnmsub213ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0xca], "vfnmsub213ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0xca], "vfnmsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0xca], "vfnmsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0xca], "vfnmsub213pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0xca], "vfnmsub213pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0xca], "vfnmsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0xca], "vfnmsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0xca], "vfnmsub213ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0xca], "vfnmsub213ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xaf, 0xca], "vfnmsub213sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xaf, 0xca], "vfnmsub213sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0xca], "vfnmsub213sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0x0a], "vfnmsub213sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xaf, 0xca], "vfnmsub213ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xaf, 0xca], "vfnmsub213ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0xca], "vfnmsub213ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0x0a], "vfnmsub213ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xaf, 0xca], "vfnmsub213sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xaf, 0xca], "vfnmsub213sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xaf, 0xca], "vfnmsub213ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xaf, 0xca], "vfnmsub213ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0xca], "vpmadd52luq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0xca], "vpmadd52luq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0xca], "vpmadd52luq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0xca], "vpmadd52luq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0xca], "vpmadd52luq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0xca], "vpmadd52luq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0xca], "vpmadd52luq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0xca], "vpmadd52huq ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0xca], "vpmadd52huq ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0xca], "vpmadd52huq ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0xca], "vpmadd52huq zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0xca], "vpmadd52huq zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0xca], "vpmadd52huq zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0xca], "vpmadd52huq xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb6, 0xca], "vfmaddsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0xca], "vfmaddsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0xca], "vfmaddsub231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb6, 0xca], "vfmaddsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0xca], "vfmaddsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0xca], "vfmaddsub231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0xca], "vfmaddsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0xca], "vfmaddsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0xca], "vfmaddsub231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0xca], "vfmaddsub231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0xca], "vfmaddsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0xca], "vfmaddsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0xca], "vfmaddsub231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0xca], "vfmaddsub231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb7, 0xca], "vfmsubadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0xca], "vfmsubadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0xca], "vfmsubadd231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb7, 0xca], "vfmsubadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0xca], "vfmsubadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0xca], "vfmsubadd231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0xca], "vfmsubadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0xca], "vfmsubadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0xca], "vfmsubadd231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0xca], "vfmsubadd231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0xca], "vfmsubadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0xca], "vfmsubadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0xca], "vfmsubadd231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0xca], "vfmsubadd231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb8, 0xca], "vfmadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0xca], "vfmadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0xca], "vfmadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0xca], "vfmadd231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0xca], "vfmadd231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb8, 0xca], "vfmadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0xca], "vfmadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0xca], "vfmadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0xca], "vfmadd231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0xca], "vfmadd231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0xca], "vfmadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0xca], "vfmadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0xca], "vfmadd231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0xca], "vfmadd231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0xca], "vfmadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0xca], "vfmadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0xca], "vfmadd231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0xca], "vfmadd231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xb9, 0xca], "vfmadd231sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xb9, 0xca], "vfmadd231sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0xca], "vfmadd231sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0x0a], "vfmadd231sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xb9, 0xca], "vfmadd231ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xb9, 0xca], "vfmadd231ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0xca], "vfmadd231ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0x0a], "vfmadd231ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xb9, 0xca], "vfmadd231sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xb9, 0xca], "vfmadd231sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xb9, 0xca], "vfmadd231ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xb9, 0xca], "vfmadd231ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xba, 0xca], "vfmsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0xca], "vfmsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0xca], "vfmsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0xca], "vfmsub231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0xca], "vfmsub231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xba, 0xca], "vfmsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0xca], "vfmsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0xca], "vfmsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0xca], "vfmsub231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0xca], "vfmsub231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0xca], "vfmsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0xca], "vfmsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0xca], "vfmsub231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0xca], "vfmsub231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0xca], "vfmsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0xca], "vfmsub231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0xca], "vfmsub231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0xca], "vfmsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0xca], "vfmsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0xca], "vfmsub231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0xca], "vfmsub231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0xca], "vfmsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0xca], "vfmsub231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0xca], "vfmsub231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbb, 0xca], "vfmsub231sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbb, 0xca], "vfmsub231sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0xca], "vfmsub231sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0x0a], "vfmsub231sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbb, 0xca], "vfmsub231ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbb, 0xca], "vfmsub231ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0xca], "vfmsub231ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0x0a], "vfmsub231ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbb, 0xca], "vfmsub231sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbb, 0xca], "vfmsub231sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbb, 0xca], "vfmsub231ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbb, 0xca], "vfmsub231ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbc, 0xca], "vfnmadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0xca], "vfnmadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0xca], "vfnmadd231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbc, 0xca], "vfnmadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0xca], "vfnmadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0xca], "vfnmadd231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0xca], "vfnmadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0xca], "vfnmadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0xca], "vfnmadd231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0xca], "vfnmadd231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0xca], "vfnmadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0xca], "vfnmadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0xca], "vfnmadd231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0xca], "vfnmadd231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbd, 0xca], "vfnmadd231sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbd, 0xca], "vfnmadd231sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0xca], "vfnmadd231sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0x0a], "vfnmadd231sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbd, 0xca], "vfnmadd231ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbd, 0xca], "vfnmadd231ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0xca], "vfnmadd231ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0x0a], "vfnmadd231ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbd, 0xca], "vfnmadd231sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbd, 0xca], "vfnmadd231sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbd, 0xca], "vfnmadd231ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbd, 0xca], "vfnmadd231ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbe, 0xca], "vfnmsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0xca], "vfnmsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0xca], "vfnmsub231pd ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbe, 0xca], "vfnmsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0xca], "vfnmsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0xca], "vfnmsub231ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0xca], "vfnmsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0xca], "vfnmsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0xca], "vfnmsub231pd zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0xca], "vfnmsub231pd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0xca], "vfnmsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0xca], "vfnmsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0xca], "vfnmsub231ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0xca], "vfnmsub231ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xbf, 0xca], "vfnmsub231sd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xbf, 0xca], "vfnmsub231sd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0xca], "vfnmsub231sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0x0a], "vfnmsub231sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xbf, 0xca], "vfnmsub231ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xbf, 0xca], "vfnmsub231ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0xca], "vfnmsub231ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0x0a], "vfnmsub231ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xbf, 0xca], "vfnmsub231sd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xbf, 0xca], "vfnmsub231sd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xbf, 0xca], "vfnmsub231ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xbf, 0xca], "vfnmsub231ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xbd, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xc4, 0x0a], "vpconflictq ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x38, 0xc4, 0x4a, 0x01], "vpconflictq ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x3d, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0xca], "vpconflictq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0xca], "vpconflictq ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0xca], "vpconflictq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0x0a], "vpconflictq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0x4a, 0x01], "vpconflictq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xbd, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xc4, 0x0a], "vpconflictd ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x38, 0xc4, 0x4a, 0x01], "vpconflictd ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x3d, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0xca], "vpconflictd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0xca], "vpconflictd ymm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0xca], "vpconflictd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0x0a], "vpconflictd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0x4a, 0x01], "vpconflictd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc4, 0x0a], "vpconflictq zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc4, 0x4a, 0x01], "vpconflictq zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x9d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xc4, 0x0a], "vpconflictq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x18, 0xc4, 0x4a, 0x01], "vpconflictq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x1d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0xca], "vpconflictq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0xca], "vpconflictq zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0xca], "vpconflictq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0x0a], "vpconflictq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0x4a, 0x01], "vpconflictq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0xca], "vpconflictq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0xca], "vpconflictq xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0xca], "vpconflictq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0x0a], "vpconflictq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0x4a, 0x01], "vpconflictq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc4, 0x0a], "vpconflictd zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc4, 0x4a, 0x01], "vpconflictd zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x9d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xc4, 0x0a], "vpconflictd xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x18, 0xc4, 0x4a, 0x01], "vpconflictd xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x1d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0xca], "vpconflictd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0xca], "vpconflictd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0xca], "vpconflictd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0x0a], "vpconflictd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0x4a, 0x01], "vpconflictd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0xca], "vpconflictd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0xca], "vpconflictd xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0xca], "vpconflictd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0x0a], "vpconflictd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0x4a, 0x01], "vpconflictd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xc8, 0xca], "vexp2pd zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xc8, 0xca], "vexp2pd zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xc8, 0xca], "vexp2ps zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xc8, 0xca], "vexp2ps zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc8, 0x0a], "vexp2pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xc8, 0x4a, 0x01], "vexp2pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0xca], "vexp2pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0xca], "vexp2pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0x0a], "vexp2pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0x4a, 0x01], "vexp2pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc8, 0x0a], "vexp2ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xc8, 0x4a, 0x01], "vexp2ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0xca], "vexp2ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0xca], "vexp2ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0x0a], "vexp2ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0x4a, 0x01], "vexp2ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xca, 0xca], "vrcp28pd zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xca, 0xca], "vrcp28pd zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xca, 0xca], "vrcp28ps zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xca, 0xca], "vrcp28ps zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xca, 0x0a], "vrcp28pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xca, 0x4a, 0x01], "vrcp28pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0xca], "vrcp28pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0xca], "vrcp28pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0x0a], "vrcp28pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0x4a, 0x01], "vrcp28pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xca, 0x0a], "vrcp28ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xca, 0x4a, 0x01], "vrcp28ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0xca], "vrcp28ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0xca], "vrcp28ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0x0a], "vrcp28ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0x4a, 0x01], "vrcp28ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcb, 0xca], "vrcp28sd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcb, 0xca], "vrcp28sd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0x0a], "vrcp28sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0xca], "vrcp28sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0xca], "vrcp28sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0x0a], "vrcp28sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0x0a], "vrcp28sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcb, 0xca], "vrcp28ss xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcb, 0xca], "vrcp28ss xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0x0a], "vrcp28ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0xca], "vrcp28ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0xca], "vrcp28ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0x0a], "vrcp28ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0x0a], "vrcp28ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcc, 0xca], "vrsqrt28pd zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcc, 0xca], "vrsqrt28ps zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xdd, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xcc, 0x0a], "vrsqrt28pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x58, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x5d, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0xca], "vrsqrt28pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0x0a], "vrsqrt28pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xdd, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xcc, 0x0a], "vrsqrt28ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x58, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x5d, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0xca], "vrsqrt28ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0x0a], "vrsqrt28ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xfd, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x78, 0xcd, 0xca], "vrsqrt28sd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x7d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0xca], "vrsqrt28sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0x0a], "vrsqrt28sd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xfd, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x78, 0xcd, 0xca], "vrsqrt28ss xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x7d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0xca], "vrsqrt28ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0x0a], "vrsqrt28ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0xca], "vgf2p8mulb ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0x0a], "vgf2p8mulb ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0xca], "vgf2p8mulb zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0x0a], "vgf2p8mulb zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0xca], "vgf2p8mulb xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0x0a], "vgf2p8mulb xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x0a], "vaesenc ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x4a, 0x01], "vaesenc ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0xca], "vaesenc zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x0a], "vaesenc zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x4a, 0x01], "vaesenc zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0x0a], "vaesenc xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0x4a, 0x01], "vaesenc xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0xca], "vaesenclast ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0x0a], "vaesenclast ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0x4a, 0x01], "vaesenclast ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0xca], "vaesenclast zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0x0a], "vaesenclast zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0x4a, 0x01], "vaesenclast zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0xca], "vaesenclast xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0x0a], "vaesenclast xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0x4a, 0x01], "vaesenclast xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0xca], "vaesdec ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0x0a], "vaesdec ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0x4a, 0x01], "vaesdec ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0xca], "vaesdec zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0x0a], "vaesdec zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0x4a, 0x01], "vaesdec zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0xca], "vaesdec xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0x0a], "vaesdec xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0x4a, 0x01], "vaesdec xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0xca], "vaesdeclast ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0x0a], "vaesdeclast ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0x4a, 0x01], "vaesdeclast ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0xca], "vaesdeclast zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0x0a], "vaesdeclast zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0x4a, 0x01], "vaesdeclast zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0xca], "vaesdeclast xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0x0a], "vaesdeclast xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0x4a, 0x01], "vaesdeclast xmm1, xmm0, xmmword [edx + 0x10]"); } #[test] fn tests_66_0f3a() { test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x0a, 0xcc], "vpermq ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0xca, 0xcc], "vpermq ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0x0a, 0xcc], "vpermq ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x00, 0x0a, 0xcc], "vpermq zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0xca, 0xcc], "vpermq zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0x0a, 0xcc], "vpermq zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x01, 0x0a, 0xcc], "vpermpd ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0xca, 0xcc], "vpermpd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0x0a, 0xcc], "vpermpd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x01, 0x0a, 0xcc], "vpermpd zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0xca, 0xcc], "vpermpd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0x0a, 0xcc], "vpermpd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0xca, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0xca, 0xcc], "valignq ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0xca, 0xcc], "valignq ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0xca, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0xca, 0xcc], "valignd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0xca, 0xcc], "valignd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0xca, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0xca, 0xcc], "valignq zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0xca, 0xcc], "valignq zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0xca, 0xcc], "valignq xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0xca, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0xca, 0xcc], "valignd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0xca, 0xcc], "valignd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0xca, 0xcc], "valignd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x0a, 0xcc], "vpermilps ymm1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0xca, 0xcc], "vpermilps ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0x0a, 0xcc], "vpermilps ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x04, 0x0a, 0xcc], "vpermilps zmm1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x04, 0x0a, 0xcc], "vpermilps xmm1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0xca, 0xcc], "vpermilps zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0x0a, 0xcc], "vpermilps zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0xca, 0xcc], "vpermilps xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0x0a, 0xcc], "vpermilps xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0xca, 0xcc], "vpermilpd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}{z}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0xca, 0xcc], "vpermilpd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0xca, 0xcc], "vpermilpd xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0xca, 0xcc], "vrndscaleps ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0xca, 0xcc], "vrndscaleps zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0xca, 0xcc], "vrndscaleps xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0xca, 0xcc], "vrndscalepd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}{z}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0xca, 0xcc], "vrndscalepd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0xca, 0xcc], "vrndscalepd xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0xca, 0xcc], "vrndscaless xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0xca, 0xcc], "vpalignr ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x0a, 0xcc], "vpalignr ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0xca, 0xcc], "vpalignr zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0x0a, 0xcc], "vpalignr zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0xca, 0xcc], "vpalignr xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x0a, 0xcc], "vpalignr xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0xca, 0xcc], "vpextrb edx, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x0a, 0xcc], "vpextrb byte [edx], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x4a, 0x01, 0xcc], "vpextrb byte [edx + 0x1], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0xca, 0xcc], "vpextrw edx, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x0a, 0xcc], "vpextrw word [edx], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x4a, 0x01, 0xcc], "vpextrw word [edx + 0x2], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0xca, 0xcc], "vpextrd edx, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x0a, 0xcc], "vpextrd dword [edx], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x4a, 0x01, 0xcc], "vpextrd dword [edx + 0x4], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0xca, 0xcc], "vextractps edx, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x0a, 0xcc], "vextractps dword [edx], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x4a, 0x01, 0xcc], "vextractps dword [edx + 0x4], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [edx], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [edx]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [edx + 0x10], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [edx + 0x10]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [edx], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [edx]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [edx + 0x10], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [edx + 0x10]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [edx + 0x10], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [edx + 0x10]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [edx + 0x10], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [edx + 0x10]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0x4a, 0x01, 0xcc], "vextractf64x4 ymmword [edx + 0x20], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0x4a, 0x01, 0xcc], "vextractf64x4 ymmword [edx + 0x20]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x4a, 0x01, 0xcc], "vextractf32x8 ymmword [edx + 0x20], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x4a, 0x01, 0xcc], "vextractf32x8 ymmword [edx + 0x20]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}{sae}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{sae}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{sae}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [edx], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [edx]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph xmmword [edx + 0x10], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph xmmword [edx + 0x10]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph ymmword [edx + 0x20], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph ymmword [edx + 0x20]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [edx], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [edx]{k5}, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph qword [edx + 0x8], xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph qword [edx + 0x8]{k5}, xmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0xca, 0xcc], "vpcmpuq k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0xca, 0xcc], "vpcmpud k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0xca, 0xcc], "vpcmpuq k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0xca, 0xcc], "vpcmpuq k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0xca, 0xcc], "vpcmpud k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0xca, 0xcc], "vpcmpud k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0xca, 0xcc], "vpcmpq k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0xca, 0xcc], "vpcmpd k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0xca, 0xcc], "vpcmpq k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0xca, 0xcc], "vpcmpq k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0xca, 0xcc], "vpcmpd k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0xca, 0xcc], "vpcmpd k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0xca, 0xcc], "vpinsrb xmm1, xmm0, edx, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x0a, 0xcc], "vpinsrb xmm1, xmm0, byte [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x4a, 0x01, 0xcc], "vpinsrb xmm1, xmm0, byte [edx + 0x1], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0xca, 0xcc], "vinsertps xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x0a, 0xcc], "vinsertps xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x4a, 0x01, 0xcc], "vinsertps xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0xca, 0xcc], "vpinsrd xmm1, xmm0, edx, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x0a, 0xcc], "vpinsrd xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x4a, 0x01, 0xcc], "vpinsrd xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0xca, 0xcc], "vpternlogq ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0xca, 0xcc], "vpternlogd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0xca, 0xcc], "vpternlogq zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0xca, 0xcc], "vpternlogq xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0xca, 0xcc], "vpternlogd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0xca, 0xcc], "vpternlogd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0xca, 0xcc], "vgetmantpd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x26, 0xca, 0xcc], "vgetmantps zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0xca, 0xcc], "vgetmantps ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}{z}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0xca, 0xcc], "vgetmantpd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0xca, 0xcc], "vgetmantpd xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0xca, 0xcc], "vgetmantps zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0xca, 0xcc], "vgetmantps xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0xca, 0xcc], "vgetmantsd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x27, 0xca, 0xcc], "vgetmantss xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0xca, 0xcc], "vgetmantss xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0x0a, 0xcc], "vgetmantss xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [edx], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [edx]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [edx + 0x10], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [edx + 0x10]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [edx], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [edx]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [edx + 0x10], ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [edx + 0x10]{k5}, ymm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [edx + 0x10], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [edx + 0x10]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [edx + 0x10], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [edx + 0x10]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0x4a, 0x01, 0xcc], "vextracti64x4 ymmword [edx + 0x20], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0x4a, 0x01, 0xcc], "vextracti64x4 ymmword [edx + 0x20]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}{z}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [edx], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [edx]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0x4a, 0x01, 0xcc], "vextracti32x8 ymmword [edx + 0x20], zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0x4a, 0x01, 0xcc], "vextracti32x8 ymmword [edx + 0x20]{k5}, zmm1, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0xca, 0xcc], "vpcmpuw k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0xca, 0xcc], "vpcmpub k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpub k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0xca, 0xcc], "vpcmpuw k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0xca, 0xcc], "vpcmpuw k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0xca, 0xcc], "vpcmpub k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpub k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0xca, 0xcc], "vpcmpub k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpub k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0xca, 0xcc], "vpcmpw k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpw k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0xca, 0xcc], "vpcmpb k1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpb k1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0xca, 0xcc], "vpcmpw k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpw k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0xca, 0xcc], "vpcmpw k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpw k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0xca, 0xcc], "vpcmpb k1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpb k1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0xca, 0xcc], "vpcmpb k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpb k1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0xca, 0xcc], "vpclmulqdq ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x0a, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0xca, 0xcc], "vpclmulqdq zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x0a, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0xca, 0xcc], "vpclmulqdq xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x0a, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x50, 0xca, 0xcc], "vrangepd zmm1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0xca, 0xcc], "vrangepd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x50, 0xca, 0xcc], "vrangeps zmm1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0xca, 0xcc], "vrangeps ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0xca, 0xcc], "vrangepd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0xca, 0xcc], "vrangepd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0xca, 0xcc], "vrangeps zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0xca, 0xcc], "vrangeps xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x51, 0xca, 0xcc], "vrangesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0xca, 0xcc], "vrangesd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0x0a, 0xcc], "vrangesd xmm1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x51, 0xca, 0xcc], "vrangess xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}{z}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1{k5}{z}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0xca, 0xcc], "vrangess xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0x0a, 0xcc], "vrangess xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0xca, 0xcc], "vfixupimmps ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0xca, 0xcc], "vfixupimmps zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0xca, 0xcc], "vfixupimmps xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0xca, 0xcc], "vfixupimmss xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x56, 0xca, 0xcc], "vreducepd zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}{z}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x56, 0x0a, 0xcc], "vreducepd ymm1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0xca, 0xcc], "vreducepd ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0x0a, 0xcc], "vreducepd ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x56, 0xca, 0xcc], "vreduceps zmm1{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{sae}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}{z}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x56, 0x0a, 0xcc], "vreduceps ymm1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0xca, 0xcc], "vreduceps ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0x0a, 0xcc], "vreduceps ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}{z}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x56, 0x0a, 0xcc], "vreducepd zmm1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}{z}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x56, 0x0a, 0xcc], "vreducepd xmm1, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0xca, 0xcc], "vreducepd zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0x0a, 0xcc], "vreducepd zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0xca, 0xcc], "vreducepd xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0x0a, 0xcc], "vreducepd xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}{z}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x56, 0x0a, 0xcc], "vreduceps zmm1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}{z}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x56, 0x0a, 0xcc], "vreduceps xmm1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0xca, 0xcc], "vreduceps zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0x0a, 0xcc], "vreduceps zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0xca, 0xcc], "vreduceps xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0x0a, 0xcc], "vreduceps xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xfd, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x78, 0x57, 0xca, 0xcc], "vreducesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x7d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0xca, 0xcc], "vreducesd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0x0a, 0xcc], "vreducesd xmm1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xfd, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x78, 0x57, 0xca, 0xcc], "vreducess xmm1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x7d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}{z}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1{k5}{z}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0xca, 0xcc], "vreducess xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0x0a, 0xcc], "vreducess xmm1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0xca, 0xcc], "vfpclasspd k1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x0a, 0xcc], "vfpclasspd k1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0xca, 0xcc], "vfpclassps k1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0x0a, 0xcc], "vfpclassps k1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0xca, 0xcc], "vfpclasspd k1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0x0a, 0xcc], "vfpclasspd k1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0xca, 0xcc], "vfpclasspd k1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0x0a, 0xcc], "vfpclasspd k1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0xca, 0xcc], "vfpclassps k1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0x0a, 0xcc], "vfpclassps k1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0xca, 0xcc], "vfpclassps k1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0x0a, 0xcc], "vfpclassps k1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0xca, 0xcc], "vfpclasssd k1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0xca, 0xcc], "vfpclasssd k1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0x0a, 0xcc], "vfpclasssd k1, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0x0a, 0xcc], "vfpclasssd k1{k5}, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0x4a, 0x01, 0xcc], "vfpclasssd k1, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0x4a, 0x01, 0xcc], "vfpclasssd k1{k5}, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0xca, 0xcc], "vfpclassss k1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0xca, 0xcc], "vfpclassss k1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0x0a, 0xcc], "vfpclassss k1, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0x0a, 0xcc], "vfpclassss k1{k5}, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0x4a, 0x01, 0xcc], "vfpclassss k1, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0x4a, 0x01, 0xcc], "vfpclassss k1{k5}, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0xca, 0xcc], "vpshldw ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0x0a, 0xcc], "vpshldw ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0xca, 0xcc], "vpshldw zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0x0a, 0xcc], "vpshldw zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0xca, 0xcc], "vpshldw xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0x0a, 0xcc], "vpshldw xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0xca, 0xcc], "vpshldq ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0xca, 0xcc], "vpshldd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0xca, 0xcc], "vpshldq zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0xca, 0xcc], "vpshldq xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0xca, 0xcc], "vpshldd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0xca, 0xcc], "vpshldd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vpshrdw ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vpshrdw ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vpshrdw zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vpshrdw zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vpshrdw xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vpshrdw xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0xca, 0xcc], "vpshrdq ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xbd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, dword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x38, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x3d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0xca, 0xcc], "vpshrdd ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0xca, 0xcc], "vpshrdq zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0xca, 0xcc], "vpshrdq xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xdd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, dword [edx]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x58, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x5d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x9d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, dword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x18, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x1d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0xca, 0xcc], "vpshrdd zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0xca, 0xcc], "vpshrdd xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xbd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, qword [edx]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x38, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x3d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, qword [edx + 0x8]{1to4}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xdd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, qword [edx]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x58, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x5d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, qword [edx + 0x8]{1to8}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x9d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, qword [edx]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x18, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x1d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, qword [edx + 0x8]{1to2}, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmmword [edx + 0x10], 0xcc"); } #[test] fn tests_f2_0f() { test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0xca], "vmovss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x0a], "vmovss xmm1{k5}{z}, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x4a, 0x01], "vmovss xmm1{k5}{z}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0xca], "vmovss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0xca], "vmovss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x0a], "vmovss xmm1, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x0a], "vmovss xmm1{k5}, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x4a, 0x01], "vmovss xmm1, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x4a, 0x01], "vmovss xmm1{k5}, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0xca], "vmovss xmm2{k5}{z}, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0xca], "vmovss xmm2, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0xca], "vmovss xmm2{k5}, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x0a], "vmovss dword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x0a], "vmovss dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x4a, 0x01], "vmovss dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x4a, 0x01], "vmovss dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0xca], "vmovsldup ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x0a], "vmovsldup ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x4a, 0x01], "vmovsldup ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0xca], "vmovsldup ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0xca], "vmovsldup ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0x0a], "vmovsldup ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0x0a], "vmovsldup ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0x4a, 0x01], "vmovsldup ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0x4a, 0x01], "vmovsldup ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0xca], "vmovsldup zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0x0a], "vmovsldup zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0x4a, 0x01], "vmovsldup zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0xca], "vmovsldup zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0xca], "vmovsldup zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0x0a], "vmovsldup zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0x0a], "vmovsldup zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0x4a, 0x01], "vmovsldup zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0x4a, 0x01], "vmovsldup zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0xca], "vmovsldup xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0x0a], "vmovsldup xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0x4a, 0x01], "vmovsldup xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0xca], "vmovsldup xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0xca], "vmovsldup xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0x0a], "vmovsldup xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0x0a], "vmovsldup xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0x4a, 0x01], "vmovsldup xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0x4a, 0x01], "vmovsldup xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0xca], "vmovshdup ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0x0a], "vmovshdup ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0x4a, 0x01], "vmovshdup ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0xca], "vmovshdup ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0xca], "vmovshdup ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0x0a], "vmovshdup ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0x0a], "vmovshdup ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0x4a, 0x01], "vmovshdup ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0x4a, 0x01], "vmovshdup ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0xca], "vmovshdup zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0x0a], "vmovshdup zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0x4a, 0x01], "vmovshdup zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0xca], "vmovshdup zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0xca], "vmovshdup zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0x0a], "vmovshdup zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0x0a], "vmovshdup zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0x4a, 0x01], "vmovshdup zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0x4a, 0x01], "vmovshdup zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0xca], "vmovshdup xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0x0a], "vmovshdup xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0x4a, 0x01], "vmovshdup xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0xca], "vmovshdup xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0xca], "vmovshdup xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0x0a], "vmovshdup xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0x0a], "vmovshdup xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0x4a, 0x01], "vmovshdup xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0x4a, 0x01], "vmovshdup xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x4a, 0x01], "vcvtsi2ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x2a, 0xca], "vcvtsi2ss xmm1{ru-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si ecx, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x4a, 0x01], "vcvttss2si ecx, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si ecx, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x4a, 0x01], "vcvtss2si ecx, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x2d, 0xca], "vcvtss2si ecx{ru-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x2d, 0xca], "vcvtss2si ecx{rne-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x51, 0xca], "vsqrtss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x51, 0xca], "vsqrtss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x51, 0xca], "vsqrtss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x51, 0xca], "vsqrtss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0xca], "vsqrtss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0x0a], "vsqrtss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0x4a, 0x01], "vsqrtss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0xca], "vsqrtss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0xca], "vsqrtss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0x0a], "vsqrtss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0x0a], "vsqrtss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0x4a, 0x01], "vsqrtss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0x4a, 0x01], "vsqrtss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x51, 0xca], "vsqrtss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x51, 0xca], "vsqrtss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x51, 0xca], "vsqrtss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x51, 0xca], "vsqrtss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x58, 0xca], "vaddss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x58, 0xca], "vaddss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x58, 0xca], "vaddss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x58, 0xca], "vaddss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0xca], "vaddss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0x0a], "vaddss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0x4a, 0x01], "vaddss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0xca], "vaddss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0xca], "vaddss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0x0a], "vaddss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0x0a], "vaddss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0x4a, 0x01], "vaddss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0x4a, 0x01], "vaddss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x58, 0xca], "vaddss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x58, 0xca], "vaddss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x58, 0xca], "vaddss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x58, 0xca], "vaddss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x58, 0xca], "vaddss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x58, 0xca], "vaddss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x59, 0xca], "vmulss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x59, 0xca], "vmulss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x59, 0xca], "vmulss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x59, 0xca], "vmulss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0xca], "vmulss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0x0a], "vmulss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0x4a, 0x01], "vmulss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0xca], "vmulss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0xca], "vmulss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0x0a], "vmulss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0x0a], "vmulss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0x4a, 0x01], "vmulss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0x4a, 0x01], "vmulss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x59, 0xca], "vmulss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x59, 0xca], "vmulss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x59, 0xca], "vmulss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x59, 0xca], "vmulss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x59, 0xca], "vmulss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x59, 0xca], "vmulss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0xca], "vcvtss2sd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0xca], "vcvtss2sd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0x0a], "vcvtss2sd xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5b, 0xca], "vcvttps2dq zmm1{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5b, 0x0a], "vcvttps2dq ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0xca], "vcvttps2dq ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0xca], "vcvttps2dq ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0xca], "vcvttps2dq ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0x0a], "vcvttps2dq ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5b, 0x0a], "vcvttps2dq zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5b, 0x0a], "vcvttps2dq xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0xca], "vcvttps2dq zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0x0a], "vcvttps2dq zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0xca], "vcvttps2dq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0x0a], "vcvttps2dq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5c, 0xca], "vsubss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5c, 0xca], "vsubss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5c, 0xca], "vsubss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5c, 0xca], "vsubss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0xca], "vsubss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0x0a], "vsubss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0x4a, 0x01], "vsubss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0xca], "vsubss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0xca], "vsubss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0x0a], "vsubss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0x0a], "vsubss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0x4a, 0x01], "vsubss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0x4a, 0x01], "vsubss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5c, 0xca], "vsubss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5c, 0xca], "vsubss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5c, 0xca], "vsubss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5c, 0xca], "vsubss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5d, 0xca], "vminss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5d, 0xca], "vminss xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5d, 0xca], "vminss xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0xca], "vminss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0x0a], "vminss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0x4a, 0x01], "vminss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0xca], "vminss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0xca], "vminss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0x0a], "vminss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0x0a], "vminss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0x4a, 0x01], "vminss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0x4a, 0x01], "vminss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5e, 0xca], "vdivss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5e, 0xca], "vdivss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x5e, 0xca], "vdivss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x5e, 0xca], "vdivss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0xca], "vdivss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0x0a], "vdivss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0x4a, 0x01], "vdivss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0xca], "vdivss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0xca], "vdivss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0x0a], "vdivss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0x0a], "vdivss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0x4a, 0x01], "vdivss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0x4a, 0x01], "vdivss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x5e, 0xca], "vdivss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x5e, 0xca], "vdivss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x5e, 0xca], "vdivss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x5e, 0xca], "vdivss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xfd, 0x5f, 0xca], "vmaxss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0x5f, 0xca], "vmaxss xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0x5f, 0xca], "vmaxss xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0xca], "vmaxss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0x0a], "vmaxss xmm1{k5}{z}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0x4a, 0x01], "vmaxss xmm1{k5}{z}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0xca], "vmaxss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0xca], "vmaxss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0x0a], "vmaxss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0x0a], "vmaxss xmm1{k5}, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0x4a, 0x01], "vmaxss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0x4a, 0x01], "vmaxss xmm1{k5}, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0xca], "vmovdqu64 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0xca], "vmovdqu64 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0xca], "vmovdqu64 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0x0a], "vmovdqu64 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0xca], "vmovdqu32 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0xca], "vmovdqu32 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0xca], "vmovdqu32 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0x0a], "vmovdqu32 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0xca], "vmovdqu64 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0xca], "vmovdqu64 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0xca], "vmovdqu64 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0x0a], "vmovdqu64 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0xca], "vmovdqu64 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0x0a], "vmovdqu64 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0xca], "vmovdqu32 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0xca], "vmovdqu32 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0xca], "vmovdqu32 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x0a], "vmovdqu32 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0xca], "vmovdqu32 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0x0a], "vmovdqu32 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0xca, 0xcc], "vpshufhw ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0x0a, 0xcc], "vpshufhw ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0xca, 0xcc], "vpshufhw zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0x0a, 0xcc], "vpshufhw zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0xca, 0xcc], "vpshufhw xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0x0a, 0xcc], "vpshufhw xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x78, 0xca], "vcvttss2usi ecx{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0xca], "vcvttss2usi ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0x0a], "vcvttss2usi ecx, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0x4a, 0x01], "vcvttss2usi ecx, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x79, 0xca], "vcvtss2usi ecx{rz-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x79, 0xca], "vcvtss2usi ecx{rd-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0xca], "vcvtss2usi ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0x0a], "vcvtss2usi ecx, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0x4a, 0x01], "vcvtss2usi ecx, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x79, 0xca], "vcvtss2usi ecx{ru-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x79, 0xca], "vcvtss2usi ecx{rne-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x7a, 0xca], "vcvtuqq2pd zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x7d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0xca], "vcvtuqq2pd zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0x0a], "vcvtuqq2pd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0xca], "vcvtuqq2pd ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0x0a], "vcvtuqq2pd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7a, 0x0a], "vcvtudq2pd ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0xca], "vcvtudq2pd ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0x0a], "vcvtudq2pd ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0xca], "vcvtuqq2pd zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0x0a], "vcvtuqq2pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0xca], "vcvtuqq2pd zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0x0a], "vcvtuqq2pd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0xca], "vcvtuqq2pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0x0a], "vcvtuqq2pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0xca], "vcvtuqq2pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0x0a], "vcvtuqq2pd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7a, 0x0a], "vcvtudq2pd zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7a, 0x0a], "vcvtudq2pd xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0xca], "vcvtudq2pd zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0x0a], "vcvtudq2pd zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0xca], "vcvtudq2pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0x0a], "vcvtudq2pd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x4a, 0x01], "vcvtusi2ss xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xca], "vmovq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x0a], "vmovq xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x4a, 0x01], "vmovq xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0x7f, 0xca], "vmovdqu64 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0xca], "vmovdqu64 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0xca], "vmovdqu64 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0x0a], "vmovdqu64 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0x0a], "vmovdqu64 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu64 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu64 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0x7f, 0xca], "vmovdqu32 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0xca], "vmovdqu32 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0xca], "vmovdqu32 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0x0a], "vmovdqu32 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0x0a], "vmovdqu32 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu32 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu32 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0x7f, 0xca], "vmovdqu64 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0xca], "vmovdqu64 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0xca], "vmovdqu64 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0x0a], "vmovdqu64 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0x0a], "vmovdqu64 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu64 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu64 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0xca], "vmovdqu64 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0x0a], "vmovdqu64 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0x0a], "vmovdqu64 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu64 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu64 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0x7f, 0xca], "vmovdqu32 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0xca], "vmovdqu32 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0xca], "vmovdqu32 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0x0a], "vmovdqu32 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0x0a], "vmovdqu32 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu32 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu32 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0xca], "vmovdqu32 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0x0a], "vmovdqu32 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0x0a], "vmovdqu32 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu32 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu32 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x78, 0xc2, 0xca, 0xcc], "vcmpss k1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x7d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0xca, 0xcc], "vcmpss k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x0a, 0xcc], "vcmpss k1, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpss k1{k5}, xmm0, dword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpss k1, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpss k1{k5}, xmm0, dword [edx + 0x4], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xfd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x78, 0xe6, 0xca], "vcvtqq2pd zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x7d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0xca], "vcvtqq2pd zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0x0a], "vcvtqq2pd ymm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0xca], "vcvtqq2pd ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0x0a], "vcvtqq2pd ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xbd, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0xe6, 0x0a], "vcvtdq2pd ymm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x38, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x3d, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0xca], "vcvtdq2pd ymm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0x0a], "vcvtdq2pd ymm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0xca], "vcvtqq2pd zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0x0a], "vcvtqq2pd zmm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0xca], "vcvtqq2pd zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0x0a], "vcvtqq2pd xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0xca], "vcvtqq2pd zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0x0a], "vcvtqq2pd zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0xca], "vcvtqq2pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0x0a], "vcvtqq2pd xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xdd, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0xe6, 0x0a], "vcvtdq2pd zmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x58, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x5d, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x9d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}{z}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0xe6, 0x0a], "vcvtdq2pd xmm1, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, dword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x18, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x1d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}, dword [edx + 0x4]{1to2}"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0xca], "vcvtdq2pd zmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0x0a], "vcvtdq2pd zmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0xca], "vcvtdq2pd xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0x0a], "vcvtdq2pd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}, qword [edx + 0x8]"); } #[test] fn tests_f2_0f38() { test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0xca], "vpmovuswb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0xca], "vpmovuswb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x0a], "vpmovuswb xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x0a], "vpmovuswb xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x4a, 0x01], "vpmovuswb xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x4a, 0x01], "vpmovuswb xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x10, 0xca], "vpmovuswb ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0xca], "vpmovuswb ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0xca], "vpmovuswb ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0x0a], "vpmovuswb ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0x0a], "vpmovuswb ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0x4a, 0x01], "vpmovuswb ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0x4a, 0x01], "vpmovuswb ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0xca], "vpmovuswb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0xca], "vpmovuswb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0x0a], "vpmovuswb qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0x0a], "vpmovuswb qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0x4a, 0x01], "vpmovuswb qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0x4a, 0x01], "vpmovuswb qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0xca], "vpmovusdb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0xca], "vpmovusdb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0x0a], "vpmovusdb qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0x0a], "vpmovusdb qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0x4a, 0x01], "vpmovusdb qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0x4a, 0x01], "vpmovusdb qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0xca], "vpmovusdb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0xca], "vpmovusdb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0x0a], "vpmovusdb xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0x0a], "vpmovusdb xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0x4a, 0x01], "vpmovusdb xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0x4a, 0x01], "vpmovusdb xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0xca], "vpmovusdb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0xca], "vpmovusdb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0x0a], "vpmovusdb dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0x0a], "vpmovusdb dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0x4a, 0x01], "vpmovusdb dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0x4a, 0x01], "vpmovusdb dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0xca], "vpmovusqb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0xca], "vpmovusqb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0x0a], "vpmovusqb dword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0x0a], "vpmovusqb dword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0x4a, 0x01], "vpmovusqb dword [edx + 0x4], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0x4a, 0x01], "vpmovusqb dword [edx + 0x4]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0xca], "vpmovusqb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0xca], "vpmovusqb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x0a], "vpmovusqb qword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x0a], "vpmovusqb qword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x4a, 0x01], "vpmovusqb qword [edx + 0x8], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x4a, 0x01], "vpmovusqb qword [edx + 0x8]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0xca], "vpmovusqb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0xca], "vpmovusqb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0x0a], "vpmovusqb word [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0x0a], "vpmovusqb word [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0x4a, 0x01], "vpmovusqb word [edx + 0x2], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0x4a, 0x01], "vpmovusqb word [edx + 0x2]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0xca], "vpmovusdw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0xca], "vpmovusdw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0x0a], "vpmovusdw xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0x0a], "vpmovusdw xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0x4a, 0x01], "vpmovusdw xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0x4a, 0x01], "vpmovusdw xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x13, 0xca], "vpmovusdw ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0xca], "vpmovusdw ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0xca], "vpmovusdw ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0x0a], "vpmovusdw ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0x0a], "vpmovusdw ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0x4a, 0x01], "vpmovusdw ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0x4a, 0x01], "vpmovusdw ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0xca], "vpmovusdw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0xca], "vpmovusdw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0x0a], "vpmovusdw qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0x0a], "vpmovusdw qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0x4a, 0x01], "vpmovusdw qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0x4a, 0x01], "vpmovusdw qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0xca], "vpmovusqw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0xca], "vpmovusqw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0x0a], "vpmovusqw qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0x0a], "vpmovusqw qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0x4a, 0x01], "vpmovusqw qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0x4a, 0x01], "vpmovusqw qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0xca], "vpmovusqw xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0xca], "vpmovusqw xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0x0a], "vpmovusqw xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0x0a], "vpmovusqw xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0x4a, 0x01], "vpmovusqw xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0x4a, 0x01], "vpmovusqw xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0xca], "vpmovusqw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0xca], "vpmovusqw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0x0a], "vpmovusqw dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0x0a], "vpmovusqw dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0x4a, 0x01], "vpmovusqw dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0x4a, 0x01], "vpmovusqw dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0xca], "vpmovusqd xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0xca], "vpmovusqd xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0x0a], "vpmovusqd xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0x0a], "vpmovusqd xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0x4a, 0x01], "vpmovusqd xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0x4a, 0x01], "vpmovusqd xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x15, 0xca], "vpmovusqd ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0xca], "vpmovusqd ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0xca], "vpmovusqd ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0x0a], "vpmovusqd ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0x0a], "vpmovusqd ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0x4a, 0x01], "vpmovusqd ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0x4a, 0x01], "vpmovusqd ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0xca], "vpmovusqd xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0xca], "vpmovusqd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0x0a], "vpmovusqd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0x0a], "vpmovusqd qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0x4a, 0x01], "vpmovusqd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0x4a, 0x01], "vpmovusqd qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0xca], "vpmovswb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0xca], "vpmovswb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0x0a], "vpmovswb xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0x0a], "vpmovswb xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0x4a, 0x01], "vpmovswb xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0x4a, 0x01], "vpmovswb xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x20, 0xca], "vpmovswb ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0xca], "vpmovswb ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0xca], "vpmovswb ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0x0a], "vpmovswb ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0x0a], "vpmovswb ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0x4a, 0x01], "vpmovswb ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0x4a, 0x01], "vpmovswb ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0xca], "vpmovswb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0xca], "vpmovswb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0x0a], "vpmovswb qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0x0a], "vpmovswb qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0x4a, 0x01], "vpmovswb qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0x4a, 0x01], "vpmovswb qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0xca], "vpmovsdb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0xca], "vpmovsdb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0x0a], "vpmovsdb qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0x0a], "vpmovsdb qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0x4a, 0x01], "vpmovsdb qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0x4a, 0x01], "vpmovsdb qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0xca], "vpmovsdb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0xca], "vpmovsdb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0x0a], "vpmovsdb xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0x0a], "vpmovsdb xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0x4a, 0x01], "vpmovsdb xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0x4a, 0x01], "vpmovsdb xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0xca], "vpmovsdb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0xca], "vpmovsdb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0x0a], "vpmovsdb dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0x0a], "vpmovsdb dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0x4a, 0x01], "vpmovsdb dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0x4a, 0x01], "vpmovsdb dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0xca], "vpmovsqb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0xca], "vpmovsqb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0x0a], "vpmovsqb dword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0x0a], "vpmovsqb dword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0x4a, 0x01], "vpmovsqb dword [edx + 0x4], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0x4a, 0x01], "vpmovsqb dword [edx + 0x4]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0xca], "vpmovsqb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0xca], "vpmovsqb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0x0a], "vpmovsqb qword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0x0a], "vpmovsqb qword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0x4a, 0x01], "vpmovsqb qword [edx + 0x8], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0x4a, 0x01], "vpmovsqb qword [edx + 0x8]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0xca], "vpmovsqb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0xca], "vpmovsqb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0x0a], "vpmovsqb word [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0x0a], "vpmovsqb word [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0x4a, 0x01], "vpmovsqb word [edx + 0x2], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0x4a, 0x01], "vpmovsqb word [edx + 0x2]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0xca], "vpmovsdw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0xca], "vpmovsdw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0x0a], "vpmovsdw xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0x0a], "vpmovsdw xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0x4a, 0x01], "vpmovsdw xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0x4a, 0x01], "vpmovsdw xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x23, 0xca], "vpmovsdw ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0xca], "vpmovsdw ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0xca], "vpmovsdw ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0x0a], "vpmovsdw ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0x0a], "vpmovsdw ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0x4a, 0x01], "vpmovsdw ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0x4a, 0x01], "vpmovsdw ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0xca], "vpmovsdw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0xca], "vpmovsdw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0x0a], "vpmovsdw qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0x0a], "vpmovsdw qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0x4a, 0x01], "vpmovsdw qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0x4a, 0x01], "vpmovsdw qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0xca], "vpmovsqw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0xca], "vpmovsqw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0x0a], "vpmovsqw qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0x0a], "vpmovsqw qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0x4a, 0x01], "vpmovsqw qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0x4a, 0x01], "vpmovsqw qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0xca], "vpmovsqw xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0xca], "vpmovsqw xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0x0a], "vpmovsqw xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0x0a], "vpmovsqw xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0x4a, 0x01], "vpmovsqw xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0x4a, 0x01], "vpmovsqw xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0xca], "vpmovsqw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0xca], "vpmovsqw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0x0a], "vpmovsqw dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0x0a], "vpmovsqw dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0x4a, 0x01], "vpmovsqw dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0x4a, 0x01], "vpmovsqw dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0xca], "vpmovsqd xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0xca], "vpmovsqd xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0x0a], "vpmovsqd xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0x0a], "vpmovsqd xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0x4a, 0x01], "vpmovsqd xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0x4a, 0x01], "vpmovsqd xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x25, 0xca], "vpmovsqd ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0xca], "vpmovsqd ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0xca], "vpmovsqd ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0x0a], "vpmovsqd ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0x0a], "vpmovsqd ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0x4a, 0x01], "vpmovsqd ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0x4a, 0x01], "vpmovsqd ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0xca], "vpmovsqd xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0xca], "vpmovsqd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0x0a], "vpmovsqd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0x0a], "vpmovsqd qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0x4a, 0x01], "vpmovsqd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0x4a, 0x01], "vpmovsqd qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0xca], "vptestnmw k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0xca], "vptestnmw k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0x0a], "vptestnmw k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0x0a], "vptestnmw k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0x4a, 0x01], "vptestnmw k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0xca], "vptestnmb k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0xca], "vptestnmb k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0x0a], "vptestnmb k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0x0a], "vptestnmb k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0x4a, 0x01], "vptestnmb k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0xca], "vptestnmw k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0xca], "vptestnmw k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0x0a], "vptestnmw k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0x0a], "vptestnmw k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0x4a, 0x01], "vptestnmw k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0xca], "vptestnmw k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0xca], "vptestnmw k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0x0a], "vptestnmw k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0x0a], "vptestnmw k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0x4a, 0x01], "vptestnmw k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0xca], "vptestnmb k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0xca], "vptestnmb k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0x0a], "vptestnmb k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0x0a], "vptestnmb k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0x4a, 0x01], "vptestnmb k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0xca], "vptestnmb k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0xca], "vptestnmb k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0x0a], "vptestnmb k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0x0a], "vptestnmb k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0x4a, 0x01], "vptestnmb k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x38, 0x27, 0x0a], "vptestnmq k1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x3d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x38, 0x27, 0x4a, 0x01], "vptestnmq k1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x3d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0xca], "vptestnmq k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0xca], "vptestnmq k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0x0a], "vptestnmq k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0x4a, 0x01], "vptestnmq k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x27, 0x0a], "vptestnmd k1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x27, 0x4a, 0x01], "vptestnmd k1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0xca], "vptestnmd k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0xca], "vptestnmd k1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0x0a], "vptestnmd k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0x4a, 0x01], "vptestnmd k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x58, 0x27, 0x0a], "vptestnmq k1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x5d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x58, 0x27, 0x4a, 0x01], "vptestnmq k1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x5d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x18, 0x27, 0x0a], "vptestnmq k1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x1d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x18, 0x27, 0x4a, 0x01], "vptestnmq k1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x1d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0xca], "vptestnmq k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0xca], "vptestnmq k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0x0a], "vptestnmq k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0x4a, 0x01], "vptestnmq k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0xca], "vptestnmq k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0xca], "vptestnmq k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0x0a], "vptestnmq k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0x4a, 0x01], "vptestnmq k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x27, 0x0a], "vptestnmd k1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x27, 0x4a, 0x01], "vptestnmd k1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x27, 0x0a], "vptestnmd k1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x27, 0x4a, 0x01], "vptestnmd k1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0xca], "vptestnmd k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0xca], "vptestnmd k1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0x0a], "vptestnmd k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0x4a, 0x01], "vptestnmd k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0xca], "vptestnmd k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0xca], "vptestnmd k1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0x0a], "vptestnmd k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0x4a, 0x01], "vptestnmd k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x28, 0xca], "vpmovm2w ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x28, 0xca], "vpmovm2b ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x28, 0xca], "vpmovm2w zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x28, 0xca], "vpmovm2w xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x28, 0xca], "vpmovm2b zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xca], "vpmovm2b xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x29, 0xca], "vpmovw2m k1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xca], "vpmovb2m k1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x29, 0xca], "vpmovw2m k1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x29, 0xca], "vpmovw2m k1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x29, 0xca], "vpmovb2m k1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x29, 0xca], "vpmovb2m k1, xmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x2a, 0xca], "vpbroadcastmb2q ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x2a, 0xca], "vpbroadcastmb2q zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x2a, 0xca], "vpbroadcastmb2q xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0xca], "vpmovwb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0xca], "vpmovwb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0x0a], "vpmovwb xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0x0a], "vpmovwb xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0x4a, 0x01], "vpmovwb xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0x4a, 0x01], "vpmovwb xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x30, 0xca], "vpmovwb ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0xca], "vpmovwb ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0xca], "vpmovwb ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0x0a], "vpmovwb ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0x0a], "vpmovwb ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0x4a, 0x01], "vpmovwb ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0x4a, 0x01], "vpmovwb ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0xca], "vpmovwb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0xca], "vpmovwb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0x0a], "vpmovwb qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0x0a], "vpmovwb qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0x4a, 0x01], "vpmovwb qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0x4a, 0x01], "vpmovwb qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0xca], "vpmovdb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0xca], "vpmovdb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0x0a], "vpmovdb qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0x0a], "vpmovdb qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0x4a, 0x01], "vpmovdb qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0x4a, 0x01], "vpmovdb qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0xca], "vpmovdb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0xca], "vpmovdb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0x0a], "vpmovdb xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0x0a], "vpmovdb xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0x4a, 0x01], "vpmovdb xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0x4a, 0x01], "vpmovdb xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0xca], "vpmovdb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0xca], "vpmovdb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0x0a], "vpmovdb dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0x0a], "vpmovdb dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0x4a, 0x01], "vpmovdb dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0x4a, 0x01], "vpmovdb dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0xca], "vpmovqb xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0xca], "vpmovqb xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0x0a], "vpmovqb dword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0x0a], "vpmovqb dword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0x4a, 0x01], "vpmovqb dword [edx + 0x4], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0x4a, 0x01], "vpmovqb dword [edx + 0x4]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0xca], "vpmovqb xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0xca], "vpmovqb xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0x0a], "vpmovqb qword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0x0a], "vpmovqb qword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0x4a, 0x01], "vpmovqb qword [edx + 0x8], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0x4a, 0x01], "vpmovqb qword [edx + 0x8]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0xca], "vpmovqb xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0xca], "vpmovqb xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0x0a], "vpmovqb word [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0x0a], "vpmovqb word [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0x4a, 0x01], "vpmovqb word [edx + 0x2], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0x4a, 0x01], "vpmovqb word [edx + 0x2]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0xca], "vpmovdw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0xca], "vpmovdw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0x0a], "vpmovdw xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0x0a], "vpmovdw xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0x4a, 0x01], "vpmovdw xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0x4a, 0x01], "vpmovdw xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x33, 0xca], "vpmovdw ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0xca], "vpmovdw ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0xca], "vpmovdw ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0x0a], "vpmovdw ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0x0a], "vpmovdw ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0x4a, 0x01], "vpmovdw ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0x4a, 0x01], "vpmovdw ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0xca], "vpmovdw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0xca], "vpmovdw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0x0a], "vpmovdw qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0x0a], "vpmovdw qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0x4a, 0x01], "vpmovdw qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0x4a, 0x01], "vpmovdw qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0xca], "vpmovqw xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0xca], "vpmovqw xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0x0a], "vpmovqw qword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0x0a], "vpmovqw qword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0x4a, 0x01], "vpmovqw qword [edx + 0x8], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0x4a, 0x01], "vpmovqw qword [edx + 0x8]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0xca], "vpmovqw xmm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0xca], "vpmovqw xmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0x0a], "vpmovqw xmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0x0a], "vpmovqw xmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0x4a, 0x01], "vpmovqw xmmword [edx + 0x10], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0x4a, 0x01], "vpmovqw xmmword [edx + 0x10]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0xca], "vpmovqw xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0xca], "vpmovqw xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0x0a], "vpmovqw dword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0x0a], "vpmovqw dword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0x4a, 0x01], "vpmovqw dword [edx + 0x4], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0x4a, 0x01], "vpmovqw dword [edx + 0x4]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0xca], "vpmovqd xmm2, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0xca], "vpmovqd xmm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0x0a], "vpmovqd xmmword [edx], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0x0a], "vpmovqd xmmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0x4a, 0x01], "vpmovqd xmmword [edx + 0x10], ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0x4a, 0x01], "vpmovqd xmmword [edx + 0x10]{k5}, ymm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x35, 0xca], "vpmovqd ymm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0xca], "vpmovqd ymm2, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0xca], "vpmovqd ymm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0x0a], "vpmovqd ymmword [edx], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0x0a], "vpmovqd ymmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0x4a, 0x01], "vpmovqd ymmword [edx + 0x20], zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0x4a, 0x01], "vpmovqd ymmword [edx + 0x20]{k5}, zmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0xca], "vpmovqd xmm2, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0xca], "vpmovqd xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0x0a], "vpmovqd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0x0a], "vpmovqd qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0x4a, 0x01], "vpmovqd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0x4a, 0x01], "vpmovqd qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x38, 0xca], "vpmovm2q ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x38, 0xca], "vpmovm2d ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x38, 0xca], "vpmovm2q zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x38, 0xca], "vpmovm2q xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x38, 0xca], "vpmovm2d zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x38, 0xca], "vpmovm2d xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x28, 0x39, 0xca], "vpmovq2m k1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x39, 0xca], "vpmovd2m k1, ymm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x48, 0x39, 0xca], "vpmovq2m k1, zmm2"); test_avx_full(&[0x62, 0xf2, 0xfe, 0x08, 0x39, 0xca], "vpmovq2m k1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x39, 0xca], "vpmovd2m k1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x39, 0xca], "vpmovd2m k1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xca], "vpbroadcastmw2d zmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x3a, 0xca], "vpbroadcastmw2d xmm1, k2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0xca], "vdpbf16ps ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0xca], "vdpbf16ps ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0xca], "vdpbf16ps ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0xca], "vdpbf16ps zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0xca], "vdpbf16ps zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0xca], "vdpbf16ps zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0xca], "vdpbf16ps xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0xca], "vdpbf16ps xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0xca], "vdpbf16ps xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0xca], "vcvtneps2bf16 xmm1, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0x0a], "vcvtneps2bf16 xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xdd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x72, 0x0a], "vcvtneps2bf16 ymm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x58, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x5d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x9d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x18, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x1d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0xca], "vcvtneps2bf16 ymm1, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0x0a], "vcvtneps2bf16 ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0xca], "vcvtneps2bf16 xmm1, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0x0a], "vcvtneps2bf16 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, xmmword [edx + 0x10]"); } #[test] fn tests_f3_0f() { test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0xca], "vmovsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x0a], "vmovsd xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x4a, 0x01], "vmovsd xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0xca], "vmovsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0xca], "vmovsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x0a], "vmovsd xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0x0a], "vmovsd xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x4a, 0x01], "vmovsd xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0x4a, 0x01], "vmovsd xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0xca], "vmovsd xmm2{k5}{z}, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0xca], "vmovsd xmm2{k5}, xmm0, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x0a], "vmovsd qword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x0a], "vmovsd qword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x4a, 0x01], "vmovsd qword [edx + 0x8], xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x4a, 0x01], "vmovsd qword [edx + 0x8]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0xca], "vmovddup ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x0a], "vmovddup ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x4a, 0x01], "vmovddup ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0xca], "vmovddup ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0xca], "vmovddup ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x0a], "vmovddup ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0x0a], "vmovddup ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x4a, 0x01], "vmovddup ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0x4a, 0x01], "vmovddup ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0xca], "vmovddup zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0x0a], "vmovddup zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0x4a, 0x01], "vmovddup zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0xca], "vmovddup zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0xca], "vmovddup zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0x0a], "vmovddup zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0x0a], "vmovddup zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0x4a, 0x01], "vmovddup zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0x4a, 0x01], "vmovddup zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0xca], "vmovddup xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0x0a], "vmovddup xmm1{k5}{z}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0x4a, 0x01], "vmovddup xmm1{k5}{z}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0xca], "vmovddup xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0xca], "vmovddup xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0x0a], "vmovddup xmm1, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0x0a], "vmovddup xmm1{k5}, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0x4a, 0x01], "vmovddup xmm1, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0x4a, 0x01], "vmovddup xmm1{k5}, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0x4a, 0x01], "vcvtsi2sd xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2c, 0xca], "vcvttsd2si ecx{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0x0a], "vcvttsd2si ecx, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0x4a, 0x01], "vcvttsd2si ecx, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x2d, 0xca], "vcvtsd2si ecx{rz-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x2d, 0xca], "vcvtsd2si ecx{rd-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0x0a], "vcvtsd2si ecx, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0x4a, 0x01], "vcvtsd2si ecx, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x2d, 0xca], "vcvtsd2si ecx{ru-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x2d, 0xca], "vcvtsd2si ecx{rne-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x51, 0xca], "vsqrtsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0xca], "vsqrtsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0x0a], "vsqrtsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0x4a, 0x01], "vsqrtsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0xca], "vsqrtsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0xca], "vsqrtsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x0a], "vsqrtsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x4a, 0x01], "vsqrtsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x4a, 0x01], "vsqrtsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x51, 0xca], "vsqrtsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x51, 0xca], "vsqrtsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x51, 0xca], "vsqrtsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x58, 0xca], "vaddsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x58, 0xca], "vaddsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x58, 0xca], "vaddsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x58, 0xca], "vaddsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0xca], "vaddsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0x0a], "vaddsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0x4a, 0x01], "vaddsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0xca], "vaddsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0xca], "vaddsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0x0a], "vaddsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0x0a], "vaddsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0x4a, 0x01], "vaddsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0x4a, 0x01], "vaddsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x58, 0xca], "vaddsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x58, 0xca], "vaddsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x58, 0xca], "vaddsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x58, 0xca], "vaddsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x59, 0xca], "vmulsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x59, 0xca], "vmulsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x59, 0xca], "vmulsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x59, 0xca], "vmulsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0xca], "vmulsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0x0a], "vmulsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0x4a, 0x01], "vmulsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0xca], "vmulsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0xca], "vmulsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0x0a], "vmulsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0x0a], "vmulsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0x4a, 0x01], "vmulsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0x4a, 0x01], "vmulsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x59, 0xca], "vmulsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x59, 0xca], "vmulsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x59, 0xca], "vmulsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x59, 0xca], "vmulsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5a, 0xca], "vcvtsd2ss xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5a, 0xca], "vcvtsd2ss xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5a, 0xca], "vcvtsd2ss xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5a, 0xca], "vcvtsd2ss xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5c, 0xca], "vsubsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5c, 0xca], "vsubsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5c, 0xca], "vsubsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5c, 0xca], "vsubsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0xca], "vsubsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0x0a], "vsubsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0x4a, 0x01], "vsubsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0xca], "vsubsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0xca], "vsubsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0x0a], "vsubsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0x0a], "vsubsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0x4a, 0x01], "vsubsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0x4a, 0x01], "vsubsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5c, 0xca], "vsubsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5c, 0xca], "vsubsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5c, 0xca], "vsubsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5c, 0xca], "vsubsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5d, 0xca], "vminsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5d, 0xca], "vminsd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5d, 0xca], "vminsd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0xca], "vminsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0x0a], "vminsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0x4a, 0x01], "vminsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0xca], "vminsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0xca], "vminsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0x0a], "vminsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0x0a], "vminsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0x4a, 0x01], "vminsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0x4a, 0x01], "vminsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5e, 0xca], "vdivsd xmm1{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5e, 0xca], "vdivsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x5e, 0xca], "vdivsd xmm1{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x5e, 0xca], "vdivsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0xca], "vdivsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0x0a], "vdivsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0x4a, 0x01], "vdivsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0xca], "vdivsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0xca], "vdivsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0x0a], "vdivsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0x0a], "vdivsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0x4a, 0x01], "vdivsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0x4a, 0x01], "vdivsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x5e, 0xca], "vdivsd xmm1{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x5e, 0xca], "vdivsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x5e, 0xca], "vdivsd xmm1{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x5e, 0xca], "vdivsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x5f, 0xca], "vmaxsd xmm1{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x5f, 0xca], "vmaxsd xmm1{k5}{sae}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x0a], "vmaxsd xmm1{k5}{z}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x4a, 0x01], "vmaxsd xmm1{k5}{z}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0xca], "vmaxsd xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0xca], "vmaxsd xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0x0a], "vmaxsd xmm1, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0x0a], "vmaxsd xmm1{k5}, xmm0, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0x4a, 0x01], "vmaxsd xmm1, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0x4a, 0x01], "vmaxsd xmm1{k5}, xmm0, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0xca], "vmovdqu16 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0xca], "vmovdqu16 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0xca], "vmovdqu16 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0x0a], "vmovdqu16 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0xca], "vmovdqu8 ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0xca], "vmovdqu8 ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0xca], "vmovdqu8 ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0x0a], "vmovdqu8 ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0xca], "vmovdqu16 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0xca], "vmovdqu16 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0xca], "vmovdqu16 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0x0a], "vmovdqu16 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0xca], "vmovdqu16 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0x0a], "vmovdqu16 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0xca], "vmovdqu8 zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0xca], "vmovdqu8 zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0xca], "vmovdqu8 zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0x0a], "vmovdqu8 zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0xca], "vmovdqu8 xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0x0a], "vmovdqu8 xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}{z}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}{z}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1{k5}{z}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0xca, 0xcc], "vpshuflw ymm1, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}, ymm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0x0a, 0xcc], "vpshuflw ymm1, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}, ymmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1{k5}, ymmword [edx + 0x20], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}{z}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}{z}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1{k5}{z}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0xca, 0xcc], "vpshuflw zmm1, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}, zmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0x0a, 0xcc], "vpshuflw zmm1, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}, zmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1{k5}, zmmword [edx + 0x40], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}{z}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}{z}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1{k5}{z}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0xca, 0xcc], "vpshuflw xmm1, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0x0a, 0xcc], "vpshuflw xmm1, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}, xmmword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1{k5}, xmmword [edx + 0x10], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x78, 0xca], "vcvttsd2usi ecx{sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0xca], "vcvttsd2usi ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0x0a], "vcvttsd2usi ecx, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0x4a, 0x01], "vcvttsd2usi ecx, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x79, 0xca], "vcvtsd2usi ecx{rz-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x79, 0xca], "vcvtsd2usi ecx{rd-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0xca], "vcvtsd2usi ecx, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0x0a], "vcvtsd2usi ecx, qword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0x4a, 0x01], "vcvtsd2usi ecx, qword [edx + 0x8]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x79, 0xca], "vcvtsd2usi ecx{ru-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x79, 0xca], "vcvtsd2usi ecx{rne-sae}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x7a, 0xca], "vcvtuqq2ps ymm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0xca], "vcvtuqq2ps ymm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0xca], "vcvtuqq2ps xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0x0a], "vcvtuqq2ps xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xfd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x78, 0x7a, 0xca], "vcvtudq2ps zmm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x7d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}{z}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0xca], "vcvtudq2ps zmm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0x0a], "vcvtudq2ps ymm1, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0xca], "vcvtudq2ps ymm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0x0a], "vcvtudq2ps ymm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0xca], "vcvtuqq2ps ymm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0x0a], "vcvtuqq2ps ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0xca], "vcvtuqq2ps ymm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0xca], "vcvtuqq2ps ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0x0a], "vcvtuqq2ps ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0xca], "vcvtuqq2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0x0a], "vcvtuqq2ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}{z}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0xca], "vcvtudq2ps zmm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0x0a], "vcvtudq2ps zmm1, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}{z}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0xca], "vcvtudq2ps zmm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0x0a], "vcvtudq2ps xmm1, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0xca], "vcvtudq2ps zmm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0x0a], "vcvtudq2ps zmm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0xca], "vcvtudq2ps xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0x0a], "vcvtudq2ps xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, edx"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, dword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x4a, 0x01], "vcvtusi2sd xmm1, xmm0, dword [edx + 0x4]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0x7f, 0xca], "vmovdqu16 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0xca], "vmovdqu16 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0xca], "vmovdqu16 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0x0a], "vmovdqu16 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0x0a], "vmovdqu16 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu16 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu16 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xad, 0x7f, 0xca], "vmovdqu8 ymm2{k5}{z}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0xca], "vmovdqu8 ymm2, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0xca], "vmovdqu8 ymm2{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0x0a], "vmovdqu8 ymmword [edx], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0x0a], "vmovdqu8 ymmword [edx]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu8 ymmword [edx + 0x20], ymm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu8 ymmword [edx + 0x20]{k5}, ymm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0x7f, 0xca], "vmovdqu16 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0xca], "vmovdqu16 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0xca], "vmovdqu16 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0x0a], "vmovdqu16 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0x0a], "vmovdqu16 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu16 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu16 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0xca], "vmovdqu16 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0x0a], "vmovdqu16 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0x0a], "vmovdqu16 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu16 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu16 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0xcd, 0x7f, 0xca], "vmovdqu8 zmm2{k5}{z}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0xca], "vmovdqu8 zmm2, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0xca], "vmovdqu8 zmm2{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0x0a], "vmovdqu8 zmmword [edx], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0x0a], "vmovdqu8 zmmword [edx]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu8 zmmword [edx + 0x40], zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu8 zmmword [edx + 0x40]{k5}, zmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x8d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}{z}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0xca], "vmovdqu8 xmm2, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0x0a], "vmovdqu8 xmmword [edx], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0x0a], "vmovdqu8 xmmword [edx]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu8 xmmword [edx + 0x10], xmm1"); test_avx_full(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu8 xmmword [edx + 0x10]{k5}, xmm1"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xc2, 0xca, 0xcc], "vcmpsd k1{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}{sae}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0xca, 0xcc], "vcmpsd k1, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}, xmm0, xmm2, 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x0a, 0xcc], "vcmpsd k1, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpsd k1{k5}, xmm0, qword [edx], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpsd k1, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpsd k1{k5}, xmm0, qword [edx + 0x8], 0xcc"); test_avx_full(&[0x62, 0xf1, 0xff, 0xfd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x78, 0xe6, 0xca], "vcvtpd2dq ymm1{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x7d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rz-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0xca], "vcvtpd2dq ymm1{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rd-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0xca], "vcvtpd2dq xmm1, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, ymm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0x0a], "vcvtpd2dq xmm1, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, ymmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}{z}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0xca], "vcvtpd2dq ymm1{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{ru-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0x0a], "vcvtpd2dq ymm1, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0xca], "vcvtpd2dq ymm1{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rne-sae}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}{z}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0xca], "vcvtpd2dq ymm1, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}, zmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0x0a], "vcvtpd2dq ymm1, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, zmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0xca], "vcvtpd2dq xmm1, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, xmm2"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0x0a], "vcvtpd2dq xmm1, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, xmmword [edx]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, xmmword [edx + 0x10]"); } #[test] fn tests_f3_0f38() { test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x52, 0x0a], "vp4dpwssd zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x52, 0x0a], "vp4dpwssd zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x52, 0x0a], "vp4dpwssd zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x53, 0x0a], "vp4dpwssds zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x53, 0x0a], "vp4dpwssds zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x53, 0x0a], "vp4dpwssds zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x38, 0x68, 0x0a], "vp2intersectq k1, ymm0, qword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x38, 0x68, 0x4a, 0x01], "vp2intersectq k1, ymm0, qword [edx + 0x8]{1to4}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0xca], "vp2intersectq k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x0a], "vp2intersectq k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x4a, 0x01], "vp2intersectq k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x68, 0x0a], "vp2intersectd k1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x68, 0x4a, 0x01], "vp2intersectd k1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0xca], "vp2intersectd k1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0x0a], "vp2intersectd k1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0x4a, 0x01], "vp2intersectd k1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x58, 0x68, 0x0a], "vp2intersectq k1, zmm0, qword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x58, 0x68, 0x4a, 0x01], "vp2intersectq k1, zmm0, qword [edx + 0x8]{1to8}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x0a], "vp2intersectq k1, xmm0, qword [edx]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x4a, 0x01], "vp2intersectq k1, xmm0, qword [edx + 0x8]{1to2}"); test_avx_full(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0xca], "vp2intersectq k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0x0a], "vp2intersectq k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0x4a, 0x01], "vp2intersectq k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0xca], "vp2intersectq k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x0a], "vp2intersectq k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x4a, 0x01], "vp2intersectq k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x68, 0x0a], "vp2intersectd k1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x68, 0x4a, 0x01], "vp2intersectd k1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x68, 0x0a], "vp2intersectd k1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x68, 0x4a, 0x01], "vp2intersectd k1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0xca], "vp2intersectd k1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0x0a], "vp2intersectd k1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0x4a, 0x01], "vp2intersectd k1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x0a], "vp2intersectd k1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x4a, 0x01], "vp2intersectd k1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xbd, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xbd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x3d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, dword [edx]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x38, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x3d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}, ymm0, dword [edx + 0x4]{1to8}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0xca], "vcvtne2ps2bf16 ymm1, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymmword [edx + 0x20]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x5d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, dword [edx]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x58, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x5d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}, zmm0, dword [edx + 0x4]{1to16}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x9d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x9d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x1d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, dword [edx]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x18, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x1d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}, xmm0, dword [edx + 0x4]{1to4}"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0xca], "vcvtne2ps2bf16 zmm1, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmmword [edx + 0x40]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0xca], "vcvtne2ps2bf16 xmm1, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmm2"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x9a, 0x0a], "v4fmaddps zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x0a], "v4fmaddps zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x9a, 0x0a], "v4fmaddps zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x9b, 0x0a], "v4fmaddss xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x9b, 0x0a], "v4fmaddss xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x9b, 0x0a], "v4fmaddss xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1{k5}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}{z}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xcd, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1{k5}{z}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x0a], "v4fnmaddps zmm1, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}, zmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x4d, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1{k5}, zmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0xab, 0x0a], "v4fnmaddss xmm1{k5}{z}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0xad, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1{k5}{z}, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x0a], "v4fnmaddss xmm1, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x0a], "v4fnmaddss xmm1{k5}, xmm0, xmmword [edx]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1, xmm0, xmmword [edx + 0x10]"); test_avx_full(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1{k5}, xmm0, xmmword [edx + 0x10]"); } yaxpeax-x86-1.2.2/test/protected_mode/mod.rs000064400000000000000000006012241046102023000170360ustar 00000000000000mod regspec; mod operand; mod opcode; #[cfg(feature="fmt")] mod display; mod evex_generated; use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, LengthedInstruction}; use yaxpeax_x86::protected_mode::InstDecoder; fn test_invalid(data: &[u8]) { test_invalid_under(&InstDecoder::default(), data); } fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) { let mut reader = yaxpeax_arch::U8Reader::new(data); if let Ok(inst) = decoder.decode(&mut reader) { // realistically, the chances an error only shows up under non-fmt builds seems unlikely, // but try to report *something* in such cases. cfg_if::cfg_if! { if #[cfg(feature="fmt")] { panic!("decoded {:?} from {:02x?} under decoder {}", inst.opcode(), data, decoder); } else { // don't warn about the unused inst here let _ = inst; panic!("decoded instruction from {:02x?} under decoder ", data); } } } else { // this is fine } } fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), data, expected); } fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = yaxpeax_arch::U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { let text = format!("{}", instr); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); } else { eprintln!("non-fmt build cannot compare text equality") } } // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u32.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } #[test] fn test_modrm_decode() { // just modrm test_display(&[0x33, 0x08], "xor ecx, dword [eax]"); test_display(&[0x33, 0x20], "xor esp, dword [eax]"); test_display(&[0x33, 0x05, 0x78, 0x56, 0x34, 0x12], "xor eax, dword [0x12345678]"); test_display(&[0x33, 0x41, 0x23], "xor eax, dword [ecx + 0x23]"); test_display(&[0x33, 0x81, 0x23, 0x01, 0x65, 0x43], "xor eax, dword [ecx + 0x43650123]"); test_display(&[0x33, 0xc1], "xor eax, ecx"); // sib test_display(&[0x33, 0x04, 0x0a], "xor eax, dword [edx + ecx * 1]"); test_display(&[0x33, 0x04, 0x4a], "xor eax, dword [edx + ecx * 2]"); test_display(&[0x33, 0x04, 0x8a], "xor eax, dword [edx + ecx * 4]"); test_display(&[0x33, 0x04, 0xca], "xor eax, dword [edx + ecx * 8]"); test_display(&[0x33, 0x04, 0x20], "xor eax, dword [eax]"); test_display(&[0x33, 0x04, 0x60], "xor eax, dword [eax]"); test_display(&[0x33, 0x04, 0xa0], "xor eax, dword [eax]"); test_display(&[0x33, 0x04, 0xe0], "xor eax, dword [eax]"); test_display(&[0x33, 0x04, 0x25, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); test_display(&[0x33, 0x44, 0x65, 0x11], "xor eax, dword [ebp + 0x11]"); test_display(&[0x33, 0x84, 0xa5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [ebp + 0x44332211]"); test_display(&[0x33, 0x04, 0xe5, 0x11, 0x22, 0x33, 0x44], "xor eax, dword [0x44332211]"); // specifically sib with base == 0b101 // mod bits 00 test_display(&[0x33, 0x34, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [0x50403020]"); // mod bits 01 test_display(&[0x33, 0x74, 0x25, 0x20], "xor esi, dword [ebp + 0x20]"); // mod bits 10 test_display(&[0x33, 0xb4, 0x25, 0x20, 0x30, 0x40, 0x50], "xor esi, dword [ebp + 0x50403020]"); } #[test] fn test_mmx() { test_display(&[0x0f, 0xf7, 0xc1], "maskmovq mm0, mm1"); test_invalid(&[0x0f, 0xf7, 0x01]); test_display(&[0x0f, 0xe7, 0x03], "movntq qword [ebx], mm0"); test_invalid(&[0x0f, 0xe7, 0xc3]); test_invalid(&[0x66, 0x0f, 0xc3, 0x03]); test_display(&[0x0f, 0xc3, 0x03], "movnti dword [ebx], eax"); test_invalid(&[0x0f, 0xc3, 0xc3]); test_display(&[0x0f, 0x7e, 0xcf], "movd edi, mm1"); test_display(&[0x0f, 0x7f, 0xcf], "movq mm7, mm1"); test_display(&[0x0f, 0x7f, 0x0f], "movq qword [edi], mm1"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, eax, 0x14"); test_display(&[0x0f, 0xc4, 0x00, 0x14], "pinsrw mm0, word [eax], 0x14"); test_display(&[0x0f, 0xd1, 0xcf], "psrlw mm1, mm7"); test_display(&[0x0f, 0xd1, 0x00], "psrlw mm0, qword [eax]"); test_invalid(&[0x0f, 0xd7, 0x00]); test_display(&[0x0f, 0xd7, 0xcf], "pmovmskb ecx, mm7"); test_display(&[0x0f, 0x3a, 0x0f, 0xc1, 0x23], "palignr mm0, mm1, 0x23"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfd, 0xd2], "paddw mm2, mm2"); test_display(&[0x0f, 0x6f, 0xe9], "movq mm5, mm1"); test_display(&[0x0f, 0xe5, 0x3d, 0xaa, 0xbb, 0xcc, 0x77], "pmulhw mm7, qword [0x77ccbbaa]"); test_display(&[0x0f, 0x38, 0x00, 0xda], "pshufb mm3, mm2"); test_display(&[0x0f, 0x74, 0xc2], "pcmpeqb mm0, mm2"); test_display(&[0x0f, 0x75, 0xc2], "pcmpeqw mm0, mm2"); test_display(&[0x0f, 0x76, 0xc2], "pcmpeqd mm0, mm2"); test_display(&[0x66, 0x0f, 0xc5, 0xd8, 0xff], "pextrw ebx, xmm0, 0xff"); test_invalid(&[0x66, 0x0f, 0xc5, 0x08, 0xff]); test_display(&[0x0f, 0xc5, 0xd1, 0x00], "pextrw edx, mm1, 0x0"); test_invalid(&[0x0f, 0xc5, 0x01, 0x00]); test_display(&[0x0f, 0xd8, 0xc2], "psubusb mm0, mm2"); test_display(&[0x0f, 0xd9, 0xc2], "psubusw mm0, mm2"); test_display(&[0x0f, 0xda, 0xc2], "pminub mm0, mm2"); test_display(&[0x0f, 0xdb, 0xc2], "pand mm0, mm2"); test_display(&[0x0f, 0xdc, 0xc2], "paddusb mm0, mm2"); test_display(&[0x0f, 0xdd, 0xc2], "paddusw mm0, mm2"); test_display(&[0x0f, 0xde, 0xc2], "pmaxub mm0, mm2"); test_display(&[0x0f, 0xdf, 0xc2], "pandn mm0, mm2"); test_display(&[0x0f, 0xe8, 0xc2], "psubsb mm0, mm2"); test_display(&[0x0f, 0xe9, 0xc2], "psubsw mm0, mm2"); test_display(&[0x0f, 0xea, 0xc2], "pminsw mm0, mm2"); test_display(&[0x0f, 0xeb, 0xc2], "por mm0, mm2"); test_display(&[0x0f, 0xec, 0xc2], "paddsb mm0, mm2"); test_display(&[0x0f, 0xed, 0xc2], "paddsw mm0, mm2"); test_display(&[0x0f, 0xee, 0xc2], "pmaxsw mm0, mm2"); test_display(&[0x0f, 0xef, 0xc2], "pxor mm0, mm2"); test_invalid(&[0x0f, 0xf0, 0xc2]); test_display(&[0x0f, 0xf1, 0xc2], "psllw mm0, mm2"); test_display(&[0x0f, 0xf2, 0xc2], "pslld mm0, mm2"); test_display(&[0x0f, 0xf3, 0xc2], "psllq mm0, mm2"); test_display(&[0x0f, 0xf4, 0xc2], "pmuludq mm0, mm2"); test_display(&[0x0f, 0xf5, 0xc2], "pmaddwd mm0, mm2"); test_display(&[0x0f, 0xf6, 0xc2], "psadbw mm0, mm2"); test_display(&[0x0f, 0xf8, 0xc2], "psubb mm0, mm2"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfa, 0xc2], "psubd mm0, mm2"); test_display(&[0x0f, 0xfb, 0xc2], "psubq mm0, mm2"); test_display(&[0x0f, 0xfc, 0xc2], "paddb mm0, mm2"); test_display(&[0x0f, 0xfc, 0x02], "paddb mm0, qword [edx]"); test_display(&[0x0f, 0xfd, 0xc2], "paddw mm0, mm2"); test_display(&[0x0f, 0xfe, 0xc2], "paddd mm0, mm2"); test_display(&[0x0f, 0xf1, 0x02], "psllw mm0, qword [edx]"); test_display(&[0x0f, 0xf2, 0x02], "pslld mm0, qword [edx]"); test_display(&[0x0f, 0xf3, 0x02], "psllq mm0, qword [edx]"); test_display(&[0x0f, 0xf4, 0x02], "pmuludq mm0, qword [edx]"); test_display(&[0x0f, 0xf5, 0x02], "pmaddwd mm0, qword [edx]"); test_display(&[0x0f, 0xf6, 0x02], "psadbw mm0, qword [edx]"); test_display(&[0x0f, 0xf8, 0x02], "psubb mm0, qword [edx]"); test_display(&[0x0f, 0xf9, 0x02], "psubw mm0, qword [edx]"); test_display(&[0x0f, 0xfa, 0x02], "psubd mm0, qword [edx]"); test_display(&[0x0f, 0xfb, 0x02], "psubq mm0, qword [edx]"); test_display(&[0x0f, 0xfc, 0x02], "paddb mm0, qword [edx]"); test_display(&[0x0f, 0xfd, 0x02], "paddw mm0, qword [edx]"); test_display(&[0x0f, 0xfe, 0x02], "paddd mm0, qword [edx]"); } #[test] fn test_cvt() { test_display(&[0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm7"); test_display(&[0x0f, 0x2a, 0xcf], "cvtpi2ps xmm1, mm7"); test_display(&[0x0f, 0x2a, 0x00], "cvtpi2ps xmm0, qword [eax]"); test_display(&[0x66, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm0, qword [eax]"); test_display(&[0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_display(&[0xf2, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm0, dword [eax]"); test_display(&[0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_display(&[0xf3, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm0, dword [eax]"); test_display(&[0xf3, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm1, edi"); } #[test] fn test_aesni() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_aesni(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [edi]"); test_instr(&[0x67, 0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [bx]"); test_instr(&[0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [edi]"); test_instr(&[0x67, 0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [bx]"); test_instr(&[0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [edi]"); test_instr(&[0x67, 0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [bx]"); test_instr(&[0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [edi]"); test_instr(&[0x67, 0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [bx]"); test_instr(&[0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [edi]"); test_instr(&[0x67, 0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [bx]"); test_instr(&[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], "aeskeygenassist xmm1, xmmword [edi], 0xaa"); } #[test] fn test_sse2() { fn test_instr(bytes: &[u8], text: &'static str) { // sse and sse2 are part of amd64, so x86_64, meaning even the minimal decoder must support // them. test_display_under(&InstDecoder::minimal(), bytes, text); } test_instr(&[0xf2, 0x0f, 0x10, 0x0c, 0xc7], "movsd xmm1, qword [edi + eax * 8]"); test_instr(&[0xf2, 0x0f, 0x11, 0x0c, 0xc7], "movsd qword [edi + eax * 8], xmm1"); test_instr(&[0x66, 0x0f, 0x11, 0x0c, 0xc7], "movupd xmmword [edi + eax * 8], xmm1"); test_instr(&[0x66, 0x0f, 0x12, 0x03], "movlpd xmm0, qword [ebx]"); // reg-mem is movlpd test_instr(&[0x66, 0x0f, 0x13, 0x03], "movlpd qword [ebx], xmm0"); test_invalid(&[0x66, 0x0f, 0x13, 0xc3]); test_instr(&[0x66, 0x0f, 0x14, 0x03], "unpcklpd xmm0, xmmword [ebx]"); test_instr(&[0x66, 0x0f, 0x14, 0xc3], "unpcklpd xmm0, xmm3"); test_instr(&[0x66, 0x0f, 0x15, 0x03], "unpckhpd xmm0, xmmword [ebx]"); test_instr(&[0x66, 0x0f, 0x15, 0xc3], "unpckhpd xmm0, xmm3"); test_instr(&[0x66, 0x0f, 0x16, 0x03], "movhpd xmm0, qword [ebx]"); test_invalid(&[0x66, 0x0f, 0x16, 0xc3]); test_instr(&[0x66, 0x0f, 0x17, 0x03], "movhpd qword [ebx], xmm0"); test_invalid(&[0x66, 0x0f, 0x17, 0xc3]); test_instr(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); test_instr(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]"); test_instr(&[0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_instr(&[0x66, 0x0f, 0x2a, 0x0f], "cvtpi2pd xmm1, qword [edi]"); test_instr(&[0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_instr(&[0xf2, 0x0f, 0x2a, 0x0f], "cvtsi2sd xmm1, dword [edi]"); test_instr(&[0x66, 0x0f, 0x2b, 0x0f], "movntpd xmmword [edi], xmm1"); test_instr(&[0x66, 0x0f, 0x2c, 0xcf], "cvttpd2pi mm1, xmm7"); test_instr(&[0x66, 0x0f, 0x2c, 0x0f], "cvttpd2pi mm1, xmmword [edi]"); test_instr(&[0xf2, 0x0f, 0x2c, 0xcf], "cvttsd2si ecx, xmm7"); test_instr(&[0xf2, 0x0f, 0x2c, 0x0f], "cvttsd2si ecx, qword [edi]"); test_instr(&[0x66, 0x0f, 0x2d, 0xcf], "cvtpd2pi mm1, xmm7"); test_instr(&[0x66, 0x0f, 0x2d, 0x0f], "cvtpd2pi mm1, xmmword [edi]"); test_instr(&[0xf2, 0x0f, 0x2d, 0xcf], "cvtsd2si ecx, xmm7"); test_instr(&[0xf2, 0x0f, 0x2d, 0x0f], "cvtsd2si ecx, qword [edi]"); test_instr(&[0x66, 0x0f, 0x2e, 0xcf], "ucomisd xmm1, xmm7"); test_instr(&[0x66, 0x0f, 0x2e, 0x0f], "ucomisd xmm1, qword [edi]"); test_instr(&[0x66, 0x0f, 0x2f, 0xcf], "comisd xmm1, xmm7"); test_instr(&[0x66, 0x0f, 0x2f, 0x0f], "comisd xmm1, qword [edi]"); /* * .... 660f38 * .... 660f7f */ test_invalid(&[0x66, 0x0f, 0x50, 0x01]); test_instr(&[0x66, 0x0f, 0x50, 0xc1], "movmskpd eax, xmm1"); test_instr(&[0x66, 0x0f, 0x51, 0x01], "sqrtpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x51, 0x01], "sqrtsd xmm0, qword [ecx]"); test_invalid(&[0x66, 0x0f, 0x52, 0x01]); test_invalid(&[0x66, 0x0f, 0x53, 0x01]); test_instr(&[0x66, 0x0f, 0x54, 0x01], "andpd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0x55, 0x01], "andnpd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0x56, 0x01], "orpd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0x57, 0x01], "xorpd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0x58, 0x01], "addpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x58, 0x01], "addsd xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x59, 0x01], "mulpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x59, 0x01], "mulsd xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x5a, 0x01], "cvtpd2ps xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x5a, 0x01], "cvtsd2ss xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x5b, 0x01], "cvtps2dq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0x5c, 0x01], "subpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x5c, 0x01], "subsd xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x5d, 0x01], "minpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x5d, 0x01], "minsd xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x5e, 0x01], "divpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x5e, 0x01], "divsd xmm0, qword [ecx]"); test_instr(&[0x66, 0x0f, 0x5f, 0x01], "maxpd xmm0, xmmword [ecx]"); test_instr(&[0xf2, 0x0f, 0x5f, 0x01], "maxsd xmm0, qword [ecx]"); test_instr( &[0x66, 0x0f, 0x60, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklbw xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x61, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklwd xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x62, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckldq xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x63, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packsswb xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x64, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtb xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x65, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtw xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x66, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "pcmpgtd xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x67, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packuswb xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x68, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhbw xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x69, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhwd xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6a, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhdq xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6b, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "packssdw xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6c, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpcklqdq xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6d, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "punpckhqdq xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6e, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movd xmm3, dword [esp + ebx * 4 - 0x334455cc]" ); test_instr( &[0x66, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqa xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_instr(&[0x66, 0x0f, 0x6e, 0xc0], "movd xmm0, eax"); test_instr(&[0x66, 0x0f, 0x70, 0xc0, 0x4e], "pshufd xmm0, xmm0, 0x4e"); test_instr(&[0xf2, 0x0f, 0x70, 0xc0, 0x4e], "pshuflw xmm0, xmm0, 0x4e"); test_instr(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_invalid(&[0x66, 0x0f, 0x71, 0x10, 0x8f]); test_instr(&[0x66, 0x0f, 0x71, 0xd0, 0x8f], "psrlw xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x71, 0x20, 0x8f]); test_instr(&[0x66, 0x0f, 0x71, 0xe0, 0x8f], "psraw xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x71, 0x30, 0x8f]); test_instr(&[0x66, 0x0f, 0x71, 0xf0, 0x8f], "psllw xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x72, 0x10, 0x8f]); test_instr(&[0x66, 0x0f, 0x72, 0xd0, 0x8f], "psrld xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x72, 0x20, 0x8f]); test_instr(&[0x66, 0x0f, 0x72, 0xe0, 0x8f], "psrad xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x72, 0x30, 0x8f]); test_instr(&[0x66, 0x0f, 0x72, 0xf0, 0x8f], "pslld xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x73, 0x10, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x18, 0x8f]); test_instr(&[0x66, 0x0f, 0x73, 0xd0, 0x8f], "psrlq xmm0, 0x8f"); test_instr(&[0x66, 0x0f, 0x73, 0xd8, 0x8f], "psrldq xmm0, 0x8f"); test_invalid(&[0x66, 0x0f, 0x73, 0x30, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x38, 0x8f]); test_instr(&[0x66, 0x0f, 0x73, 0xf0, 0x8f], "psllq xmm0, 0x8f"); test_instr(&[0x66, 0x0f, 0x73, 0xf8, 0x8f], "pslldq xmm0, 0x8f"); test_instr(&[0x66, 0x0f, 0x7e, 0xc1], "movd ecx, xmm0"); test_instr(&[0x66, 0x0f, 0x7e, 0x01], "movd dword [ecx], xmm0"); test_instr( &[0x66, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqa xmmword [esp + ebx * 4 - 0x334455cc], xmm3" ); test_instr(&[0x66, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x0f, 0xc2, 0x03, 0x08], "cmppd xmm0, xmmword [ebx], 0x8"); test_instr(&[0xf2, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm0, xmm3, 0x8"); test_instr(&[0xf2, 0x0f, 0xc2, 0x03, 0x08], "cmpsd xmm0, qword [ebx], 0x8"); test_instr(&[0x66, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm0, ebx, 0x8"); test_instr(&[0x66, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm0, word [ebx], 0x8"); // test_instr(&[0x66, 0x0f, 0xc5, 0xc3, 0x08], "pextrw eax, xmm3, 0x8"); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x03, 0x08]); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x40, 0x08]); // test_instr_invalid(&[0x66, 0x0f, 0xc5, 0x80, 0x08]); test_instr(&[0x66, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm0, xmmword [ebx], 0x8"); test_instr(&[0x66, 0x0f, 0xc6, 0xc3, 0x08], "shufpd xmm0, xmm3, 0x8"); test_instr(&[0x66, 0x0f, 0xd1, 0xc1], "psrlw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd1, 0x01], "psrlw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd2, 0xc1], "psrld xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd2, 0x01], "psrld xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd3, 0xc1], "psrlq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd3, 0x01], "psrlq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd4, 0xc1], "paddq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd4, 0x01], "paddq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd5, 0xc1], "pmullw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd5, 0x01], "pmullw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd6, 0xc1], "movq xmm1, xmm0"); test_instr(&[0x66, 0x0f, 0xd6, 0x01], "movq qword [ecx], xmm0"); test_invalid(&[0xf3, 0x0f, 0xd6, 0x03]); test_instr(&[0xf3, 0x0f, 0xd6, 0xc3], "movq2dq xmm0, mm3"); test_instr(&[0xf2, 0x0f, 0xd6, 0xc3], "movdq2q mm0, xmm3"); test_instr(&[0x66, 0x0f, 0xd7, 0xc1], "pmovmskb eax, xmm1"); test_invalid(&[0x66, 0x0f, 0xd7, 0x01]); test_instr(&[0x66, 0x0f, 0xd8, 0xc1], "psubusb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd8, 0x01], "psubusb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xd9, 0xc1], "psubusw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xd9, 0x01], "psubusw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xda, 0xc1], "pminub xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xda, 0x01], "pminub xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xdb, 0xc1], "pand xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdb, 0x01], "pand xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xdc, 0xc1], "paddusb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdc, 0x01], "paddusb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xdd, 0xc1], "paddusw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdd, 0x01], "paddusw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xde, 0xc1], "pmaxub xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xde, 0x01], "pmaxub xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xdf, 0xc1], "pandn xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xdf, 0x01], "pandn xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe0, 0xc1], "pavgb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe0, 0x01], "pavgb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe1, 0xc1], "psraw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe1, 0x01], "psraw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe2, 0xc1], "psrad xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe2, 0x01], "psrad xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe3, 0xc1], "pavgw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe3, 0x01], "pavgw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe4, 0xc1], "pmulhuw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe4, 0x01], "pmulhuw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe5, 0xc1], "pmulhw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe5, 0x01], "pmulhw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe6, 0xc1], "cvttpd2dq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe6, 0x01], "cvttpd2dq xmm0, xmmword [ecx]"); test_invalid(&[0x66, 0x0f, 0xe7, 0xc1]); test_instr(&[0x66, 0x0f, 0xe7, 0x01], "movntdq xmmword [ecx], xmm0"); test_instr(&[0x66, 0x0f, 0xe8, 0xc1], "psubsb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe8, 0x01], "psubsb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xe9, 0xc1], "psubsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xe9, 0x01], "psubsw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xea, 0xc1], "pminsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xea, 0x01], "pminsw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc3], "por xmm0, xmm3"); test_instr(&[0x66, 0x0f, 0xeb, 0xc4], "por xmm0, xmm4"); test_instr(&[0x66, 0x0f, 0xeb, 0xd3], "por xmm2, xmm3"); test_instr(&[0x66, 0x0f, 0xeb, 0x12], "por xmm2, xmmword [edx]"); test_instr(&[0x66, 0x0f, 0xeb, 0xc1], "por xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xeb, 0x01], "por xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xec, 0xc1], "paddsb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xec, 0x01], "paddsb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xed, 0xc1], "paddsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xed, 0x01], "paddsw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xee, 0xc1], "pmaxsw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xee, 0x01], "pmaxsw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xef, 0xc1], "pxor xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xef, 0x01], "pxor xmm0, xmmword [ecx]"); test_invalid(&[0x66, 0x0f, 0xf0, 0xc1]); test_invalid(&[0x66, 0x0f, 0xf0, 0x01]); test_instr(&[0x66, 0x0f, 0xf1, 0xc1], "psllw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf1, 0x01], "psllw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf2, 0xc1], "pslld xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf2, 0x01], "pslld xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf3, 0xc1], "psllq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf3, 0x01], "psllq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf4, 0xc1], "pmuludq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf4, 0x01], "pmuludq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf5, 0xc1], "pmaddwd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf5, 0x01], "pmaddwd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf6, 0xc1], "psadbw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf6, 0x01], "psadbw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf7, 0xc1], "maskmovdqu xmm0, xmm1"); test_invalid(&[0x66, 0x0f, 0xf7, 0x01]); test_instr(&[0x66, 0x0f, 0xf8, 0xc1], "psubb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf8, 0x01], "psubb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xf9, 0xc1], "psubw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xf9, 0x01], "psubw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xfa, 0xc1], "psubd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfa, 0x01], "psubd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xfb, 0xc1], "psubq xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfb, 0x01], "psubq xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xfc, 0xc1], "paddb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfc, 0x01], "paddb xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xfd, 0xc1], "paddw xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfd, 0x01], "paddw xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xfe, 0xc1], "paddd xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0xfe, 0x01], "paddd xmm0, xmmword [ecx]"); test_instr(&[0x66, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf2, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0xf3, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_instr(&[0x66, 0x0f, 0xff, 0x01], "ud0 eax, dword [ecx]"); test_instr(&[0x66, 0x0f, 0x74, 0xc1], "pcmpeqb xmm0, xmm1"); test_instr(&[0x66, 0x0f, 0x74, 0x12], "pcmpeqb xmm2, xmmword [edx]"); test_instr(&[0x66, 0x0f, 0xf8, 0xc8], "psubb xmm1, xmm0"); test_instr(&[0x66, 0x0f, 0xf8, 0xd0], "psubb xmm2, xmm0"); test_instr(&[0x66, 0x0f, 0xf8, 0x12], "psubb xmm2, xmmword [edx]"); } #[test] fn test_sse3() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse3(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse3(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0xf2, 0x0f, 0xf0, 0x0f], "lddqu xmm1, xmmword [edi]"); test_instr_invalid(&[0xf2, 0x0f, 0xf0, 0xcf]); test_instr(&[0xf2, 0x0f, 0xd0, 0x0f], "addsubps xmm1, xmmword [edi]"); test_instr(&[0xf2, 0x0f, 0xd0, 0xcf], "addsubps xmm1, xmm7"); test_invalid(&[0xf3, 0x0f, 0xd0, 0x0f]); test_instr(&[0x66, 0x0f, 0xd0, 0x0f], "addsubpd xmm1, xmmword [edi]"); test_instr(&[0x66, 0x0f, 0xd0, 0xcf], "addsubpd xmm1, xmm7"); test_instr(&[0xf2, 0x0f, 0x7c, 0x0f], "haddps xmm1, xmmword [edi]"); test_instr(&[0xf2, 0x0f, 0x7c, 0xcf], "haddps xmm1, xmm7"); test_instr(&[0x66, 0x0f, 0x7c, 0x0f], "haddpd xmm1, xmmword [edi]"); test_instr(&[0x66, 0x0f, 0x7c, 0xcf], "haddpd xmm1, xmm7"); test_instr(&[0xf2, 0x0f, 0x7d, 0x0f], "hsubps xmm1, xmmword [edi]"); test_instr(&[0xf2, 0x0f, 0x7d, 0xcf], "hsubps xmm1, xmm7"); test_instr(&[0x66, 0x0f, 0x7d, 0x0f], "hsubpd xmm1, xmmword [edi]"); test_instr(&[0x66, 0x0f, 0x7d, 0xcf], "hsubpd xmm1, xmm7"); test_instr(&[0xf3, 0x0f, 0x12, 0x0f], "movsldup xmm1, xmmword [edi]"); test_instr(&[0xf3, 0x0f, 0x12, 0xcf], "movsldup xmm1, xmm7"); test_instr(&[0xf3, 0x0f, 0x16, 0x0f], "movshdup xmm1, xmmword [edi]"); test_instr(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_instr(&[0xf2, 0x0f, 0x12, 0x0f], "movddup xmm1, qword [edi]"); test_instr(&[0xf2, 0x0f, 0x12, 0xcf], "movddup xmm1, xmm7"); test_instr(&[0x0f, 0x01, 0xc8], "monitor"); test_invalid(&[0x66, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc8]); test_instr(&[0x0f, 0x01, 0xc9], "mwait"); test_invalid(&[0x66, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc9]); } #[test] fn test_sse4_2() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4_2(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0x37, 0x03], "pcmpgtq xmm0, xmmword [ebx]"); test_instr(&[0x66, 0x0f, 0x38, 0x37, 0xc3], "pcmpgtq xmm0, xmm3"); test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0x06], "crc32 eax, byte [esi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf0, 0xc6], "crc32 eax, dh"); test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0x06], "crc32 eax, dword [esi]"); test_instr(&[0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, esi"); test_instr(&[0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, si"); test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0xc6, 0x54], "pcmpestrm xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x60, 0x06, 0x54], "pcmpestrm xmm0, xmmword [esi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0xc6, 0x54], "pcmpestri xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x61, 0x06, 0x54], "pcmpestri xmm0, xmmword [esi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0xc6, 0x54], "pcmpistrm xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x62, 0x06, 0x54], "pcmpistrm xmm0, xmmword [esi], 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0xc6, 0x54], "pcmpistri xmm0, xmm6, 0x54"); test_instr(&[0x66, 0x0f, 0x3a, 0x63, 0x06, 0x54], "pcmpistri xmm0, xmmword [esi], 0x54"); } #[test] fn test_sse4_1() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4_1(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4_2 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], "blendps xmm2, xmmword [ecx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0c, 0xc1, 0x22], "blendps xmm0, xmm1, 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], "blendpd xmm2, xmmword [ecx], 0x22"); test_instr(&[0x66, 0x0f, 0x3a, 0x0d, 0xc1, 0x22], "blendpd xmm0, xmm1, 0x22"); test_instr(&[0x66, 0x0f, 0x38, 0x10, 0x06], "pblendvb xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x10, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x14, 0x06], "blendvps xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x14, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x15, 0x06], "blendvpd xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x15, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x17, 0x06], "ptest xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x17, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x20, 0x06], "pmovsxbw xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x20, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x21, 0x06], "pmovsxbd xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x21, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x22, 0x06], "pmovsxbq xmm0, word [esi]"); test_invalid(&[0x0f, 0x38, 0x22, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x23, 0x06], "pmovsxwd xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x23, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x24, 0x06], "pmovsxwq xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x24, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x25, 0x06], "pmovsxdq xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x25, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x28, 0x06], "pmuldq xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x28, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x29, 0x06], "pcmpeqq xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x29, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x2a, 0x06], "movntdqa xmm0, xmmword [esi]"); test_invalid(&[0x66, 0x0f, 0x38, 0x2a, 0xc6]); test_invalid(&[0x0f, 0x38, 0x2a, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x2b, 0x06], "packusdw xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x2b, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x30, 0x06], "pmovzxbw xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x30, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x31, 0x06], "pmovzxbd xmm0, dword [esi]"); test_invalid(&[0x0f, 0x38, 0x31, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x32, 0x06], "pmovzxbq xmm0, word [esi]"); test_invalid(&[0x0f, 0x38, 0x32, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x33, 0x06], "pmovzxwd xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x33, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x34, 0x06], "pmovzxwq xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x34, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x35, 0x06], "pmovzxdq xmm0, qword [esi]"); test_invalid(&[0x0f, 0x38, 0x35, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x38, 0x06], "pminsb xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x38, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x39, 0x06], "pminsd xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x39, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3a, 0x06], "pminuw xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3a, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3b, 0x06], "pminud xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3b, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3c, 0x06], "pmaxsb xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3c, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3d, 0x06], "pmaxsd xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3d, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3e, 0x06], "pmaxuw xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3e, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x3f, 0x06], "pmaxud xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x3f, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x40, 0x06], "pmulld xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x40, 0x06]); test_instr(&[0x66, 0x0f, 0x38, 0x41, 0x06], "phminposuw xmm0, xmmword [esi]"); test_invalid(&[0x0f, 0x38, 0x41, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x08, 0x06, 0x31], "roundps xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x08, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x09, 0x06, 0x31], "roundpd xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x09, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0a, 0x06, 0x31], "roundss xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0a, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0b, 0x06, 0x31], "roundsd xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0b, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x0e, 0x06, 0x31], "pblendw xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x0e, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x14, 0x06, 0x31], "pextrb xmm0, byte [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x14, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x15, 0x06, 0x31], "pextrw xmm0, word [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x15, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x16, 0x06, 0x31], "pextrd xmm0, dword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x16, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x17, 0x06, 0x31], "extractps xmm0, dword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x17, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x20, 0x06, 0x31], "pinsrb xmm0, byte [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x20, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x21, 0x06, 0x31], "insertps xmm0, dword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x21, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x22, 0x06, 0x31], "pinsrd xmm0, dword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x22, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x40, 0x06, 0x31], "dpps xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x40, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x41, 0x06, 0x31], "dppd xmm0, xmmword [esi], 0x31"); test_invalid(&[0x0f, 0x3a, 0x41, 0x06]); test_instr(&[0x66, 0x0f, 0x3a, 0x42, 0x06, 0x44], "mpsadbw xmm0, xmmword [esi], 0x44"); test_invalid(&[0x0f, 0x3a, 0x42, 0x06]); } #[test] fn test_ssse3() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_ssse3(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); // avx doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); // sse4 doesn't imply older instructions are necessarily valid test_invalid_under(&InstDecoder::minimal().with_sse4_1(), bytes); test_invalid_under(&InstDecoder::minimal().with_sse4_2(), bytes); } #[allow(unused)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_ssse3(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } test_instr(&[0x66, 0x0f, 0x38, 0x00, 0xda], "pshufb xmm3, xmm2"); test_instr(&[0x66, 0x0f, 0x38, 0x00, 0x06], "pshufb xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x00, 0x06], "pshufb mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x01, 0x06], "phaddw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x01, 0x06], "phaddw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x02, 0x06], "phaddd xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x02, 0x06], "phaddd mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x03, 0x06], "phaddsw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x03, 0x06], "phaddsw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x04, 0x06], "pmaddubsw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x04, 0x06], "pmaddubsw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x05, 0x06], "phsubw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x05, 0x06], "phsubw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x06, 0x06], "phsubd xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x06, 0x06], "phsubd mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x07, 0x06], "phsubsw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x07, 0x06], "phsubsw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x08, 0x06], "psignb xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x08, 0x06], "psignb mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x09, 0x06], "psignw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x09, 0x06], "psignw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x0a, 0x06], "psignd xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x0a, 0x06], "psignd mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x0b, 0x06], "pmulhrsw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x0b, 0x06], "pmulhrsw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1c, 0x06], "pabsb xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x1c, 0x06], "pabsb mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1d, 0x06], "pabsw xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x1d, 0x06], "pabsw mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x38, 0x1e, 0x06], "pabsd xmm0, xmmword [esi]"); test_instr(&[0x0f, 0x38, 0x1e, 0x06], "pabsd mm0, qword [esi]"); test_instr(&[0x66, 0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr xmm0, xmmword [esi], 0x30"); test_instr(&[0x0f, 0x3a, 0x0f, 0x06, 0x30], "palignr mm0, qword [esi], 0x30"); } #[test] fn test_0f01() { // drawn heavily from "Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group // Number" test_display(&[0x0f, 0x01, 0x38], "invlpg byte [eax]"); test_display(&[0x0f, 0x01, 0x3f], "invlpg byte [edi]"); test_display(&[0x0f, 0x01, 0x40, 0xff], "sgdt ptr [eax - 0x1]"); test_display(&[0x0f, 0x01, 0x41, 0xff], "sgdt ptr [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0x49, 0xff], "sidt ptr [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0x51, 0xff], "lgdt ptr [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0x59, 0xff], "lidt ptr [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0x61, 0xff], "smsw word [ecx - 0x1]"); test_invalid(&[0x0f, 0x01, 0x69, 0xff]); test_display(&[0x0f, 0x01, 0x71, 0xff], "lmsw word [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0x79, 0xff], "invlpg byte [ecx - 0x1]"); test_display(&[0x0f, 0x01, 0xc0], "enclv"); test_display(&[0x0f, 0x01, 0xc1], "vmcall"); test_display(&[0x0f, 0x01, 0xc2], "vmlaunch"); test_display(&[0x0f, 0x01, 0xc3], "vmresume"); test_display(&[0x0f, 0x01, 0xc4], "vmxoff"); test_display(&[0x0f, 0x01, 0xc5], "pconfig"); test_invalid(&[0x0f, 0x01, 0xc6]); test_invalid(&[0x0f, 0x01, 0xc7]); test_display(&[0x0f, 0x01, 0xc8], "monitor"); test_display(&[0x0f, 0x01, 0xc9], "mwait"); test_display(&[0x0f, 0x01, 0xca], "clac"); test_display(&[0x0f, 0x01, 0xcb], "stac"); test_invalid(&[0x0f, 0x01, 0xcc]); test_invalid(&[0x0f, 0x01, 0xcd]); test_invalid(&[0x0f, 0x01, 0xce]); test_display(&[0x0f, 0x01, 0xcf], "encls"); test_display(&[0x0f, 0x01, 0xd0], "xgetbv"); test_display(&[0x0f, 0x01, 0xd1], "xsetbv"); test_invalid(&[0x0f, 0x01, 0xd2]); test_invalid(&[0x0f, 0x01, 0xd3]); test_display(&[0x0f, 0x01, 0xd4], "vmfunc"); test_display(&[0x0f, 0x01, 0xd5], "xend"); test_display(&[0x0f, 0x01, 0xd6], "xtest"); test_display(&[0x0f, 0x01, 0xd7], "enclu"); test_display(&[0x0f, 0x01, 0xd8], "vmrun eax"); test_display(&[0x0f, 0x01, 0xd9], "vmmcall"); test_display(&[0x0f, 0x01, 0xda], "vmload eax"); test_display(&[0x0f, 0x01, 0xdb], "vmsave eax"); test_display(&[0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x0f, 0x01, 0xdd], "clgi"); test_display(&[0x0f, 0x01, 0xde], "skinit eax"); test_display(&[0x0f, 0x01, 0xdf], "invlpga eax, ecx"); // TODO: not clear what SHOULD be reported for invlpgb. certainly not a `rax` operand. xed claims // that this is UD in protected mode. the AMD manual explicitly says this does not #UD in protected // mode. same for tlbsync. // test_display(&[0x0f, 0x01, 0xfe], "invlpgb rax, edx, ecx"); // test_display(&[0x0f, 0x01, 0xff], "tlbsync"); // test_display(&[0x2e, 0x67, 0x65, 0x2e, 0x46, 0x0f, 0x01, 0xff], "tlbsync"); test_display(&[0x0f, 0x01, 0xe0], "smsw ax"); test_display(&[0x0f, 0x01, 0xe1], "smsw cx"); test_display(&[0x0f, 0x01, 0xe2], "smsw dx"); test_display(&[0x0f, 0x01, 0xe3], "smsw bx"); test_display(&[0x0f, 0x01, 0xe4], "smsw sp"); test_display(&[0x0f, 0x01, 0xe5], "smsw bp"); test_display(&[0x0f, 0x01, 0xe6], "smsw si"); test_display(&[0x0f, 0x01, 0xe7], "smsw di"); test_invalid(&[0x0f, 0x01, 0xe8]); test_invalid(&[0x0f, 0x01, 0xe8]); test_invalid(&[0x0f, 0x01, 0xe9]); test_invalid(&[0x0f, 0x01, 0xea]); test_invalid(&[0x0f, 0x01, 0xeb]); test_display(&[0x0f, 0x01, 0xee], "rdpkru"); test_display(&[0x0f, 0x01, 0xef], "wrpkru"); test_invalid(&[0xf2, 0x0f, 0x01, 0xee]); test_invalid(&[0xf2, 0x0f, 0x01, 0xef]); test_display(&[0x0f, 0x01, 0xf0], "lmsw ax"); test_display(&[0x0f, 0x01, 0xf1], "lmsw cx"); test_display(&[0x0f, 0x01, 0xf2], "lmsw dx"); test_display(&[0x0f, 0x01, 0xf3], "lmsw bx"); test_display(&[0x0f, 0x01, 0xf4], "lmsw sp"); test_display(&[0x0f, 0x01, 0xf5], "lmsw bp"); test_display(&[0x0f, 0x01, 0xf6], "lmsw si"); test_display(&[0x0f, 0x01, 0xf7], "lmsw di"); test_invalid(&[0x0f, 0x01, 0xf8]); test_display(&[0x0f, 0x01, 0xf9], "rdtscp"); test_display(&[0x0f, 0x01, 0xfa], "monitorx"); test_display(&[0x0f, 0x01, 0xfb], "mwaitx"); test_display(&[0x0f, 0x01, 0xfc], "clzero"); test_display(&[0x0f, 0x01, 0xfd], "rdpru ecx"); } #[test] fn test_0fae() { let intel = InstDecoder::minimal().with_intel_quirks(); let amd = InstDecoder::minimal().with_amd_quirks(); let default = InstDecoder::default(); let minimal = InstDecoder::minimal(); // drawn heavily from "Table A-6. Opcode Extensions for One- and Two-byte Opcodes by Group // Number" test_invalid(&[0xf3, 0x0f, 0xae, 0x87]); test_invalid(&[0xf3, 0x0f, 0xae, 0x04, 0x4f]); test_display(&[0x0f, 0xae, 0x04, 0x4f], "fxsave ptr [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x0c, 0x4f], "fxrstor ptr [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x14, 0x4f], "ldmxcsr dword [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x1c, 0x4f], "stmxcsr dword [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x24, 0x4f], "xsave ptr [edi + ecx * 2]"); test_display(&[0x0f, 0xc7, 0x5c, 0x24, 0x40], "xrstors ptr [esp + 0x40]"); test_display(&[0x0f, 0xc7, 0x64, 0x24, 0x40], "xsavec ptr [esp + 0x40]"); test_display(&[0x0f, 0xc7, 0x6c, 0x24, 0x40], "xsaves ptr [esp + 0x40]"); test_display(&[0x0f, 0xc7, 0x74, 0x24, 0x40], "vmptrld qword [esp + 0x40]"); test_display(&[0x0f, 0xc7, 0x7c, 0x24, 0x40], "vmptrst qword [esp + 0x40]"); test_display(&[0x0f, 0xae, 0x2c, 0x4f], "xrstor ptr [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x34, 0x4f], "xsaveopt ptr [edi + ecx * 2]"); test_display(&[0x0f, 0xae, 0x3c, 0x4f], "clflush zmmword [edi + ecx * 2]"); for (modrm, text) in &[(0xe8u8, "lfence"), (0xf0u8, "mfence"), (0xf8u8, "sfence")] { test_display_under(&intel, &[0x0f, 0xae, *modrm], text); test_display_under(&amd, &[0x0f, 0xae, *modrm], text); test_display_under(&default, &[0x0f, 0xae, *modrm], text); test_display_under(&minimal, &[0x0f, 0xae, *modrm], text); // it turns out intel and amd accept m != 0 for {l,m,s}fence: // from intel: // ``` // Specification of the instruction's opcode above indicates a ModR/M byte of F0. For this // instruction, the processor ignores the r/m field of the ModR/M byte. Thus, MFENCE is encoded // by any opcode of the form 0F AE Fx, where x is in the range 0-7. // ``` // whereas amd does not discuss the r/m field at all. at least as of zen, amd also accepts // these encodings. for m in 1u8..8u8 { test_display_under(&intel, &[0x0f, 0xae, modrm | m], text); test_display_under(&amd, &[0x0f, 0xae, modrm | m], text); test_display_under(&default, &[0x0f, 0xae, modrm | m], text); test_invalid_under(&minimal, &[0x0f, 0xae, modrm | m]); } } } #[test] fn test_system() { test_display(&[0x63, 0xc1], "arpl cx, ax"); test_display(&[0x63, 0x04, 0xba], "arpl word [edx + edi * 4], ax"); test_display(&[0x0f, 0x06], "clts"); } #[test] fn test_arithmetic() { test_display(&[0x81, 0xec, 0x10, 0x03, 0x00, 0x00], "sub esp, 0x310"); test_display(&[0x0f, 0xaf, 0xc2], "imul eax, edx"); test_display(&[0x69, 0x43, 0x6f, 0x6d, 0x70, 0x6c, 0x65], "imul eax, dword [ebx + 0x6f], 0x656c706d"); test_display(&[0x66, 0x0f, 0xaf, 0xd1], "imul dx, cx"); test_display(&[0xf6, 0xe8], "imul al"); test_display(&[0xf6, 0x28], "imul byte [eax]"); test_display(&[0x6b, 0x43, 0x6f, 0x6d], "imul eax, dword [ebx + 0x6f], 0x6d"); test_display(&[0x00, 0xcc], "add ah, cl"); } #[test] #[allow(non_snake_case)] fn test_E_decode() { test_display(&[0xff, 0x75, 0xb8], "push dword [ebp - 0x48]"); test_display(&[0xff, 0x75, 0x08], "push dword [ebp + 0x8]"); } #[test] fn test_sse() { test_display(&[0xf3, 0x0f, 0x10, 0x0c, 0xc7], "movss xmm1, dword [edi + eax * 8]"); test_display(&[0xf3, 0x0f, 0x11, 0x0c, 0xc7], "movss dword [edi + eax * 8], xmm1"); test_display(&[0x0f, 0x28, 0x00], "movaps xmm0, xmmword [eax]"); test_display(&[0x0f, 0x29, 0x00], "movaps xmmword [eax], xmm0"); test_display(&[0xf3, 0x0f, 0x2a, 0xc1], "cvtsi2ss xmm0, ecx"); test_display(&[0xf3, 0x0f, 0x2a, 0x01], "cvtsi2ss xmm0, dword [ecx]"); test_display(&[0x0f, 0x2b, 0x00], "movntps xmmword [eax], xmm0"); test_display(&[0xf3, 0x0f, 0x2c, 0xc1], "cvttss2si eax, xmm1"); test_display(&[0xf3, 0x0f, 0x2c, 0x01], "cvttss2si eax, dword [ecx]"); test_display(&[0xf3, 0x0f, 0x2d, 0xc1], "cvtss2si eax, xmm1"); test_display(&[0xf3, 0x0f, 0x2d, 0x01], "cvtss2si eax, dword [ecx]"); test_display(&[0x0f, 0x2e, 0x00], "ucomiss xmm0, dword [eax]"); test_display(&[0x0f, 0x2f, 0x00], "comiss xmm0, dword [eax]"); test_display(&[0x0f, 0x28, 0xd0], "movaps xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]"); test_display(&[0x67, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [bx + si * 1]"); test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd xmmword [eax], xmm0"); test_invalid(&[0x0f, 0x50, 0x00]); test_display(&[0x0f, 0x50, 0xc1], "movmskps eax, xmm1"); test_display(&[0x0f, 0x51, 0x01], "sqrtps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x51, 0x01], "sqrtss xmm0, dword [ecx]"); test_display(&[0x0f, 0x52, 0x01], "rsqrtps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x52, 0x01], "rsqrtss xmm0, dword [ecx]"); test_display(&[0x0f, 0x53, 0x01], "rcpps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x53, 0x01], "rcpss xmm0, dword [ecx]"); test_display(&[0xf3, 0x0f, 0x53, 0xc1], "rcpss xmm0, xmm1"); test_display(&[0x0f, 0x54, 0x01], "andps xmm0, xmmword [ecx]"); test_display(&[0x0f, 0x55, 0x01], "andnps xmm0, xmmword [ecx]"); test_display(&[0x0f, 0x56, 0x01], "orps xmm0, xmmword [ecx]"); test_display(&[0x0f, 0x57, 0x01], "xorps xmm0, xmmword [ecx]"); test_display(&[0x0f, 0x58, 0x01], "addps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x58, 0x01], "addss xmm0, dword [ecx]"); test_display(&[0x0f, 0x59, 0x01], "mulps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x59, 0x01], "mulss xmm0, dword [ecx]"); test_display(&[0x0f, 0x5a, 0x01], "cvtps2pd xmm0, qword [ecx]"); test_display(&[0xf3, 0x0f, 0x5a, 0x01], "cvtss2sd xmm0, dword [ecx]"); test_display(&[0x0f, 0x5b, 0x01], "cvtdq2ps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x5b, 0x01], "cvttps2dq xmm0, xmmword [ecx]"); test_display(&[0x67, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5c, 0x01], "subps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x5c, 0x01], "subss xmm0, dword [ecx]"); test_display(&[0x0f, 0x5d, 0x01], "minps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x5d, 0x01], "minss xmm0, dword [ecx]"); test_display(&[0x0f, 0x5e, 0x01], "divps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x5e, 0x01], "divss xmm0, dword [ecx]"); test_display(&[0x0f, 0x5f, 0x01], "maxps xmm0, xmmword [ecx]"); test_display(&[0xf3, 0x0f, 0x5f, 0x01], "maxss xmm0, dword [ecx]"); test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [eax], 0x7f"); test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0"); test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0"); test_display(&[0xf2, 0x0f, 0x10, 0x0c, 0xc6], "movsd xmm1, qword [esi + eax * 8]"); test_display(&[0xf3, 0x0f, 0x10, 0x04, 0x86], "movss xmm0, dword [esi + eax * 4]"); test_display(&[0xf2, 0x0f, 0x59, 0xc8], "mulsd xmm1, xmm0"); test_display(&[0xf3, 0x0f, 0x59, 0xc8], "mulss xmm1, xmm0"); test_display( &[0xf3, 0x0f, 0x6f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqu xmm3, xmmword [esp + ebx * 4 - 0x334455cc]" ); test_display(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_display(&[0xf3, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); test_display( &[0xf3, 0x0f, 0x7f, 0x9c, 0x9c, 0x34, 0xaa, 0xbb, 0xcc], "movdqu xmmword [esp + ebx * 4 - 0x334455cc], xmm3" ); test_display(&[0xf3, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm0, xmm3, 0x8"); test_display(&[0xf3, 0x0f, 0xc2, 0x03, 0x08], "cmpss xmm0, dword [ebx], 0x8"); } // SETLE, SETNG, ... #[test] fn test_mov() { test_display(&[0xa0, 0x93, 0x62, 0xc4, 0x00], "mov al, byte [0xc46293]"); test_display(&[0x67, 0xa0, 0x93, 0x62], "mov al, byte [0x6293]"); test_display(&[0xa1, 0x93, 0x62, 0xc4, 0x00], "mov eax, dword [0xc46293]"); test_display(&[0x67, 0xa1, 0x93, 0x62], "mov eax, dword [0x6293]"); test_display(&[0xa2, 0x93, 0x62, 0xc4, 0x00], "mov byte [0xc46293], al"); test_display(&[0x67, 0xa2, 0x93, 0x62], "mov byte [0x6293], al"); test_display(&[0xa3, 0x93, 0x62, 0xc4, 0x00], "mov dword [0xc46293], eax"); test_display(&[0x67, 0xa3, 0x93, 0x62], "mov dword [0x6293], eax"); test_display(&[0xba, 0x01, 0x00, 0x00, 0x00], "mov edx, 0x1"); test_display(&[0xc7, 0x04, 0x24, 0x00, 0x00, 0x00, 0x00], "mov dword [esp], 0x0"); test_display(&[0x89, 0x44, 0x24, 0x08], "mov dword [esp + 0x8], eax"); test_display(&[0x89, 0x43, 0x18], "mov dword [ebx + 0x18], eax"); test_display(&[0xc7, 0x43, 0x10, 0x00, 0x00, 0x00, 0x00], "mov dword [ebx + 0x10], 0x0"); test_display(&[0x89, 0x4e, 0x08], "mov dword [esi + 0x8], ecx"); test_display(&[0x8b, 0x32], "mov esi, dword [edx]"); test_display(&[0x8b, 0x4c, 0x10, 0xf8], "mov ecx, dword [eax + edx * 1 - 0x8]"); test_display(&[0x89, 0x46, 0x10], "mov dword [esi + 0x10], eax"); test_display(&[0x0f, 0x43, 0xec], "cmovnb ebp, esp"); test_display(&[0x0f, 0xb6, 0x06], "movzx eax, byte [esi]"); test_display(&[0x0f, 0xb7, 0x06], "movzx eax, word [esi]"); test_display(&[0x89, 0x55, 0x94], "mov dword [ebp - 0x6c], edx"); test_display(&[0x65, 0x89, 0x04, 0x25, 0xa8, 0x01, 0x00, 0x00], "mov dword gs:[0x1a8], eax"); test_display(&[0x0f, 0xbe, 0x83, 0xb4, 0x00, 0x00, 0x00], "movsx eax, byte [ebx + 0xb4]"); test_display(&[0xf3, 0x0f, 0x6f, 0x07], "movdqu xmm0, xmmword [edi]"); test_display(&[0xf3, 0x0f, 0x7f, 0x45, 0x00], "movdqu xmmword [ebp], xmm0"); test_display(&[0x0f, 0x97, 0xc0], "seta al"); test_display(&[0x0f, 0x97, 0xc8], "seta al"); test_display(&[0x0f, 0x97, 0x00], "seta byte [eax]"); test_display(&[0x0f, 0x97, 0x08], "seta byte [eax]"); // test_display(&[0xd6], "salc"); test_display(&[0x8e, 0x00], "mov es, word [eax]"); // cs is not an allowed destination test_invalid(&[0x8e, 0x08]); test_display(&[0x8e, 0x10], "mov ss, word [eax]"); test_display(&[0x8e, 0x18], "mov ds, word [eax]"); test_display(&[0x8e, 0x20], "mov fs, word [eax]"); test_display(&[0x8e, 0x28], "mov gs, word [eax]"); test_invalid(&[0x8e, 0x30]); test_invalid(&[0x8e, 0x38]); } #[test] fn test_xchg() { test_display(&[0x90], "nop"); test_display(&[0x91], "xchg eax, ecx"); test_display(&[0x66, 0x91], "xchg ax, cx"); } #[test] fn test_stack() { test_display(&[0x66, 0x50], "push ax"); } #[test] fn test_prefixes() { test_display(&[0x66, 0x31, 0xc0], "xor ax, ax"); test_display(&[0x66, 0x32, 0xc0], "xor al, al"); test_display(&[0x66, 0x32, 0xc5], "xor al, ch"); test_invalid(&[0xf0, 0x33, 0xc0]); test_display(&[0xf0, 0x31, 0x00], "lock xor dword [eax], eax"); test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor byte [eax], 0x0"); test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [edi], edx"); test_display(&[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], "xacquire lock btc word cs:[ebx], dx"); test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]); test_display(&[0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x66, 0x0f, 0xc1, 0xcc], "xadd sp, cx"); test_display(&[0xf2, 0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0xf3, 0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0x66, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf2, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf3, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); } #[test] fn test_control_flow() { test_display(&[0x73, 0x31], "jnb $+0x31"); test_display(&[0x72, 0x5a], "jb $+0x5a"); test_display(&[0x72, 0xf0], "jb $-0x10"); test_display(&[0x0f, 0x86, 0x8b, 0x01, 0x00, 0x00], "jna $+0x18b"); test_display(&[0x74, 0x47], "jz $+0x47"); test_display(&[0xff, 0x15, 0x7e, 0x72, 0x24, 0x00], "call dword [0x24727e]"); test_display(&[0xff, 0x24, 0xcd, 0x70, 0xa0, 0xbc, 0x01], "jmp dword [ecx * 8 + 0x1bca070]"); test_display(&[0xff, 0xe0], "jmp eax"); test_display(&[0x66, 0xff, 0xe0], "jmp eax"); test_display(&[0x67, 0xff, 0xe0], "jmp eax"); test_invalid(&[0xff, 0xd8]); test_display(&[0xff, 0x18], "callf far [eax]"); test_display(&[0xe0, 0x12], "loopnz $+0x12"); test_display(&[0xe1, 0x12], "loopz $+0x12"); test_display(&[0xe2, 0x12], "loop $+0x12"); test_display(&[0xe3, 0x12], "jecxz $+0x12"); test_display(&[0xe3, 0xf0], "jecxz $-0x10"); test_display(&[0xc3], "ret"); } #[test] fn bad_instructions() { // too long test_invalid(&[ 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x2e, 0x33, 0xc0, ]); } #[test] fn test_test_cmp() { test_display(&[0xf6, 0x05, 0x2c, 0x9b, 0xff, 0xff, 0x01], "test byte [0xffff9b2c], 0x1"); test_display(&[0x3d, 0x01, 0xf0, 0xff, 0xff], "cmp eax, -0xfff"); test_display(&[0x83, 0xf8, 0xff], "cmp eax, -0x1"); test_display(&[0x39, 0xc6], "cmp esi, eax"); } #[test] fn test_push_pop() { test_display(&[0x5b], "pop ebx"); test_display(&[0x5e], "pop esi"); test_display(&[0x68, 0x7f, 0x63, 0xc4, 0x00], "push 0xc4637f"); test_display(&[0x66, 0x8f, 0x00], "pop word [eax]"); test_display(&[0x8f, 0x00], "pop dword [eax]"); } #[test] fn test_bmi1() { let bmi1 = InstDecoder::minimal().with_bmi1(); let no_bmi1 = InstDecoder::minimal(); test_display_under(&bmi1, &[0xf3, 0x0f, 0xbc, 0xd3], "tzcnt edx, ebx"); test_display_under(&bmi1, &[0xf2, 0x0f, 0xbc, 0xd3], "bsf edx, ebx"); test_display_under(&bmi1, &[0x0f, 0xbc, 0xd3], "bsf edx, ebx"); test_display_under(&no_bmi1, &[0xf3, 0x0f, 0xbc, 0xd3], "bsf edx, ebx"); // from the intel manual [`ANDN`, though this is true for `BMI1` generally]: // ``` // VEX.W1 is ignored in non-64-bit modes. // ``` // just 0f38 test_display_under(&bmi1, &[0xc4, 0xe2, 0x60, 0xf2, 0x01], "andn eax, ebx, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0xe0, 0xf2, 0x01], "andn eax, ebx, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0x78, 0xf3, 0x09], "blsr eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0xf8, 0xf3, 0x09], "blsr eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0x78, 0xf3, 0x11], "blsmsk eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0xf8, 0xf3, 0x11], "blsmsk eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0x78, 0xf3, 0x19], "blsi eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0xf8, 0xf3, 0x19], "blsi eax, dword [ecx]"); test_display_under(&bmi1, &[0xc4, 0xe2, 0x60, 0xf7, 0x01], "bextr eax, dword [ecx], ebx"); test_display_under(&bmi1, &[0xc4, 0xe2, 0xe0, 0xf7, 0x01], "bextr eax, dword [ecx], ebx"); } #[test] fn test_bmi2() { let bmi2 = InstDecoder::minimal().with_bmi2(); // from the intel manual [`PDEP`, though this is true for `BMI2` generally]: // ``` // VEX.W1 is ignored in non-64-bit modes. // ``` // f2 0f3a test_display_under(&bmi2, &[0xc4, 0xe3, 0x7b, 0xf0, 0x01, 0x05], "rorx eax, dword [ecx], 0x5"); test_display_under(&bmi2, &[0xc4, 0xe3, 0xfb, 0xf0, 0x01, 0x05], "rorx eax, dword [ecx], 0x5"); // f2 0f38 map test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf5, 0x07], "pdep eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf5, 0x07], "pdep eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf6, 0x07], "mulx eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf6, 0x07], "mulx eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0x63, 0xf7, 0x01], "shrx eax, dword [ecx], ebx"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe3, 0xf7, 0x01], "shrx eax, dword [ecx], ebx"); // f3 0f38 map test_display_under(&bmi2, &[0xc4, 0xe2, 0x62, 0xf5, 0x07], "pext eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe2, 0xf5, 0x07], "pext eax, ebx, dword [edi]"); test_display_under(&bmi2, &[0xc4, 0xe2, 0x62, 0xf7, 0x01], "sarx eax, dword [ecx], ebx"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe2, 0xf7, 0x01], "sarx eax, dword [ecx], ebx"); // just 0f38 test_display_under(&bmi2, &[0xc4, 0xe2, 0x60, 0xf5, 0x07], "bzhi eax, dword [edi], ebx"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe0, 0xf5, 0x07], "bzhi eax, dword [edi], ebx"); // 66 0f38 test_display_under(&bmi2, &[0xc4, 0xe2, 0x61, 0xf7, 0x01], "shlx eax, dword [ecx], ebx"); test_display_under(&bmi2, &[0xc4, 0xe2, 0xe1, 0xf7, 0x01], "shlx eax, dword [ecx], ebx"); } #[test] fn test_popcnt() { let popcnt = InstDecoder::minimal().with_popcnt(); let intel_popcnt = InstDecoder::minimal().with_intel_quirks().with_sse4_2(); let no_popcnt = InstDecoder::minimal(); test_display_under(&popcnt, &[0xf3, 0x0f, 0xb8, 0xc1], "popcnt eax, ecx"); test_display_under(&intel_popcnt, &[0xf3, 0x0f, 0xb8, 0xc1], "popcnt eax, ecx"); test_invalid_under(&no_popcnt, &[0xf3, 0x0f, 0xb8, 0xc1]); } #[test] fn test_bitwise() { test_display_under(&InstDecoder::minimal(), &[0x0f, 0xbc, 0xd3], "bsf edx, ebx"); test_display_under(&InstDecoder::minimal(), &[0x0f, 0xbb, 0x17], "btc dword [edi], edx"); test_display_under(&InstDecoder::minimal(), &[0xf0, 0x0f, 0xbb, 0x17], "lock btc dword [edi], edx"); test_display(&[0x0f, 0xa3, 0xd0], "bt eax, edx"); test_display(&[0x0f, 0xab, 0xd0], "bts eax, edx"); test_display(&[0x0f, 0xb3, 0xd0], "btr eax, edx"); test_display(&[0x66, 0x0f, 0xb3, 0xc0], "btr ax, ax"); test_display(&[0xd2, 0xe0], "shl al, cl"); } #[test] fn test_misc() { test_display(&[0xf1], "int 0x1"); test_display(&[0xf5], "cmc"); test_display(&[0xc8, 0x01, 0x02, 0x03], "enter 0x201, 0x3"); test_display(&[0xc9], "leave"); test_display(&[0xca, 0x12, 0x34], "retf 0x3412"); test_display(&[0xcb], "retf"); test_display(&[0x66, 0xcf], "iret"); test_display(&[0xcf], "iretd"); test_display(&[0xf2, 0x0f, 0x38, 0xf0, 0xc1], "crc32 eax, cl"); test_display(&[0xf2, 0x0f, 0x38, 0xf1, 0xc1], "crc32 eax, ecx"); test_display(&[0xfe, 0x00], "inc byte [eax]"); test_display(&[0xfe, 0x08], "dec byte [eax]"); test_display(&[0xff, 0x00], "inc dword [eax]"); test_display(&[0xff, 0x08], "dec dword [eax]"); test_display(&[0xe4, 0x99], "in al, 0x99"); test_display(&[0xe5, 0x99], "in eax, 0x99"); test_display(&[0x67, 0xe5, 0x99], "in eax, 0x99"); test_display(&[0xe5, 0x99], "in eax, 0x99"); test_display(&[0xe6, 0x99], "out 0x99, al"); test_display(&[0xe7, 0x99], "out 0x99, eax"); test_display(&[0xec], "in al, dx"); test_display(&[0xed], "in eax, dx"); test_display(&[0xee], "out dx, al"); test_display(&[0xef], "out dx, eax"); test_display(&[0xcd, 0x00], "int 0x0"); test_display(&[0xcd, 0xff], "int 0xff"); test_display(&[0x9c], "pushf"); test_display(&[0x98], "cwde"); test_display(&[0x66, 0x99], "cwd"); test_display(&[0x66, 0x2e, 0x0f, 0x1f, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00], "nop word cs:[eax + eax * 1]"); test_display(&[0x66, 0x0f, 0x1f, 0x44, 0x00, 0x00], "nop word [eax + eax * 1]"); test_display(&[0x8d, 0xa4, 0xc7, 0x20, 0x00, 0x00, 0x12], "lea esp, dword [edi + eax * 8 + 0x12000020]"); test_display(&[0x33, 0xc0], "xor eax, eax"); test_display(&[0x8d, 0x53, 0x08], "lea edx, dword [ebx + 0x8]"); test_invalid(&[0x8d, 0xdd]); test_display(&[0x31, 0xc9], "xor ecx, ecx"); test_display(&[0x29, 0xc8], "sub eax, ecx"); test_display(&[0x03, 0x0b], "add ecx, dword [ebx]"); test_display(&[0x8d, 0x0c, 0x12], "lea ecx, dword [edx + edx * 1]"); test_display(&[0xf6, 0xc2, 0x18], "test dl, 0x18"); test_display(&[0xf3, 0xab], "rep stos dword es:[edi], eax"); test_display(&[0xf3, 0xa5], "rep movs dword es:[edi], dword ds:[esi]"); test_display(&[0xf3, 0x0f, 0xbc, 0xd7], "tzcnt edx, edi"); // TODO: // this is actually vmx // test_invalid(&[0x66, 0x0f, 0xc7, 0x03]); test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear qword [ebx]"); test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon qword [ebx]"); test_display(&[0xf3, 0x0f, 0xae, 0x26], "ptwrite dword [esi]"); test_display(&[0xf3, 0x0f, 0xae, 0xe6], "ptwrite esi"); test_invalid(&[0x66, 0xf3, 0x0f, 0xae, 0xe6]); test_display(&[0xf3, 0x0f, 0xae, 0xc4], "rdfsbase esp"); test_display(&[0xf3, 0x0f, 0xae, 0xcc], "rdgsbase esp"); test_display(&[0xf3, 0x0f, 0xae, 0xd4], "wrfsbase esp"); test_display(&[0xf3, 0x0f, 0xae, 0xdc], "wrgsbase esp"); test_display(&[0x66, 0x0f, 0xae, 0x3f], "clflushopt zmmword [edi]"); // or clflush without 66 test_invalid(&[0x66, 0x0f, 0xae, 0xff]); test_display(&[0x66, 0x0f, 0xae, 0x37], "clwb zmmword [edi]"); test_display(&[0x66, 0x0f, 0xae, 0xf7], "tpause edi"); test_display(&[0xf3, 0x0f, 0xae, 0xf1], "umonitor ecx"); test_display(&[0x67, 0xf3, 0x0f, 0xae, 0xf1], "umonitor cx"); test_display(&[0xf2, 0x0f, 0xae, 0xf1], "umwait ecx"); test_display(&[0x66, 0x0f, 0x38, 0x80, 0x2f], "invept ebp, xmmword [edi]"); test_invalid(&[0x0f, 0x38, 0x80, 0x2f]); test_display(&[0x66, 0x0f, 0x38, 0x81, 0x2f], "invvpid ebp, xmmword [edi]"); test_invalid(&[0x0f, 0x38, 0x81, 0x2f]); test_display(&[0x66, 0x0f, 0x38, 0x82, 0x2f], "invpcid ebp, xmmword [edi]"); test_invalid(&[0x0f, 0x38, 0x82, 0x2f]); test_display(&[0x66, 0x0f, 0xae, 0xf1], "tpause ecx"); } #[test] fn evex() { // vpbroadcastmw2d. similar to `vpmovm2*`, out-of-range `k` are just masked down. test_display(&[0x62, 0xd2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // vpmovm2b (and larger forms). for some reason the source operand is a mask register but uses // modrm bits as a register selector. out-of-range `k` seem to just get masked down.. test_display(&[0x62, 0xd2, 0x7e, 0x08, 0x28, 0xc2], "vpmovm2b xmm0, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xc1], "vpmovm2b xmm0, k1"); // vpmovb2m (and larger forms). out-of-range `k` are invalid in 64-bit mode, are part of the // `bound` instruction for 32- and 16-bit modes. test_display(&[0x62, 0x72, 0x7e /* , 0x28, 0x29, 0xfd */], "bound esi, qword [edx + 0x7e]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xfd], "vpmovb2m k7, ymm5"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa zmm0, zmmword [eax + eax * 2 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x44, 0x40, 0x01], "vmovntdqa xmm0, xmmword [eax + eax * 2 + 0x10]"); } #[test] fn test_vex() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } fn test_avx2(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx().with_avx2(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } fn test_instr_vex_aesni(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_avx().with_aesni(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } #[allow(dead_code)] fn test_instr_invalid(bytes: &[u8]) { test_invalid_under(&InstDecoder::minimal().with_avx(), bytes); test_invalid_under(&InstDecoder::default(), bytes); } // prefix 03 test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x00, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x00, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b110_00011, 0b1_1111_101, 0x00, 0b11_001_010, 0x77], "vpermq ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x01, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x01, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b110_00011, 0b1_1111_101, 0x01, 0b11_001_010, 0x77], "vpermpd ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x02, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x02, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_001, 0x02, 0b11_001_010, 0x77], "vpblendd xmm1, xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_001, 0x02, 0b00_001_010, 0x77], "vpblendd xmm1, xmm0, xmmword [edx], 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_101, 0x02, 0b11_001_010, 0x77], "vpblendd ymm1, ymm0, ymm2, 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_101, 0x02, 0b00_001_010, 0x77], "vpblendd ymm1, ymm0, ymmword [edx], 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x04, 0b11_001_010, 0x77], "vpermilps xmm1, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x04, 0b11_001_010, 0x77], "vpermilps ymm1, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x05, 0b11_001_010, 0x77], "vpermilpd xmm1, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x05, 0b11_001_010, 0x77], "vpermilpd ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x06, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x06, 0b11_001_010, 0x77], "vperm2f128 ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x06, 0b00_001_010, 0x77], "vperm2f128 ymm1, ymm0, ymmword [edx], 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x0c, 0b11_001_010, 0x77], "vblendps xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x0c, 0b11_001_010, 0x77], "vblendps ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x0d, 0b11_001_010, 0x77], "vblendpd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x0d, 0b11_001_010, 0x77], "vblendpd ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x0e, 0b11_001_010, 0x77], "vpblendw xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x0e, 0b11_001_010, 0x77], "vpblendw ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x08, 0b11_001_010, 0x77], "vroundps xmm1, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x08, 0b11_001_010, 0x77], "vroundps ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x08, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x08, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x09, 0b11_001_010, 0x77], "vroundpd xmm1, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x09, 0b11_001_010, 0x77], "vroundpd ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x09, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x09, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x0a, 0b11_001_010, 0x77], "vroundss xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x0a, 0b11_001_010, 0x77], "vroundss xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x0b, 0b11_001_010, 0x77], "vroundsd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x0b, 0b11_001_010, 0x77], "vroundsd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b1_0111_001, 0x0f, 0b11_001_010, 0x77], "vpalignr xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b1_0111_101, 0x0f, 0b11_001_010, 0x77], "vpalignr ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x14, 0b11_001_010, 0x77], "vpextrb edx, xmm1, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x14, 0b00_001_010, 0x77], "vpextrb byte [edx], xmm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x14, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x14, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x15, 0b11_001_010, 0x77], "vpextrw edx, xmm1, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x15, 0b00_001_010, 0x77], "vpextrw word [edx], xmm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x15, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x15, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrd edx, xmm1, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrd dword [edx], xmm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x16, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b1_1111_001, 0x16, 0b11_001_010, 0x77], "vpextrd edx, xmm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x16, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b1_1111_001, 0x16, 0b00_001_010, 0x77], "vpextrd dword [edx], xmm1, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x17, 0b11_001_010, 0x77], "vextractps edx, xmm1, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x17, 0b00_001_010, 0x77], "vextractps dword [edx], xmm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x18, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x18, 0b11_001_010, 0x77], "vinsertf128 ymm1, ymm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x18, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_101, 0x19, 0b11_001_010, 0x77], "vextractf128 xmm2, ymm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x18, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b110_00011, 0b0_0111_101, 0x38, 0b11_001_010, 0x77], "vinserti128 ymm1, ymm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x18, 0b11_001_010, 0x77]); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_101, 0x39, 0b11_001_010, 0x77], "vextracti128 xmm2, ymm1, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x20, 0b11_001_010, 0x77], "vpinsrb xmm1, xmm0, edx, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x20, 0b00_001_010, 0x77], "vpinsrb xmm1, xmm0, byte [edx], 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x20, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x21, 0b11_001_010, 0x77], "vinsertps xmm1, xmm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x21, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrd xmm1, xmm0, edx, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrd xmm1, xmm0, dword [edx], 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b1_0111_001, 0x22, 0b11_001_010, 0x77], "vpinsrd xmm1, xmm0, edx, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b1_0111_001, 0x22, 0b00_001_010, 0x77], "vpinsrd xmm1, xmm0, dword [edx], 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x22, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x40, 0b11_001_010, 0x77], "vdpps xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_101, 0x40, 0b11_001_010, 0x77], "vdpps ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x41, 0b11_001_010, 0x77], "vdppd xmm1, xmm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x41, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x42, 0b11_001_010, 0x77], "vmpsadbw xmm1, xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_0111_101, 0x42, 0b11_001_010, 0x77], "vmpsadbw ymm1, ymm0, ymm2, 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_101, 0x46, 0b11_001_010, 0x77], "vperm2i128 ymm1, ymm0, ymm2, 0x77"); test_avx2(&[0xc4, 0b110_00011, 0b0_1111_101, 0x46, 0b00_001_010, 0x77], "vperm2i128 ymm1, ymm0, ymmword [edx], 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x46, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x46, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_0111_001, 0x4c, 0b11_001_010, 0x77], "vpblendvb xmm1, xmm0, xmm2, xmm7"); test_avx2(&[0xc4, 0b110_00011, 0b0_0111_101, 0x4c, 0b11_001_010, 0x77], "vpblendvb ymm1, ymm0, ymm2, ymm7"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x4c, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x4c, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x60, 0b11_001_010, 0x77], "vpcmpestrm xmm1, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x60, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x61, 0b11_001_010, 0x77], "vpcmpestri xmm1, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x61, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x62, 0b11_001_010, 0x77], "vpcmpistrm xmm1, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x62, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00011, 0b0_1111_001, 0x63, 0b11_001_010, 0x77], "vpcmpistri xmm1, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x63, 0b11_001_010, 0x77]); test_instr_vex_aesni(&[0xc4, 0b110_00011, 0b1_1111_001, 0xdf, 0b11_001_010, 0x77], "vaeskeygenassist xmm1, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0xdf, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0xdf, 0b11_001_010, 0x77]); // prefix 02 test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x00, 0b11_001_010], "vpshufb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x00, 0b11_001_010], "vpshufb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x01, 0b11_001_010], "vphaddw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x01, 0b11_001_010], "vphaddw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x02, 0b11_001_010], "vphaddd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x02, 0b11_001_010], "vphaddd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x03, 0b11_001_010], "vphaddsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x03, 0b11_001_010], "vphaddsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x04, 0b11_001_010], "vpmaddubsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x04, 0b11_001_010], "vpmaddubsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x05, 0b11_001_010], "vphsubw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x05, 0b11_001_010], "vphsubw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x06, 0b11_001_010], "vphsubd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x06, 0b11_001_010], "vphsubd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x07, 0b11_001_010], "vphsubsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x07, 0b11_001_010], "vphsubsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x08, 0b11_001_010], "vpsignb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x08, 0b11_001_010], "vpsignb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x09, 0b11_001_010], "vpsignw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x09, 0b11_001_010], "vpsignw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x0a, 0b11_001_010], "vpsignd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x0a, 0b11_001_010], "vpsignd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x0b, 0b11_001_010], "vpmulhrsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x0b, 0b11_001_010], "vpmulhrsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x0c, 0b11_001_010], "vpermilps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_101, 0x0c, 0b11_001_010], "vpermilps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x0d, 0b11_001_010], "vpermilpd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_101, 0x0d, 0b11_001_010], "vpermilpd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x0e, 0b11_001_010], "vtestps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x0e, 0b11_001_010], "vtestps ymm1, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x0f, 0b11_001_010], "vtestpd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x0f, 0b11_001_010], "vtestpd ymm1, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x16, 0b11_001_010], "vpermps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x16, 0b00_001_010], "vpermps ymm1, ymm0, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x16, 0b00_011_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x16, 0b00_011_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x17, 0b11_001_010], "vptest xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x17, 0b11_001_010], "vptest ymm1, ymm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x17, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x17, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x18, 0b00_001_010], "vbroadcastss xmm1, dword [edx]"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm1, dword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_001, 0x18, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x18, 0b00_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm1, qword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x19, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x19, 0b00_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x1a, 0b00_001_010], "vbroadcastf128 ymm1, xmmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x1a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x1a, 0b00_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x5a, 0b00_001_010], "vbroadcasti128 ymm1, xmmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_101, 0x5a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x5a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x5a, 0b00_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x18, 0b11_001_010], "vbroadcastss xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x18, 0b11_001_010], "vbroadcastss ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x18, 0b00_001_010], "vbroadcastss ymm1, dword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x18, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x18, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x19, 0b11_001_010], "vbroadcastsd ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x19, 0b00_001_010], "vbroadcastsd ymm1, qword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x1a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x1a, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x1c, 0b11_001_010], "vpabsb xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x1c, 0b11_001_010], "vpabsb ymm1, ymm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1c, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x1d, 0b11_001_010], "vpabsw xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x1d, 0b11_001_010], "vpabsw ymm1, ymm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1d, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x1e, 0b11_001_010], "vpabsd xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x1e, 0b11_001_010], "vpabsd ymm1, ymm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1e, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x20, 0b11_001_010], "vpmovsxbw xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x20, 0b11_001_010], "vpmovsxbw ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x20, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x21, 0b11_001_010], "vpmovsxbd xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x21, 0b11_001_010], "vpmovsxbd ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x21, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x22, 0b11_001_010], "vpmovsxbq xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x22, 0b11_001_010], "vpmovsxbq ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x22, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x23, 0b11_001_010], "vpmovsxwd xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x23, 0b11_001_010], "vpmovsxwd ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x23, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x24, 0b11_001_010], "vpmovsxwq xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x24, 0b11_001_010], "vpmovsxwq ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x24, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x25, 0b11_001_010], "vpmovsxdq xmm1, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x25, 0b11_001_010], "vpmovsxdq ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x25, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x28, 0b11_001_010], "vpmuldq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x28, 0b11_001_010], "vpmuldq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x29, 0b11_001_010], "vpcmpeqq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x29, 0b11_001_010], "vpcmpeqq ymm1, ymm0, ymm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x2a, 0b11_001_010]); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x2a, 0b00_001_010], "vmovntdqa xmm1, xmmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x2a, 0b00_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x2a, 0b00_001_010], "vmovntdqa ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x2b, 0b11_001_010], "vpackusdw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x2b, 0b11_001_010], "vpackusdw ymm1, ymm0, ymm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x2b, 0b00_001_010], "vpackusdw ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x30, 0b11_001_010], "vpmovzxbw xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x30, 0b11_001_010], "vpmovzxbw ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x31, 0b11_001_010], "vpmovzxbd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x31, 0b11_001_010], "vpmovzxbd ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x32, 0b11_001_010], "vpmovzxbq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x32, 0b11_001_010], "vpmovzxbq ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x33, 0b11_001_010], "vpmovzxwd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x33, 0b11_001_010], "vpmovzxwd ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x34, 0b11_001_010], "vpmovzxwq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x34, 0b11_001_010], "vpmovzxwq ymm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x35, 0b11_001_010], "vpmovzxdq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_101, 0x35, 0b11_001_010], "vpmovzxdq ymm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x36, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x36, 0b11_001_010], "vpermd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x37, 0b11_001_010], "vpcmpgtq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x37, 0b11_001_010], "vpcmpgtq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x38, 0b11_001_010], "vpminsb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x38, 0b11_001_010], "vpminsb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x39, 0b11_001_010], "vpminsd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x39, 0b11_001_010], "vpminsd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3a, 0b11_001_010], "vpminuw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3a, 0b11_001_010], "vpminuw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3b, 0b11_001_010], "vpminud xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3b, 0b11_001_010], "vpminud ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3c, 0b11_001_010], "vpmaxsb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3c, 0b11_001_010], "vpmaxsb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3d, 0b11_001_010], "vpmaxsd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3d, 0b11_001_010], "vpmaxsd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3e, 0b11_001_010], "vpmaxuw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3e, 0b11_001_010], "vpmaxuw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x3f, 0b11_001_010], "vpmaxud xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x3f, 0b11_001_010], "vpmaxud ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_0111_001, 0x40, 0b11_001_010], "vpmulld xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_0111_101, 0x40, 0b11_001_010], "vpmulld ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00010, 0b0_1111_001, 0x41, 0b11_001_010], "vphminposuw xmm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x41, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x41, 0b11_001_010]); // TODO: should something b11at opcode 42 here? // test_instr(&[0xc4, 0b110_00010, 0b1_0111_001, 0x42, 0b11_001_010], "vphminposuw xmm"); // test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x41, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x45, 0b00_001_010], "vpsrlvd xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x45, 0b00_001_010], "vpsrlvd ymm1, ymm0, ymmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x45, 0b11_001_010], "vpsrlvd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x45, 0b11_001_010], "vpsrlvd ymm1, ymm0, ymm2"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x45, 0b00_001_010], "vpsrlvq xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x45, 0b00_001_010], "vpsrlvq ymm1, ymm0, ymmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x45, 0b11_001_010], "vpsrlvq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x45, 0b11_001_010], "vpsrlvq ymm1, ymm0, ymm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x46, 0b00_001_010], "vpsravd xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x46, 0b00_001_010], "vpsravd ymm1, ymm0, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_001, 0x46, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x46, 0b00_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x47, 0b00_001_010], "vpsllvd xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x47, 0b00_001_010], "vpsllvd ymm1, ymm0, ymmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x47, 0b11_001_010], "vpsllvd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x47, 0b11_001_010], "vpsllvd ymm1, ymm0, ymm2"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x47, 0b00_001_010], "vpsllvq xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x47, 0b00_001_010], "vpsllvq ymm1, ymm0, ymmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x47, 0b11_001_010], "vpsllvq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x47, 0b11_001_010], "vpsllvq ymm1, ymm0, ymm2"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8c, 0b00_001_010], "vpmaskmovd xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x8c, 0b00_001_010], "vpmaskmovd ymm1, ymm0, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x8c, 0b00_001_010], "vpmaskmovq xmm1, xmm0, xmmword [edx]"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x8c, 0b00_001_010], "vpmaskmovq ymm1, ymm0, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8e, 0b00_001_010], "vpmaskmovd xmmword [edx], xmm0, xmm1"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x8e, 0b00_001_010], "vpmaskmovd ymmword [edx], ymm0, ymm1"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x8e, 0b00_001_010], "vpmaskmovq xmmword [edx], xmm0, xmm1"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x8e, 0b00_001_010], "vpmaskmovq ymmword [edx], ymm0, ymm1"); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); /* test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdd xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdd ymm0, dword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x90, 0b00_000_100, 0xa1], "vpgatherdq xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x90, 0b00_000_100, 0xa1], "vpgatherdq ymm0, qword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm0, dword xmmword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b0_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqd xmm0, dword xmmword [ecx + ymm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_001, 0x91, 0b00_000_100, 0xa1], "vpgatherqq xmm0, dword xmmword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b000_00010, 0b1_1111_101, 0x91, 0b00_000_100, 0xa1], "vpgatherqq ymm0, qword xmmword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdps xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdps ymm0, qword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x92, 0b00_000_100, 0xa1], "vgatherdpd xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x92, 0b00_000_100, 0xa1], "vgatherdpd ymm0, qword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqps xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b0_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqps ymm0, qword [ecx + ymm12 * 4], ymm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_001, 0x93, 0b00_000_100, 0xa1], "vgatherqpd xmm0, dword [ecx + xmm12 * 4], xmm0"); test_avx2(&[0xc4, 0b110_00010, 0b1_1111_101, 0x93, 0b00_000_100, 0xa1], "vgatherqpd ymm0, qword [ecx + ymm12 * 4], ymm0"); */ test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b0_1111_001, 0xdb, 0b11_001_010], "vaesimc xmm1, xmm2"); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0xdb, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0xdb, 0b11_001_010]); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_001, 0xdc, 0b11_001_010], "vaesenc xmm1, xmm0, xmm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_101, 0xdc, 0b11_001_010], "vaesenc ymm1, ymm0, ymm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_001, 0xdd, 0b11_001_010], "vaesenclast xmm1, xmm0, xmm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_101, 0xdd, 0b11_001_010], "vaesenclast ymm1, ymm0, ymm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_001, 0xde, 0b11_001_010], "vaesdec xmm1, xmm0, xmm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_101, 0xde, 0b11_001_010], "vaesdec ymm1, ymm0, ymm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_001, 0xdf, 0b11_001_010], "vaesdeclast xmm1, xmm0, xmm2"); test_instr_vex_aesni(&[0xc4, 0b110_00010, 0b1_0111_101, 0xdf, 0b11_001_010], "vaesdeclast ymm1, ymm0, ymm2"); // prefix 01 test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x10, 0b00_001_010], "vmovsd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x10, 0b00_001_010], "vmovsd xmm1, qword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x10, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x11, 0b00_001_010], "vmovsd qword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x11, 0b00_001_010], "vmovsd qword [edx], xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0x11, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x11, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x10, 0b00_001_010], "vmovupd xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x10, 0b00_001_010], "vmovupd ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x10, 0b00_001_010], "vmovss xmm1, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x10, 0b00_001_010], "vmovss xmm1, dword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_010, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_110, 0x10, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x10, 0b00_001_010], "vmovups xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x10, 0b00_001_010], "vmovups ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x11, 0b11_001_010], "vmovsd xmm2, xmm0, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x11, 0b11_001_010], "vmovsd xmm2, xmm0, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x11, 0b00_001_010], "vmovss dword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x11, 0b00_001_010], "vmovss dword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x11, 0b00_001_010], "vmovups xmmword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x11, 0b00_001_010], "vmovups ymmword [edx], ymm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x12, 0b00_001_010], "vmovddup xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x12, 0b00_001_010], "vmovddup ymm1, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_011, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_111, 0x12, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x12, 0b11_001_010], "vmovhlps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x12, 0b00_001_010], "vmovlps xmm1, xmm0, qword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x12, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x12, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x12, 0b00_001_010], "vmovsldup xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x12, 0b00_001_010], "vmovsldup ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x12, 0b00_001_010], "vmovlpd xmm1, xmm0, qword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x12, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x13, 0b00_001_010], "vmovlpd qword [edx], xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x13, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x13, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_0111_000, 0x14, 0b00_001_010], "vunpcklps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_100, 0x14, 0b00_001_010], "vunpcklps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x14, 0b00_001_010], "vunpcklpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_101, 0x14, 0b00_001_010], "vunpcklpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_000, 0x15, 0b00_001_010], "vunpckhps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_100, 0x15, 0b00_001_010], "vunpckhps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x15, 0b00_001_010], "vunpckhpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_101, 0x15, 0b00_001_010], "vunpckhpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x16, 0b11_001_010], "vmovshdup xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x16, 0b11_001_010], "vmovshdup ymm1, ymm2"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_010, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_110, 0x16, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x16, 0b00_001_010], "vmovhps xmm1, xmm0, qword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x16, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x16, 0b00_001_010], "vmovhpd xmm1, xmm0, qword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x16, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x16, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x17, 0b00_001_010], "vmovhps qword [edx], xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_000, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x17, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x17, 0b00_001_010], "vmovhpd qword [edx], xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x17, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0x28, 0b11_001_010], "vmovaps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x28, 0b11_001_010], "vmovaps ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0x29, 0b11_001_010], "vmovaps xmm2, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x29, 0b11_001_010], "vmovaps ymm2, ymm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x28, 0b11_001_010], "vmovapd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x28, 0b11_001_010], "vmovapd ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x29, 0b11_001_010], "vmovapd xmm2, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x29, 0b11_001_010], "vmovapd ymm2, ymm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x2a, 0b11_001_010], "vcvtsi2ss xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x2a, 0b00_001_010], "vcvtsi2ss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x2a, 0b11_001_010], "vcvtsi2ss xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x2a, 0b00_001_010], "vcvtsi2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc5, 0b1_1111_011, 0x2a, 0b11_001_010], "vcvtsi2sd xmm1, xmm0, edx"); test_instr(&[0xc5, 0b1_1111_111, 0x2a, 0b11_001_010], "vcvtsi2sd xmm1, xmm0, edx"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0x2b, 0b00_001_010], "vmovntps xmmword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x2b, 0b00_001_010], "vmovntps ymmword [edx], ymm1"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x2b, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2b, 0b00_001_010], "vmovntpd xmmword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x2b, 0b00_001_010], "vmovntpd ymmword [edx], ymm1"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x2b, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x2c, 0b11_001_010], "vcvttss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x2c, 0b11_001_010], "vcvttss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x2c, 0b11_001_010], "vcvttss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x2c, 0b00_001_010], "vcvttss2si ecx, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x2c, 0b00_001_010], "vcvttss2si ecx, dword [edx]"); test_instr(&[0xc5, 0b1_1111_010, 0x2c, 0b11_001_010], "vcvttss2si ecx, xmm2"); test_instr(&[0xc5, 0b1_1111_010, 0x2c, 0b00_001_010], "vcvttss2si ecx, dword [edx]"); test_instr(&[0xc5, 0b1_1111_110, 0x2c, 0b11_001_010], "vcvttss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si ecx, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si ecx, qword [edx]"); test_instr(&[0xc5, 0b1_1111_011, 0x2c, 0b11_001_010], "vcvttsd2si ecx, xmm2"); test_instr(&[0xc5, 0b1_1111_111, 0x2c, 0b11_001_010], "vcvttsd2si ecx, xmm2"); test_instr(&[0xc5, 0b1_1111_111, 0x2c, 0b00_001_010], "vcvttsd2si ecx, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x2d, 0b11_001_010], "vcvtss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x2d, 0b11_001_010], "vcvtss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x2d, 0b00_001_010], "vcvtss2si ecx, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x2d, 0b00_001_010], "vcvtss2si ecx, dword [edx]"); test_instr(&[0xc5, 0b1_1111_010, 0x2d, 0b11_001_010], "vcvtss2si ecx, xmm2"); test_instr(&[0xc5, 0b1_1111_010, 0x2d, 0b00_001_010], "vcvtss2si ecx, dword [edx]"); test_instr(&[0xc5, 0b1_1111_110, 0x2d, 0b11_001_010], "vcvtss2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si ecx, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x2d, 0b00_001_010], "vcvtsd2si ecx, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x2d, 0b00_001_010], "vcvtsd2si ecx, qword [edx]"); test_instr(&[0xc5, 0b1_1111_011, 0x2d, 0b11_001_010], "vcvtsd2si ecx, xmm2"); test_instr(&[0xc5, 0b1_1111_111, 0x2d, 0b11_001_010], "vcvtsd2si ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2e, 0b00_001_010], "vucomisd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x2e, 0b00_001_010], "vucomisd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2e, 0b11_001_010], "vucomisd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x2e, 0b11_001_010], "vucomisd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2f, 0b00_001_010], "vcomisd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x2f, 0b00_001_010], "vcomisd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2f, 0b11_001_010], "vcomisd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x2f, 0b11_001_010], "vcomisd xmm1, xmm2"); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2f, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2f, 0b11_001_010]); test_instr(&[0xc5, 0b1_1111_000, 0x2e, 0b11_001_010], "vucomiss xmm1, xmm2"); test_instr(&[0xc5, 0b1_1111_100, 0x2e, 0b00_001_010], "vucomiss xmm1, dword [edx]"); test_instr(&[0xc5, 0b1_1111_000, 0x2f, 0b11_001_010], "vcomiss xmm1, xmm2"); test_instr(&[0xc5, 0b1_1111_100, 0x2f, 0b00_001_010], "vcomiss xmm1, dword [edx]"); test_invalid(&[0xc5, 0b1_1111_111, 0x2f, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x50, 0b11_001_010], "vmovmskps ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x50, 0b11_001_010], "vmovmskps ecx, ymm2"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_000, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x50, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x50, 0b11_001_010], "vmovmskpd ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x50, 0b11_001_010], "vmovmskpd ecx, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x50, 0b11_001_010], "vmovmskpd ecx, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x50, 0b11_001_010], "vmovmskpd ecx, ymm2"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_101, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x50, 0b00_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x51, 0b00_001_010], "vsqrtpd xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x51, 0b00_001_010], "vsqrtpd ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_011, 0x51, 0b00_001_010], "vsqrtsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_111, 0x51, 0b00_001_010], "vsqrtsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x51, 0b00_001_010], "vsqrtps xmm1, xmmword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_000, 0x51, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x51, 0b00_001_010], "vsqrtps ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x51, 0b00_001_010], "vsqrtss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x51, 0b00_001_010], "vsqrtss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x52, 0b11_001_010], "vrsqrtps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x52, 0b11_001_010], "vrsqrtps ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x52, 0b11_001_010], "vrsqrtss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x52, 0b11_001_010], "vrsqrtss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x53, 0b11_001_010], "vrcpps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x53, 0b11_001_010], "vrcpps ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x53, 0b11_001_010], "vrcpss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x53, 0b11_001_010], "vrcpss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x54, 0b11_001_010], "vandps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x54, 0b11_001_010], "vandps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x55, 0b11_001_010], "vandnps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x55, 0b11_001_010], "vandnps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x54, 0b00_001_010], "vandpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x54, 0b00_001_010], "vandpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x55, 0b00_001_010], "vandnpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x55, 0b00_001_010], "vandnpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x56, 0b00_001_010], "vorpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x56, 0b00_001_010], "vorpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x56, 0b00_001_010], "vorps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x56, 0b00_001_010], "vorps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x57, 0b11_001_010], "vxorps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x57, 0b11_001_010], "vxorps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x57, 0b11_001_010], "vxorpd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x57, 0b11_001_010], "vxorpd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x58, 0b11_001_010], "vaddps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x58, 0b11_001_010], "vaddps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x58, 0b11_001_010], "vaddss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x58, 0b11_001_010], "vaddss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x58, 0b00_001_010], "vaddss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x58, 0b00_001_010], "vaddss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x58, 0b00_001_010], "vaddpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x58, 0b00_001_010], "vaddpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x58, 0b00_001_010], "vaddsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x58, 0b00_001_010], "vaddsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x59, 0b00_001_010], "vmulps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x59, 0b00_001_010], "vmulps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x59, 0b00_001_010], "vmulpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x59, 0b00_001_010], "vmulpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x59, 0b00_001_010], "vmulss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x59, 0b00_001_010], "vmulss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x59, 0b00_001_010], "vmulsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x59, 0b00_001_010], "vmulsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x5a, 0b11_001_010], "vcvtps2pd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x5a, 0b11_001_010], "vcvtps2pd ymm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x5a, 0b00_001_010], "vcvtps2pd xmm1, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x5a, 0b00_001_010], "vcvtps2pd ymm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x5a, 0b11_001_010], "vcvtpd2ps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x5a, 0b11_001_010], "vcvtpd2ps xmm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x5a, 0b11_001_010], "vcvtsd2ss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x5a, 0b11_001_010], "vcvtsd2ss xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x5a, 0b00_001_010], "vcvtsd2ss xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0x5a, 0b00_001_010], "vcvtsd2ss xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_011, 0x5a, 0b00_001_010], "vcvtsd2ss xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_111, 0x5a, 0b00_001_010], "vcvtsd2ss xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x5a, 0b11_001_010], "vcvtss2sd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x5a, 0b11_001_010], "vcvtss2sd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x5a, 0b00_001_010], "vcvtss2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x5a, 0b00_001_010], "vcvtss2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x5a, 0b00_001_010], "vcvtss2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x5a, 0b00_001_010], "vcvtss2sd xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x5b, 0b11_001_010], "vcvtps2dq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x5b, 0b11_001_010], "vcvtps2dq ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x5b, 0b11_001_010], "vcvttps2dq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0x5b, 0b11_001_010], "vcvttps2dq ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x5b, 0b11_001_010], "vcvtdq2ps xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_000, 0x5b, 0b00_001_010], "vcvtdq2ps xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x5b, 0b11_001_010], "vcvtdq2ps ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_100, 0x5b, 0b00_001_010], "vcvtdq2ps ymm1, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0x5c, 0b00_001_010], "vsubps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_100, 0x5c, 0b00_001_010], "vsubps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_010, 0x5c, 0b00_001_010], "vsubss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_110, 0x5c, 0b00_001_010], "vsubss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x5c, 0b00_001_010], "vsubpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x5c, 0b00_001_010], "vsubpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_011, 0x5c, 0b00_001_010], "vsubsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_111, 0x5c, 0b00_001_010], "vsubsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x5d, 0b00_001_010], "vminps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x5d, 0b00_001_010], "vminps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x5d, 0b00_001_010], "vminss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x5d, 0b00_001_010], "vminss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x5d, 0b00_001_010], "vminpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x5d, 0b00_001_010], "vminpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x5d, 0b00_001_010], "vminsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x5d, 0b00_001_010], "vminsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x5e, 0b00_001_010], "vdivps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x5e, 0b00_001_010], "vdivpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x5e, 0b00_001_010], "vdivss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x5e, 0b00_001_010], "vdivsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x5e, 0b00_001_010], "vdivps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x5e, 0b00_001_010], "vdivpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x5e, 0b00_001_010], "vdivss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x5e, 0b00_001_010], "vdivsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0x5f, 0b00_001_010], "vmaxps xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x5f, 0b00_001_010], "vmaxpd xmm1, xmm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_010, 0x5f, 0b00_001_010], "vmaxss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x5f, 0b00_001_010], "vmaxsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0x5f, 0b00_001_010], "vmaxps ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x5f, 0b00_001_010], "vmaxpd ymm1, ymm0, ymmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_110, 0x5f, 0b00_001_010], "vmaxss xmm1, xmm0, dword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x5f, 0b00_001_010], "vmaxsd xmm1, xmm0, qword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x60, 0b11_001_010], "vpunpcklbw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x60, 0b11_001_010], "vpunpcklbw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x61, 0b11_001_010], "vpunpcklwd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x61, 0b11_001_010], "vpunpcklwd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x62, 0b11_001_010], "vpunpckldq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x62, 0b11_001_010], "vpunpckldq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x63, 0b11_001_010], "vpacksswb xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_101, 0x63, 0b11_001_010], "vpacksswb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x64, 0b11_001_010], "vpcmpgtb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x64, 0b11_001_010], "vpcmpgtb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x65, 0b11_001_010], "vpcmpgtw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x65, 0b11_001_010], "vpcmpgtw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x66, 0b11_001_010], "vpcmpgtd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x66, 0b11_001_010], "vpcmpgtd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x67, 0b11_001_010], "vpackuswb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x67, 0b11_001_010], "vpackuswb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x68, 0b11_001_010], "vpunpckhbw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x68, 0b11_001_010], "vpunpckhbw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x69, 0b11_001_010], "vpunpckhwd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x69, 0b11_001_010], "vpunpckhwd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x6a, 0b11_001_010], "vpunpckhdq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x6a, 0b11_001_010], "vpunpckhdq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0x6b, 0b11_001_010], "vpackssdw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0x6b, 0b11_001_010], "vpackssdw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x6c, 0b11_001_010], "vpunpcklqdq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x6c, 0b11_001_010], "vpunpcklqdq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x6d, 0b11_001_010], "vpunpckhqdq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x6d, 0b11_001_010], "vpunpckhqdq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x6e, 0b11_001_010], "vmovd xmm1, edx"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x6e, 0b00_001_010], "vmovd xmm1, dword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x6e, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x6f, 0b11_001_010], "vmovdqa xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x6f, 0b11_001_010], "vmovdqa ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x6f, 0b11_001_010], "vmovdqu xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x6f, 0b11_001_010], "vmovdqu ymm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x70, 0b11_001_010, 0x77], "vpshufd xmm1, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x70, 0b11_001_010, 0x77], "vpshufd ymm1, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0x70, 0b11_001_010, 0x77], "vpshufhw xmm1, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_110, 0x70, 0b11_001_010, 0x77], "vpshufhw ymm1, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0x70, 0b11_001_010, 0x77], "vpshuflw xmm1, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_111, 0x70, 0b11_001_010, 0x77], "vpshuflw ymm1, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b11_010_010, 0x77], "vpsrlw xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x71, 0b11_010_010, 0x77], "vpsrlw xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x71, 0b11_010_010, 0x77], "vpsrlw ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b00_011_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b11_100_010, 0x77], "vpsraw xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x71, 0b11_100_010, 0x77], "vpsraw ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b11_101_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b11_110_010, 0x77], "vpsllw xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x71, 0b11_110_010, 0x77], "vpsllw ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_000_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b11_010_010, 0x77], "vpsrld xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x72, 0b11_010_010, 0x77], "vpsrld ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x72, 0b11_011_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b11_100_010, 0x77], "vpsrad xmm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_100_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0x72, 0b11_100_010, 0x77], "vpsrad ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_101_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b11_110_010, 0x77], "vpslld xmm0, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_110_010, 0x77]); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x72, 0b11_110_010, 0x77], "vpslld ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_111_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_000_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_010_010, 0x77], "vpsrlq xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_011_010, 0x77], "vpsrldq xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x73, 0b11_010_010, 0x77], "vpsrlq ymm0, ymm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x73, 0b11_011_010, 0x77], "vpsrldq ymm0, ymm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_100_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_101_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_110_010, 0x77], "vpsllq xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_111_010, 0x77], "vpslldq xmm0, xmm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x73, 0b11_110_010, 0x77], "vpsllq ymm0, ymm2, 0x77"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0x73, 0b11_111_010, 0x77], "vpslldq ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x74, 0b11_001_010], "vpcmpeqb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0x74, 0b11_001_010], "vpcmpeqb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x75, 0b11_001_010], "vpcmpeqw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0x75, 0b11_001_010], "vpcmpeqw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x76, 0b11_001_010], "vpcmpeqd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0x76, 0b11_001_010], "vpcmpeqd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x7c, 0b11_001_010], "vhaddpd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x7c, 0b11_001_010], "vhaddpd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x7c, 0b11_001_010], "vhaddps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x7c, 0b11_001_010], "vhaddps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0x7d, 0b11_001_010], "vhsubpd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0x7d, 0b11_001_010], "vhsubpd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0x7d, 0b11_001_010], "vhsubps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0x7d, 0b11_001_010], "vhsubps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x7e, 0b11_001_010], "vmovd edx, xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_101, 0x7e, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0x7e, 0b11_001_010], "vmovd edx, xmm1"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x7e, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0x7f, 0b11_001_010], "vmovdqa xmm2, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_101, 0x7f, 0b11_001_010], "vmovdqa ymm2, ymm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_010, 0x7f, 0b11_001_010], "vmovdqu xmm2, xmm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_110, 0x7f, 0b11_001_010], "vmovdqu ymm2, ymm1"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b00_010_001], "vldmxcsr dword [ecx]"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_100, 0xae, 0b00_010_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b11_010_001]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b00_011_001], "vstmxcsr dword [ecx]"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_100, 0xae, 0b00_011_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b11_011_001]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_000, 0xc2, 0b11_001_010, 0x77], "vcmpps xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_100, 0xc2, 0b11_001_010, 0x77], "vcmpps ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xc2, 0b11_001_010, 0x77], "vcmppd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0xc2, 0b11_001_010, 0x77], "vcmppd ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0xc2, 0b11_001_010, 0x77], "vcmpsd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0xc2, 0b11_001_010, 0x77], "vcmpsd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xc4, 0b11_001_010, 0x77], "vpinsrw xmm1, xmm0, edx, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xc4, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0xc5, 0b00_001_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0xc5, 0b11_001_010, 0x77], "vpextrw ecx, xmm2, 0x77"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xc5, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xc5, 0b11_001_010, 0x77]); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xc6, 0b11_001_010, 0x77], "vshufpd xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_101, 0xc6, 0b11_001_010, 0x77], "vshufpd ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_000, 0xc6, 0b11_001_010, 0x77], "vshufps xmm1, xmm0, xmm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_100, 0xc6, 0b11_001_010, 0x77], "vshufps ymm1, ymm0, ymm2, 0x77"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd0, 0b11_001_010], "vaddsubpd xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd0, 0b11_001_010], "vaddsubpd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_011, 0xd0, 0b11_001_010], "vaddsubps xmm1, xmm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_111, 0xd0, 0b11_001_010], "vaddsubps ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd1, 0b11_001_010], "vpsrlw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd1, 0b11_001_010], "vpsrlw ymm1, ymm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd1, 0b00_001_010], "vpsrlw ymm1, ymm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd2, 0b11_001_010], "vpsrld xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd2, 0b11_001_010], "vpsrld ymm1, ymm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd2, 0b00_001_010], "vpsrld ymm1, ymm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd3, 0b11_001_010], "vpsrlq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd3, 0b11_001_010], "vpsrlq ymm1, ymm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd3, 0b00_001_010], "vpsrlq ymm1, ymm0, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd4, 0b11_001_010], "vpaddq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd4, 0b11_001_010], "vpaddq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xd5, 0b11_001_010], "vpmullw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xd5, 0b11_001_010], "vpmullw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_1111_001, 0xd7, 0b11_001_010], "vpmovmskb ecx, xmm2"); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0xd7, 0b00_001_010]); test_avx2(&[0xc4, 0b110_00001, 0b0_1111_101, 0xd7, 0b11_001_010], "vpmovmskb ecx, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd8, 0b11_001_010], "vpsubusb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd8, 0b11_001_010], "vpsubusb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xd9, 0b11_001_010], "vpsubusw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xd9, 0b11_001_010], "vpsubusw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xda, 0b11_001_010], "vpminub xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xda, 0b11_001_010], "vpminub ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xdb, 0b11_001_010], "vpand xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xdb, 0b11_001_010], "vpand ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xdc, 0b11_001_010], "vpaddusb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xdc, 0b11_001_010], "vpaddusb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xdd, 0b11_001_010], "vpaddusw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xdd, 0b11_001_010], "vpaddusw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xde, 0b11_001_010], "vpmaxub xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xde, 0b11_001_010], "vpmaxub ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xdf, 0b11_001_010], "vpandn xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xdf, 0b11_001_010], "vpandn ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe0, 0b11_001_010], "vpavgb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe0, 0b11_001_010], "vpavgb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe1, 0b11_001_010], "vpsraw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe1, 0b11_001_010], "vpsraw ymm1, ymm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe2, 0b11_001_010], "vpsrad xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe2, 0b11_001_010], "vpsrad ymm1, ymm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe3, 0b11_001_010], "vpavgw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe3, 0b11_001_010], "vpavgw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe4, 0b11_001_010], "vpmulhuw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe4, 0b11_001_010], "vpmulhuw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe5, 0b11_001_010], "vpmulhw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe5, 0b11_001_010], "vpmulhw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0xe6, 0b11_001_010], "vcvttpd2dq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0xe6, 0b11_001_010], "vcvttpd2dq xmm1, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_010, 0xe6, 0b11_001_010], "vcvtdq2pd xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_110, 0xe6, 0b11_001_010], "vcvtdq2pd ymm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0xe6, 0b11_001_010], "vcvtpd2dq xmm1, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0xe6, 0b11_001_010], "vcvtpd2dq xmm1, ymm2"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xe7, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xe7, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0xe7, 0b00_001_010], "vmovntdq xmmword [edx], xmm1"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_101, 0xe7, 0b00_001_010], "vmovntdq ymmword [edx], ymm1"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe8, 0b11_001_010], "vpsubsb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe8, 0b11_001_010], "vpsubsb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xe9, 0b11_001_010], "vpsubsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xe9, 0b11_001_010], "vpsubsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xea, 0b11_001_010], "vpminsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xea, 0b11_001_010], "vpminsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xeb, 0b11_001_010], "vpor xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xeb, 0b11_001_010], "vpor ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xec, 0b11_001_010], "vpaddsb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xec, 0b11_001_010], "vpaddsb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xed, 0b11_001_010], "vpaddsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xed, 0b11_001_010], "vpaddsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xee, 0b11_001_010], "vpmaxsw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xee, 0b11_001_010], "vpmaxsw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b0_0111_001, 0xef, 0b11_001_010], "vpxor xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b0_0111_101, 0xef, 0b11_001_010], "vpxor ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_011, 0xf0, 0b00_001_010], "vlddqu xmm1, xmmword [edx]"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_111, 0xf0, 0b00_001_010], "vlddqu ymm1, ymmword [edx]"); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_111, 0xf0, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf1, 0b11_001_010], "vpsllw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf1, 0b11_001_010], "vpsllw ymm1, ymm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf2, 0b11_001_010], "vpslld xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf2, 0b11_001_010], "vpslld ymm1, ymm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf3, 0b11_001_010], "vpsllq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf3, 0b11_001_010], "vpsllq ymm1, ymm0, xmm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf4, 0b11_001_010], "vpmuludq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf4, 0b11_001_010], "vpmuludq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0xf5, 0b11_001_010], "vpmaddwd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0xf5, 0b11_001_010], "vpmaddwd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0xf6, 0b11_001_010], "vpsadbw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_1111_101, 0xf6, 0b11_001_010], "vpsadbw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_1111_001, 0xf7, 0b11_001_010], "vmaskmovdqu xmm1, xmm2"); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xf7, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xf7, 0b11_001_010]); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf8, 0b11_001_010], "vpsubb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf8, 0b11_001_010], "vpsubb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xf9, 0b11_001_010], "vpsubw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xf9, 0b11_001_010], "vpsubw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xfa, 0b11_001_010], "vpsubd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xfa, 0b11_001_010], "vpsubd ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xfb, 0b11_001_010], "vpsubq xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xfb, 0b11_001_010], "vpsubq ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xfc, 0b11_001_010], "vpaddb xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xfc, 0b11_001_010], "vpaddb ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xfd, 0b11_001_010], "vpaddw xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xfd, 0b11_001_010], "vpaddw ymm1, ymm0, ymm2"); test_instr(&[0xc4, 0b110_00001, 0b1_0111_001, 0xfe, 0b11_001_010], "vpaddd xmm1, xmm0, xmm2"); test_avx2(&[0xc4, 0b110_00001, 0b1_0111_101, 0xfe, 0b11_001_010], "vpaddd ymm1, ymm0, ymm2"); test_instr(&[0xc5, 0xf8, 0x10, 0x00], "vmovups xmm0, xmmword [eax]"); test_instr(&[0xc5, 0xf8, 0x10, 0x01], "vmovups xmm0, xmmword [ecx]"); } #[test] fn strange_prefixing() { test_display(&[0x66, 0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0xf2, 0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0xf3, 0x0f, 0x21, 0xc8], "mov eax, dr1"); } #[test] fn prefixed_0f() { test_display(&[0x0f, 0x02, 0x01], "lar eax, word [ecx]"); test_display(&[0x0f, 0x02, 0xc1], "lar eax, ecx"); test_display(&[0x66, 0x0f, 0x02, 0x01], "lar ax, word [ecx]"); test_display(&[0x66, 0x0f, 0x02, 0xc1], "lar ax, cx"); test_display(&[0x0f, 0x03, 0x01], "lsl eax, word [ecx]"); test_display(&[0x0f, 0x03, 0xc1], "lsl eax, ecx"); test_display(&[0x66, 0x0f, 0x03, 0x01], "lsl ax, word [ecx]"); test_display(&[0x66, 0x0f, 0x03, 0xc1], "lsl ax, cx"); test_display(&[0x0f, 0x05], "syscall"); test_display(&[0x66, 0x0f, 0x05], "syscall"); test_display(&[0x0f, 0x06], "clts"); test_display(&[0xf2, 0x0f, 0x06], "clts"); test_display(&[0x0f, 0x07], "sysret"); test_display(&[0xf2, 0x0f, 0x07], "sysret"); test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, qword [edi]"); test_display(&[0x0f, 0x12, 0xcf], "movhlps xmm1, xmm7"); test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [edi]"); test_display(&[0x0f, 0x16, 0xcf], "movlhps xmm1, xmm7"); test_display(&[0x0f, 0x12, 0xc0], "movhlps xmm0, xmm0"); test_invalid(&[0x0f, 0x13, 0xc0]); test_display(&[0x0f, 0x13, 0x00], "movlps qword [eax], xmm0"); test_display(&[0x0f, 0x14, 0x08], "unpcklps xmm1, xmmword [eax]"); test_display(&[0x0f, 0x15, 0x08], "unpckhps xmm1, xmmword [eax]"); test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [edi]"); test_display(&[0x0f, 0x16, 0xc0], "movlhps xmm0, xmm0"); test_invalid(&[0x0f, 0x17, 0xc0]); test_display(&[0x0f, 0x17, 0x00], "movhps qword [eax], xmm0"); test_display(&[0x0f, 0x18, 0xc0], "nop eax"); // capstone says invalid, xed says nop test_display(&[0x0f, 0x18, 0x00], "prefetchnta zmmword [eax]"); test_display(&[0x0f, 0x18, 0x08], "prefetch0 zmmword [eax]"); test_display(&[0x0f, 0x18, 0x10], "prefetch1 zmmword [eax]"); test_display(&[0x0f, 0x18, 0x18], "prefetch2 zmmword [eax]"); test_display(&[0x0f, 0x18, 0x20], "nop zmmword [eax]"); test_display(&[0x0f, 0x18, 0xcc], "nop esp"); test_display(&[0x0f, 0x19, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1a, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1b, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1c, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1d, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1e, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x1f, 0x20], "nop dword [eax]"); test_display(&[0x0f, 0x20, 0xc0], "mov eax, cr0"); test_invalid(&[0x0f, 0x20, 0xc8]); test_display(&[0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0x0f, 0x22, 0xc0], "mov cr0, eax"); test_invalid(&[0x0f, 0x22, 0xc8]); test_display(&[0x0f, 0x22, 0xc7], "mov cr0, edi"); test_display(&[0x0f, 0x23, 0xc8], "mov dr1, eax"); test_display(&[0x0f, 0x23, 0xcf], "mov dr1, edi"); test_display(&[0x0f, 0x30], "wrmsr"); test_display(&[0x0f, 0x31], "rdtsc"); test_display(&[0x0f, 0x32], "rdmsr"); test_display(&[0x0f, 0x33], "rdpmc"); test_display(&[0x0f, 0x34], "sysenter"); test_display(&[0x0f, 0x35], "sysexit"); test_invalid(&[0x0f, 0x36]); test_display(&[0x0f, 0x37], "getsec"); test_invalid(&[0x66, 0x0f, 0x37]); test_invalid(&[0xf2, 0x0f, 0x37]); test_invalid(&[0xf3, 0x0f, 0x37]); test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, dword [eax]"); test_display(&[0x0f, 0x60, 0xc2], "punpcklbw mm0, mm2"); test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, dword [eax]"); test_display(&[0x0f, 0x61, 0xc2], "punpcklwd mm0, mm2"); test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, dword [eax]"); test_display(&[0x0f, 0x62, 0xc2], "punpckldq mm0, mm2"); test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, qword [eax]"); test_display(&[0x0f, 0x63, 0xc2], "packsswb mm0, mm2"); test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, qword [eax]"); test_display(&[0x0f, 0x64, 0xc2], "pcmpgtb mm0, mm2"); test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, qword [eax]"); test_display(&[0x0f, 0x65, 0xc2], "pcmpgtw mm0, mm2"); test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, qword [eax]"); test_display(&[0x0f, 0x66, 0xc2], "pcmpgtd mm0, mm2"); test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, qword [eax]"); test_display(&[0x0f, 0x67, 0xc2], "packuswb mm0, mm2"); test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, qword [eax]"); test_display(&[0x0f, 0x68, 0xc2], "punpckhbw mm0, mm2"); test_display(&[0x0f, 0x69, 0x00], "punpckhwd mm0, qword [eax]"); test_display(&[0x0f, 0x69, 0xc2], "punpckhwd mm0, mm2"); test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, qword [eax]"); test_display(&[0x0f, 0x6a, 0xc2], "punpckhdq mm0, mm2"); test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, qword [eax]"); test_display(&[0x0f, 0x6b, 0xc2], "packssdw mm0, mm2"); test_invalid(&[0x0f, 0x6c]); test_invalid(&[0x0f, 0x6d]); test_display(&[0x0f, 0x6e, 0x00], "movd mm0, dword [eax]"); test_display(&[0x0f, 0x6e, 0xc2], "movd mm0, edx"); test_display(&[0x0f, 0x6f, 0x00], "movq mm0, qword [eax]"); test_display(&[0x0f, 0x6f, 0xc2], "movq mm0, mm2"); test_display(&[0x0f, 0x6f, 0xfb], "movq mm7, mm3"); test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [eax], 0x7f"); test_invalid(&[0x0f, 0x71, 0x00, 0x7f]); test_invalid(&[0x0f, 0x71, 0xc0, 0x7f]); test_display(&[0x0f, 0x71, 0xd0, 0x7f], "psrlw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xe0, 0x7f], "psraw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xf0, 0x7f], "psllw mm0, 0x7f"); test_invalid(&[0x0f, 0x72, 0x00, 0x7f]); test_invalid(&[0x0f, 0x72, 0xc0, 0x7f]); test_display(&[0x0f, 0x72, 0xd0, 0x7f], "psrld mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xe0, 0x7f], "psrad mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xf0, 0x7f], "pslld mm0, 0x7f"); test_invalid(&[0x0f, 0x73, 0x00, 0x7f]); test_invalid(&[0x0f, 0x73, 0xc0, 0x7f]); test_display(&[0x0f, 0x73, 0xd0, 0x7f], "psrlq mm0, 0x7f"); test_invalid(&[0x0f, 0x73, 0xe0, 0x7f]); test_display(&[0x0f, 0x73, 0xf0, 0x7f], "psllq mm0, 0x7f"); test_display(&[0x0f, 0xa0], "push fs"); test_display(&[0x0f, 0xa1], "pop fs"); test_display(&[0x0f, 0xa2], "cpuid"); test_display(&[0x0f, 0xa4, 0xc0, 0x11], "shld eax, eax, 0x11"); test_display(&[0x66, 0x0f, 0xa4, 0xcf, 0x11], "shld di, cx, 0x11"); test_display(&[0x0f, 0xa5, 0xc0], "shld eax, eax, cl"); test_display(&[0x0f, 0xa5, 0xc9], "shld ecx, ecx, cl"); test_display(&[0x0f, 0xac, 0xc0, 0x11], "shrd eax, eax, 0x11"); test_display(&[0x66, 0x0f, 0xac, 0xcf, 0x11], "shrd di, cx, 0x11"); test_display(&[0x0f, 0xad, 0xc9], "shrd ecx, ecx, cl"); } #[test] fn prefixed_660f() { test_display(&[0x66, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0"); test_display(&[0xf2, 0x66, 0x66, 0x0f, 0x10, 0xc0], "movsd xmm0, xmm0"); } #[test] fn prefixed_f20f() { test_invalid(&[0xf2, 0x0f, 0x16, 0xcf]); test_invalid(&[0x66, 0xf2, 0x66, 0x0f, 0x16, 0xcf]); } #[test] fn prefixed_f30f() { test_display(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_display(&[0xf3, 0x0f, 0x1e, 0xfa], "endbr64"); test_display(&[0xf3, 0x0f, 0x1e, 0xfb], "endbr32"); test_display(&[0xf3, 0x0f, 0x1e, 0xfc], "nop esp, edi"); } #[test] fn only_32bit() { test_display(&[0x9a, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66], "callf 0x6655:0x44332211"); test_display(&[0x66, 0x9a, 0x11, 0x22, 0x33, 0x44], "callf 0x4433:0x2211"); test_display(&[0x67, 0xac], "lods al, byte ds:[si]"); test_display(&[0x67, 0xae], "scas byte es:[di], al"); test_display(&[0xac], "lods al, byte ds:[esi]"); test_display(&[0xae], "scas byte es:[edi], al"); test_display(&[0x67, 0xf3, 0xa4], "rep movs byte es:[di], byte ds:[si]"); test_display(&[0xf3, 0xa4], "rep movs byte es:[edi], byte ds:[esi]"); test_display(&[0x67, 0xf3, 0xa5], "rep movs dword es:[di], dword ds:[si]"); test_display(&[0xf3, 0xa5], "rep movs dword es:[edi], dword ds:[esi]"); test_display(&[0x66, 0x67, 0x8b, 0x0e, 0x55, 0xaa], "mov cx, word [0xaa55]"); test_display(&[0x66, 0x8b, 0x0e], "mov cx, word [esi]"); test_display(&[0x40], "inc eax"); test_display(&[0x41], "inc ecx"); test_display(&[0x47], "inc edi"); test_display(&[0x48], "dec eax"); test_display(&[0x4f], "dec edi"); test_display(&[0xa0, 0xc0, 0xb0, 0xa0, 0x90], "mov al, byte [0x90a0b0c0]"); test_display(&[0x67, 0xa0, 0xc0, 0xb0], "mov al, byte [0xb0c0]"); test_display(&[0x67, 0xa1, 0xc0, 0xb0], "mov eax, dword [0xb0c0]"); test_display(&[0x66, 0x67, 0xa1, 0xc0, 0xb0], "mov ax, word [0xb0c0]"); test_display(&[0x60], "pusha"); test_display(&[0x61], "popa"); test_display(&[0xce], "into"); test_display(&[0x06], "push es"); test_display(&[0x07], "pop es"); test_display(&[0x0e], "push cs"); test_display(&[0x16], "push ss"); test_display(&[0x17], "pop ss"); test_display(&[0x1e], "push ds"); test_display(&[0x1f], "pop ds"); test_display(&[0x27], "daa"); test_display(&[0x2f], "das"); test_display(&[0x37], "aaa"); test_display(&[0x3f], "aas"); test_display(&[0xd4, 0x01], "aam 0x1"); test_display(&[0xd4, 0x0a], "aam 0xa"); test_display(&[0xd5, 0x01], "aad 0x1"); test_display(&[0xd5, 0x0a], "aad 0xa"); test_display(&[0xc5, 0x78, 0x10], "lds edi, far [eax + 0x10]"); test_display(&[0x66, 0xc5, 0x78, 0x10], "lds di, dword [eax + 0x10]"); } #[test] fn test_adx() { test_display(&[0x66, 0x0f, 0x38, 0xf6, 0xc1], "adcx eax, ecx"); test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, dword [ecx]"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0xc1], "adox eax, ecx"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, dword [ecx]"); } #[test] fn test_prefetchw() { test_display(&[0x0f, 0x0d, 0x08], "prefetchw zmmword [eax]"); } #[test] fn test_lzcnt() { test_display(&[0x66, 0xf3, 0x0f, 0xbd, 0xc1], "lzcnt ax, cx"); test_display(&[0xf3, 0x0f, 0xbd, 0xc1], "lzcnt eax, ecx"); } #[test] fn test_svm() { test_display(&[0x0f, 0x01, 0xdf], "invlpga eax, ecx"); test_display(&[0x0f, 0x01, 0xde], "skinit eax"); test_display(&[0x0f, 0x01, 0xdd], "clgi"); test_display(&[0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x0f, 0x01, 0xdb], "vmsave eax"); test_display(&[0x0f, 0x01, 0xda], "vmload eax"); test_display(&[0x0f, 0x01, 0xd9], "vmmcall"); test_display(&[0x0f, 0x01, 0xd8], "vmrun eax"); test_display(&[0x0f, 0x78, 0xc4], "vmread esp, eax"); test_display(&[0x0f, 0x79, 0xc5], "vmwrite eax, ebp"); test_display(&[0x0f, 0x78, 0x0b], "vmread qword [ebx], ecx"); test_invalid(&[0x66, 0x0f, 0x78, 0x03]); test_display(&[0x0f, 0x79, 0x0b], "vmwrite ecx, qword [ebx]"); test_invalid(&[0x66, 0x0f, 0x79, 0x03]); } #[test] fn test_movbe() { test_display(&[0x0f, 0x38, 0xf0, 0x06], "movbe eax, dword [esi]"); test_invalid(&[0x0f, 0x38, 0xf0, 0xc6]); test_display(&[0x0f, 0x38, 0xf1, 0x06], "movbe dword [esi], eax"); test_display(&[0x66, 0x0f, 0x38, 0xf1, 0x06], "movbe word [esi], ax"); test_invalid(&[0x66, 0x0f, 0x38, 0xf1, 0xc6]); } #[test] fn test_tsx() { test_display(&[0xc6, 0xf8, 0x10], "xabort 0x10"); test_display(&[0xc7, 0xf8, 0x10, 0x12, 0x34, 0x56], "xbegin $+0x56341210"); test_display(&[0x66, 0xc7, 0xf8, 0x10, 0x12], "xbegin $+0x1210"); test_display(&[0x0f, 0x01, 0xd5], "xend"); test_display(&[0x0f, 0x01, 0xd6], "xtest"); } #[test] fn test_rand() { test_display(&[0x0f, 0xc7, 0xfd], "rdseed ebp"); test_display(&[0x66, 0x0f, 0xc7, 0xfd], "rdseed bp"); test_display(&[0x0f, 0xc7, 0xf5], "rdrand ebp"); test_display(&[0x66, 0x0f, 0xc7, 0xf5], "rdrand bp"); } #[test] fn test_sha() { test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, xmmword [edx], 0x40"); test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0xff], "sha1rnds4 xmm2, xmmword [edx], 0xff"); test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, xmmword [edx]"); test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, xmmword [edx]"); test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, xmmword [edx]"); test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, xmmword [edx]"); test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, xmmword [edx]"); test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, xmmword [edx]"); } #[test] fn test_vmx() { test_display(&[0x0f, 0xc7, 0x3f], "vmptrst qword [edi]"); test_display(&[0x0f, 0xc7, 0x37], "vmptrld qword [edi]"); test_display(&[0xf3, 0x0f, 0xc7, 0x37], "vmxon qword [edi]"); test_display(&[0x66, 0x0f, 0xc7, 0xf7], "rdrand di"); test_display(&[0x66, 0x0f, 0xc7, 0x37], "vmclear qword [edi]"); // this is actually vmx // test_invalid(&[0x66, 0x0f, 0xc7, 0x03]); test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear qword [ebx]"); test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon qword [ebx]"); } #[test] fn test_rdpid() { test_display(&[0xf3, 0x0f, 0xc7, 0xfd], "rdpid ebp"); } #[test] fn test_cmpxchg8b() { test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [edi]"); test_display(&[0xf2, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [edi]"); test_display(&[0xf3, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [edi]"); test_display(&[0x66, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [edi]"); } #[test] fn test_x87() { // test_display(&[0xd8, 0x03], "fadd st, dword ptr [ebx]"); test_display(&[0xd8, 0x03], "fadd st(0), dword [ebx]"); // test_display(&[0xd8, 0x0b], "fmul st, dword ptr [ebx]"); test_display(&[0xd8, 0x0b], "fmul st(0), dword [ebx]"); // test_display(&[0xd8, 0x13], "fcom st, dword ptr [ebx]"); test_display(&[0xd8, 0x13], "fcom st(0), dword [ebx]"); // test_display(&[0xd8, 0x1b], "fcomp st, dword ptr [ebx]"); test_display(&[0xd8, 0x1b], "fcomp st(0), dword [ebx]"); // test_display(&[0xd8, 0x23], "fsub st, dword ptr [ebx]"); test_display(&[0xd8, 0x23], "fsub st(0), dword [ebx]"); // test_display(&[0xd8, 0x2b], "fsubr st, dword ptr [ebx]"); test_display(&[0xd8, 0x2b], "fsubr st(0), dword [ebx]"); // test_display(&[0xd8, 0x33], "fdiv st, dword ptr [ebx]"); test_display(&[0xd8, 0x33], "fdiv st(0), dword [ebx]"); // test_display(&[0xd8, 0x3b], "fdivr st, dword ptr [ebx]"); test_display(&[0xd8, 0x3b], "fdivr st(0), dword [ebx]"); // test_display(&[0xd8, 0xc3], "fadd st, st(3)"); test_display(&[0xd8, 0xc3], "fadd st(0), st(3)"); // test_display(&[0xd8, 0xcb], "fmul st, st(3)"); test_display(&[0xd8, 0xcb], "fmul st(0), st(3)"); // test_display(&[0xd8, 0xd3], "fcom st, st(3)"); test_display(&[0xd8, 0xd3], "fcom st(0), st(3)"); // test_display(&[0xd8, 0xdb], "fcomp st, st(3)"); test_display(&[0xd8, 0xdb], "fcomp st(0), st(3)"); // test_display(&[0xd8, 0xe3], "fsub st, st(3)"); test_display(&[0xd8, 0xe3], "fsub st(0), st(3)"); // test_display(&[0xd8, 0xeb], "fsubr st, st(3)"); test_display(&[0xd8, 0xeb], "fsubr st(0), st(3)"); // test_display(&[0xd8, 0xf3], "fdiv st, st(3)"); test_display(&[0xd8, 0xf3], "fdiv st(0), st(3)"); // test_display(&[0xd8, 0xfb], "fdivr st, st(3)"); test_display(&[0xd8, 0xfb], "fdivr st(0), st(3)"); // test_display(&[0xd9, 0x03], "fld st, dword ptr [ebx]"); test_display(&[0xd9, 0x03], "fld st(0), dword [ebx]"); test_invalid(&[0xd9, 0x08]); test_invalid(&[0xd9, 0x09]); test_invalid(&[0xd9, 0x0a]); test_invalid(&[0xd9, 0x0b]); test_invalid(&[0xd9, 0x0c]); test_invalid(&[0xd9, 0x0d]); test_invalid(&[0xd9, 0x0e]); test_invalid(&[0xd9, 0x0f]); // test_display(&[0xd9, 0x13], "fst dword ptr [ebx], st"); test_display(&[0xd9, 0x13], "fst dword [ebx], st(0)"); // test_display(&[0xd9, 0x1b], "fstp dword ptr [ebx], st"); test_display(&[0xd9, 0x1b], "fstp dword [ebx], st(0)"); // test_display(&[0xd9, 0x23], "fldenv ptr [ebx]"); test_display(&[0xd9, 0x23], "fldenv ptr [ebx]"); // test_display(&[0xd9, 0x2b], "fldcw word ptr [ebx]"); test_display(&[0xd9, 0x2b], "fldcw word [ebx]"); // test_display(&[0xd9, 0x33], "fnstenv ptr [ebx]"); test_display(&[0xd9, 0x33], "fnstenv ptr [ebx]"); // test_display(&[0xd9, 0x3b], "fnstcw word ptr [ebx]"); test_display(&[0xd9, 0x3b], "fnstcw word [ebx]"); // test_display(&[0xd9, 0xc3], "fld st, st(3)"); test_display(&[0xd9, 0xc3], "fld st(0), st(3)"); // test_display(&[0xd9, 0xcb], "fxch st, st(3)"); test_display(&[0xd9, 0xcb], "fxch st(0), st(3)"); test_display(&[0xd9, 0xd0], "fnop"); test_invalid(&[0xd9, 0xd1]); test_invalid(&[0xd9, 0xd2]); test_invalid(&[0xd9, 0xd3]); test_invalid(&[0xd9, 0xd4]); test_invalid(&[0xd9, 0xd5]); test_invalid(&[0xd9, 0xd6]); test_invalid(&[0xd9, 0xd7]); // undocumented save for intel xed // test_display(&[0xd9, 0xdb], "fstpnce st(3), st"); test_display(&[0xd9, 0xdb], "fstpnce st(3), st(0)"); test_display(&[0xd9, 0xe0], "fchs"); test_display(&[0xd9, 0xe1], "fabs"); test_invalid(&[0xd9, 0xe2]); test_invalid(&[0xd9, 0xe3]); test_display(&[0xd9, 0xe4], "ftst"); test_display(&[0xd9, 0xe5], "fxam"); test_invalid(&[0xd9, 0xe6]); test_invalid(&[0xd9, 0xe7]); test_display(&[0xd9, 0xe8], "fld1"); test_display(&[0xd9, 0xe9], "fldl2t"); test_display(&[0xd9, 0xea], "fldl2e"); test_display(&[0xd9, 0xeb], "fldpi"); test_display(&[0xd9, 0xec], "fldlg2"); test_display(&[0xd9, 0xed], "fldln2"); test_display(&[0xd9, 0xee], "fldz"); test_invalid(&[0xd9, 0xef]); test_display(&[0xd9, 0xf0], "f2xm1"); test_display(&[0xd9, 0xf1], "fyl2x"); test_display(&[0xd9, 0xf2], "fptan"); test_display(&[0xd9, 0xf3], "fpatan"); test_display(&[0xd9, 0xf4], "fxtract"); test_display(&[0xd9, 0xf5], "fprem1"); test_display(&[0xd9, 0xf6], "fdecstp"); test_display(&[0xd9, 0xf7], "fincstp"); test_display(&[0xd9, 0xf8], "fprem"); test_display(&[0xd9, 0xf9], "fyl2xp1"); test_display(&[0xd9, 0xfa], "fsqrt"); test_display(&[0xd9, 0xfb], "fsincos"); test_display(&[0xd9, 0xfc], "frndint"); test_display(&[0xd9, 0xfd], "fscale"); test_display(&[0xd9, 0xfe], "fsin"); test_display(&[0xd9, 0xff], "fcos"); // test_display(&[0xda, 0x03], "fiadd st, dword ptr [ebx]"); test_display(&[0xda, 0x03], "fiadd st(0), dword [ebx]"); // test_display(&[0xda, 0x0b], "fimul st, dword ptr [ebx]"); test_display(&[0xda, 0x0b], "fimul st(0), dword [ebx]"); // test_display(&[0xda, 0x13], "ficom st, dword ptr [ebx]"); test_display(&[0xda, 0x13], "ficom st(0), dword [ebx]"); // test_display(&[0xda, 0x1b], "ficomp st, dword ptr [ebx]"); test_display(&[0xda, 0x1b], "ficomp st(0), dword [ebx]"); // test_display(&[0xda, 0x23], "fisub st, dword ptr [ebx]"); test_display(&[0xda, 0x23], "fisub st(0), dword [ebx]"); // test_display(&[0xda, 0x2b], "fisubr st, dword ptr [ebx]"); test_display(&[0xda, 0x2b], "fisubr st(0), dword [ebx]"); // test_display(&[0xda, 0x33], "fidiv st, dword ptr [ebx]"); test_display(&[0xda, 0x33], "fidiv st(0), dword [ebx]"); // test_display(&[0xda, 0x3b], "fidivr st, dword ptr [ebx]"); test_display(&[0xda, 0x3b], "fidivr st(0), dword [ebx]"); // test_display(&[0xda, 0xc3], "fcmovb st, st(3)"); test_display(&[0xda, 0xc3], "fcmovb st(0), st(3)"); // test_display(&[0xda, 0xcb], "fcmove st, st(3)"); test_display(&[0xda, 0xcb], "fcmove st(0), st(3)"); // test_display(&[0xda, 0xd3], "fcmovbe st, st(3)"); test_display(&[0xda, 0xd3], "fcmovbe st(0), st(3)"); // test_display(&[0xda, 0xdb], "fcmovu st, st(3)"); test_display(&[0xda, 0xdb], "fcmovu st(0), st(3)"); test_invalid(&[0xda, 0xe0]); test_invalid(&[0xda, 0xe1]); test_invalid(&[0xda, 0xe2]); test_invalid(&[0xda, 0xe3]); test_invalid(&[0xda, 0xe4]); test_invalid(&[0xda, 0xe5]); test_invalid(&[0xda, 0xe6]); test_invalid(&[0xda, 0xe7]); test_invalid(&[0xda, 0xe8]); test_display(&[0xda, 0xe9], "fucompp"); test_invalid(&[0xda, 0xea]); test_invalid(&[0xda, 0xeb]); test_invalid(&[0xda, 0xec]); test_invalid(&[0xda, 0xed]); test_invalid(&[0xda, 0xee]); test_invalid(&[0xda, 0xef]); test_invalid(&[0xda, 0xf0]); test_invalid(&[0xda, 0xf1]); test_invalid(&[0xda, 0xf2]); test_invalid(&[0xda, 0xf3]); test_invalid(&[0xda, 0xf4]); test_invalid(&[0xda, 0xf5]); test_invalid(&[0xda, 0xf6]); test_invalid(&[0xda, 0xf7]); test_invalid(&[0xda, 0xf8]); test_invalid(&[0xda, 0xf9]); test_invalid(&[0xda, 0xfa]); test_invalid(&[0xda, 0xfb]); test_invalid(&[0xda, 0xfc]); test_invalid(&[0xda, 0xfd]); test_invalid(&[0xda, 0xfe]); test_invalid(&[0xda, 0xff]); // test_display(&[0xdb, 0x03], "fild st, dword ptr [ebx]"); test_display(&[0xdb, 0x03], "fild st(0), dword [ebx]"); // test_display(&[0xdb, 0x0b], "fisttp dword ptr [ebx], st"); test_display(&[0xdb, 0x0b], "fisttp dword [ebx], st(0)"); // test_display(&[0xdb, 0x13], "fist dword ptr [ebx], st"); test_display(&[0xdb, 0x13], "fist dword [ebx], st(0)"); // test_display(&[0xdb, 0x1b], "fistp dword ptr [ebx], st"); test_display(&[0xdb, 0x1b], "fistp dword [ebx], st(0)"); test_invalid(&[0xdb, 0x20]); test_invalid(&[0xdb, 0x21]); test_invalid(&[0xdb, 0x22]); test_invalid(&[0xdb, 0x23]); test_invalid(&[0xdb, 0x24]); test_invalid(&[0xdb, 0x25]); test_invalid(&[0xdb, 0x26]); test_invalid(&[0xdb, 0x27]); // test_display(&[0xdb, 0x2b], "fld st, ptr [ebx]"); test_display(&[0xdb, 0x2b], "fld st(0), mword [ebx]"); test_invalid(&[0xdb, 0x30]); test_invalid(&[0xdb, 0x31]); test_invalid(&[0xdb, 0x32]); test_invalid(&[0xdb, 0x33]); test_invalid(&[0xdb, 0x34]); test_invalid(&[0xdb, 0x35]); test_invalid(&[0xdb, 0x36]); test_invalid(&[0xdb, 0x37]); // test_display(&[0xdb, 0x3b], "fstp ptr [ebx], st"); test_display(&[0xdb, 0x3b], "fstp mword [ebx], st(0)"); // test_display(&[0xdb, 0xc3], "fcmovnb st, st(3)"); test_display(&[0xdb, 0xc3], "fcmovnb st(0), st(3)"); // test_display(&[0xdb, 0xcb], "fcmovne st, st(3)"); test_display(&[0xdb, 0xcb], "fcmovne st(0), st(3)"); // test_display(&[0xdb, 0xd3], "fcmovnbe st, st(3)"); test_display(&[0xdb, 0xd3], "fcmovnbe st(0), st(3)"); // test_display(&[0xdb, 0xdb], "fcmovnu st, st(3)"); test_display(&[0xdb, 0xdb], "fcmovnu st(0), st(3)"); test_display(&[0xdb, 0xe0], "feni8087_nop"); test_display(&[0xdb, 0xe1], "fdisi8087_nop"); test_display(&[0xdb, 0xe2], "fnclex"); test_display(&[0xdb, 0xe3], "fninit"); test_display(&[0xdb, 0xe4], "fsetpm287_nop"); test_invalid(&[0xdb, 0xe5]); test_invalid(&[0xdb, 0xe6]); test_invalid(&[0xdb, 0xe7]); // test_display(&[0xdb, 0xeb], "fucomi st, st(3)"); test_display(&[0xdb, 0xeb], "fucomi st(0), st(3)"); // test_display(&[0xdb, 0xf3], "fcomi st, st(3)"); test_display(&[0xdb, 0xf3], "fcomi st(0), st(3)"); test_invalid(&[0xdb, 0xf8]); test_invalid(&[0xdb, 0xf9]); test_invalid(&[0xdb, 0xfa]); test_invalid(&[0xdb, 0xfb]); test_invalid(&[0xdb, 0xfc]); test_invalid(&[0xdb, 0xfd]); test_invalid(&[0xdb, 0xfe]); test_invalid(&[0xdb, 0xff]); // test_display(&[0xdc, 0x03], "fadd st, qword ptr [ebx]"); test_display(&[0xdc, 0x03], "fadd st(0), qword [ebx]"); // test_display(&[0xdc, 0x0b], "fmul st, qword ptr [ebx]"); test_display(&[0xdc, 0x0b], "fmul st(0), qword [ebx]"); // test_display(&[0xdc, 0x13], "fcom st, qword ptr [ebx]"); test_display(&[0xdc, 0x13], "fcom st(0), qword [ebx]"); // test_display(&[0xdc, 0x1b], "fcomp st, qword ptr [ebx]"); test_display(&[0xdc, 0x1b], "fcomp st(0), qword [ebx]"); // test_display(&[0xdc, 0x23], "fsub st, qword ptr [ebx]"); test_display(&[0xdc, 0x23], "fsub st(0), qword [ebx]"); // test_display(&[0xdc, 0x2b], "fsubr st, qword ptr [ebx]"); test_display(&[0xdc, 0x2b], "fsubr st(0), qword [ebx]"); // test_display(&[0xdc, 0x33], "fdiv st, qword ptr [ebx]"); test_display(&[0xdc, 0x33], "fdiv st(0), qword [ebx]"); // test_display(&[0xdc, 0x3b], "fdivr st, qword ptr [ebx]"); test_display(&[0xdc, 0x3b], "fdivr st(0), qword [ebx]"); // test_display(&[0xdc, 0xc3], "fadd st(3), st"); test_display(&[0xdc, 0xc3], "fadd st(3), st(0)"); // test_display(&[0xdc, 0xcb], "fmul st(3), st"); test_display(&[0xdc, 0xcb], "fmul st(3), st(0)"); // test_display(&[0xdc, 0xd3], "fcom st, st(3)"); test_display(&[0xdc, 0xd3], "fcom st(0), st(3)"); // test_display(&[0xdc, 0xdb], "fcomp st, st(3)"); test_display(&[0xdc, 0xdb], "fcomp st(0), st(3)"); // test_display(&[0xdc, 0xe3], "fsubr st(3), st"); test_display(&[0xdc, 0xe3], "fsubr st(3), st(0)"); // test_display(&[0xdc, 0xeb], "fsub st(3), st"); test_display(&[0xdc, 0xeb], "fsub st(3), st(0)"); // test_display(&[0xdc, 0xf3], "fdivr st(3), st"); test_display(&[0xdc, 0xf3], "fdivr st(3), st(0)"); // test_display(&[0xdc, 0xfb], "fdiv st(3), st"); test_display(&[0xdc, 0xfb], "fdiv st(3), st(0)"); // test_display(&[0xdd, 0x03], "fld st, qword ptr [ebx]"); test_display(&[0xdd, 0x03], "fld st(0), qword [ebx]"); // test_display(&[0xdd, 0x0b], "fisttp qword ptr [ebx], st"); test_display(&[0xdd, 0x0b], "fisttp qword [ebx], st(0)"); // test_display(&[0xdd, 0x13], "fst qword ptr [ebx], st"); test_display(&[0xdd, 0x13], "fst qword [ebx], st(0)"); // test_display(&[0xdd, 0x1b], "fstp qword ptr [ebx], st"); test_display(&[0xdd, 0x1b], "fstp qword [ebx], st(0)"); // test_display(&[0xdd, 0x23], "frstor ptr [ebx]"); test_display(&[0xdd, 0x23], "frstor ptr [ebx]"); test_invalid(&[0xdd, 0x28]); test_invalid(&[0xdd, 0x29]); test_invalid(&[0xdd, 0x2a]); test_invalid(&[0xdd, 0x2b]); test_invalid(&[0xdd, 0x2c]); test_invalid(&[0xdd, 0x2d]); test_invalid(&[0xdd, 0x2e]); test_invalid(&[0xdd, 0x2f]); // test_display(&[0xdd, 0x33], "fnsave ptr [ebx]"); test_display(&[0xdd, 0x33], "fnsave ptr [ebx]"); // test_display(&[0xdd, 0x3b], "fnstsw word ptr [ebx]"); test_display(&[0xdd, 0x3b], "fnstsw word [ebx]"); test_display(&[0xdd, 0xc3], "ffree st(3)"); // test_display(&[0xdd, 0xcb], "fxch st, st(3)"); test_display(&[0xdd, 0xcb], "fxch st(0), st(3)"); // test_display(&[0xdd, 0xd3], "fst st(3), st"); test_display(&[0xdd, 0xd3], "fst st(3), st(0)"); // test_display(&[0xdd, 0xdb], "fstp st(3), st"); test_display(&[0xdd, 0xdb], "fstp st(3), st(0)"); // test_display(&[0xdd, 0xe3], "fucom st, st(3)"); test_display(&[0xdd, 0xe3], "fucom st(0), st(3)"); // test_display(&[0xdd, 0xeb], "fucomp st, st(3)"); test_display(&[0xdd, 0xeb], "fucomp st(0), st(3)"); test_invalid(&[0xdd, 0xf0]); test_invalid(&[0xdd, 0xf1]); test_invalid(&[0xdd, 0xf2]); test_invalid(&[0xdd, 0xf3]); test_invalid(&[0xdd, 0xf4]); test_invalid(&[0xdd, 0xf5]); test_invalid(&[0xdd, 0xf6]); test_invalid(&[0xdd, 0xf7]); test_invalid(&[0xdd, 0xf8]); test_invalid(&[0xdd, 0xf9]); test_invalid(&[0xdd, 0xfa]); test_invalid(&[0xdd, 0xfb]); test_invalid(&[0xdd, 0xfc]); test_invalid(&[0xdd, 0xfd]); test_invalid(&[0xdd, 0xfe]); test_invalid(&[0xdd, 0xff]); // test_display(&[0xde, 0x03], "fiadd st, word ptr [ebx]"); test_display(&[0xde, 0x03], "fiadd st(0), word [ebx]"); // test_display(&[0xde, 0x0b], "fimul st, word ptr [ebx]"); test_display(&[0xde, 0x0b], "fimul st(0), word [ebx]"); // test_display(&[0xde, 0x13], "ficom st, word ptr [ebx]"); test_display(&[0xde, 0x13], "ficom st(0), word [ebx]"); // test_display(&[0xde, 0x1b], "ficomp st, word ptr [ebx]"); test_display(&[0xde, 0x1b], "ficomp st(0), word [ebx]"); // test_display(&[0xde, 0x23], "fisub st, word ptr [ebx]"); test_display(&[0xde, 0x23], "fisub st(0), word [ebx]"); // test_display(&[0xde, 0x2b], "fisubr st, word ptr [ebx]"); test_display(&[0xde, 0x2b], "fisubr st(0), word [ebx]"); // test_display(&[0xde, 0x33], "fidiv st, word ptr [ebx]"); test_display(&[0xde, 0x33], "fidiv st(0), word [ebx]"); // test_display(&[0xde, 0x3b], "fidivr st, word ptr [ebx]"); test_display(&[0xde, 0x3b], "fidivr st(0), word [ebx]"); // test_display(&[0xde, 0xc3], "faddp st(3), st"); test_display(&[0xde, 0xc3], "faddp st(3), st(0)"); // test_display(&[0xde, 0xcb], "fmulp st(3), st"); test_display(&[0xde, 0xcb], "fmulp st(3), st(0)"); // test_display(&[0xde, 0xd3], "fcomp st, st(3)"); test_display(&[0xde, 0xd3], "fcomp st(0), st(3)"); test_invalid(&[0xde, 0xd8]); test_display(&[0xde, 0xd9], "fcompp"); test_invalid(&[0xde, 0xda]); test_invalid(&[0xde, 0xdb]); test_invalid(&[0xde, 0xdc]); test_invalid(&[0xde, 0xdd]); test_invalid(&[0xde, 0xde]); test_invalid(&[0xde, 0xdf]); // test_display(&[0xde, 0xe3], "fsubrp st(3), st"); test_display(&[0xde, 0xe3], "fsubrp st(3), st(0)"); // test_display(&[0xde, 0xeb], "fsubp st(3), st"); test_display(&[0xde, 0xeb], "fsubp st(3), st(0)"); // test_display(&[0xde, 0xf3], "fdivrp st(3), st"); test_display(&[0xde, 0xf3], "fdivrp st(3), st(0)"); // test_display(&[0xde, 0xfb], "fdivp st(3), st"); test_display(&[0xde, 0xfb], "fdivp st(3), st(0)"); // test_display(&[0xdf, 0x03], "fild st, word ptr [ebx]"); test_display(&[0xdf, 0x03], "fild st(0), word [ebx]"); // test_display(&[0xdf, 0x0b], "fisttp word ptr [ebx], st"); test_display(&[0xdf, 0x0b], "fisttp word [ebx], st(0)"); // test_display(&[0xdf, 0x13], "fist word ptr [ebx], st"); test_display(&[0xdf, 0x13], "fist word [ebx], st(0)"); // test_display(&[0xdf, 0x1b], "fistp word ptr [ebx], st"); test_display(&[0xdf, 0x1b], "fistp word [ebx], st(0)"); // test_display(&[0xdf, 0x23], "fbld st, ptr [ebx]"); test_display(&[0xdf, 0x23], "fbld st(0), mword [ebx]"); // test_display(&[0xdf, 0x2b], "fild st, qword ptr [ebx]"); test_display(&[0xdf, 0x2b], "fild st(0), qword [ebx]"); // test_display(&[0xdf, 0x33], "fbstp ptr [ebx], st"); test_display(&[0xdf, 0x33], "fbstp mword [ebx], st(0)"); // test_display(&[0xdf, 0x3b], "fistp qword ptr [ebx], st"); test_display(&[0xdf, 0x3b], "fistp qword [ebx], st(0)"); // test_display(&[0xdf, 0xc3], "ffreep st(3)"); test_display(&[0xdf, 0xc3], "ffreep st(3)"); // test_display(&[0xdf, 0xcb], "fxch st, st(3)"); test_display(&[0xdf, 0xcb], "fxch st(0), st(3)"); // test_display(&[0xdf, 0xd3], "fstp st(3), st"); test_display(&[0xdf, 0xd3], "fstp st(3), st(0)"); // test_display(&[0xdf, 0xdb], "fstp st(3), st"); test_display(&[0xdf, 0xdb], "fstp st(3), st(0)"); test_display(&[0xdf, 0xe0], "fnstsw ax"); test_invalid(&[0xdf, 0xe1]); test_invalid(&[0xdf, 0xe2]); test_invalid(&[0xdf, 0xe3]); test_invalid(&[0xdf, 0xe4]); test_invalid(&[0xdf, 0xe5]); test_invalid(&[0xdf, 0xe6]); test_invalid(&[0xdf, 0xe7]); // test_display(&[0xdf, 0xeb], "fucomip st, st(3)"); test_display(&[0xdf, 0xeb], "fucomip st(0), st(3)"); // test_display(&[0xdf, 0xf3], "fcomip st, st(3)"); test_display(&[0xdf, 0xf3], "fcomip st(0), st(3)"); test_invalid(&[0xdf, 0xf8]); test_invalid(&[0xdf, 0xf9]); test_invalid(&[0xdf, 0xfa]); test_invalid(&[0xdf, 0xfb]); test_invalid(&[0xdf, 0xfc]); test_invalid(&[0xdf, 0xfd]); test_invalid(&[0xdf, 0xfe]); test_invalid(&[0xdf, 0xff]); } #[test] fn test_mishegos_finds() { test_invalid(&[0xc5, 0x8c, 0x77]); test_display(&[0x0f, 0xfc, 0xaf, 0x40, 0x38, 0x25, 0xbf], "paddb mm5, qword [edi - 0x40dac7c0]"); test_invalid(&[0xf3, 0x67, 0x0f, 0x3a, 0xf0, 0xfb, 0xb4]); test_display(&[0x65, 0x66, 0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x66, 0x0f, 0x01, 0xd8], "vmrun eax"); test_invalid(&[0x2e, 0x2e, 0xf2, 0x36, 0x0f, 0xb2, 0xdb, 0x42, 0xd6, 0xa3, 0x16]); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x26, 0x66, 0x67, 0x0f, 0x38, 0xdf, 0xe4], "aesdeclast xmm4, xmm4"); test_display(&[0x65, 0x66, 0x66, 0x64, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[edi]"); test_invalid(&[0xf3, 0xf2, 0x0f, 0xae, 0x8f, 0x54, 0x3c, 0x58, 0xb7]); /* test_display(&[652e662e0f3814ff], "blendvps"); test_display(&[66666565450f3acf2b4b], "gf2 "); */ // might just be yax trying to do a f20f decode when it should not be f2 // impossible instruction if operands could be read: lock is illegal here. // test_display(&[f06565f2640f16], "???"); // test_display(&[0x0f, 0x38, 0xf6, 0x8c, 0x98, 0x4d, 0x33, 0xf5, 0xd3, ], "wrssd"); test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword ss:[eax - 0x5]"); test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [edi]"); test_display(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b], "movntdqa xmm5, xmmword cs:[ebx]"); test_display(&[0x66, 0x2e, 0x67, 0x0f, 0x3a, 0x0d, 0xb8, 0xf0, 0x2f, 0x7c], "blendpd xmm7, xmmword cs:[bx + si * 1 + 0x2ff0], 0x7c"); test_display(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f, 0xa8, 0x2d], "pmovsxwd xmm3, qword [ebp + 0x2da80f69]"); test_display(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[ebx], -0x4f"); test_display(&[0x66, 0x26, 0x0f, 0x3a, 0x42, 0x96, 0x74, 0x29, 0x96, 0xf9, 0x6a], "mpsadbw xmm2, xmmword es:[esi - 0x669d68c], 0x6a"); test_display(&[0x67, 0x26, 0x66, 0x65, 0x0f, 0x38, 0x3f, 0x9d, 0xcc, 0x03], "pmaxud xmm3, xmmword gs:[di + 0x3cc]"); test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e], "movdiri dword cs:[ebp + 0x3e], edx"); test_invalid(&[0x66, 0x2e, 0x64, 0x66, 0x0f, 0x38, 0xf8, 0xe2]); test_display(&[0x67, 0x66, 0x65, 0x3e, 0x0f, 0x6d, 0xd1], "punpckhqdq xmm2, xmm1"); test_display(&[0x2e, 0x66, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, xmmword cs:[eax + 0x2d], 0x57"); test_display(&[0xf2, 0x3e, 0x26, 0x67, 0x0f, 0xf0, 0xa0, 0x1b, 0x5f], "lddqu xmm4, xmmword es:[bx + si * 1 + 0x5f1b]"); test_display(&[0x2e, 0x3e, 0x66, 0x3e, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, xmmword [eax], 0x48"); test_display(&[0x2e, 0x36, 0x0f, 0x18, 0xe7], "nop edi"); test_display(&[0x65, 0xf0, 0x87, 0x0f], "lock xchg dword gs:[edi], ecx"); test_display(&[0x66, 0x0f, 0x3a, 0x44, 0x88, 0xb3, 0xad, 0x26, 0x35, 0x75], "pclmulqdq xmm1, xmmword [eax + 0x3526adb3], 0x75"); test_display(&[0x0f, 0xff, 0x6b, 0xac], "ud0 ebp, dword [ebx - 0x54]"); test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd eax, zmmword ss:[ebx + 0x3f9d1c09]"); test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds esi, zmmword fs:[edx + 0x54]"); test_invalid(&[0xf3, 0x0f, 0x38, 0xf8, 0xf3]); test_display(&[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], "loadiwkey xmm5, xmm0"); test_invalid(&[0xf3, 0x2e, 0x0f, 0x6a, 0x18]); } #[test] fn test_cet() { // see // https://software.intel.com/sites/default/files/managed/4d/2a/control-flow-enforcement-technology-preview.pdf // includes encodings: // wruss{d,q} 066 f 38 f5 // wrss{d,q} 0f 38 f6 // rstorssp f3 0f 01 /5 // saveprevssp f3 0f 01 ea // rdssp{d,q} f3 0f 1e // incssp{d,q} f3 0f ae /5 // test_display(&[0x0f, 0x38, 0xf6, 0x8c, 0x98, 0x4d, 0x33, 0xf5, 0xd3, ], "wrssd [eax + ebx * 4 - 0x2c0accb3], ecx"); // setssbsy f3 0f 01 e8 // clrssbsy f3 0f ae /6 // endbr64 f3 0f ae fa // endbr32 f3 0f ae fb test_display(&[0xf3, 0x0f, 0xae, 0xe9], "incssp ecx"); test_display(&[0x3e, 0x0f, 0x38, 0xf6, 0x23], "wrss dword [ebx], esp"); test_display(&[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], "wruss dword [edi - 0x17], eax"); test_invalid(&[0x0f, 0x38, 0xf5, 0x47, 0xe9]); test_invalid(&[0x66, 0x3e, 0x65, 0x3e, 0x0f, 0x38, 0xf5, 0xf0]); test_display(&[0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x0f, 0x01, 0x29], "rstorssp qword [ecx]"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0x29], "rstorssp qword [ecx]"); test_display(&[0xf3, 0x0f, 0xae, 0x30], "clrssbsy qword [eax]"); } #[test] fn test_sse4a() { fn test_instr(bytes: &[u8], text: &'static str) { test_display_under(&InstDecoder::minimal().with_sse4a(), bytes, text); test_display_under(&InstDecoder::default(), bytes, text); test_invalid_under(&InstDecoder::minimal(), bytes); } test_instr(&[0xf2, 0x0f, 0x2b, 0x06], "movntsd qword [esi], xmm0"); test_invalid(&[0xf2, 0x0f, 0x2b, 0xc6]); test_instr(&[0xf3, 0x0f, 0x2b, 0x06], "movntss dword [esi], xmm0"); test_invalid(&[0xf3, 0x0f, 0xba, 0xc6]); test_instr(&[0x66, 0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_invalid(&[0x66, 0xf2, 0x0f, 0x79, 0x0f]); test_instr(&[0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_instr(&[0xf2, 0x0f, 0x78, 0xf1, 0x4e, 0x76], "insertq xmm6, xmm1, 0x4e, 0x76"); test_invalid(&[0xf2, 0x0f, 0x79, 0x0f]); test_instr(&[0x66, 0x0f, 0x79, 0xcf], "extrq xmm1, xmm7"); test_invalid(&[0x66, 0x0f, 0x79, 0x0f]); test_instr(&[0x66, 0x0f, 0x78, 0xc1, 0x4e, 0x76], "extrq xmm1, 0x4e, 0x76"); test_invalid(&[0x66, 0x0f, 0x78, 0xc9, 0x4e, 0x76]); } #[test] fn test_3dnow() { test_display(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [eax]"); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x3e, 0xf3, 0x2e, 0xf2, 0x0f, 0x0f, 0x64, 0x93, 0x93, 0xa4], "pfmax mm4, qword cs:[ebx + edx * 4 - 0x6d]"); test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword ss:[eax - 0x5]"); test_display(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); test_display(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); } // first appeared in tremont #[test] fn test_direct_stores() { test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e, ], "movdiri dword cs:[ebp + 0x3e], edx"); test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08], "movdir64b bp, zmmword es:[di + 0x80b]"); test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword es:[ebp + 0x729080b]"); } #[test] fn test_key_locker() { test_display(&[0xf3, 0x64, 0x2e, 0x65, 0x0f, 0x38, 0xdc, 0xe8], "loadiwkey xmm5, xmm0"); test_display(&[0xf3, 0x0f, 0x38, 0xfa, 0xde], "encodekey128 ebx, esi"); test_display(&[0xf3, 0x0f, 0x38, 0xfb, 0xde], "encodekey256 ebx, esi"); } // these uinter test cases come from llvm: // https://reviews.llvm.org/differential/changeset/?ref=2226860 #[test] fn test_uintr() { test_display(&[0xf3, 0x0f, 0x01, 0xec], "uiret"); test_display(&[0xf3, 0x0f, 0x01, 0xed], "testui"); test_display(&[0xf3, 0x0f, 0x01, 0xee], "clui"); test_display(&[0xf3, 0x0f, 0x01, 0xef], "stui"); test_display(&[0xf3, 0x0f, 0xc7, 0xf0], "senduipi eax"); test_display(&[0xf3, 0x0f, 0xc7, 0xf2], "senduipi edx"); } // started shipping in sapphire rapids #[test] fn test_enqcmd() { test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c, 0x9d, 0x3f], "enqcmd eax, zmmword ss:[ebx + 0x3f9d1c09]"); test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds esi, zmmword fs:[edx + 0x54]"); } #[test] fn test_gfni() { test_display(&[0x3e, 0x64, 0x64, 0x66, 0x0f, 0x3a, 0xcf, 0xba, 0x13, 0x23, 0x04, 0xba, 0x6b], "gf2p8affineinvqb xmm7, xmmword fs:[edx - 0x45fbdced], 0x6b"); test_display(&[0x66, 0x36, 0x0f, 0x3a, 0xce, 0x8c, 0x56, 0x9e, 0x82, 0xd1, 0xbe, 0xad], "gf2p8affineqb xmm1, xmmword ss:[esi + edx * 2 - 0x412e7d62], 0xad"); test_display(&[0x66, 0x0f, 0x38, 0xcf, 0x1c, 0x54], "gf2p8mulb xmm3, xmmword [esp + edx * 2]"); } #[test] fn test_tdx() { test_display(&[0x66, 0x0f, 0x01, 0xcc], "tdcall"); test_display(&[0x66, 0x0f, 0x01, 0xcd], "seamret"); test_display(&[0x66, 0x0f, 0x01, 0xce], "seamops"); test_display(&[0x66, 0x0f, 0x01, 0xcf], "seamcall"); } #[test] fn test_tsxldtrk() { test_display(&[0xf2, 0x0f, 0x01, 0xe8], "xsusldtrk"); test_display(&[0xf2, 0x0f, 0x01, 0xe9], "xresldtrk"); } #[test] fn test_sevsnp() { test_display(&[0xf3, 0x0f, 0x01, 0xff], "psmash"); test_display(&[0xf2, 0x0f, 0x01, 0xff], "pvalidate"); test_display(&[0xf3, 0x0f, 0x01, 0xfe], "rmpadjust"); test_display(&[0xf2, 0x0f, 0x01, 0xfe], "rmpupdate"); } #[test] fn test_keylocker() { test_display(&[0xf3, 0x0f, 0x38, 0xdd, 0x03], "aesdec128kl xmm0, m384b [ebx]"); } // some test cases are best just lifted from llvm or gcc. #[test] fn from_llvm() { test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); assert_eq!(hreset.operand_count(), 1); } #[test] fn from_reports() { // negative compressed evex displacements should not overflow and panic test_display(&[0x62, 0xf2, 0x6d, 0xac, 0x00, 0x59, 0xa7], "vpshufb ymm3{k4}{z}, ymm2, ymmword [ecx - 0xb20]"); test_display(&[0x62, 0xf2, 0xfd, 0x0f, 0x8a, 0x62, 0xf2], "vcompresspd xmmword [edx - 0x70]{k7}, xmm4"); test_display(&[0xf3, 0x0f, 0x1e, 0x0f], "nop dword [edi], ecx"); } mod reg_specs { use yaxpeax_x86::protected_mode::RegSpec; #[test] fn reg_specs_are_correct() { #[cfg(feature = "fmt")] { let cases: Vec<(RegSpec, &'static str)> = vec![ (RegSpec::d(0), "eax"), (RegSpec::eax(), "eax"), (RegSpec::d(1), "ecx"), (RegSpec::ecx(), "ecx"), (RegSpec::d(2), "edx"), (RegSpec::edx(), "edx"), (RegSpec::d(3), "ebx"), (RegSpec::ebx(), "ebx"), (RegSpec::d(4), "esp"), (RegSpec::esp(), "esp"), (RegSpec::d(5), "ebp"), (RegSpec::ebp(), "ebp"), (RegSpec::d(6), "esi"), (RegSpec::esi(), "esi"), (RegSpec::d(7), "edi"), (RegSpec::edi(), "edi"), (RegSpec::w(0), "ax"), (RegSpec::ax(), "ax"), (RegSpec::w(1), "cx"), (RegSpec::cx(), "cx"), (RegSpec::w(2), "dx"), (RegSpec::dx(), "dx"), (RegSpec::w(3), "bx"), (RegSpec::bx(), "bx"), (RegSpec::w(4), "sp"), (RegSpec::sp(), "sp"), (RegSpec::w(5), "bp"), (RegSpec::bp(), "bp"), (RegSpec::w(6), "si"), (RegSpec::si(), "si"), (RegSpec::w(7), "di"), (RegSpec::di(), "di"), (RegSpec::b(0), "al"), (RegSpec::al(), "al"), (RegSpec::b(1), "cl"), (RegSpec::cl(), "cl"), (RegSpec::b(2), "dl"), (RegSpec::dl(), "dl"), (RegSpec::b(3), "bl"), (RegSpec::bl(), "bl"), (RegSpec::b(4), "ah"), (RegSpec::ah(), "ah"), (RegSpec::b(5), "ch"), (RegSpec::ch(), "ch"), (RegSpec::b(6), "dh"), (RegSpec::dh(), "dh"), (RegSpec::b(7), "bh"), (RegSpec::bh(), "bh"), (RegSpec::eip(), "eip"), (RegSpec::eflags(), "eflags"), (RegSpec::es(), "es"), (RegSpec::cs(), "cs"), (RegSpec::ss(), "ss"), (RegSpec::ds(), "ds"), (RegSpec::fs(), "fs"), (RegSpec::gs(), "gs"), (RegSpec::mask(0), "k0"), (RegSpec::mask(1), "k1"), (RegSpec::mask(2), "k2"), (RegSpec::mask(3), "k3"), (RegSpec::mask(4), "k4"), (RegSpec::mask(5), "k5"), (RegSpec::mask(6), "k6"), (RegSpec::mask(7), "k7"), ]; for (reg, name) in cases.iter() { assert_eq!(reg.name(), *name); } } let cases: Vec<(RegSpec, RegSpec)> = vec![ (RegSpec::d(0), RegSpec::eax()), (RegSpec::d(1), RegSpec::ecx()), (RegSpec::d(2), RegSpec::edx()), (RegSpec::d(3), RegSpec::ebx()), (RegSpec::d(4), RegSpec::esp()), (RegSpec::d(5), RegSpec::ebp()), (RegSpec::d(6), RegSpec::esi()), (RegSpec::d(7), RegSpec::edi()), (RegSpec::w(0), RegSpec::ax()), (RegSpec::w(1), RegSpec::cx()), (RegSpec::w(2), RegSpec::dx()), (RegSpec::w(3), RegSpec::bx()), (RegSpec::w(4), RegSpec::sp()), (RegSpec::w(5), RegSpec::bp()), (RegSpec::w(6), RegSpec::si()), (RegSpec::w(7), RegSpec::di()), (RegSpec::b(0), RegSpec::al()), (RegSpec::b(1), RegSpec::cl()), (RegSpec::b(2), RegSpec::dl()), (RegSpec::b(3), RegSpec::bl()), (RegSpec::b(4), RegSpec::ah()), (RegSpec::b(5), RegSpec::ch()), (RegSpec::b(6), RegSpec::dh()), (RegSpec::b(7), RegSpec::bh()), ]; for (reg1, reg2) in cases.iter() { assert_eq!(reg1, reg2); } } #[test] #[should_panic] fn invalid_mask_reg_panics() { RegSpec::mask(8); } #[test] #[should_panic] fn invalid_dword_reg_panics() { RegSpec::d(8); } #[test] #[should_panic] fn invalid_word_reg_panics() { RegSpec::w(8); } #[test] #[should_panic] fn invalid_byte_reg_panics() { RegSpec::b(8); } #[test] #[should_panic] fn invalid_x87_reg_panics() { RegSpec::st(8); } #[test] #[should_panic] fn invalid_xmm_reg_panics() { RegSpec::xmm(32); } #[test] #[should_panic] fn invalid_ymm_reg_panics() { RegSpec::ymm(32); } #[test] #[should_panic] fn invalid_zmm_reg_panics() { RegSpec::zmm(32); } } yaxpeax-x86-1.2.2/test/protected_mode/opcode.rs000064400000000000000000000055671046102023000175400ustar 00000000000000use yaxpeax_x86::protected_mode::{ConditionCode, Opcode}; #[test] fn conditional_instructions() { const JCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::JO, ConditionCode::O), (Opcode::JNO, ConditionCode::NO), (Opcode::JB, ConditionCode::B), (Opcode::JNB, ConditionCode::AE), (Opcode::JZ, ConditionCode::Z), (Opcode::JNZ, ConditionCode::NZ), (Opcode::JA, ConditionCode::A), (Opcode::JNA, ConditionCode::BE), (Opcode::JS, ConditionCode::S), (Opcode::JNS, ConditionCode::NS), (Opcode::JP, ConditionCode::P), (Opcode::JNP, ConditionCode::NP), (Opcode::JL, ConditionCode::L), (Opcode::JGE, ConditionCode::GE), (Opcode::JG, ConditionCode::G), (Opcode::JLE, ConditionCode::LE), ]; for (opc, cond) in JCC.iter() { assert!(opc.is_jcc()); assert!(!opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const SETCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::SETO, ConditionCode::O), (Opcode::SETNO, ConditionCode::NO), (Opcode::SETB, ConditionCode::B), (Opcode::SETAE, ConditionCode::AE), (Opcode::SETZ, ConditionCode::Z), (Opcode::SETNZ, ConditionCode::NZ), (Opcode::SETA, ConditionCode::A), (Opcode::SETBE, ConditionCode::BE), (Opcode::SETS, ConditionCode::S), (Opcode::SETNS, ConditionCode::NS), (Opcode::SETP, ConditionCode::P), (Opcode::SETNP, ConditionCode::NP), (Opcode::SETL, ConditionCode::L), (Opcode::SETGE, ConditionCode::GE), (Opcode::SETG, ConditionCode::G), (Opcode::SETLE, ConditionCode::LE), ]; for (opc, cond) in SETCC.iter() { assert!(!opc.is_jcc()); assert!(opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const CMOVCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::CMOVO, ConditionCode::O), (Opcode::CMOVNO, ConditionCode::NO), (Opcode::CMOVB, ConditionCode::B), (Opcode::CMOVNB, ConditionCode::AE), (Opcode::CMOVZ, ConditionCode::Z), (Opcode::CMOVNZ, ConditionCode::NZ), (Opcode::CMOVA, ConditionCode::A), (Opcode::CMOVNA, ConditionCode::BE), (Opcode::CMOVS, ConditionCode::S), (Opcode::CMOVNS, ConditionCode::NS), (Opcode::CMOVP, ConditionCode::P), (Opcode::CMOVNP, ConditionCode::NP), (Opcode::CMOVL, ConditionCode::L), (Opcode::CMOVGE, ConditionCode::GE), (Opcode::CMOVG, ConditionCode::G), (Opcode::CMOVLE, ConditionCode::LE), ]; for (opc, cond) in CMOVCC.iter() { assert!(!opc.is_jcc()); assert!(!opc.is_setcc()); assert!(opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } } yaxpeax-x86-1.2.2/test/protected_mode/operand.rs000064400000000000000000000040131046102023000177000ustar 00000000000000use yaxpeax_x86::protected_mode::{InstDecoder, Operand, RegSpec}; use yaxpeax_x86::MemoryAccessSize; #[test] fn register_widths() { assert_eq!(Operand::Register(RegSpec::esp()).width(), Some(4)); assert_eq!(Operand::Register(RegSpec::sp()).width(), Some(2)); assert_eq!(Operand::Register(RegSpec::cl()).width(), Some(1)); assert_eq!(Operand::Register(RegSpec::ch()).width(), Some(1)); assert_eq!(Operand::Register(RegSpec::gs()).width(), Some(2)); } #[test] fn memory_widths() { // the register operand directly doesn't report a size - it comes from the `Instruction` for // which this is an operand. assert_eq!(Operand::RegDeref(RegSpec::esp()).width(), None); fn mem_size_of(data: &[u8]) -> MemoryAccessSize { let decoder = InstDecoder::default(); decoder.decode_slice(data).unwrap().mem_size().unwrap() } // and checking the memory size direcly reports correct names assert_eq!(mem_size_of(&[0x32, 0x00]).size_name(), "byte"); assert_eq!(mem_size_of(&[0x66, 0x33, 0x00]).size_name(), "word"); assert_eq!(mem_size_of(&[0x33, 0x00]).size_name(), "dword"); } #[test] fn test_implied_memory_width() { fn mem_size_of(data: &[u8]) -> Option { let decoder = InstDecoder::default(); decoder.decode_slice(data).unwrap().mem_size().unwrap().bytes_size() } // test push, pop, call, and ret assert_eq!(mem_size_of(&[0xc3]), Some(4)); assert_eq!(mem_size_of(&[0xe8, 0x11, 0x22, 0x33, 0x44]), Some(4)); assert_eq!(mem_size_of(&[0x50]), Some(4)); assert_eq!(mem_size_of(&[0x58]), Some(4)); assert_eq!(mem_size_of(&[0x66, 0x50]), Some(4)); assert_eq!(mem_size_of(&[0x66, 0x58]), Some(4)); assert_eq!(mem_size_of(&[0xff, 0xf0]), Some(4)); assert_eq!(mem_size_of(&[0x66, 0xff, 0xf0]), Some(2)); // unlike 64-bit mode, operand-size prefixed call and jump do have a different size: they read // two bytes. assert_eq!(mem_size_of(&[0x66, 0xff, 0x10]), Some(2)); assert_eq!(mem_size_of(&[0x66, 0xff, 0x20]), Some(2)); } yaxpeax-x86-1.2.2/test/protected_mode/regspec.rs000064400000000000000000000030051046102023000177000ustar 00000000000000use yaxpeax_x86::protected_mode::{register_class, RegSpec}; use std::collections::{BTreeMap, HashMap}; #[test] fn test_ord() { let _: BTreeMap = BTreeMap::new(); } #[test] fn test_hash() { let _: HashMap = HashMap::new(); } #[cfg(features="fmt")] #[test] fn test_labels() { assert_eq!(RegSpec::eip().name(), "eip"); assert_eq!(RegSpec::ebp().name(), "ebp"); assert_eq!(RegSpec::gs().name(), "gs"); assert_eq!(RegSpec::al().name(), "al"); } #[cfg(features="fmt")] #[test] fn test_bank_names() { assert_eq!(RegSpec::al().class().name(), "byte"); assert_eq!(RegSpec::ax().class().name(), "word"); assert_eq!(RegSpec::eax().class().name(), "dword"); assert_eq!(RegSpec::fs().class().name(), "segment"); assert_eq!(RegSpec::eflags().class().name(), "eflags"); assert_eq!(RegSpec::eip().class().name(), "eip"); assert_eq!(RegSpec::st0().class().name(), "x87-stack"); assert_eq!(RegSpec::mm0().class().name(), "mmx"); assert_eq!(RegSpec::xmm0().class().name(), "xmm"); assert_eq!(RegSpec::ymm0().class().name(), "ymm"); assert_eq!(RegSpec::zmm0().class().name(), "zmm"); } // this should compile. #[test] fn match_bank_kind() { match RegSpec::al().class() { register_class::X => { panic!("al is an xmm register? don't think so"); } register_class::B => { println!("al is a byte register"); } other => { panic!("unknown register kind: {:?}", other); } } } yaxpeax-x86-1.2.2/test/real_mode/mod.rs000064400000000000000000071773071046102023000160110ustar 00000000000000mod operand; mod opcode; use std::fmt::Write; use yaxpeax_arch::{AddressBase, Decoder, U8Reader, LengthedInstruction}; use yaxpeax_x86::real_mode::InstDecoder; fn test_invalid(data: &[u8]) { test_invalid_under(&InstDecoder::default(), data); } fn test_invalid_under(decoder: &InstDecoder, data: &[u8]) { let mut reader = U8Reader::new(data); if let Ok(inst) = decoder.decode(&mut reader) { // realistically, the chances an error only shows up under non-fmt builds seems unlikely, // but try to report *something* in such cases. cfg_if::cfg_if! { if #[cfg(feature="fmt")] { panic!("decoded {:?} from {:02x?} under decoder {}", inst.opcode(), data, decoder); } else { // don't warn about the unused inst here let _ = inst; panic!("decoded instruction from {:02x?} under decoder ", data); } } } else { // this is fine } } #[allow(dead_code)] fn test_display(data: &[u8], expected: &'static str) { test_display_under(&InstDecoder::default(), data, expected); } fn test_display_under(decoder: &InstDecoder, data: &[u8], expected: &'static str) { let mut hex = String::new(); for b in data { write!(hex, "{:02x}", b).unwrap(); } let mut reader = U8Reader::new(data); match decoder.decode(&mut reader) { Ok(instr) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { let text = format!("{}", instr); assert!( text == expected, "display error for {}:\n decoded: {:?} under decoder {}\n displayed: {}\n expected: {}\n", hex, instr, decoder, text, expected ); } else { eprintln!("non-fmt build cannot compare text equality") } } // while we're at it, test that the instruction is as long, and no longer, than its // input assert_eq!((0u32.wrapping_offset(instr.len()).to_linear()) as usize, data.len(), "instruction length is incorrect, wanted instruction {}", expected); }, Err(e) => { cfg_if::cfg_if! { if #[cfg(feature="fmt")] { assert!(false, "decode error ({}) for {} under decoder {}:\n expected: {}\n", e, hex, decoder, expected); } else { // avoid the unused `e` warning let _ = e; assert!(false, "decode error () for {} under decoder :\n expected: {}\n", hex, expected); } } } } } #[test] fn only_16bit() { test_display(&[0x66, 0x9a, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66], "callf 0x6655:0x44332211"); test_display(&[0x9a, 0x11, 0x22, 0x33, 0x44], "callf 0x4433:0x2211"); test_display(&[0xac], "lods al, byte ds:[si]"); test_display(&[0xae], "scas byte es:[di], al"); test_display(&[0x67, 0xac], "lods al, byte ds:[esi]"); test_display(&[0x67, 0xae], "scas byte es:[edi], al"); test_display(&[0xf3, 0xa4], "rep movs byte es:[di], byte ds:[si]"); test_display(&[0x67, 0xf3, 0xa4], "rep movs byte es:[edi], byte ds:[esi]"); test_display(&[0xf3, 0xa5], "rep movs word es:[di], word ds:[si]"); test_display(&[0x67, 0xf3, 0xa5], "rep movs word es:[edi], word ds:[esi]"); test_display(&[0x8b, 0x0e, 0x55, 0xaa], "mov cx, word [0xaa55]"); test_display(&[0x66, 0x8b, 0x0e, 0x55, 0xaa], "mov ecx, dword [0xaa55]"); test_display(&[0x67, 0x8b, 0x0e], "mov cx, word [esi]"); test_display(&[0x66, 0x67, 0x8b, 0x0e], "mov ecx, dword [esi]"); } #[test] fn test_real_mode() { test_display(&[0x00, 0xcc], "add ah, cl"); test_display(&[0x03, 0x0b], "add cx, word [bp + di * 1]"); test_display(&[0x06], "push es"); test_display(&[0x07], "pop es"); test_display(&[0x0e], "push cs"); test_display(&[0x0f, 0x01, 0x38], "invlpg byte [bx + si * 1]"); test_display(&[0x0f, 0x01, 0x3f], "invlpg byte [bx]"); test_display(&[0x0f, 0x01, 0x40, 0xff], "sgdt ptr [bx + si * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x41, 0xff], "sgdt ptr [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x49, 0xff], "sidt ptr [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x51, 0xff], "lgdt ptr [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x59, 0xff], "lidt ptr [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x61, 0xff], "smsw word [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x71, 0xff], "lmsw word [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0x79, 0xff], "invlpg byte [bx + di * 1 - 0x1]"); test_display(&[0x0f, 0x01, 0xc0], "enclv"); test_display(&[0x0f, 0x01, 0xc1], "vmcall"); test_display(&[0x0f, 0x01, 0xc2], "vmlaunch"); test_display(&[0x0f, 0x01, 0xc3], "vmresume"); test_display(&[0x0f, 0x01, 0xc4], "vmxoff"); test_display(&[0x0f, 0x01, 0xc5], "pconfig"); test_display(&[0x0f, 0x01, 0xc8], "monitor"); test_display(&[0x0f, 0x01, 0xc8], "monitor"); test_display(&[0x0f, 0x01, 0xc9], "mwait"); test_display(&[0x0f, 0x01, 0xc9], "mwait"); test_display(&[0x0f, 0x01, 0xca], "clac"); test_display(&[0x0f, 0x01, 0xcb], "stac"); test_display(&[0x0f, 0x01, 0xcf], "encls"); test_display(&[0x0f, 0x01, 0xd0], "xgetbv"); test_display(&[0x0f, 0x01, 0xd1], "xsetbv"); test_display(&[0x0f, 0x01, 0xd4], "vmfunc"); test_display(&[0x0f, 0x01, 0xd5], "xend"); test_display(&[0x0f, 0x01, 0xd6], "xtest"); test_display(&[0x0f, 0x01, 0xd7], "enclu"); test_display(&[0x0f, 0x01, 0xd8], "vmrun ax"); test_display(&[0x0f, 0x01, 0xd9], "vmmcall"); test_display(&[0x0f, 0x01, 0xda], "vmload ax"); test_display(&[0x0f, 0x01, 0xdb], "vmsave ax"); test_display(&[0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x0f, 0x01, 0xdd], "clgi"); test_display(&[0x0f, 0x01, 0xde], "skinit eax"); test_display(&[0x0f, 0x01, 0xdf], "invlpga ax, ecx"); test_display(&[0x0f, 0x01, 0xe0], "smsw ax"); test_display(&[0x0f, 0x01, 0xe1], "smsw cx"); test_display(&[0x0f, 0x01, 0xe2], "smsw dx"); test_display(&[0x0f, 0x01, 0xe3], "smsw bx"); test_display(&[0x0f, 0x01, 0xe4], "smsw sp"); test_display(&[0x0f, 0x01, 0xe5], "smsw bp"); test_display(&[0x0f, 0x01, 0xe6], "smsw si"); test_display(&[0x0f, 0x01, 0xe7], "smsw di"); test_display(&[0x0f, 0x01, 0xee], "rdpkru"); test_display(&[0x0f, 0x01, 0xef], "wrpkru"); test_display(&[0x0f, 0x01, 0xf0], "lmsw ax"); test_display(&[0x0f, 0x01, 0xf1], "lmsw cx"); test_display(&[0x0f, 0x01, 0xf2], "lmsw dx"); test_display(&[0x0f, 0x01, 0xf3], "lmsw bx"); test_display(&[0x0f, 0x01, 0xf4], "lmsw sp"); test_display(&[0x0f, 0x01, 0xf5], "lmsw bp"); test_display(&[0x0f, 0x01, 0xf6], "lmsw si"); test_display(&[0x0f, 0x01, 0xf7], "lmsw di"); test_display(&[0x0f, 0x01, 0xf9], "rdtscp"); test_display(&[0x0f, 0x01, 0xfa], "monitorx"); test_display(&[0x0f, 0x01, 0xfb], "mwaitx"); test_display(&[0x0f, 0x01, 0xfc], "clzero"); test_display(&[0x0f, 0x01, 0xfd], "rdpru ecx"); test_display(&[0x0f, 0x02, 0x01], "lar ax, word [bx + di * 1]"); test_display(&[0x0f, 0x02, 0xc1], "lar ax, cx"); test_display(&[0x0f, 0x03, 0x01], "lsl ax, word [bx + di * 1]"); test_display(&[0x0f, 0x03, 0xc1], "lsl ax, cx"); test_display(&[0x0f, 0x05], "syscall"); test_display(&[0x0f, 0x06], "clts"); test_display(&[0x0f, 0x07], "sysret"); test_display(&[0x0f, 0x0d, 0x08], "prefetchw zmmword [bx + si * 1]"); test_display(&[0x0f, 0x0f, 0x38, 0x8e], "pfpnacc mm7, qword [bx + si * 1]"); test_display(&[0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); test_display(&[0x0f, 0x0f, 0xe0, 0x8a], "pfnacc mm4, mm0"); test_display(&[0x0f, 0x12, 0x0f], "movlps xmm1, qword [bx]"); test_display(&[0x0f, 0x12, 0xc0], "movhlps xmm0, xmm0"); test_display(&[0x0f, 0x12, 0xcf], "movhlps xmm1, xmm7"); test_display(&[0x0f, 0x13, 0x00], "movlps qword [bx + si * 1], xmm0"); test_display(&[0x0f, 0x14, 0x08], "unpcklps xmm1, xmmword [bx + si * 1]"); test_display(&[0x0f, 0x15, 0x08], "unpckhps xmm1, xmmword [bx + si * 1]"); test_display(&[0x0f, 0x16, 0x0f], "movhps xmm1, qword [bx]"); test_display(&[0x0f, 0x16, 0xc0], "movlhps xmm0, xmm0"); test_display(&[0x0f, 0x16, 0xcf], "movlhps xmm1, xmm7"); test_display(&[0x0f, 0x17, 0x00], "movhps qword [bx + si * 1], xmm0"); test_display(&[0x0f, 0x18, 0x00], "prefetchnta zmmword [bx + si * 1]"); test_display(&[0x0f, 0x18, 0x08], "prefetch0 zmmword [bx + si * 1]"); test_display(&[0x0f, 0x18, 0x10], "prefetch1 zmmword [bx + si * 1]"); test_display(&[0x0f, 0x18, 0x18], "prefetch2 zmmword [bx + si * 1]"); test_display(&[0x0f, 0x18, 0x20], "nop zmmword [bx + si * 1]"); test_display(&[0x0f, 0x18, 0xc0], "nop ax"); test_display(&[0x0f, 0x18, 0xcc], "nop sp"); test_display(&[0x0f, 0x19, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1a, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1b, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1c, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1d, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1e, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x1f, 0x20], "nop word [bx + si * 1]"); test_display(&[0x0f, 0x20, 0xc0], "mov eax, cr0"); test_display(&[0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0x0f, 0x22, 0xc0], "mov cr0, eax"); test_display(&[0x0f, 0x22, 0xc7], "mov cr0, edi"); test_display(&[0x0f, 0x23, 0xc8], "mov dr1, eax"); test_display(&[0x0f, 0x23, 0xcf], "mov dr1, edi"); test_display(&[0x0f, 0x28, 0x00], "movaps xmm0, xmmword [bx + si * 1]"); test_display(&[0x0f, 0x28, 0xd0], "movaps xmm2, xmm0"); test_display(&[0x0f, 0x29, 0x00], "movaps xmmword [bx + si * 1], xmm0"); test_display(&[0x0f, 0x2a, 0x00], "cvtpi2ps xmm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x2a, 0xcf], "cvtpi2ps xmm1, mm7"); test_display(&[0x0f, 0x2b, 0x00], "movntps xmmword [bx + si * 1], xmm0"); test_display(&[0x0f, 0x2c, 0xcf], "cvttps2pi mm1, xmm7"); test_display(&[0x0f, 0x2e, 0x00], "ucomiss xmm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x2f, 0x00], "comiss xmm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x30], "wrmsr"); test_display(&[0x0f, 0x31], "rdtsc"); test_display(&[0x0f, 0x32], "rdmsr"); test_display(&[0x0f, 0x33], "rdpmc"); test_display(&[0x0f, 0x34], "sysenter"); test_display(&[0x0f, 0x35], "sysexit"); test_display(&[0x0f, 0x37], "getsec"); test_display(&[0x0f, 0x38, 0x00, 0xda], "pshufb mm3, mm2"); test_display(&[0x0f, 0x38, 0xc8, 0x12], "sha1nexte xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x38, 0xc9, 0x12], "sha1msg1 xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x38, 0xca, 0x12], "sha1msg2 xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x38, 0xcb, 0x12], "sha256rnds2 xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x38, 0xcc, 0x12], "sha256msg1 xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x38, 0xcd, 0x12], "sha256msg2 xmm2, xmmword [bp + si * 1]"); test_display(&[0x0f, 0x3a, 0x0f, 0xc1, 0x23], "palignr mm0, mm1, 0x23"); test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0x40], "sha1rnds4 xmm2, xmmword [bp + si * 1], 0x40"); test_display(&[0x0f, 0x3a, 0xcc, 0x12, 0xff], "sha1rnds4 xmm2, xmmword [bp + si * 1], 0xff"); test_display(&[0x0f, 0x43, 0xec], "cmovnb bp, sp"); test_display(&[0x0f, 0x50, 0xc1], "movmskps eax, xmm1"); test_display(&[0x0f, 0x51, 0x01], "sqrtps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x52, 0x01], "rsqrtps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x53, 0x01], "rcpps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x54, 0x01], "andps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x55, 0x01], "andnps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x56, 0x01], "orps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x57, 0x01], "xorps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x58, 0x01], "addps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x59, 0x01], "mulps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5a, 0x01], "cvtps2pd xmm0, qword [bx + di * 1]"); test_display(&[0x0f, 0x5b, 0x01], "cvtdq2ps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5c, 0x01], "subps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5d, 0x01], "minps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5e, 0x01], "divps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x5f, 0x01], "maxps xmm0, xmmword [bx + di * 1]"); test_display(&[0x0f, 0x60, 0x00], "punpcklbw mm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x60, 0xc2], "punpcklbw mm0, mm2"); test_display(&[0x0f, 0x61, 0x00], "punpcklwd mm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x61, 0xc2], "punpcklwd mm0, mm2"); test_display(&[0x0f, 0x62, 0x00], "punpckldq mm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x62, 0xc2], "punpckldq mm0, mm2"); test_display(&[0x0f, 0x63, 0x00], "packsswb mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x63, 0xc2], "packsswb mm0, mm2"); test_display(&[0x0f, 0x64, 0x00], "pcmpgtb mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x64, 0xc2], "pcmpgtb mm0, mm2"); test_display(&[0x0f, 0x65, 0x00], "pcmpgtw mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x65, 0xc2], "pcmpgtw mm0, mm2"); test_display(&[0x0f, 0x66, 0x00], "pcmpgtd mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x66, 0xc2], "pcmpgtd mm0, mm2"); test_display(&[0x0f, 0x67, 0x00], "packuswb mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x67, 0xc2], "packuswb mm0, mm2"); test_display(&[0x0f, 0x68, 0x00], "punpckhbw mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x68, 0xc2], "punpckhbw mm0, mm2"); test_display(&[0x0f, 0x69, 0x00], "punpckhwd mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x69, 0xc2], "punpckhwd mm0, mm2"); test_display(&[0x0f, 0x6a, 0x00], "punpckhdq mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x6a, 0xc2], "punpckhdq mm0, mm2"); test_display(&[0x0f, 0x6b, 0x00], "packssdw mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x6b, 0xc2], "packssdw mm0, mm2"); test_display(&[0x0f, 0x6e, 0x00], "movd mm0, dword [bx + si * 1]"); test_display(&[0x0f, 0x6e, 0xc2], "movd mm0, edx"); test_display(&[0x0f, 0x6f, 0x00], "movq mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0x6f, 0xc2], "movq mm0, mm2"); test_display(&[0x0f, 0x6f, 0xe9], "movq mm5, mm1"); test_display(&[0x0f, 0x6f, 0xfb], "movq mm7, mm3"); test_display(&[0x0f, 0x70, 0x00, 0x7f], "pshufw mm0, qword [bx + si * 1], 0x7f"); test_display(&[0x0f, 0x71, 0xd0, 0x7f], "psrlw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xe0, 0x7f], "psraw mm0, 0x7f"); test_display(&[0x0f, 0x71, 0xf0, 0x7f], "psllw mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xd0, 0x7f], "psrld mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xe0, 0x7f], "psrad mm0, 0x7f"); test_display(&[0x0f, 0x72, 0xf0, 0x7f], "pslld mm0, 0x7f"); test_display(&[0x0f, 0x73, 0xd0, 0x7f], "psrlq mm0, 0x7f"); test_display(&[0x0f, 0x73, 0xf0, 0x7f], "psllq mm0, 0x7f"); test_display(&[0x0f, 0x74, 0xc2], "pcmpeqb mm0, mm2"); test_display(&[0x0f, 0x75, 0xc2], "pcmpeqw mm0, mm2"); test_display(&[0x0f, 0x76, 0xc2], "pcmpeqd mm0, mm2"); test_display(&[0x0f, 0x78, 0x0b], "vmread dword [bp + di * 1], ecx"); test_display(&[0x0f, 0x78, 0xc4], "vmread esp, eax"); test_display(&[0x0f, 0x79, 0x0b], "vmwrite ecx, dword [bp + di * 1]"); test_display(&[0x0f, 0x79, 0xc5], "vmwrite eax, ebp"); test_display(&[0x0f, 0x7e, 0xcf], "movd edi, mm1"); test_display(&[0x0f, 0x7f, 0x0f], "movq qword [bx], mm1"); test_display(&[0x0f, 0x7f, 0xcf], "movq mm7, mm1"); test_display(&[0x0f, 0x86, 0x8b, 0x01], "jna $+0x18b"); test_display(&[0x0f, 0x97, 0x00], "seta byte [bx + si * 1]"); test_display(&[0x0f, 0x97, 0x08], "seta byte [bx + si * 1]"); test_display(&[0x0f, 0x97, 0xc0], "seta al"); test_display(&[0x0f, 0x97, 0xc8], "seta al"); test_display(&[0x0f, 0xa0], "push fs"); test_display(&[0x0f, 0xa1], "pop fs"); test_display(&[0x0f, 0xa2], "cpuid"); test_display(&[0x0f, 0xa3, 0xd0], "bt ax, dx"); test_display(&[0x0f, 0xa4, 0xc0, 0x11], "shld ax, ax, 0x11"); test_display(&[0x0f, 0xa5, 0xc0], "shld ax, ax, cl"); test_display(&[0x0f, 0xa5, 0xc9], "shld cx, cx, cl"); test_display(&[0x0f, 0xab, 0xd0], "bts ax, dx"); test_display(&[0x0f, 0xac, 0xc0, 0x11], "shrd ax, ax, 0x11"); test_display(&[0x0f, 0xad, 0xc9], "shrd cx, cx, cl"); test_display(&[0x0f, 0xae, 0x04], "fxsave ptr [si]"); test_display(&[0x0f, 0xae, 0x0c], "fxrstor ptr [si]"); test_display(&[0x0f, 0xae, 0x14], "ldmxcsr dword [si]"); test_display(&[0x0f, 0xae, 0x1c], "stmxcsr dword [si]"); test_display(&[0x0f, 0xae, 0x24], "xsave ptr [si]"); test_display(&[0x0f, 0xae, 0x2c], "xrstor ptr [si]"); test_display(&[0x0f, 0xae, 0x34], "xsaveopt ptr [si]"); test_display(&[0x0f, 0xae, 0x3c], "clflush zmmword [si]"); test_display(&[0x0f, 0xaf, 0xc2], "imul ax, dx"); test_display(&[0x0f, 0xb3, 0xd0], "btr ax, dx"); test_display(&[0x0f, 0xbb, 0x17], "btc word [bx], dx"); test_display(&[0x0f, 0xbc, 0xd3], "bsf dx, bx"); test_display(&[0x0f, 0xbc, 0xd3], "bsf dx, bx"); test_display(&[0x0f, 0xbe, 0x83, 0xb4, 0x00], "movsx ax, byte [bp + di * 1 + 0xb4]"); test_display(&[0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0x0f, 0xc1, 0xcc], "xadd sp, cx"); test_display(&[0x0f, 0xc3, 0x03], "movnti dword [bp + di * 1], eax"); test_display(&[0x0f, 0xc4, 0x00, 0x14], "pinsrw mm0, word [bx + si * 1], 0x14"); test_display(&[0x0f, 0xc4, 0xc0, 0x14], "pinsrw mm0, eax, 0x14"); test_display(&[0x0f, 0xc5, 0xd1, 0x00], "pextrw edx, mm1, 0x0"); test_display(&[0x0f, 0xc7, 0x0f], "cmpxchg8b qword [bx]"); test_display(&[0x0f, 0xc7, 0x37], "vmptrld qword [bx]"); test_display(&[0x0f, 0xc7, 0x3f], "vmptrst qword [bx]"); test_display(&[0x0f, 0xc7, 0x5c, 0x24], "xrstors ptr [si + 0x24]"); test_display(&[0x0f, 0xc7, 0x64, 0x24], "xsavec ptr [si + 0x24]"); test_display(&[0x0f, 0xc7, 0x6c, 0x24], "xsaves ptr [si + 0x24]"); test_display(&[0x0f, 0xc7, 0x74, 0x24], "vmptrld qword [si + 0x24]"); test_display(&[0x0f, 0xc7, 0x7c, 0x24], "vmptrst qword [si + 0x24]"); test_display(&[0x0f, 0xc7, 0xf5], "rdrand bp"); test_display(&[0x0f, 0xc7, 0xfd], "rdseed bp"); test_display(&[0x0f, 0xd1, 0x00], "psrlw mm0, qword [bx + si * 1]"); test_display(&[0x0f, 0xd1, 0xcf], "psrlw mm1, mm7"); test_display(&[0x0f, 0xd7, 0xcf], "pmovmskb ecx, mm7"); test_display(&[0x0f, 0xd8, 0xc2], "psubusb mm0, mm2"); test_display(&[0x0f, 0xd9, 0xc2], "psubusw mm0, mm2"); test_display(&[0x0f, 0xda, 0xc2], "pminub mm0, mm2"); test_display(&[0x0f, 0xdb, 0xc2], "pand mm0, mm2"); test_display(&[0x0f, 0xdc, 0xc2], "paddusb mm0, mm2"); test_display(&[0x0f, 0xdd, 0xc2], "paddusw mm0, mm2"); test_display(&[0x0f, 0xde, 0xc2], "pmaxub mm0, mm2"); test_display(&[0x0f, 0xdf, 0xc2], "pandn mm0, mm2"); test_display(&[0x0f, 0xe5, 0x3d], "pmulhw mm7, qword [di]"); test_display(&[0x0f, 0xe7, 0x03], "movntq qword [bp + di * 1], mm0"); test_display(&[0x0f, 0xe8, 0xc2], "psubsb mm0, mm2"); test_display(&[0x0f, 0xe9, 0xc2], "psubsw mm0, mm2"); test_display(&[0x0f, 0xea, 0xc2], "pminsw mm0, mm2"); test_display(&[0x0f, 0xeb, 0xc2], "por mm0, mm2"); test_display(&[0x0f, 0xec, 0xc2], "paddsb mm0, mm2"); test_display(&[0x0f, 0xed, 0xc2], "paddsw mm0, mm2"); test_display(&[0x0f, 0xee, 0xc2], "pmaxsw mm0, mm2"); test_display(&[0x0f, 0xef, 0xc2], "pxor mm0, mm2"); test_display(&[0x0f, 0xf1, 0x02], "psllw mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf1, 0xc2], "psllw mm0, mm2"); test_display(&[0x0f, 0xf2, 0x02], "pslld mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf2, 0xc2], "pslld mm0, mm2"); test_display(&[0x0f, 0xf3, 0x02], "psllq mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf3, 0xc2], "psllq mm0, mm2"); test_display(&[0x0f, 0xf4, 0x02], "pmuludq mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf4, 0xc2], "pmuludq mm0, mm2"); test_display(&[0x0f, 0xf5, 0x02], "pmaddwd mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf5, 0xc2], "pmaddwd mm0, mm2"); test_display(&[0x0f, 0xf6, 0x02], "psadbw mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf6, 0xc2], "psadbw mm0, mm2"); test_display(&[0x0f, 0xf7, 0xc1], "maskmovq mm0, mm1"); test_display(&[0x0f, 0xf8, 0x02], "psubb mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf8, 0xc2], "psubb mm0, mm2"); test_display(&[0x0f, 0xf9, 0x02], "psubw mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xf9, 0xc2], "psubw mm0, mm2"); test_display(&[0x0f, 0xfa, 0x02], "psubd mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xfa, 0xc2], "psubd mm0, mm2"); test_display(&[0x0f, 0xfb, 0x02], "psubq mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xfb, 0xc2], "psubq mm0, mm2"); test_display(&[0x0f, 0xfc, 0x02], "paddb mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xfc, 0xc2], "paddb mm0, mm2"); test_display(&[0x0f, 0xfd, 0x02], "paddw mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xfd, 0xc2], "paddw mm0, mm2"); test_display(&[0x0f, 0xfd, 0xd2], "paddw mm2, mm2"); test_display(&[0x0f, 0xfe, 0x02], "paddd mm0, qword [bp + si * 1]"); test_display(&[0x0f, 0xfe, 0xc2], "paddd mm0, mm2"); test_display(&[0x0f, 0xff, 0x6b, 0xac], "ud0 ebp, dword [bp + di * 1 - 0x54]"); test_display(&[0x16], "push ss"); test_display(&[0x17], "pop ss"); test_display(&[0x1e], "push ds"); test_display(&[0x1f], "pop ds"); test_display(&[0x26, 0x36, 0x0f, 0x0f, 0x70, 0xfb, 0x0c], "pi2fw mm6, qword ss:[bx + si * 1 - 0x5]"); test_display(&[0x26, 0x66, 0x67, 0x0f, 0x38, 0xdf, 0xe4], "aesdeclast xmm4, xmm4"); test_display(&[0x27], "daa"); test_display(&[0x29, 0xc8], "sub ax, cx"); test_display(&[0x2e, 0x36, 0x0f, 0x18, 0xe7], "nop di"); test_display(&[0x2e, 0x3e, 0x66, 0x3e, 0x0f, 0x3a, 0x41, 0x30, 0x48], "dppd xmm6, xmmword [bx + si * 1], 0x48"); test_display(&[0x2e, 0x66, 0x0f, 0x3a, 0x0d, 0x40, 0x2d, 0x57], "blendpd xmm0, xmmword cs:[bx + si * 1 + 0x2d], 0x57"); test_display(&[0x2e, 0x66, 0x26, 0x64, 0x0f, 0x3a, 0x21, 0x0b, 0xb1], "insertps xmm1, dword fs:[bp + di * 1], -0x4f"); test_display(&[0x2f], "das"); test_display(&[0x31, 0xc9], "xor cx, cx"); test_display(&[0x33, 0x04], "xor ax, word [si]"); test_display(&[0x33, 0x05], "xor ax, word [di]"); test_display(&[0x33, 0x08], "xor cx, word [bx + si * 1]"); test_display(&[0x33, 0x20], "xor sp, word [bx + si * 1]"); test_display(&[0x33, 0x34], "xor si, word [si]"); test_display(&[0x33, 0x41, 0x23], "xor ax, word [bx + di * 1 + 0x23]"); test_display(&[0x33, 0x81, 0x23, 0x01], "xor ax, word [bx + di * 1 + 0x123]"); test_display(&[0x33, 0x84, 0xa5, 0x11], "xor ax, word [si + 0x11a5]"); test_display(&[0x33, 0xb4, 0x25, 0x20], "xor si, word [si + 0x2025]"); test_display(&[0x30, 0x40, 0x50], "xor byte [bx + si * 1 + 0x50], al"); test_display(&[0x33, 0xc0], "xor ax, ax"); test_display(&[0x33, 0xc1], "xor ax, cx"); test_display(&[0x36, 0x26, 0x66, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08], "movdir64b bp, zmmword es:[di + 0x80b]"); test_display(&[0x36, 0x26, 0x66, 0x67, 0x0f, 0x38, 0xf8, 0xad, 0x0b, 0x08, 0x29, 0x07], "movdir64b ebp, zmmword es:[ebp + 0x729080b]"); test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e], "movdiri dword cs:[di + 0x3e], edx"); test_display(&[0x36, 0x36, 0x2e, 0x0f, 0x38, 0xf9, 0x55, 0x3e], "movdiri dword cs:[di + 0x3e], edx"); test_display(&[0x37], "aaa"); test_display(&[0x39, 0xc6], "cmp si, ax"); test_display(&[0x3e, 0x0f, 0x38, 0xf6, 0x23], "wrss dword [bp + di * 1], esp"); test_display(&[0x3e, 0x64, 0xf3, 0x64, 0x0f, 0x38, 0xf8, 0x72, 0x54], "enqcmds si, zmmword fs:[bp + si * 1 + 0x54]"); test_display(&[0x3f], "aas"); test_display(&[0x40], "inc ax"); test_display(&[0x41], "inc cx"); test_display(&[0x47], "inc di"); test_display(&[0x48], "dec ax"); test_display(&[0x4f], "dec di"); test_display(&[0x5b], "pop bx"); test_display(&[0x5e], "pop si"); test_display(&[0x60], "pusha"); test_display(&[0x61], "popa"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0x0a], "vmovups xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0x4a, 0x01], "vmovups xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x10, 0xca], "vmovups xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x0a], "vmovups xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0x4a, 0x01], "vmovups xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x11, 0xca], "vmovups xmm2, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0x4a, 0x01], "vmovlps xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x0a], "vmovlps qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x13, 0x4a, 0x01], "vmovlps qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0x0a], "vunpcklps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0x4a, 0x01], "vunpcklps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x14, 0xca], "vunpcklps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0x4a, 0x01], "vunpckhps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x15, 0xca], "vunpckhps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0x4a, 0x01], "vmovhps xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x16, 0xca], "vmovlhps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x0a], "vmovhps qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x17, 0x4a, 0x01], "vmovhps qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0x0a], "vmovaps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0x4a, 0x01], "vmovaps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x28, 0xca], "vmovaps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x0a], "vmovaps xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0x4a, 0x01], "vmovaps xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x29, 0xca], "vmovaps xmm2, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x0a], "vmovntps xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x2b, 0x4a, 0x01], "vmovntps xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0x0a], "vsqrtps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0x4a, 0x01], "vsqrtps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x51, 0xca], "vsqrtps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0x0a], "vandps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0x4a, 0x01], "vandps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x54, 0xca], "vandps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0x0a], "vandnps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0x4a, 0x01], "vandnps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x55, 0xca], "vandnps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0x0a], "vorps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0x4a, 0x01], "vorps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x56, 0xca], "vorps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0x0a], "vxorps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0x4a, 0x01], "vxorps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x57, 0xca], "vxorps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0x0a], "vaddps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0x4a, 0x01], "vaddps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x58, 0xca], "vaddps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0x0a], "vmulps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0x4a, 0x01], "vmulps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x59, 0xca], "vmulps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0x0a], "vcvtps2pd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5a, 0xca], "vcvtps2pd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0x0a], "vcvtdq2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5b, 0xca], "vcvtdq2ps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0x0a], "vsubps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0x4a, 0x01], "vsubps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5c, 0xca], "vsubps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0x0a], "vminps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0x4a, 0x01], "vminps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5d, 0xca], "vminps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0x0a], "vdivps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0x4a, 0x01], "vdivps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5e, 0xca], "vdivps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0x0a], "vmaxps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0x4a, 0x01], "vmaxps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x5f, 0xca], "vmaxps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0x0a], "vcvttps2udq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x78, 0xca], "vcvttps2udq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0x0a], "vcvtps2udq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0x79, 0xca], "vcvtps2udq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc2, 0xca, 0xcc], "vcmpps k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x08, 0xc6, 0xca, 0xcc], "vshufps xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0x0a], "vmovups xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0x4a, 0x01], "vmovups xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x10, 0xca], "vmovups xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x0a], "vmovups xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0x4a, 0x01], "vmovups xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x11, 0xca], "vmovups xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x14, 0xca], "vunpcklps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x15, 0xca], "vunpckhps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0x0a], "vmovaps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0x4a, 0x01], "vmovaps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x28, 0xca], "vmovaps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0x0a], "vmovaps xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0x4a, 0x01], "vmovaps xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x29, 0xca], "vmovaps xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0x0a], "vsqrtps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x51, 0xca], "vsqrtps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x54, 0xca], "vandps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x55, 0xca], "vandnps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x56, 0xca], "vorps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x57, 0xca], "vxorps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x58, 0xca], "vaddps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x59, 0xca], "vmulps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5c, 0xca], "vsubps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5d, 0xca], "vminps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5e, 0xca], "vdivps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x5f, 0xca], "vmaxps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x78, 0xca], "vcvttps2udq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0x79, 0xca], "vcvtps2udq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x0d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x14, 0x0a], "vunpcklps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x14, 0x4a, 0x01], "vunpcklps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x15, 0x0a], "vunpckhps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x15, 0x4a, 0x01], "vunpckhps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0x0a], "vsqrtps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0x4a, 0x01], "vsqrtps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x51, 0xca], "vsqrtps zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x54, 0x0a], "vandps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x54, 0x4a, 0x01], "vandps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x55, 0x0a], "vandnps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x55, 0x4a, 0x01], "vandnps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x56, 0x0a], "vorps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x56, 0x4a, 0x01], "vorps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x57, 0x0a], "vxorps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x57, 0x4a, 0x01], "vxorps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0x0a], "vaddps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0x4a, 0x01], "vaddps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x58, 0xca], "vaddps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0x0a], "vmulps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0x4a, 0x01], "vmulps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x59, 0xca], "vmulps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5a, 0x0a], "vcvtps2pd xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0x0a], "vcvtdq2ps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5b, 0xca], "vcvtdq2ps zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0x0a], "vsubps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0x4a, 0x01], "vsubps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5c, 0xca], "vsubps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5d, 0x0a], "vminps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5d, 0x4a, 0x01], "vminps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0x0a], "vdivps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0x4a, 0x01], "vdivps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5e, 0xca], "vdivps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5f, 0x0a], "vmaxps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x5f, 0x4a, 0x01], "vmaxps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x78, 0x0a], "vcvttps2udq xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0x0a], "vcvtps2udq xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0x79, 0xca], "vcvtps2udq zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0xc2, 0x0a, 0xcc], "vcmpps k1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0xc6, 0x0a, 0xcc], "vshufps xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x18, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x14, 0x0a], "vunpcklps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x15, 0x0a], "vunpckhps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0x0a], "vsqrtps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x51, 0xca], "vsqrtps zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x54, 0x0a], "vandps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x55, 0x0a], "vandnps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x56, 0x0a], "vorps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x57, 0x0a], "vxorps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0x0a], "vaddps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x58, 0xca], "vaddps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0x0a], "vmulps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x59, 0xca], "vmulps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0x0a], "vsubps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5c, 0xca], "vsubps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5d, 0x0a], "vminps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0x0a], "vdivps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5e, 0xca], "vdivps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5f, 0x0a], "vmaxps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x1d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0x0a], "vmovups ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0x4a, 0x01], "vmovups ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x10, 0xca], "vmovups ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0x0a], "vmovups ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0x4a, 0x01], "vmovups ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x11, 0xca], "vmovups ymm2, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0x0a], "vunpcklps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0x4a, 0x01], "vunpcklps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x14, 0xca], "vunpcklps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0x0a], "vunpckhps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0x4a, 0x01], "vunpckhps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x15, 0xca], "vunpckhps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x0a], "vmovaps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0x4a, 0x01], "vmovaps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x28, 0xca], "vmovaps ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0x0a], "vmovaps ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0x4a, 0x01], "vmovaps ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x29, 0xca], "vmovaps ymm2, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x0a], "vmovntps ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2b, 0x4a, 0x01], "vmovntps ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x0a], "vucomiss xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0x4a, 0x01], "vucomiss xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2e, 0xca], "vucomiss xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x0a], "vcomiss xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0x4a, 0x01], "vcomiss xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x2f, 0xca], "vcomiss xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0x0a], "vsqrtps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0x4a, 0x01], "vsqrtps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x51, 0xca], "vsqrtps ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0x0a], "vandps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0x4a, 0x01], "vandps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x54, 0xca], "vandps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0x0a], "vandnps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0x4a, 0x01], "vandnps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x55, 0xca], "vandnps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0x0a], "vorps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0x4a, 0x01], "vorps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x56, 0xca], "vorps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0x0a], "vxorps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0x4a, 0x01], "vxorps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x57, 0xca], "vxorps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0x0a], "vaddps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0x4a, 0x01], "vaddps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x58, 0xca], "vaddps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0x0a], "vmulps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0x4a, 0x01], "vmulps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x59, 0xca], "vmulps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0x0a], "vcvtps2pd ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5a, 0xca], "vcvtps2pd ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0x0a], "vcvtdq2ps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5b, 0xca], "vcvtdq2ps ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0x0a], "vsubps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0x4a, 0x01], "vsubps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5c, 0xca], "vsubps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0x0a], "vminps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0x4a, 0x01], "vminps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5d, 0xca], "vminps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0x0a], "vdivps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0x4a, 0x01], "vdivps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5e, 0xca], "vdivps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0x0a], "vmaxps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0x4a, 0x01], "vmaxps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x5f, 0xca], "vmaxps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0x0a], "vcvttps2udq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x78, 0xca], "vcvttps2udq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0x0a], "vcvtps2udq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0x79, 0xca], "vcvtps2udq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc2, 0xca, 0xcc], "vcmpps k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x28, 0xc6, 0xca, 0xcc], "vshufps ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0x0a], "vmovups ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0x4a, 0x01], "vmovups ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x10, 0xca], "vmovups ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0x0a], "vmovups ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0x4a, 0x01], "vmovups ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x11, 0xca], "vmovups ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x14, 0xca], "vunpcklps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x15, 0xca], "vunpckhps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0x0a], "vmovaps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0x4a, 0x01], "vmovaps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x28, 0xca], "vmovaps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0x0a], "vmovaps ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0x4a, 0x01], "vmovaps ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x29, 0xca], "vmovaps ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0x0a], "vsqrtps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x51, 0xca], "vsqrtps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0x4a, 0x01], "vandps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x54, 0xca], "vandps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x55, 0xca], "vandnps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0x4a, 0x01], "vorps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x56, 0xca], "vorps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x57, 0xca], "vxorps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x58, 0xca], "vaddps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x59, 0xca], "vmulps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5a, 0xca], "vcvtps2pd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5c, 0xca], "vsubps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5d, 0xca], "vminps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5e, 0xca], "vdivps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x5f, 0xca], "vmaxps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x78, 0xca], "vcvttps2udq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0x79, 0xca], "vcvtps2udq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x2d, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x14, 0x0a], "vunpcklps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x14, 0x4a, 0x01], "vunpcklps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x15, 0x0a], "vunpckhps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x15, 0x4a, 0x01], "vunpckhps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0x0a], "vsqrtps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0x4a, 0x01], "vsqrtps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x51, 0xca], "vsqrtps zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x54, 0x0a], "vandps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x54, 0x4a, 0x01], "vandps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x55, 0x0a], "vandnps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x55, 0x4a, 0x01], "vandnps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x56, 0x0a], "vorps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x56, 0x4a, 0x01], "vorps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x57, 0x0a], "vxorps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x57, 0x4a, 0x01], "vxorps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0x0a], "vaddps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0x4a, 0x01], "vaddps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x58, 0xca], "vaddps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0x0a], "vmulps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0x4a, 0x01], "vmulps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x59, 0xca], "vmulps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x0a], "vcvtps2pd ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0x0a], "vcvtdq2ps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5b, 0xca], "vcvtdq2ps zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0x0a], "vsubps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0x4a, 0x01], "vsubps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5c, 0xca], "vsubps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5d, 0x0a], "vminps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5d, 0x4a, 0x01], "vminps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0x0a], "vdivps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0x4a, 0x01], "vdivps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5e, 0xca], "vdivps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5f, 0x0a], "vmaxps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x5f, 0x4a, 0x01], "vmaxps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x78, 0x0a], "vcvttps2udq ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0x0a], "vcvtps2udq ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0x79, 0xca], "vcvtps2udq zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x0a, 0xcc], "vcmpps k1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x0a, 0xcc], "vshufps ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x38, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x14, 0x0a], "vunpcklps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x15, 0x0a], "vunpckhps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0x0a], "vsqrtps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x51, 0xca], "vsqrtps zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x54, 0x0a], "vandps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x54, 0x4a, 0x01], "vandps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x55, 0x0a], "vandnps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x56, 0x0a], "vorps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x56, 0x4a, 0x01], "vorps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x57, 0x0a], "vxorps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0x0a], "vaddps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x58, 0xca], "vaddps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0x0a], "vmulps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x59, 0xca], "vmulps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0x0a], "vsubps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5c, 0xca], "vsubps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5d, 0x0a], "vminps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0x0a], "vdivps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5e, 0xca], "vdivps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5f, 0x0a], "vmaxps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x78, 0x0a], "vcvttps2udq ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0x0a], "vcvtps2udq ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x3d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0x0a], "vmovups zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0x4a, 0x01], "vmovups zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x10, 0xca], "vmovups zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0x0a], "vmovups zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0x4a, 0x01], "vmovups zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x11, 0xca], "vmovups zmm2, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0x0a], "vunpcklps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0x4a, 0x01], "vunpcklps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x14, 0xca], "vunpcklps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0x0a], "vunpckhps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0x4a, 0x01], "vunpckhps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x15, 0xca], "vunpckhps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0x0a], "vmovaps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0x4a, 0x01], "vmovaps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x28, 0xca], "vmovaps zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x0a], "vmovaps zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0x4a, 0x01], "vmovaps zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x29, 0xca], "vmovaps zmm2, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x0a], "vmovntps zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x2b, 0x4a, 0x01], "vmovntps zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0x0a], "vsqrtps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0x4a, 0x01], "vsqrtps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x51, 0xca], "vsqrtps zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0x0a], "vandps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0x4a, 0x01], "vandps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x54, 0xca], "vandps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0x0a], "vandnps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0x4a, 0x01], "vandnps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x55, 0xca], "vandnps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0x0a], "vorps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0x4a, 0x01], "vorps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x56, 0xca], "vorps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0x0a], "vxorps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0x4a, 0x01], "vxorps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x57, 0xca], "vxorps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0x0a], "vaddps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0x4a, 0x01], "vaddps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x58, 0xca], "vaddps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0x0a], "vmulps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0x4a, 0x01], "vmulps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x59, 0xca], "vmulps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0x0a], "vcvtps2pd zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5a, 0xca], "vcvtps2pd zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0x0a], "vcvtdq2ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5b, 0xca], "vcvtdq2ps zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0x0a], "vsubps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0x4a, 0x01], "vsubps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5c, 0xca], "vsubps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0x0a], "vminps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0x4a, 0x01], "vminps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5d, 0xca], "vminps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0x0a], "vdivps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0x4a, 0x01], "vdivps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5e, 0xca], "vdivps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0x0a], "vmaxps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0x4a, 0x01], "vmaxps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x5f, 0xca], "vmaxps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0x0a], "vcvttps2udq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x78, 0xca], "vcvttps2udq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0x0a], "vcvtps2udq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0x79, 0xca], "vcvtps2udq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc2, 0xca, 0xcc], "vcmpps k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x48, 0xc6, 0xca, 0xcc], "vshufps zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0x0a], "vmovups zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0x4a, 0x01], "vmovups zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x10, 0xca], "vmovups zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0x0a], "vmovups zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0x4a, 0x01], "vmovups zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x11, 0xca], "vmovups zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x14, 0xca], "vunpcklps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x15, 0xca], "vunpckhps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x0a], "vmovaps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0x4a, 0x01], "vmovaps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x28, 0xca], "vmovaps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x0a], "vmovaps zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0x4a, 0x01], "vmovaps zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x29, 0xca], "vmovaps zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0x0a], "vsqrtps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x51, 0xca], "vsqrtps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0x4a, 0x01], "vandps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x54, 0xca], "vandps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x55, 0xca], "vandnps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0x4a, 0x01], "vorps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x56, 0xca], "vorps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x57, 0xca], "vxorps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x58, 0xca], "vaddps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x59, 0xca], "vmulps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5c, 0xca], "vsubps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5d, 0xca], "vminps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5e, 0xca], "vdivps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x5f, 0xca], "vmaxps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x78, 0xca], "vcvttps2udq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0x79, 0xca], "vcvtps2udq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x4d, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x14, 0x0a], "vunpcklps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x14, 0x4a, 0x01], "vunpcklps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x15, 0x0a], "vunpckhps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x15, 0x4a, 0x01], "vunpckhps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0x0a], "vsqrtps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0x4a, 0x01], "vsqrtps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x51, 0xca], "vsqrtps zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x54, 0x0a], "vandps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x54, 0x4a, 0x01], "vandps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x55, 0x0a], "vandnps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x55, 0x4a, 0x01], "vandnps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x56, 0x0a], "vorps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x56, 0x4a, 0x01], "vorps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x57, 0x0a], "vxorps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x57, 0x4a, 0x01], "vxorps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0x0a], "vaddps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0x4a, 0x01], "vaddps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x58, 0xca], "vaddps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0x0a], "vmulps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0x4a, 0x01], "vmulps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x59, 0xca], "vmulps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5a, 0x0a], "vcvtps2pd zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0x0a], "vcvtdq2ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5b, 0xca], "vcvtdq2ps zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0x0a], "vsubps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0x4a, 0x01], "vsubps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5c, 0xca], "vsubps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5d, 0x0a], "vminps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5d, 0x4a, 0x01], "vminps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0x0a], "vdivps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0x4a, 0x01], "vdivps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5e, 0xca], "vdivps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5f, 0x0a], "vmaxps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x5f, 0x4a, 0x01], "vmaxps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x78, 0x0a], "vcvttps2udq zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0x0a], "vcvtps2udq zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0x79, 0xca], "vcvtps2udq zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0xc2, 0x0a, 0xcc], "vcmpps k1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0xc6, 0x0a, 0xcc], "vshufps zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x58, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x14, 0x0a], "vunpcklps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x15, 0x0a], "vunpckhps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0x0a], "vsqrtps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x51, 0xca], "vsqrtps zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x54, 0x0a], "vandps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x54, 0x4a, 0x01], "vandps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x55, 0x0a], "vandnps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x56, 0x0a], "vorps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x56, 0x4a, 0x01], "vorps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x57, 0x0a], "vxorps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0x0a], "vaddps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x58, 0xca], "vaddps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0x0a], "vmulps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x59, 0xca], "vmulps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0x0a], "vsubps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5c, 0xca], "vsubps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5d, 0x0a], "vminps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0x0a], "vdivps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5e, 0xca], "vdivps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5f, 0x0a], "vmaxps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x78, 0x0a], "vcvttps2udq zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0x0a], "vcvtps2udq zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0xc2, 0x0a, 0xcc], "vcmpps k1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpps k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x5d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x2e, 0xca], "vucomiss xmm1{sae}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x2f, 0xca], "vcomiss xmm1{sae}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x51, 0xca], "vsqrtps zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x58, 0xca], "vaddps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x59, 0xca], "vmulps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5a, 0xca], "vcvtps2pd zmm1{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5b, 0xca], "vcvtdq2ps zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5c, 0xca], "vsubps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5d, 0xca], "vminps zmm1{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5e, 0xca], "vdivps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x5f, 0xca], "vmaxps zmm1{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x78, 0xca], "vcvttps2udq zmm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0x79, 0xca], "vcvtps2udq zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x78, 0xc2, 0xca, 0xcc], "vcmpps k1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x51, 0xca], "vsqrtps zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x58, 0xca], "vaddps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x59, 0xca], "vmulps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5c, 0xca], "vsubps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5d, 0xca], "vminps zmm1{k5}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5e, 0xca], "vdivps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x5f, 0xca], "vmaxps zmm1{k5}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x78, 0xca], "vcvttps2udq zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x7d, 0xc2, 0xca, 0xcc], "vcmpps k1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0x0a], "vmovups xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0x4a, 0x01], "vmovups xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x10, 0xca], "vmovups xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x11, 0xca], "vmovups xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x14, 0xca], "vunpcklps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x15, 0xca], "vunpckhps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x0a], "vmovaps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0x4a, 0x01], "vmovaps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x28, 0xca], "vmovaps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x29, 0xca], "vmovaps xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x51, 0xca], "vsqrtps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x54, 0xca], "vandps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x55, 0xca], "vandnps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x56, 0xca], "vorps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x57, 0xca], "vxorps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x58, 0xca], "vaddps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x59, 0xca], "vmulps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5a, 0xca], "vcvtps2pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5b, 0xca], "vcvtdq2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5c, 0xca], "vsubps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5d, 0xca], "vminps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5e, 0xca], "vdivps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x5f, 0xca], "vmaxps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x78, 0xca], "vcvttps2udq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0x79, 0xca], "vcvtps2udq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x8d, 0xc6, 0xca, 0xcc], "vshufps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x14, 0x0a], "vunpcklps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x14, 0x4a, 0x01], "vunpcklps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x15, 0x0a], "vunpckhps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x15, 0x4a, 0x01], "vunpckhps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0x0a], "vsqrtps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0x4a, 0x01], "vsqrtps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x54, 0x0a], "vandps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x54, 0x4a, 0x01], "vandps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x55, 0x0a], "vandnps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x55, 0x4a, 0x01], "vandnps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x56, 0x0a], "vorps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x56, 0x4a, 0x01], "vorps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x57, 0x0a], "vxorps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x57, 0x4a, 0x01], "vxorps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0x0a], "vaddps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0x4a, 0x01], "vaddps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x58, 0xca], "vaddps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0x0a], "vmulps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0x4a, 0x01], "vmulps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x59, 0xca], "vmulps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5a, 0x0a], "vcvtps2pd xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5a, 0x4a, 0x01], "vcvtps2pd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0x0a], "vcvtdq2ps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0x4a, 0x01], "vcvtdq2ps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0x0a], "vsubps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0x4a, 0x01], "vsubps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5d, 0x0a], "vminps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5d, 0x4a, 0x01], "vminps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0x0a], "vdivps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0x4a, 0x01], "vdivps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5f, 0x0a], "vmaxps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x5f, 0x4a, 0x01], "vmaxps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x78, 0x0a], "vcvttps2udq xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x78, 0x4a, 0x01], "vcvttps2udq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0x0a], "vcvtps2udq xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0x4a, 0x01], "vcvtps2udq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0xc6, 0x0a, 0xcc], "vshufps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0x9d, 0xc6, 0x4a, 0x01, 0xcc], "vshufps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0x0a], "vmovups ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0x4a, 0x01], "vmovups ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x10, 0xca], "vmovups ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x11, 0xca], "vmovups ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x14, 0xca], "vunpcklps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x15, 0xca], "vunpckhps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x0a], "vmovaps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0x4a, 0x01], "vmovaps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x28, 0xca], "vmovaps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x29, 0xca], "vmovaps ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x51, 0xca], "vsqrtps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0x4a, 0x01], "vandps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x54, 0xca], "vandps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x55, 0xca], "vandnps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0x4a, 0x01], "vorps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x56, 0xca], "vorps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x57, 0xca], "vxorps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x58, 0xca], "vaddps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x59, 0xca], "vmulps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5a, 0xca], "vcvtps2pd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5b, 0xca], "vcvtdq2ps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5c, 0xca], "vsubps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5d, 0xca], "vminps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5e, 0xca], "vdivps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x5f, 0xca], "vmaxps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x78, 0xca], "vcvttps2udq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0x79, 0xca], "vcvtps2udq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xad, 0xc6, 0xca, 0xcc], "vshufps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x0a], "vunpcklps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x14, 0x4a, 0x01], "vunpcklps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x15, 0x0a], "vunpckhps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x15, 0x4a, 0x01], "vunpckhps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0x0a], "vsqrtps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0x4a, 0x01], "vsqrtps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x54, 0x0a], "vandps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x54, 0x4a, 0x01], "vandps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x55, 0x0a], "vandnps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x55, 0x4a, 0x01], "vandnps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x56, 0x0a], "vorps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x56, 0x4a, 0x01], "vorps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x57, 0x0a], "vxorps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x57, 0x4a, 0x01], "vxorps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0x0a], "vaddps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0x4a, 0x01], "vaddps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0x0a], "vmulps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0x4a, 0x01], "vmulps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x0a], "vcvtps2pd ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5a, 0x4a, 0x01], "vcvtps2pd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0x0a], "vcvtdq2ps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0x4a, 0x01], "vcvtdq2ps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0x0a], "vsubps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0x4a, 0x01], "vsubps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5d, 0x0a], "vminps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5d, 0x4a, 0x01], "vminps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0x0a], "vdivps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0x4a, 0x01], "vdivps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5f, 0x0a], "vmaxps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x5f, 0x4a, 0x01], "vmaxps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x78, 0x0a], "vcvttps2udq ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x78, 0x4a, 0x01], "vcvttps2udq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0x0a], "vcvtps2udq ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0x4a, 0x01], "vcvtps2udq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x0a, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xbd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0x0a], "vmovups zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0x4a, 0x01], "vmovups zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x10, 0xca], "vmovups zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x11, 0xca], "vmovups zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x14, 0xca], "vunpcklps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x15, 0xca], "vunpckhps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0x0a], "vmovaps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0x4a, 0x01], "vmovaps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x28, 0xca], "vmovaps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x29, 0xca], "vmovaps zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0x4a, 0x01], "vandps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x54, 0xca], "vandps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x55, 0xca], "vandnps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0x4a, 0x01], "vorps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x56, 0xca], "vorps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x57, 0xca], "vxorps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x58, 0xca], "vaddps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x59, 0xca], "vmulps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5c, 0xca], "vsubps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5d, 0xca], "vminps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5e, 0xca], "vdivps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xcd, 0xc6, 0xca, 0xcc], "vshufps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x14, 0x0a], "vunpcklps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x14, 0x4a, 0x01], "vunpcklps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x15, 0x0a], "vunpckhps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x15, 0x4a, 0x01], "vunpckhps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0x0a], "vsqrtps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0x4a, 0x01], "vsqrtps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x54, 0x0a], "vandps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x54, 0x4a, 0x01], "vandps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x55, 0x0a], "vandnps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x55, 0x4a, 0x01], "vandnps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x56, 0x0a], "vorps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x56, 0x4a, 0x01], "vorps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x57, 0x0a], "vxorps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x57, 0x4a, 0x01], "vxorps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0x0a], "vaddps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0x4a, 0x01], "vaddps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x58, 0xca], "vaddps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0x0a], "vmulps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0x4a, 0x01], "vmulps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x59, 0xca], "vmulps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5a, 0x0a], "vcvtps2pd zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5a, 0x4a, 0x01], "vcvtps2pd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0x0a], "vcvtdq2ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0x4a, 0x01], "vcvtdq2ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0x0a], "vsubps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0x4a, 0x01], "vsubps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5d, 0x0a], "vminps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5d, 0x4a, 0x01], "vminps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0x0a], "vdivps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0x4a, 0x01], "vdivps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5f, 0x0a], "vmaxps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x5f, 0x4a, 0x01], "vmaxps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x78, 0x0a], "vcvttps2udq zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x78, 0x4a, 0x01], "vcvttps2udq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0x0a], "vcvtps2udq zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0x4a, 0x01], "vcvtps2udq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0xc6, 0x0a, 0xcc], "vshufps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xdd, 0xc6, 0x4a, 0x01, 0xcc], "vshufps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x51, 0xca], "vsqrtps zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x58, 0xca], "vaddps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x59, 0xca], "vmulps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5a, 0xca], "vcvtps2pd zmm1{k5}{z}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5b, 0xca], "vcvtdq2ps zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5c, 0xca], "vsubps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5d, 0xca], "vminps zmm1{k5}{z}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5e, 0xca], "vdivps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x5f, 0xca], "vmaxps zmm1{k5}{z}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x78, 0xca], "vcvttps2udq zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7c, 0xfd, 0x79, 0xca], "vcvtps2udq zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0x0a], "vcvtps2dq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x5b, 0xca], "vcvtps2dq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0x4a, 0x01], "vpunpckldq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x62, 0xca], "vpunpckldq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0x0a], "vpcmpgtd k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0x4a, 0x01], "vpcmpgtd k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x66, 0xca], "vpcmpgtd k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6a, 0xca], "vpunpckhdq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0x4a, 0x01], "vpackssdw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6b, 0xca], "vpackssdw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0x0a], "vmovdqa32 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x6f, 0xca], "vmovdqa32 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0x0a, 0xcc], "vpshufd xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x70, 0xca, 0xcc], "vpshufd xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0x0a, 0xcc], "vprold xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x72, 0xca, 0xcc], "vprold xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0x0a], "vpcmpeqd k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0x4a, 0x01], "vpcmpeqd k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x76, 0xca], "vpcmpeqd k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0x0a], "vcvttps2uqq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x78, 0xca], "vcvttps2uqq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0x0a], "vcvtps2uqq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x79, 0xca], "vcvtps2uqq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0x0a], "vcvttps2qq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7a, 0xca], "vcvttps2qq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0x0a], "vcvtps2qq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7b, 0xca], "vcvtps2qq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x0a], "vmovdqa32 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0x4a, 0x01], "vmovdqa32 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0x7f, 0xca], "vmovdqa32 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0x0a], "vpsrld xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0x4a, 0x01], "vpsrld xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xd2, 0xca], "vpsrld xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0x0a], "vpandd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0x4a, 0x01], "vpandd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdb, 0xca], "vpandd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0x0a], "vpandnd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0x4a, 0x01], "vpandnd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xdf, 0xca], "vpandnd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0x0a], "vpsrad xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0x4a, 0x01], "vpsrad xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xe2, 0xca], "vpsrad xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x0a], "vmovntdq xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xe7, 0x4a, 0x01], "vmovntdq xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0x0a], "vpord xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0x4a, 0x01], "vpord xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xeb, 0xca], "vpord xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0x0a], "vpxord xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0x4a, 0x01], "vpxord xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xef, 0xca], "vpxord xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0x0a], "vpslld xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0x4a, 0x01], "vpslld xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xf2, 0xca], "vpslld xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0x0a], "vpsubd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0x4a, 0x01], "vpsubd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfa, 0xca], "vpsubd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0x0a], "vpaddd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0x4a, 0x01], "vpaddd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x08, 0xfe, 0xca], "vpaddd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x62, 0xca], "vpunpckldq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x66, 0xca], "vpcmpgtd k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6b, 0xca], "vpackssdw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x76, 0xca], "vpcmpeqd k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0x0a], "vmovdqa32 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqa32 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0x0a], "vpsrld xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0x4a, 0x01], "vpsrld xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xd2, 0xca], "vpsrld xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdb, 0xca], "vpandd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xdf, 0xca], "vpandnd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0x0a], "vpsrad xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0x4a, 0x01], "vpsrad xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xe2, 0xca], "vpsrad xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xeb, 0xca], "vpord xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xef, 0xca], "vpxord xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0x0a], "vpslld xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0x4a, 0x01], "vpslld xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xf2, 0xca], "vpslld xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfa, 0xca], "vpsubd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x0d, 0xfe, 0xca], "vpaddd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0x0a], "vcvtps2dq xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x5b, 0xca], "vcvtps2dq zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x62, 0x0a], "vpunpckldq xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x62, 0x4a, 0x01], "vpunpckldq xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x66, 0x0a], "vpcmpgtd k1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x66, 0x4a, 0x01], "vpcmpgtd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x6a, 0x0a], "vpunpckhdq xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x6b, 0x0a], "vpackssdw xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x6b, 0x4a, 0x01], "vpackssdw xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x70, 0x0a, 0xcc], "vpshufd xmm1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x72, 0x0a, 0xcc], "vprold xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x76, 0x0a], "vpcmpeqd k1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x76, 0x4a, 0x01], "vpcmpeqd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x78, 0x0a], "vcvttps2uqq xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0x0a], "vcvtps2uqq xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x79, 0xca], "vcvtps2uqq zmm1{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x7a, 0x0a], "vcvttps2qq xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0x0a], "vcvtps2qq xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0x7b, 0xca], "vcvtps2qq zmm1{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xdb, 0x0a], "vpandd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xdb, 0x4a, 0x01], "vpandd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xdf, 0x0a], "vpandnd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xdf, 0x4a, 0x01], "vpandnd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xeb, 0x0a], "vpord xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xeb, 0x4a, 0x01], "vpord xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xef, 0x0a], "vpxord xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xef, 0x4a, 0x01], "vpxord xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xfa, 0x0a], "vpsubd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xfa, 0x4a, 0x01], "vpsubd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xfe, 0x0a], "vpaddd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x18, 0xfe, 0x4a, 0x01], "vpaddd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x62, 0x0a], "vpunpckldq xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x66, 0x0a], "vpcmpgtd k1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x6b, 0x0a], "vpackssdw xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x76, 0x0a], "vpcmpeqd k1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xdb, 0x0a], "vpandd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xdf, 0x0a], "vpandnd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xeb, 0x0a], "vpord xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xef, 0x0a], "vpxord xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xfa, 0x0a], "vpsubd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xfe, 0x0a], "vpaddd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x1d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x0a], "vcvtps2dq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0x4a, 0x01], "vpunpckldq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x62, 0xca], "vpunpckldq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x0a], "vpcmpgtd k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0x4a, 0x01], "vpcmpgtd k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x66, 0xca], "vpcmpgtd k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6a, 0xca], "vpunpckhdq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0x4a, 0x01], "vpackssdw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6b, 0xca], "vpackssdw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0x0a], "vmovdqa32 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x6f, 0xca], "vmovdqa32 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0x0a, 0xcc], "vpshufd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x70, 0xca, 0xcc], "vpshufd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0x0a, 0xcc], "vprold ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x72, 0xca, 0xcc], "vprold ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0x0a], "vpcmpeqd k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0x4a, 0x01], "vpcmpeqd k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x76, 0xca], "vpcmpeqd k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0x0a], "vcvttps2uqq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x78, 0xca], "vcvttps2uqq ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0x0a], "vcvtps2uqq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x79, 0xca], "vcvtps2uqq ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0x0a], "vcvttps2qq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7a, 0xca], "vcvttps2qq ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0x0a], "vcvtps2qq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7b, 0xca], "vcvtps2qq ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0x0a], "vmovdqa32 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0x4a, 0x01], "vmovdqa32 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0x7f, 0xca], "vmovdqa32 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0x0a], "vpsrld ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0x4a, 0x01], "vpsrld ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xd2, 0xca], "vpsrld ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0x0a], "vpandd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0x4a, 0x01], "vpandd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdb, 0xca], "vpandd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0x0a], "vpandnd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0x4a, 0x01], "vpandnd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xdf, 0xca], "vpandnd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0x0a], "vpsrad ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0x4a, 0x01], "vpsrad ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xe2, 0xca], "vpsrad ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x0a], "vmovntdq ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xe7, 0x4a, 0x01], "vmovntdq ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0x0a], "vpord ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0x4a, 0x01], "vpord ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xeb, 0xca], "vpord ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0x0a], "vpxord ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0x4a, 0x01], "vpxord ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xef, 0xca], "vpxord ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0x0a], "vpslld ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0x4a, 0x01], "vpslld ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xf2, 0xca], "vpslld ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0x0a], "vpsubd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0x4a, 0x01], "vpsubd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfa, 0xca], "vpsubd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0x0a], "vpaddd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0x4a, 0x01], "vpaddd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x28, 0xfe, 0xca], "vpaddd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x5b, 0xca], "vcvtps2dq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x62, 0xca], "vpunpckldq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x66, 0xca], "vpcmpgtd k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6a, 0xca], "vpunpckhdq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6b, 0xca], "vpackssdw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x6f, 0xca], "vmovdqa32 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x72, 0xca, 0xcc], "vprold ymm0{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x76, 0xca], "vpcmpeqd k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x78, 0xca], "vcvttps2uqq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x79, 0xca], "vcvtps2uqq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7a, 0xca], "vcvttps2qq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7b, 0xca], "vcvtps2qq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0x0a], "vmovdqa32 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqa32 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0x7f, 0xca], "vmovdqa32 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0x0a], "vpsrld ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0x4a, 0x01], "vpsrld ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xd2, 0xca], "vpsrld ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdb, 0xca], "vpandd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xdf, 0xca], "vpandnd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0x0a], "vpsrad ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0x4a, 0x01], "vpsrad ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xe2, 0xca], "vpsrad ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xeb, 0xca], "vpord ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xef, 0xca], "vpxord ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0x0a], "vpslld ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0x4a, 0x01], "vpslld ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xf2, 0xca], "vpslld ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfa, 0xca], "vpsubd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x2d, 0xfe, 0xca], "vpaddd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0x0a], "vcvtps2dq ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x5b, 0xca], "vcvtps2dq zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x62, 0x0a], "vpunpckldq ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x62, 0x4a, 0x01], "vpunpckldq ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x66, 0x0a], "vpcmpgtd k1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x66, 0x4a, 0x01], "vpcmpgtd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x6a, 0x0a], "vpunpckhdq ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x6b, 0x0a], "vpackssdw ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x6b, 0x4a, 0x01], "vpackssdw ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x70, 0x0a, 0xcc], "vpshufd ymm1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x72, 0x0a, 0xcc], "vprold ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x76, 0x0a], "vpcmpeqd k1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x76, 0x4a, 0x01], "vpcmpeqd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x78, 0x0a], "vcvttps2uqq ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0x0a], "vcvtps2uqq ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x79, 0xca], "vcvtps2uqq zmm1{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x7a, 0x0a], "vcvttps2qq ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0x0a], "vcvtps2qq ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0x7b, 0xca], "vcvtps2qq zmm1{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xdb, 0x0a], "vpandd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xdb, 0x4a, 0x01], "vpandd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xdf, 0x0a], "vpandnd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xdf, 0x4a, 0x01], "vpandnd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xeb, 0x0a], "vpord ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xeb, 0x4a, 0x01], "vpord ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xef, 0x0a], "vpxord ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xef, 0x4a, 0x01], "vpxord ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xfa, 0x0a], "vpsubd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xfa, 0x4a, 0x01], "vpsubd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xfe, 0x0a], "vpaddd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x38, 0xfe, 0x4a, 0x01], "vpaddd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x62, 0x0a], "vpunpckldq ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x0a], "vpcmpgtd k1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x6b, 0x0a], "vpackssdw ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x76, 0x0a], "vpcmpeqd k1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xdb, 0x0a], "vpandd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xdf, 0x0a], "vpandnd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xeb, 0x0a], "vpord ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xef, 0x0a], "vpxord ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xfa, 0x0a], "vpsubd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xfe, 0x0a], "vpaddd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x3d, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0x0a], "vcvtps2dq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x5b, 0xca], "vcvtps2dq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0x4a, 0x01], "vpunpckldq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x62, 0xca], "vpunpckldq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0x0a], "vpcmpgtd k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0x4a, 0x01], "vpcmpgtd k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x66, 0xca], "vpcmpgtd k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6a, 0xca], "vpunpckhdq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0x4a, 0x01], "vpackssdw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6b, 0xca], "vpackssdw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0x0a], "vmovdqa32 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x6f, 0xca], "vmovdqa32 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0x0a, 0xcc], "vpshufd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x70, 0xca, 0xcc], "vpshufd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0x0a, 0xcc], "vprold zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x72, 0xca, 0xcc], "vprold zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0x0a], "vpcmpeqd k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0x4a, 0x01], "vpcmpeqd k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x76, 0xca], "vpcmpeqd k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0x0a], "vcvttps2uqq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x78, 0xca], "vcvttps2uqq zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0x0a], "vcvtps2uqq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x79, 0xca], "vcvtps2uqq zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0x0a], "vcvttps2qq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7a, 0xca], "vcvttps2qq zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0x0a], "vcvtps2qq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7b, 0xca], "vcvtps2qq zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0x0a], "vmovdqa32 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0x4a, 0x01], "vmovdqa32 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0x7f, 0xca], "vmovdqa32 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0x0a], "vpsrld zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0x4a, 0x01], "vpsrld zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xd2, 0xca], "vpsrld zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0x0a], "vpandd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0x4a, 0x01], "vpandd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdb, 0xca], "vpandd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0x0a], "vpandnd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0x4a, 0x01], "vpandnd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xdf, 0xca], "vpandnd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0x0a], "vpsrad zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0x4a, 0x01], "vpsrad zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xe2, 0xca], "vpsrad zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x0a], "vmovntdq zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xe7, 0x4a, 0x01], "vmovntdq zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0x0a], "vpord zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0x4a, 0x01], "vpord zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xeb, 0xca], "vpord zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0x0a], "vpxord zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0x4a, 0x01], "vpxord zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xef, 0xca], "vpxord zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0x0a], "vpslld zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0x4a, 0x01], "vpslld zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xf2, 0xca], "vpslld zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0x0a], "vpsubd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0x4a, 0x01], "vpsubd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfa, 0xca], "vpsubd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x0a], "vpaddd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0x4a, 0x01], "vpaddd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x48, 0xfe, 0xca], "vpaddd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x62, 0xca], "vpunpckldq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x66, 0xca], "vpcmpgtd k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6a, 0xca], "vpunpckhdq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6b, 0xca], "vpackssdw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x6f, 0xca], "vmovdqa32 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x72, 0xca, 0xcc], "vprold zmm0{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x76, 0xca], "vpcmpeqd k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0x0a], "vmovdqa32 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqa32 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0x7f, 0xca], "vmovdqa32 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0x0a], "vpsrld zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0x4a, 0x01], "vpsrld zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xd2, 0xca], "vpsrld zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdb, 0xca], "vpandd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xdf, 0xca], "vpandnd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0x0a], "vpsrad zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0x4a, 0x01], "vpsrad zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xe2, 0xca], "vpsrad zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xeb, 0xca], "vpord zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xef, 0xca], "vpxord zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0x0a], "vpslld zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0x4a, 0x01], "vpslld zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xf2, 0xca], "vpslld zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfa, 0xca], "vpsubd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0x4d, 0xfe, 0xca], "vpaddd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0x0a], "vcvtps2dq zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x5b, 0xca], "vcvtps2dq zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x62, 0x0a], "vpunpckldq zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x62, 0x4a, 0x01], "vpunpckldq zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x0a], "vpcmpgtd k1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x66, 0x4a, 0x01], "vpcmpgtd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x6a, 0x0a], "vpunpckhdq zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x6b, 0x0a], "vpackssdw zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x6b, 0x4a, 0x01], "vpackssdw zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x70, 0x0a, 0xcc], "vpshufd zmm1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x72, 0x0a, 0xcc], "vprold zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x76, 0x0a], "vpcmpeqd k1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x76, 0x4a, 0x01], "vpcmpeqd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x78, 0x0a], "vcvttps2uqq zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0x0a], "vcvtps2uqq zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x79, 0xca], "vcvtps2uqq zmm1{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x7a, 0x0a], "vcvttps2qq zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0x0a], "vcvtps2qq zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0x7b, 0xca], "vcvtps2qq zmm1{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xdb, 0x0a], "vpandd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xdb, 0x4a, 0x01], "vpandd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xdf, 0x0a], "vpandnd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xdf, 0x4a, 0x01], "vpandnd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xeb, 0x0a], "vpord zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xeb, 0x4a, 0x01], "vpord zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xef, 0x0a], "vpxord zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xef, 0x4a, 0x01], "vpxord zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xfa, 0x0a], "vpsubd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xfa, 0x4a, 0x01], "vpsubd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xfe, 0x0a], "vpaddd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x58, 0xfe, 0x4a, 0x01], "vpaddd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x62, 0x0a], "vpunpckldq zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x66, 0x0a], "vpcmpgtd k1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x66, 0x4a, 0x01], "vpcmpgtd k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x6b, 0x0a], "vpackssdw zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x76, 0x0a], "vpcmpeqd k1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x76, 0x4a, 0x01], "vpcmpeqd k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xdb, 0x0a], "vpandd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xdf, 0x0a], "vpandnd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xeb, 0x0a], "vpord zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xef, 0x0a], "vpxord zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xfa, 0x0a], "vpsubd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xfe, 0x0a], "vpaddd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x5d, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0x78, 0x5b, 0xca], "vcvtps2dq zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x78, 0x78, 0xca], "vcvttps2uqq zmm1{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x78, 0x79, 0xca], "vcvtps2uqq zmm1{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x78, 0x7a, 0xca], "vcvttps2qq zmm1{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x78, 0x7b, 0xca], "vcvtps2qq zmm1{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x7d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x7d, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x7d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x7d, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x7d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x5b, 0xca], "vcvtps2dq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x62, 0xca], "vpunpckldq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6a, 0xca], "vpunpckhdq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6b, 0xca], "vpackssdw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0x0a], "vmovdqa32 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqa32 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x6f, 0xca], "vmovdqa32 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x70, 0xca, 0xcc], "vpshufd xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x72, 0xca, 0xcc], "vprold xmm0{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x78, 0xca], "vcvttps2uqq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x79, 0xca], "vcvtps2uqq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7a, 0xca], "vcvttps2qq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7b, 0xca], "vcvtps2qq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0x7f, 0xca], "vmovdqa32 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0x0a], "vpsrld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0x4a, 0x01], "vpsrld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xd2, 0xca], "vpsrld xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdb, 0xca], "vpandd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xdf, 0xca], "vpandnd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0x0a], "vpsrad xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0x4a, 0x01], "vpsrad xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xe2, 0xca], "vpsrad xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xeb, 0xca], "vpord xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xef, 0xca], "vpxord xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0x0a], "vpslld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0x4a, 0x01], "vpslld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xf2, 0xca], "vpslld xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfa, 0xca], "vpsubd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0x8d, 0xfe, 0xca], "vpaddd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0x0a], "vcvtps2dq xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0x4a, 0x01], "vcvtps2dq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x62, 0x0a], "vpunpckldq xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x62, 0x4a, 0x01], "vpunpckldq xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x6a, 0x0a], "vpunpckhdq xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x6a, 0x4a, 0x01], "vpunpckhdq xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x6b, 0x0a], "vpackssdw xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x6b, 0x4a, 0x01], "vpackssdw xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x70, 0x0a, 0xcc], "vpshufd xmm1{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x70, 0x4a, 0x01, 0xcc], "vpshufd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x72, 0x0a, 0xcc], "vprold xmm0{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x72, 0x4a, 0x01, 0xcc], "vprold xmm0{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x78, 0x0a], "vcvttps2uqq xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x78, 0x4a, 0x01], "vcvttps2uqq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0x0a], "vcvtps2uqq xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0x4a, 0x01], "vcvtps2uqq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x7a, 0x0a], "vcvttps2qq xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x7a, 0x4a, 0x01], "vcvttps2qq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0x0a], "vcvtps2qq xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0x4a, 0x01], "vcvtps2qq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rne-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xdb, 0x0a], "vpandd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xdb, 0x4a, 0x01], "vpandd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xdf, 0x0a], "vpandnd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xdf, 0x4a, 0x01], "vpandnd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xeb, 0x0a], "vpord xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xeb, 0x4a, 0x01], "vpord xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xef, 0x0a], "vpxord xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xef, 0x4a, 0x01], "vpxord xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xfa, 0x0a], "vpsubd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xfa, 0x4a, 0x01], "vpsubd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xfe, 0x0a], "vpaddd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0x9d, 0xfe, 0x4a, 0x01], "vpaddd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x5b, 0xca], "vcvtps2dq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x62, 0xca], "vpunpckldq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6a, 0xca], "vpunpckhdq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6b, 0xca], "vpackssdw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0x0a], "vmovdqa32 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0x4a, 0x01], "vmovdqa32 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x6f, 0xca], "vmovdqa32 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x70, 0xca, 0xcc], "vpshufd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x72, 0xca, 0xcc], "vprold ymm0{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x78, 0xca], "vcvttps2uqq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x79, 0xca], "vcvtps2uqq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7a, 0xca], "vcvttps2qq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7b, 0xca], "vcvtps2qq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0x7f, 0xca], "vmovdqa32 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0x0a], "vpsrld ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0x4a, 0x01], "vpsrld ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xd2, 0xca], "vpsrld ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdb, 0xca], "vpandd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xdf, 0xca], "vpandnd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0x0a], "vpsrad ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0x4a, 0x01], "vpsrad ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xe2, 0xca], "vpsrad ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xeb, 0xca], "vpord ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xef, 0xca], "vpxord ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0x0a], "vpslld ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0x4a, 0x01], "vpslld ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xf2, 0xca], "vpslld ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfa, 0xca], "vpsubd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xad, 0xfe, 0xca], "vpaddd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0x0a], "vcvtps2dq ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0x4a, 0x01], "vcvtps2dq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x62, 0x0a], "vpunpckldq ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x62, 0x4a, 0x01], "vpunpckldq ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x6a, 0x0a], "vpunpckhdq ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x6a, 0x4a, 0x01], "vpunpckhdq ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x6b, 0x0a], "vpackssdw ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x6b, 0x4a, 0x01], "vpackssdw ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x70, 0x0a, 0xcc], "vpshufd ymm1{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x72, 0x0a, 0xcc], "vprold ymm0{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x72, 0x4a, 0x01, 0xcc], "vprold ymm0{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x78, 0x0a], "vcvttps2uqq ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x78, 0x4a, 0x01], "vcvttps2uqq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0x0a], "vcvtps2uqq ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0x4a, 0x01], "vcvtps2uqq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x7a, 0x0a], "vcvttps2qq ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x7a, 0x4a, 0x01], "vcvttps2qq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0x0a], "vcvtps2qq ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0x4a, 0x01], "vcvtps2qq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rd-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xdb, 0x0a], "vpandd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xdb, 0x4a, 0x01], "vpandd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xdf, 0x0a], "vpandnd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xdf, 0x4a, 0x01], "vpandnd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xeb, 0x0a], "vpord ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xeb, 0x4a, 0x01], "vpord ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xef, 0x0a], "vpxord ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xef, 0x4a, 0x01], "vpxord ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xfa, 0x0a], "vpsubd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xfa, 0x4a, 0x01], "vpsubd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xfe, 0x0a], "vpaddd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xbd, 0xfe, 0x4a, 0x01], "vpaddd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x62, 0xca], "vpunpckldq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6a, 0xca], "vpunpckhdq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6b, 0xca], "vpackssdw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0x0a], "vmovdqa32 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqa32 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x6f, 0xca], "vmovdqa32 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x70, 0xca, 0xcc], "vpshufd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x72, 0xca, 0xcc], "vprold zmm0{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0x7f, 0xca], "vmovdqa32 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0x0a], "vpsrld zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0x4a, 0x01], "vpsrld zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xd2, 0xca], "vpsrld zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdb, 0xca], "vpandd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xdf, 0xca], "vpandnd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0x0a], "vpsrad zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0x4a, 0x01], "vpsrad zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xe2, 0xca], "vpsrad zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xeb, 0xca], "vpord zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xef, 0xca], "vpxord zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0x0a], "vpslld zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0x4a, 0x01], "vpslld zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xf2, 0xca], "vpslld zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfa, 0xca], "vpsubd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7d, 0xcd, 0xfe, 0xca], "vpaddd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0x0a], "vcvtps2dq zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0x4a, 0x01], "vcvtps2dq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x62, 0x0a], "vpunpckldq zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x62, 0x4a, 0x01], "vpunpckldq zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x6a, 0x0a], "vpunpckhdq zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x6a, 0x4a, 0x01], "vpunpckhdq zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x6b, 0x0a], "vpackssdw zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x6b, 0x4a, 0x01], "vpackssdw zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x70, 0x0a, 0xcc], "vpshufd zmm1{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x70, 0x4a, 0x01, 0xcc], "vpshufd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x72, 0x0a, 0xcc], "vprold zmm0{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x72, 0x4a, 0x01, 0xcc], "vprold zmm0{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x78, 0x0a], "vcvttps2uqq zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x78, 0x4a, 0x01], "vcvttps2uqq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0x0a], "vcvtps2uqq zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0x4a, 0x01], "vcvtps2uqq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x7a, 0x0a], "vcvttps2qq zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x7a, 0x4a, 0x01], "vcvttps2qq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0x0a], "vcvtps2qq zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0x4a, 0x01], "vcvtps2qq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{ru-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xdb, 0x0a], "vpandd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xdb, 0x4a, 0x01], "vpandd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xdf, 0x0a], "vpandnd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xdf, 0x4a, 0x01], "vpandnd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xeb, 0x0a], "vpord zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xeb, 0x4a, 0x01], "vpord zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xef, 0x0a], "vpxord zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xef, 0x4a, 0x01], "vpxord zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xfa, 0x0a], "vpsubd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xfa, 0x4a, 0x01], "vpsubd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xfe, 0x0a], "vpaddd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xdd, 0xfe, 0x4a, 0x01], "vpaddd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7d, 0xfd, 0x5b, 0xca], "vcvtps2dq zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7d, 0xfd, 0x78, 0xca], "vcvttps2uqq zmm1{k5}{z}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xfd, 0x79, 0xca], "vcvtps2uqq zmm1{k5}{z}{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xfd, 0x7a, 0xca], "vcvttps2qq zmm1{k5}{z}{sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7d, 0xfd, 0x7b, 0xca], "vcvtps2qq zmm1{k5}{z}{rz-sae}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0x0a], "vmovsldup xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0x4a, 0x01], "vmovsldup xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x12, 0xca], "vmovsldup xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0x0a], "vmovshdup xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0x4a, 0x01], "vmovshdup xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x16, 0xca], "vmovshdup xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0x0a], "vcvttps2dq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x5b, 0xca], "vcvttps2dq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0x0a], "vmovdqu32 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x6f, 0xca], "vmovdqu32 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0x0a], "vcvtudq2pd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7a, 0xca], "vcvtudq2pd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0x0a], "vmovdqu32 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu32 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0x7f, 0xca], "vmovdqu32 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0x0a], "vcvtdq2pd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x08, 0xe6, 0xca], "vcvtdq2pd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0x0a], "vmovsldup xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0x4a, 0x01], "vmovsldup xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x12, 0xca], "vmovsldup xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0x0a], "vmovshdup xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0x4a, 0x01], "vmovshdup xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x16, 0xca], "vmovshdup xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0x0a], "vmovdqu32 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu32 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x0d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x51, 0xca], "vsqrtss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x58, 0xca], "vaddss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x59, 0xca], "vmulss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x5b, 0x0a], "vcvttps2dq xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x5c, 0xca], "vsubss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x5e, 0xca], "vdivss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x7a, 0x0a], "vcvtudq2pd xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0xe6, 0x0a], "vcvtdq2pd xmm1, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x18, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x51, 0xca], "vsqrtss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x58, 0xca], "vaddss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x59, 0xca], "vmulss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x5c, 0xca], "vsubss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x5e, 0xca], "vdivss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x1d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x0a], "vmovss xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0x4a, 0x01], "vmovss xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x10, 0xca], "vmovss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x0a], "vmovss dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0x4a, 0x01], "vmovss dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x11, 0xca], "vmovss xmm2, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0x0a], "vmovsldup ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0x4a, 0x01], "vmovsldup ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x12, 0xca], "vmovsldup ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0x0a], "vmovshdup ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0x4a, 0x01], "vmovshdup ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x16, 0xca], "vmovshdup ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0x0a], "vsqrtss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0x4a, 0x01], "vsqrtss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x51, 0xca], "vsqrtss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0x0a], "vaddss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0x4a, 0x01], "vaddss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x58, 0xca], "vaddss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0x0a], "vmulss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0x4a, 0x01], "vmulss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x59, 0xca], "vmulss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0x0a], "vcvtss2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5a, 0xca], "vcvtss2sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0x0a], "vcvttps2dq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5b, 0xca], "vcvttps2dq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0x0a], "vsubss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0x4a, 0x01], "vsubss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5c, 0xca], "vsubss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0x0a], "vminss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0x4a, 0x01], "vminss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5d, 0xca], "vminss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0x0a], "vdivss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0x4a, 0x01], "vdivss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5e, 0xca], "vdivss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0x0a], "vmaxss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0x4a, 0x01], "vmaxss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x5f, 0xca], "vmaxss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0x0a], "vmovdqu32 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x6f, 0xca], "vmovdqu32 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0x0a], "vcvtudq2pd ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7a, 0xca], "vcvtudq2pd ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0x0a], "vmovdqu32 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu32 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0x7f, 0xca], "vmovdqu32 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x0a, 0xcc], "vcmpss k1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpss k1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xc2, 0xca, 0xcc], "vcmpss k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0x0a], "vcvtdq2pd ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x28, 0xe6, 0xca], "vcvtdq2pd ymm1, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x0a], "vmovss xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0x4a, 0x01], "vmovss xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x10, 0xca], "vmovss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x0a], "vmovss dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0x4a, 0x01], "vmovss dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x11, 0xca], "vmovss xmm2{k5}, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0x0a], "vmovsldup ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0x4a, 0x01], "vmovsldup ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x12, 0xca], "vmovsldup ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0x0a], "vmovshdup ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0x4a, 0x01], "vmovshdup ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x16, 0xca], "vmovshdup ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0x0a], "vsqrtss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0x4a, 0x01], "vsqrtss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x51, 0xca], "vsqrtss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0x0a], "vaddss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0x4a, 0x01], "vaddss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x58, 0xca], "vaddss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0x0a], "vmulss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0x4a, 0x01], "vmulss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x59, 0xca], "vmulss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5b, 0xca], "vcvttps2dq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0x0a], "vsubss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0x4a, 0x01], "vsubss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5c, 0xca], "vsubss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0x0a], "vminss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0x4a, 0x01], "vminss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5d, 0xca], "vminss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0x0a], "vdivss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0x4a, 0x01], "vdivss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5e, 0xca], "vdivss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0x0a], "vmaxss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0x4a, 0x01], "vmaxss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x5f, 0xca], "vmaxss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x6f, 0xca], "vmovdqu32 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0x0a], "vmovdqu32 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu32 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0x7f, 0xca], "vmovdqu32 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpss k1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpss k1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x2d, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x51, 0xca], "vsqrtss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x58, 0xca], "vaddss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x59, 0xca], "vmulss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x5b, 0x0a], "vcvttps2dq ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x5c, 0xca], "vsubss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x5e, 0xca], "vdivss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x7a, 0x0a], "vcvtudq2pd ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0xe6, 0x0a], "vcvtdq2pd ymm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x38, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x51, 0xca], "vsqrtss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x58, 0xca], "vaddss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x59, 0xca], "vmulss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x5c, 0xca], "vsubss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x5e, 0xca], "vdivss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x3d, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0x0a], "vmovsldup zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0x4a, 0x01], "vmovsldup zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x12, 0xca], "vmovsldup zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0x0a], "vmovshdup zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0x4a, 0x01], "vmovshdup zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x16, 0xca], "vmovshdup zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0x0a], "vcvttps2dq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x5b, 0xca], "vcvttps2dq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x0a], "vmovdqu32 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x6f, 0xca], "vmovdqu32 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0x0a], "vcvtudq2pd zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7a, 0xca], "vcvtudq2pd zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0x0a], "vmovdqu32 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu32 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0x7f, 0xca], "vmovdqu32 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0x0a], "vcvtdq2pd zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x48, 0xe6, 0xca], "vcvtdq2pd zmm1, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0x0a], "vmovsldup zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0x4a, 0x01], "vmovsldup zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x12, 0xca], "vmovsldup zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0x0a], "vmovshdup zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0x4a, 0x01], "vmovshdup zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x16, 0xca], "vmovshdup zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x6f, 0xca], "vmovdqu32 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0x0a], "vmovdqu32 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu32 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0x7f, 0xca], "vmovdqu32 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0x4d, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x51, 0xca], "vsqrtss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x58, 0xca], "vaddss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x59, 0xca], "vmulss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x5b, 0x0a], "vcvttps2dq zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x5c, 0xca], "vsubss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x5e, 0xca], "vdivss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x7a, 0x0a], "vcvtudq2pd zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0xe6, 0x0a], "vcvtdq2pd zmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x58, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x51, 0xca], "vsqrtss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x58, 0xca], "vaddss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x59, 0xca], "vmulss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x5c, 0xca], "vsubss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x5e, 0xca], "vdivss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x5d, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x51, 0xca], "vsqrtss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x58, 0xca], "vaddss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x59, 0xca], "vmulss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5a, 0xca], "vcvtss2sd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5b, 0xca], "vcvttps2dq zmm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5c, 0xca], "vsubss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5d, 0xca], "vminss xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5e, 0xca], "vdivss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0x5f, 0xca], "vmaxss xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x78, 0xc2, 0xca, 0xcc], "vcmpss k1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x51, 0xca], "vsqrtss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x58, 0xca], "vaddss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x59, 0xca], "vmulss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5c, 0xca], "vsubss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5d, 0xca], "vminss xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5e, 0xca], "vdivss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0x5f, 0xca], "vmaxss xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x7d, 0xc2, 0xca, 0xcc], "vcmpss k1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0x0a], "vmovsldup xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0x4a, 0x01], "vmovsldup xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x12, 0xca], "vmovsldup xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0x0a], "vmovshdup xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0x4a, 0x01], "vmovshdup xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x16, 0xca], "vmovshdup xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x5b, 0xca], "vcvttps2dq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0x0a], "vmovdqu32 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu32 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x6f, 0xca], "vmovdqu32 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x7a, 0xca], "vcvtudq2pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0x7f, 0xca], "vmovdqu32 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0x7e, 0x8d, 0xe6, 0xca], "vcvtdq2pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x58, 0xca], "vaddss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x59, 0xca], "vmulss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x5b, 0x0a], "vcvttps2dq xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x5b, 0x4a, 0x01], "vcvttps2dq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x7a, 0x0a], "vcvtudq2pd xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0x7a, 0x4a, 0x01], "vcvtudq2pd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0xe6, 0x0a], "vcvtdq2pd xmm1{k5}{z}, dword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0x9d, 0xe6, 0x4a, 0x01], "vcvtdq2pd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to2}"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x0a], "vmovss xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0x4a, 0x01], "vmovss xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x10, 0xca], "vmovss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x11, 0xca], "vmovss xmm2{k5}{z}, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x0a], "vmovsldup ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0x4a, 0x01], "vmovsldup ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x12, 0xca], "vmovsldup ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0x0a], "vmovshdup ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0x4a, 0x01], "vmovshdup ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x16, 0xca], "vmovshdup ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0x0a], "vsqrtss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0x4a, 0x01], "vsqrtss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x51, 0xca], "vsqrtss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0x0a], "vaddss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0x4a, 0x01], "vaddss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x58, 0xca], "vaddss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0x0a], "vmulss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0x4a, 0x01], "vmulss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x59, 0xca], "vmulss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x0a], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0x4a, 0x01], "vcvtss2sd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5b, 0xca], "vcvttps2dq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0x0a], "vsubss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0x4a, 0x01], "vsubss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5c, 0xca], "vsubss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0x0a], "vminss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0x4a, 0x01], "vminss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5d, 0xca], "vminss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0x0a], "vdivss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0x4a, 0x01], "vdivss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5e, 0xca], "vdivss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0x0a], "vmaxss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0x4a, 0x01], "vmaxss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x5f, 0xca], "vmaxss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0x0a], "vmovdqu32 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu32 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x6f, 0xca], "vmovdqu32 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x7a, 0xca], "vcvtudq2pd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0x7f, 0xca], "vmovdqu32 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7e, 0xad, 0xe6, 0xca], "vcvtdq2pd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x5b, 0x0a], "vcvttps2dq ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x5b, 0x4a, 0x01], "vcvttps2dq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x7a, 0x0a], "vcvtudq2pd ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0x7a, 0x4a, 0x01], "vcvtudq2pd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0xe6, 0x0a], "vcvtdq2pd ymm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0xbd, 0xe6, 0x4a, 0x01], "vcvtdq2pd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0x0a], "vmovsldup zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0x4a, 0x01], "vmovsldup zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x12, 0xca], "vmovsldup zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0x0a], "vmovshdup zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0x4a, 0x01], "vmovshdup zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x16, 0xca], "vmovshdup zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0x0a], "vmovdqu32 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu32 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x6f, 0xca], "vmovdqu32 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x7a, 0xca], "vcvtudq2pd zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0x7f, 0xca], "vmovdqu32 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7e, 0xcd, 0xe6, 0xca], "vcvtdq2pd zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x58, 0xca], "vaddss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x59, 0xca], "vmulss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x5b, 0x0a], "vcvttps2dq zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x5b, 0x4a, 0x01], "vcvttps2dq zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x7a, 0x0a], "vcvtudq2pd zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0x7a, 0x4a, 0x01], "vcvtudq2pd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0xe6, 0x0a], "vcvtdq2pd zmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xdd, 0xe6, 0x4a, 0x01], "vcvtdq2pd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x51, 0xca], "vsqrtss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x58, 0xca], "vaddss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x59, 0xca], "vmulss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5a, 0xca], "vcvtss2sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5b, 0xca], "vcvttps2dq zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5c, 0xca], "vsubss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5d, 0xca], "vminss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5e, 0xca], "vdivss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7e, 0xfd, 0x5f, 0xca], "vmaxss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0x0a], "vmovdqu8 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x6f, 0xca], "vmovdqu8 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0x0a], "vcvtudq2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7a, 0xca], "vcvtudq2ps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0x0a], "vmovdqu8 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu8 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x08, 0x7f, 0xca], "vmovdqu8 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0x0a], "vmovdqu8 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu8 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x0d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0x0a], "vcvtudq2ps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x18, 0x7a, 0xca], "vcvtudq2ps zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x1d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0x0a], "vmovdqu8 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x6f, 0xca], "vmovdqu8 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0x0a], "vcvtudq2ps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7a, 0xca], "vcvtudq2ps ymm1, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0x0a], "vmovdqu8 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu8 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x28, 0x7f, 0xca], "vmovdqu8 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x6f, 0xca], "vmovdqu8 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0x0a], "vmovdqu8 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu8 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x2d, 0x7f, 0xca], "vmovdqu8 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0x0a], "vcvtudq2ps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0x38, 0x7a, 0xca], "vcvtudq2ps zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0x3d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0x0a], "vmovdqu8 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x6f, 0xca], "vmovdqu8 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0x0a], "vcvtudq2ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7a, 0xca], "vcvtudq2ps zmm1, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0x0a], "vmovdqu8 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu8 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x48, 0x7f, 0xca], "vmovdqu8 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x6f, 0xca], "vmovdqu8 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0x0a], "vmovdqu8 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu8 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x4d, 0x7f, 0xca], "vmovdqu8 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0x0a], "vcvtudq2ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0x58, 0x7a, 0xca], "vcvtudq2ps zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0x5d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x78, 0x7a, 0xca], "vcvtudq2ps zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x7d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0x0a], "vmovdqu8 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu8 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x6f, 0xca], "vmovdqu8 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x7a, 0xca], "vcvtudq2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0x7f, 0x8d, 0x7f, 0xca], "vmovdqu8 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0x0a], "vcvtudq2ps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0x4a, 0x01], "vcvtudq2ps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf1, 0x7f, 0x9d, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0x0a], "vmovdqu8 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu8 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x6f, 0xca], "vmovdqu8 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x7a, 0xca], "vcvtudq2ps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0x7f, 0xad, 0x7f, 0xca], "vmovdqu8 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0x0a], "vcvtudq2ps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0x4a, 0x01], "vcvtudq2ps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf1, 0x7f, 0xbd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0x0a], "vmovdqu8 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu8 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x6f, 0xca], "vmovdqu8 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0xcd, 0x7f, 0xca], "vmovdqu8 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0x0a], "vcvtudq2ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0x4a, 0x01], "vcvtudq2ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf1, 0x7f, 0xdd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0x7f, 0xfd, 0x7a, 0xca], "vcvtudq2ps zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0x0a], "vcvtqq2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x5b, 0xca], "vcvtqq2ps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0x0a], "vcvttpd2udq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x78, 0xca], "vcvttpd2udq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0x0a], "vcvtpd2udq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x08, 0x79, 0xca], "vcvtpd2udq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x0d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x5b, 0xca], "vcvtqq2ps ymm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x18, 0x79, 0xca], "vcvtpd2udq ymm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x1d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0x0a], "vcvtqq2ps xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x5b, 0xca], "vcvtqq2ps xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0x0a], "vcvttpd2udq xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x78, 0xca], "vcvttpd2udq xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0x0a], "vcvtpd2udq xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x28, 0x79, 0xca], "vcvtpd2udq xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0x2d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0x0a], "vcvtqq2ps xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x5b, 0xca], "vcvtqq2ps ymm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x78, 0x0a], "vcvttpd2udq xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0x0a], "vcvtpd2udq xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x38, 0x79, 0xca], "vcvtpd2udq ymm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0x3d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0x0a], "vcvtqq2ps ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x5b, 0xca], "vcvtqq2ps ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0x0a], "vcvttpd2udq ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x78, 0xca], "vcvttpd2udq ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0x0a], "vcvtpd2udq ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x48, 0x79, 0xca], "vcvtpd2udq ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0x4d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0x0a], "vcvtqq2ps ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x5b, 0xca], "vcvtqq2ps ymm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x78, 0x0a], "vcvttpd2udq ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0x0a], "vcvtpd2udq ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x58, 0x79, 0xca], "vcvtpd2udq ymm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0x5d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x78, 0x5b, 0xca], "vcvtqq2ps ymm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x78, 0x78, 0xca], "vcvttpd2udq ymm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x78, 0x79, 0xca], "vcvtpd2udq ymm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x7d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x7d, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x7d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfc, 0x8d, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfc, 0x9d, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x5b, 0xca], "vcvtqq2ps xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x78, 0xca], "vcvttpd2udq xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfc, 0xad, 0x79, 0xca], "vcvtpd2udq xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0x0a], "vcvtqq2ps xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0x4a, 0x01], "vcvtqq2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x78, 0x0a], "vcvttpd2udq xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x78, 0x4a, 0x01], "vcvttpd2udq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0x0a], "vcvtpd2udq xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0x4a, 0x01], "vcvtpd2udq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfc, 0xbd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfc, 0xcd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0x0a], "vcvtqq2ps ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0x4a, 0x01], "vcvtqq2ps ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x78, 0x0a], "vcvttpd2udq ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x78, 0x4a, 0x01], "vcvttpd2udq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0x0a], "vcvtpd2udq ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0x4a, 0x01], "vcvtpd2udq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfc, 0xdd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xfd, 0x5b, 0xca], "vcvtqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xfd, 0x78, 0xca], "vcvttpd2udq ymm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfc, 0xfd, 0x79, 0xca], "vcvtpd2udq ymm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0x0a], "vmovupd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0x4a, 0x01], "vmovupd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x10, 0xca], "vmovupd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0x0a], "vmovupd xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0x4a, 0x01], "vmovupd xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x11, 0xca], "vmovupd xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x12, 0x0a], "vmovlpd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x12, 0x4a, 0x01], "vmovlpd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x13, 0x0a], "vmovlpd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x13, 0x4a, 0x01], "vmovlpd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0x4a, 0x01], "vunpcklpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x14, 0xca], "vunpcklpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0x4a, 0x01], "vunpckhpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x15, 0xca], "vunpckhpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x16, 0x0a], "vmovhpd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x16, 0x4a, 0x01], "vmovhpd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x17, 0x0a], "vmovhpd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x17, 0x4a, 0x01], "vmovhpd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0x0a], "vmovapd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0x4a, 0x01], "vmovapd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x28, 0xca], "vmovapd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0x0a], "vmovapd xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0x4a, 0x01], "vmovapd xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x29, 0xca], "vmovapd xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x0a], "vmovntpd xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x2b, 0x4a, 0x01], "vmovntpd xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0x0a], "vsqrtpd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0x4a, 0x01], "vsqrtpd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x51, 0xca], "vsqrtpd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0x0a], "vandpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0x4a, 0x01], "vandpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x54, 0xca], "vandpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0x0a], "vandnpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0x4a, 0x01], "vandnpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x55, 0xca], "vandnpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0x0a], "vorpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0x4a, 0x01], "vorpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x56, 0xca], "vorpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0x0a], "vxorpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0x4a, 0x01], "vxorpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x57, 0xca], "vxorpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0x0a], "vaddpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0x4a, 0x01], "vaddpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x58, 0xca], "vaddpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0x0a], "vmulpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0x4a, 0x01], "vmulpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x59, 0xca], "vmulpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0x0a], "vcvtpd2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5a, 0xca], "vcvtpd2ps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0x0a], "vsubpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0x4a, 0x01], "vsubpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5c, 0xca], "vsubpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0x0a], "vminpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0x4a, 0x01], "vminpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5d, 0xca], "vminpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0x0a], "vdivpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0x4a, 0x01], "vdivpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5e, 0xca], "vdivpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0x4a, 0x01], "vmaxpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x5f, 0xca], "vmaxpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0x0a], "vpunpcklbw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x60, 0xca], "vpunpcklbw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0x0a], "vpunpcklwd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x61, 0xca], "vpunpcklwd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0x0a], "vpacksswb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0x4a, 0x01], "vpacksswb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x63, 0xca], "vpacksswb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0x0a], "vpcmpgtb k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0x4a, 0x01], "vpcmpgtb k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x64, 0xca], "vpcmpgtb k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0x0a], "vpcmpgtw k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0x4a, 0x01], "vpcmpgtw k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x65, 0xca], "vpcmpgtw k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0x0a], "vpackuswb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0x4a, 0x01], "vpackuswb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x67, 0xca], "vpackuswb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0x0a], "vpunpckhbw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x68, 0xca], "vpunpckhbw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0x0a], "vpunpckhwd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x69, 0xca], "vpunpckhwd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6c, 0xca], "vpunpcklqdq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6d, 0xca], "vpunpckhqdq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x0a], "vmovd xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0x4a, 0x01], "vmovd xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6e, 0xca], "vmovd xmm1, edx"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0x0a], "vmovdqa64 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x6f, 0xca], "vmovdqa64 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vprolq xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vprolq xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0x0a], "vpcmpeqb k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0x4a, 0x01], "vpcmpeqb k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x74, 0xca], "vpcmpeqb k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0x0a], "vpcmpeqw k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0x4a, 0x01], "vpcmpeqw k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x75, 0xca], "vpcmpeqw k1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0x0a], "vcvttpd2uqq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x78, 0xca], "vcvttpd2uqq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0x0a], "vcvtpd2uqq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x79, 0xca], "vcvtpd2uqq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0x0a], "vcvttpd2qq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7a, 0xca], "vcvttpd2qq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0x0a], "vcvtpd2qq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7b, 0xca], "vcvtpd2qq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x0a], "vmovd dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0x4a, 0x01], "vmovd dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7e, 0xca], "vmovd edx, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0x0a], "vmovdqa64 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0x4a, 0x01], "vmovdqa64 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0x7f, 0xca], "vmovdqa64 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc2, 0xca, 0xcc], "vcmppd k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0x0a, 0xcc], "vpinsrw xmm1, xmm0, word [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0x4a, 0x01, 0xcc], "vpinsrw xmm1, xmm0, word [bp + si * 1 + 0x2], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc4, 0xca, 0xcc], "vpinsrw xmm1, xmm0, edx, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc5, 0xca, 0xcc], "vpextrw ecx, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xc6, 0xca, 0xcc], "vshufpd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0x0a], "vpsrlw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0x4a, 0x01], "vpsrlw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd1, 0xca], "vpsrlw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0x0a], "vpsrlq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0x4a, 0x01], "vpsrlq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd3, 0xca], "vpsrlq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0x0a], "vpaddq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0x4a, 0x01], "vpaddq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd4, 0xca], "vpaddq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0x0a], "vpmullw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0x4a, 0x01], "vpmullw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd5, 0xca], "vpmullw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0x0a], "vmovq qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0x4a, 0x01], "vmovq qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd6, 0xca], "vmovq xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0x0a], "vpsubusb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0x4a, 0x01], "vpsubusb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd8, 0xca], "vpsubusb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0x0a], "vpsubusw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0x4a, 0x01], "vpsubusw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xd9, 0xca], "vpsubusw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0x0a], "vpminub xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0x4a, 0x01], "vpminub xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xda, 0xca], "vpminub xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0x0a], "vpandq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0x4a, 0x01], "vpandq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdb, 0xca], "vpandq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0x0a], "vpaddusb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0x4a, 0x01], "vpaddusb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdc, 0xca], "vpaddusb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0x0a], "vpaddusw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0x4a, 0x01], "vpaddusw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdd, 0xca], "vpaddusw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0x0a], "vpmaxub xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0x4a, 0x01], "vpmaxub xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xde, 0xca], "vpmaxub xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0x0a], "vpandnq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0x4a, 0x01], "vpandnq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xdf, 0xca], "vpandnq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0x0a], "vpavgb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0x4a, 0x01], "vpavgb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe0, 0xca], "vpavgb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0x0a], "vpsraw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0x4a, 0x01], "vpsraw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe1, 0xca], "vpsraw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0x0a], "vpsraq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0x4a, 0x01], "vpsraq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe2, 0xca], "vpsraq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0x0a], "vpavgw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0x4a, 0x01], "vpavgw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe3, 0xca], "vpavgw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0x0a], "vpmulhuw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe4, 0xca], "vpmulhuw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0x0a], "vpmulhw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0x4a, 0x01], "vpmulhw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe5, 0xca], "vpmulhw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0x0a], "vcvttpd2dq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe6, 0xca], "vcvttpd2dq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0x0a], "vpsubsb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0x4a, 0x01], "vpsubsb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe8, 0xca], "vpsubsb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0x0a], "vpsubsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0x4a, 0x01], "vpsubsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xe9, 0xca], "vpsubsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0x0a], "vpminsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0x4a, 0x01], "vpminsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xea, 0xca], "vpminsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0x0a], "vporq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0x4a, 0x01], "vporq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xeb, 0xca], "vporq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0x0a], "vpaddsb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0x4a, 0x01], "vpaddsb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xec, 0xca], "vpaddsb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0x0a], "vpaddsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0x4a, 0x01], "vpaddsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xed, 0xca], "vpaddsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0x0a], "vpmaxsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0x4a, 0x01], "vpmaxsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xee, 0xca], "vpmaxsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0x0a], "vpxorq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0x4a, 0x01], "vpxorq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xef, 0xca], "vpxorq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0x0a], "vpsllw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0x4a, 0x01], "vpsllw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf1, 0xca], "vpsllw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0x0a], "vpsllq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0x4a, 0x01], "vpsllq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf3, 0xca], "vpsllq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0x4a, 0x01], "vpmuludq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf4, 0xca], "vpmuludq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0x0a], "vpmaddwd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf5, 0xca], "vpmaddwd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0x0a], "vpsadbw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0x4a, 0x01], "vpsadbw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0x0a], "vpsubb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0x4a, 0x01], "vpsubb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf8, 0xca], "vpsubb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0x0a], "vpsubw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0x4a, 0x01], "vpsubw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xf9, 0xca], "vpsubw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0x0a], "vpsubq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0x4a, 0x01], "vpsubq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfb, 0xca], "vpsubq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0x0a], "vpaddb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0x4a, 0x01], "vpaddb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfc, 0xca], "vpaddb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0x0a], "vpaddw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0x4a, 0x01], "vpaddw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x08, 0xfd, 0xca], "vpaddw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0x0a], "vmovupd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0x4a, 0x01], "vmovupd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x10, 0xca], "vmovupd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0x0a], "vmovupd xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0x4a, 0x01], "vmovupd xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x11, 0xca], "vmovupd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x14, 0xca], "vunpcklpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x15, 0xca], "vunpckhpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0x0a], "vmovapd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0x4a, 0x01], "vmovapd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x28, 0xca], "vmovapd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0x0a], "vmovapd xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0x4a, 0x01], "vmovapd xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x29, 0xca], "vmovapd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x51, 0xca], "vsqrtpd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x54, 0xca], "vandpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x55, 0xca], "vandnpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x56, 0xca], "vorpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x57, 0xca], "vxorpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x58, 0xca], "vaddpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x59, 0xca], "vmulpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5c, 0xca], "vsubpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5d, 0xca], "vminpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5e, 0xca], "vdivpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x5f, 0xca], "vmaxpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x60, 0xca], "vpunpcklbw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x61, 0xca], "vpunpcklwd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0x0a], "vpacksswb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0x4a, 0x01], "vpacksswb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x63, 0xca], "vpacksswb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0x0a], "vpcmpgtb k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x64, 0xca], "vpcmpgtb k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0x0a], "vpcmpgtw k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x65, 0xca], "vpcmpgtw k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0x0a], "vpackuswb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0x4a, 0x01], "vpackuswb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x67, 0xca], "vpackuswb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x68, 0xca], "vpunpckhbw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x69, 0xca], "vpunpckhwd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0x0a], "vpcmpeqb k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x74, 0xca], "vpcmpeqb k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0x0a], "vpcmpeqw k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x75, 0xca], "vpcmpeqw k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0x0a], "vmovdqa64 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqa64 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0x0a], "vpsrlw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0x4a, 0x01], "vpsrlw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd1, 0xca], "vpsrlw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0x0a], "vpsrlq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0x4a, 0x01], "vpsrlq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd3, 0xca], "vpsrlq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd4, 0xca], "vpaddq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0x0a], "vpmullw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0x4a, 0x01], "vpmullw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd5, 0xca], "vpmullw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0x0a], "vpsubusb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0x4a, 0x01], "vpsubusb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd8, 0xca], "vpsubusb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0x0a], "vpsubusw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0x4a, 0x01], "vpsubusw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xd9, 0xca], "vpsubusw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0x0a], "vpminub xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0x4a, 0x01], "vpminub xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xda, 0xca], "vpminub xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdb, 0xca], "vpandq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0x0a], "vpaddusb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0x4a, 0x01], "vpaddusb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdc, 0xca], "vpaddusb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0x0a], "vpaddusw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0x4a, 0x01], "vpaddusw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdd, 0xca], "vpaddusw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0x0a], "vpmaxub xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0x4a, 0x01], "vpmaxub xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xde, 0xca], "vpmaxub xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xdf, 0xca], "vpandnq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0x0a], "vpavgb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0x4a, 0x01], "vpavgb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe0, 0xca], "vpavgb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0x0a], "vpsraw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0x4a, 0x01], "vpsraw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe1, 0xca], "vpsraw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0x0a], "vpsraq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0x4a, 0x01], "vpsraq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe2, 0xca], "vpsraq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0x0a], "vpavgw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0x4a, 0x01], "vpavgw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe3, 0xca], "vpavgw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe4, 0xca], "vpmulhuw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x0a], "vpmulhw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0x4a, 0x01], "vpmulhw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe5, 0xca], "vpmulhw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0x0a], "vpsubsb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0x4a, 0x01], "vpsubsb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe8, 0xca], "vpsubsb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0x0a], "vpsubsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0x4a, 0x01], "vpsubsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xe9, 0xca], "vpsubsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0x0a], "vpminsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0x4a, 0x01], "vpminsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xea, 0xca], "vpminsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xeb, 0xca], "vporq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0x0a], "vpaddsb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0x4a, 0x01], "vpaddsb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xec, 0xca], "vpaddsb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0x0a], "vpaddsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0x4a, 0x01], "vpaddsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xed, 0xca], "vpaddsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0x0a], "vpmaxsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0x4a, 0x01], "vpmaxsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xee, 0xca], "vpmaxsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xef, 0xca], "vpxorq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0x0a], "vpsllw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0x4a, 0x01], "vpsllw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf1, 0xca], "vpsllw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0x0a], "vpsllq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0x4a, 0x01], "vpsllq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf3, 0xca], "vpsllq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf4, 0xca], "vpmuludq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf5, 0xca], "vpmaddwd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0x0a], "vpsubb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0x4a, 0x01], "vpsubb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf8, 0xca], "vpsubb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0x0a], "vpsubw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0x4a, 0x01], "vpsubw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xf9, 0xca], "vpsubw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfb, 0xca], "vpsubq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0x0a], "vpaddb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0x4a, 0x01], "vpaddb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfc, 0xca], "vpaddb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0x0a], "vpaddw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0x4a, 0x01], "vpaddw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x0d, 0xfd, 0xca], "vpaddw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x14, 0x4a, 0x01], "vunpcklpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x15, 0x4a, 0x01], "vunpckhpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0x0a], "vsqrtpd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0x4a, 0x01], "vsqrtpd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x51, 0xca], "vsqrtpd zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x54, 0x0a], "vandpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x54, 0x4a, 0x01], "vandpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x55, 0x0a], "vandnpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x55, 0x4a, 0x01], "vandnpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x56, 0x0a], "vorpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x56, 0x4a, 0x01], "vorpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x57, 0x0a], "vxorpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x57, 0x4a, 0x01], "vxorpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0x0a], "vaddpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0x4a, 0x01], "vaddpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x58, 0xca], "vaddpd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0x0a], "vmulpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0x4a, 0x01], "vmulpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x59, 0xca], "vmulpd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5a, 0xca], "vcvtpd2ps ymm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0x0a], "vsubpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0x4a, 0x01], "vsubpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5c, 0xca], "vsubpd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5d, 0x0a], "vminpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5d, 0x4a, 0x01], "vminpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0x0a], "vdivpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0x4a, 0x01], "vdivpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5e, 0xca], "vdivpd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x5f, 0x4a, 0x01], "vmaxpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x6c, 0x0a], "vpunpcklqdq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x6d, 0x0a], "vpunpckhqdq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x72, 0x0a, 0xcc], "vprolq xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x78, 0x0a], "vcvttpd2uqq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0x0a], "vcvtpd2uqq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x79, 0xca], "vcvtpd2uqq zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x7a, 0x0a], "vcvttpd2qq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0x0a], "vcvtpd2qq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0x7b, 0xca], "vcvtpd2qq zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xc2, 0x0a, 0xcc], "vcmppd k1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xc6, 0x0a, 0xcc], "vshufpd xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xd4, 0x0a], "vpaddq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xd4, 0x4a, 0x01], "vpaddq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xdb, 0x0a], "vpandq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xdb, 0x4a, 0x01], "vpandq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xdf, 0x0a], "vpandnq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xdf, 0x4a, 0x01], "vpandnq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xeb, 0x0a], "vporq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xeb, 0x4a, 0x01], "vporq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xef, 0x0a], "vpxorq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xef, 0x4a, 0x01], "vpxorq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xf4, 0x0a], "vpmuludq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xf4, 0x4a, 0x01], "vpmuludq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xfb, 0x0a], "vpsubq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x18, 0xfb, 0x4a, 0x01], "vpsubq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x14, 0x0a], "vunpcklpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x15, 0x0a], "vunpckhpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0x0a], "vsqrtpd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x54, 0x0a], "vandpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x55, 0x0a], "vandnpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x56, 0x0a], "vorpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x57, 0x0a], "vxorpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0x0a], "vaddpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x58, 0xca], "vaddpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0x0a], "vmulpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x59, 0xca], "vmulpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0x0a], "vsubpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5c, 0xca], "vsubpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5d, 0x0a], "vminpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0x0a], "vdivpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5e, 0xca], "vdivpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5f, 0x0a], "vmaxpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xd4, 0x0a], "vpaddq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xdb, 0x0a], "vpandq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xdf, 0x0a], "vpandnq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xeb, 0x0a], "vporq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xef, 0x0a], "vpxorq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xf4, 0x0a], "vpmuludq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xfb, 0x0a], "vpsubq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x1d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0x0a], "vmovupd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0x4a, 0x01], "vmovupd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x10, 0xca], "vmovupd ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0x0a], "vmovupd ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0x4a, 0x01], "vmovupd ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x11, 0xca], "vmovupd ymm2, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0x4a, 0x01], "vunpcklpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x14, 0xca], "vunpcklpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0x4a, 0x01], "vunpckhpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x15, 0xca], "vunpckhpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x0a], "vmovapd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0x4a, 0x01], "vmovapd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x28, 0xca], "vmovapd ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0x0a], "vmovapd ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0x4a, 0x01], "vmovapd ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x29, 0xca], "vmovapd ymm2, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x0a], "vmovntpd ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2b, 0x4a, 0x01], "vmovntpd ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x0a], "vucomisd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0x4a, 0x01], "vucomisd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2e, 0xca], "vucomisd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x0a], "vcomisd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0x4a, 0x01], "vcomisd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x2f, 0xca], "vcomisd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0x0a], "vsqrtpd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0x4a, 0x01], "vsqrtpd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x51, 0xca], "vsqrtpd ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0x0a], "vandpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0x4a, 0x01], "vandpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x54, 0xca], "vandpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0x0a], "vandnpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0x4a, 0x01], "vandnpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x55, 0xca], "vandnpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0x0a], "vorpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0x4a, 0x01], "vorpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x56, 0xca], "vorpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0x0a], "vxorpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0x4a, 0x01], "vxorpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x57, 0xca], "vxorpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0x0a], "vaddpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0x4a, 0x01], "vaddpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x58, 0xca], "vaddpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0x0a], "vmulpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0x4a, 0x01], "vmulpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x59, 0xca], "vmulpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0x0a], "vcvtpd2ps xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5a, 0xca], "vcvtpd2ps xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0x0a], "vsubpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0x4a, 0x01], "vsubpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5c, 0xca], "vsubpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0x0a], "vminpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0x4a, 0x01], "vminpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5d, 0xca], "vminpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0x0a], "vdivpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0x4a, 0x01], "vdivpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5e, 0xca], "vdivpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0x4a, 0x01], "vmaxpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x5f, 0xca], "vmaxpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0x0a], "vpunpcklbw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x60, 0xca], "vpunpcklbw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0x0a], "vpunpcklwd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x61, 0xca], "vpunpcklwd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0x0a], "vpacksswb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0x4a, 0x01], "vpacksswb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x63, 0xca], "vpacksswb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0x0a], "vpcmpgtb k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0x4a, 0x01], "vpcmpgtb k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x64, 0xca], "vpcmpgtb k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0x0a], "vpcmpgtw k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0x4a, 0x01], "vpcmpgtw k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x65, 0xca], "vpcmpgtw k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0x0a], "vpackuswb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0x4a, 0x01], "vpackuswb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x67, 0xca], "vpackuswb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0x0a], "vpunpckhbw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x68, 0xca], "vpunpckhbw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0x0a], "vpunpckhwd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x69, 0xca], "vpunpckhwd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6c, 0xca], "vpunpcklqdq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6d, 0xca], "vpunpckhqdq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0x0a], "vmovdqa64 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x6f, 0xca], "vmovdqa64 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vprolq ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vprolq ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0x0a], "vpcmpeqb k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0x4a, 0x01], "vpcmpeqb k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x74, 0xca], "vpcmpeqb k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0x0a], "vpcmpeqw k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0x4a, 0x01], "vpcmpeqw k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x75, 0xca], "vpcmpeqw k1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0x0a], "vcvttpd2uqq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x78, 0xca], "vcvttpd2uqq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0x0a], "vcvtpd2uqq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x79, 0xca], "vcvtpd2uqq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0x0a], "vcvttpd2qq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7a, 0xca], "vcvttpd2qq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0x0a], "vcvtpd2qq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7b, 0xca], "vcvtpd2qq ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0x0a], "vmovdqa64 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0x4a, 0x01], "vmovdqa64 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0x7f, 0xca], "vmovdqa64 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc2, 0xca, 0xcc], "vcmppd k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xc6, 0xca, 0xcc], "vshufpd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0x0a], "vpsrlw ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0x4a, 0x01], "vpsrlw ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd1, 0xca], "vpsrlw ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0x0a], "vpsrlq ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0x4a, 0x01], "vpsrlq ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd3, 0xca], "vpsrlq ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0x0a], "vpaddq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0x4a, 0x01], "vpaddq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd4, 0xca], "vpaddq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0x0a], "vpmullw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0x4a, 0x01], "vpmullw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd5, 0xca], "vpmullw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0x0a], "vpsubusb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0x4a, 0x01], "vpsubusb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd8, 0xca], "vpsubusb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0x0a], "vpsubusw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0x4a, 0x01], "vpsubusw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xd9, 0xca], "vpsubusw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0x0a], "vpminub ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0x4a, 0x01], "vpminub ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xda, 0xca], "vpminub ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0x0a], "vpandq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0x4a, 0x01], "vpandq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdb, 0xca], "vpandq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0x0a], "vpaddusb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0x4a, 0x01], "vpaddusb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdc, 0xca], "vpaddusb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0x0a], "vpaddusw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0x4a, 0x01], "vpaddusw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdd, 0xca], "vpaddusw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0x0a], "vpmaxub ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0x4a, 0x01], "vpmaxub ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xde, 0xca], "vpmaxub ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0x0a], "vpandnq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0x4a, 0x01], "vpandnq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xdf, 0xca], "vpandnq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0x0a], "vpavgb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0x4a, 0x01], "vpavgb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe0, 0xca], "vpavgb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0x0a], "vpsraw ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0x4a, 0x01], "vpsraw ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe1, 0xca], "vpsraw ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0x0a], "vpsraq ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0x4a, 0x01], "vpsraq ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe2, 0xca], "vpsraq ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0x0a], "vpavgw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0x4a, 0x01], "vpavgw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe3, 0xca], "vpavgw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0x0a], "vpmulhuw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe4, 0xca], "vpmulhuw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0x0a], "vpmulhw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0x4a, 0x01], "vpmulhw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe5, 0xca], "vpmulhw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0x0a], "vcvttpd2dq xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe6, 0xca], "vcvttpd2dq xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0x0a], "vpsubsb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0x4a, 0x01], "vpsubsb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0x0a], "vpsubsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0x4a, 0x01], "vpsubsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xe9, 0xca], "vpsubsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0x0a], "vpminsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0x4a, 0x01], "vpminsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xea, 0xca], "vpminsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0x0a], "vporq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0x4a, 0x01], "vporq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xeb, 0xca], "vporq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0x0a], "vpaddsb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0x4a, 0x01], "vpaddsb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xec, 0xca], "vpaddsb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0x0a], "vpaddsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0x4a, 0x01], "vpaddsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xed, 0xca], "vpaddsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0x0a], "vpmaxsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0x4a, 0x01], "vpmaxsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xee, 0xca], "vpmaxsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0x0a], "vpxorq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0x4a, 0x01], "vpxorq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xef, 0xca], "vpxorq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0x0a], "vpsllw ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0x4a, 0x01], "vpsllw ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf1, 0xca], "vpsllw ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0x0a], "vpsllq ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0x4a, 0x01], "vpsllq ymm1, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf3, 0xca], "vpsllq ymm1, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0x4a, 0x01], "vpmuludq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf4, 0xca], "vpmuludq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0x0a], "vpmaddwd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf5, 0xca], "vpmaddwd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x0a], "vpsadbw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0x4a, 0x01], "vpsadbw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0x0a], "vpsubb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0x4a, 0x01], "vpsubb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf8, 0xca], "vpsubb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0x0a], "vpsubw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0x4a, 0x01], "vpsubw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xf9, 0xca], "vpsubw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0x0a], "vpsubq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0x4a, 0x01], "vpsubq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfb, 0xca], "vpsubq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0x0a], "vpaddb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0x4a, 0x01], "vpaddb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfc, 0xca], "vpaddb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0x0a], "vpaddw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0x4a, 0x01], "vpaddw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x28, 0xfd, 0xca], "vpaddw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x0a], "vmovupd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0x4a, 0x01], "vmovupd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x10, 0xca], "vmovupd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0x0a], "vmovupd ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0x4a, 0x01], "vmovupd ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x11, 0xca], "vmovupd ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x14, 0xca], "vunpcklpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x15, 0xca], "vunpckhpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x0a], "vmovapd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0x4a, 0x01], "vmovapd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x28, 0xca], "vmovapd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0x0a], "vmovapd ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0x4a, 0x01], "vmovapd ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x29, 0xca], "vmovapd ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x51, 0xca], "vsqrtpd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x54, 0xca], "vandpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x55, 0xca], "vandnpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x56, 0xca], "vorpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x57, 0xca], "vxorpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x58, 0xca], "vaddpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x59, 0xca], "vmulpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5c, 0xca], "vsubpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5d, 0xca], "vminpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5e, 0xca], "vdivpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x5f, 0xca], "vmaxpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0x0a], "vpunpcklbw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x60, 0xca], "vpunpcklbw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0x0a], "vpunpcklwd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x61, 0xca], "vpunpcklwd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0x0a], "vpacksswb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0x4a, 0x01], "vpacksswb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x63, 0xca], "vpacksswb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0x0a], "vpcmpgtb k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x64, 0xca], "vpcmpgtb k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0x0a], "vpcmpgtw k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x65, 0xca], "vpcmpgtw k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0x0a], "vpackuswb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0x4a, 0x01], "vpackuswb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x67, 0xca], "vpackuswb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0x0a], "vpunpckhbw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x68, 0xca], "vpunpckhbw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0x0a], "vpunpckhwd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x69, 0xca], "vpunpckhwd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x6f, 0xca], "vmovdqa64 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0x0a], "vpcmpeqb k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x74, 0xca], "vpcmpeqb k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0x0a], "vpcmpeqw k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x75, 0xca], "vpcmpeqw k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0x0a], "vmovdqa64 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqa64 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0x7f, 0xca], "vmovdqa64 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0x0a], "vpsrlw ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0x4a, 0x01], "vpsrlw ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd1, 0xca], "vpsrlw ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0x0a], "vpsrlq ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0x4a, 0x01], "vpsrlq ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd3, 0xca], "vpsrlq ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd4, 0xca], "vpaddq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0x0a], "vpmullw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0x4a, 0x01], "vpmullw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd5, 0xca], "vpmullw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0x0a], "vpsubusb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0x4a, 0x01], "vpsubusb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd8, 0xca], "vpsubusb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0x0a], "vpsubusw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0x4a, 0x01], "vpsubusw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xd9, 0xca], "vpsubusw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0x0a], "vpminub ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0x4a, 0x01], "vpminub ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xda, 0xca], "vpminub ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdb, 0xca], "vpandq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0x0a], "vpaddusb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0x4a, 0x01], "vpaddusb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdc, 0xca], "vpaddusb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0x0a], "vpaddusw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0x4a, 0x01], "vpaddusw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdd, 0xca], "vpaddusw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0x0a], "vpmaxub ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0x4a, 0x01], "vpmaxub ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xde, 0xca], "vpmaxub ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xdf, 0xca], "vpandnq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0x0a], "vpavgb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0x4a, 0x01], "vpavgb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe0, 0xca], "vpavgb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0x0a], "vpsraw ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0x4a, 0x01], "vpsraw ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe1, 0xca], "vpsraw ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0x0a], "vpsraq ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0x4a, 0x01], "vpsraq ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe2, 0xca], "vpsraq ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0x0a], "vpavgw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0x4a, 0x01], "vpavgw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe3, 0xca], "vpavgw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0x0a], "vpmulhuw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe4, 0xca], "vpmulhuw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0x0a], "vpmulhw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0x4a, 0x01], "vpmulhw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe5, 0xca], "vpmulhw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0x0a], "vpsubsb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0x4a, 0x01], "vpsubsb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe8, 0xca], "vpsubsb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0x0a], "vpsubsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0x4a, 0x01], "vpsubsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xe9, 0xca], "vpsubsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0x0a], "vpminsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0x4a, 0x01], "vpminsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xea, 0xca], "vpminsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xeb, 0xca], "vporq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0x0a], "vpaddsb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0x4a, 0x01], "vpaddsb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xec, 0xca], "vpaddsb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0x0a], "vpaddsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0x4a, 0x01], "vpaddsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xed, 0xca], "vpaddsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0x0a], "vpmaxsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0x4a, 0x01], "vpmaxsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xee, 0xca], "vpmaxsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xef, 0xca], "vpxorq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0x0a], "vpsllw ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0x4a, 0x01], "vpsllw ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf1, 0xca], "vpsllw ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0x0a], "vpsllq ymm1{k5}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0x4a, 0x01], "vpsllq ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf3, 0xca], "vpsllq ymm1{k5}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf4, 0xca], "vpmuludq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0x0a], "vpmaddwd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf5, 0xca], "vpmaddwd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0x0a], "vpsubb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0x4a, 0x01], "vpsubb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf8, 0xca], "vpsubb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0x0a], "vpsubw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0x4a, 0x01], "vpsubw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xf9, 0xca], "vpsubw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfb, 0xca], "vpsubq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0x0a], "vpaddb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0x4a, 0x01], "vpaddb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfc, 0xca], "vpaddb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0x0a], "vpaddw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0x4a, 0x01], "vpaddw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0x2d, 0xfd, 0xca], "vpaddw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x14, 0x4a, 0x01], "vunpcklpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x15, 0x4a, 0x01], "vunpckhpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0x0a], "vsqrtpd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0x4a, 0x01], "vsqrtpd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x51, 0xca], "vsqrtpd zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x54, 0x0a], "vandpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x54, 0x4a, 0x01], "vandpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x55, 0x0a], "vandnpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x55, 0x4a, 0x01], "vandnpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x56, 0x0a], "vorpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x56, 0x4a, 0x01], "vorpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x57, 0x0a], "vxorpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x57, 0x4a, 0x01], "vxorpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0x0a], "vaddpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0x4a, 0x01], "vaddpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x58, 0xca], "vaddpd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0x0a], "vmulpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0x4a, 0x01], "vmulpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x59, 0xca], "vmulpd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0x0a], "vcvtpd2ps xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5a, 0xca], "vcvtpd2ps ymm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0x0a], "vsubpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0x4a, 0x01], "vsubpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5c, 0xca], "vsubpd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5d, 0x0a], "vminpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5d, 0x4a, 0x01], "vminpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0x0a], "vdivpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0x4a, 0x01], "vdivpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5e, 0xca], "vdivpd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x5f, 0x4a, 0x01], "vmaxpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x6c, 0x0a], "vpunpcklqdq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x6d, 0x0a], "vpunpckhqdq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x72, 0x0a, 0xcc], "vprolq ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x78, 0x0a], "vcvttpd2uqq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0x0a], "vcvtpd2uqq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x79, 0xca], "vcvtpd2uqq zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x7a, 0x0a], "vcvttpd2qq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0x0a], "vcvtpd2qq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0x7b, 0xca], "vcvtpd2qq zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x0a, 0xcc], "vcmppd k1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xc6, 0x0a, 0xcc], "vshufpd ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xd4, 0x0a], "vpaddq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xd4, 0x4a, 0x01], "vpaddq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xdb, 0x0a], "vpandq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xdb, 0x4a, 0x01], "vpandq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xdf, 0x0a], "vpandnq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xdf, 0x4a, 0x01], "vpandnq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x0a], "vcvttpd2dq xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xeb, 0x0a], "vporq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xeb, 0x4a, 0x01], "vporq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xef, 0x0a], "vpxorq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xef, 0x4a, 0x01], "vpxorq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xf4, 0x0a], "vpmuludq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xf4, 0x4a, 0x01], "vpmuludq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xfb, 0x0a], "vpsubq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x38, 0xfb, 0x4a, 0x01], "vpsubq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0x0a], "vsqrtpd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x54, 0x0a], "vandpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x55, 0x0a], "vandnpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x56, 0x0a], "vorpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x57, 0x0a], "vxorpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0x0a], "vaddpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x58, 0xca], "vaddpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0x0a], "vmulpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x59, 0xca], "vmulpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0x0a], "vsubpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5c, 0xca], "vsubpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5d, 0x0a], "vminpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0x0a], "vdivpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5e, 0xca], "vdivpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5f, 0x0a], "vmaxpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xd4, 0x0a], "vpaddq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xdb, 0x0a], "vpandq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xdf, 0x0a], "vpandnq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xeb, 0x0a], "vporq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xef, 0x0a], "vpxorq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xf4, 0x0a], "vpmuludq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xfb, 0x0a], "vpsubq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x3d, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x0a], "vmovupd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0x4a, 0x01], "vmovupd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x10, 0xca], "vmovupd zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0x0a], "vmovupd zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0x4a, 0x01], "vmovupd zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x11, 0xca], "vmovupd zmm2, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0x4a, 0x01], "vunpcklpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x14, 0xca], "vunpcklpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0x4a, 0x01], "vunpckhpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x15, 0xca], "vunpckhpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0x0a], "vmovapd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0x4a, 0x01], "vmovapd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x28, 0xca], "vmovapd zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0x0a], "vmovapd zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0x4a, 0x01], "vmovapd zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x29, 0xca], "vmovapd zmm2, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x0a], "vmovntpd zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x2b, 0x4a, 0x01], "vmovntpd zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0x0a], "vsqrtpd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0x4a, 0x01], "vsqrtpd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x51, 0xca], "vsqrtpd zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0x0a], "vandpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0x4a, 0x01], "vandpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x54, 0xca], "vandpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0x0a], "vandnpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0x4a, 0x01], "vandnpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x55, 0xca], "vandnpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0x0a], "vorpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0x4a, 0x01], "vorpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x56, 0xca], "vorpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0x0a], "vxorpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0x4a, 0x01], "vxorpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x57, 0xca], "vxorpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0x0a], "vaddpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0x4a, 0x01], "vaddpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x58, 0xca], "vaddpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0x0a], "vmulpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0x4a, 0x01], "vmulpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x59, 0xca], "vmulpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0x0a], "vcvtpd2ps ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5a, 0xca], "vcvtpd2ps ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0x0a], "vsubpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0x4a, 0x01], "vsubpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5c, 0xca], "vsubpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0x0a], "vminpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0x4a, 0x01], "vminpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5d, 0xca], "vminpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0x0a], "vdivpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0x4a, 0x01], "vdivpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5e, 0xca], "vdivpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0x4a, 0x01], "vmaxpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x5f, 0xca], "vmaxpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0x0a], "vpunpcklbw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x60, 0xca], "vpunpcklbw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0x0a], "vpunpcklwd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x61, 0xca], "vpunpcklwd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0x0a], "vpacksswb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0x4a, 0x01], "vpacksswb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x63, 0xca], "vpacksswb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0x0a], "vpcmpgtb k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0x4a, 0x01], "vpcmpgtb k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x64, 0xca], "vpcmpgtb k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0x0a], "vpcmpgtw k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0x4a, 0x01], "vpcmpgtw k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x65, 0xca], "vpcmpgtw k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0x0a], "vpackuswb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0x4a, 0x01], "vpackuswb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x67, 0xca], "vpackuswb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0x0a], "vpunpckhbw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x68, 0xca], "vpunpckhbw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0x0a], "vpunpckhwd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x69, 0xca], "vpunpckhwd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6c, 0xca], "vpunpcklqdq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6d, 0xca], "vpunpckhqdq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0x0a], "vmovdqa64 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x6f, 0xca], "vmovdqa64 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vprolq zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vprolq zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0x0a], "vpcmpeqb k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0x4a, 0x01], "vpcmpeqb k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x74, 0xca], "vpcmpeqb k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0x0a], "vpcmpeqw k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0x4a, 0x01], "vpcmpeqw k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x75, 0xca], "vpcmpeqw k1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0x0a], "vcvttpd2uqq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x78, 0xca], "vcvttpd2uqq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0x0a], "vcvtpd2uqq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x79, 0xca], "vcvtpd2uqq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0x0a], "vcvttpd2qq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7a, 0xca], "vcvttpd2qq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0x0a], "vcvtpd2qq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7b, 0xca], "vcvtpd2qq zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0x0a], "vmovdqa64 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0x4a, 0x01], "vmovdqa64 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0x7f, 0xca], "vmovdqa64 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc2, 0xca, 0xcc], "vcmppd k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xc6, 0xca, 0xcc], "vshufpd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0x0a], "vpsrlw zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0x4a, 0x01], "vpsrlw zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd1, 0xca], "vpsrlw zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0x0a], "vpsrlq zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0x4a, 0x01], "vpsrlq zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd3, 0xca], "vpsrlq zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0x0a], "vpaddq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0x4a, 0x01], "vpaddq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd4, 0xca], "vpaddq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0x0a], "vpmullw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0x4a, 0x01], "vpmullw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd5, 0xca], "vpmullw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0x0a], "vpsubusb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0x4a, 0x01], "vpsubusb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd8, 0xca], "vpsubusb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0x0a], "vpsubusw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0x4a, 0x01], "vpsubusw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xd9, 0xca], "vpsubusw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0x0a], "vpminub zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0x4a, 0x01], "vpminub zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xda, 0xca], "vpminub zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0x0a], "vpandq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0x4a, 0x01], "vpandq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdb, 0xca], "vpandq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0x0a], "vpaddusb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0x4a, 0x01], "vpaddusb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdc, 0xca], "vpaddusb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0x0a], "vpaddusw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0x4a, 0x01], "vpaddusw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdd, 0xca], "vpaddusw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0x0a], "vpmaxub zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0x4a, 0x01], "vpmaxub zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xde, 0xca], "vpmaxub zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0x0a], "vpandnq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0x4a, 0x01], "vpandnq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xdf, 0xca], "vpandnq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0x0a], "vpavgb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0x4a, 0x01], "vpavgb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe0, 0xca], "vpavgb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0x0a], "vpsraw zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0x4a, 0x01], "vpsraw zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe1, 0xca], "vpsraw zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0x0a], "vpsraq zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0x4a, 0x01], "vpsraq zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe2, 0xca], "vpsraq zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0x0a], "vpavgw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0x4a, 0x01], "vpavgw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe3, 0xca], "vpavgw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0x0a], "vpmulhuw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe4, 0xca], "vpmulhuw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0x0a], "vpmulhw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0x4a, 0x01], "vpmulhw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe5, 0xca], "vpmulhw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0x0a], "vcvttpd2dq ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe6, 0xca], "vcvttpd2dq ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0x0a], "vpsubsb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0x4a, 0x01], "vpsubsb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe8, 0xca], "vpsubsb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0x0a], "vpsubsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0x4a, 0x01], "vpsubsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xe9, 0xca], "vpsubsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0x0a], "vpminsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0x4a, 0x01], "vpminsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xea, 0xca], "vpminsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0x0a], "vporq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0x4a, 0x01], "vporq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xeb, 0xca], "vporq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0x0a], "vpaddsb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0x4a, 0x01], "vpaddsb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xec, 0xca], "vpaddsb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0x0a], "vpaddsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0x4a, 0x01], "vpaddsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xed, 0xca], "vpaddsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0x0a], "vpmaxsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0x4a, 0x01], "vpmaxsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xee, 0xca], "vpmaxsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0x0a], "vpxorq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0x4a, 0x01], "vpxorq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xef, 0xca], "vpxorq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0x0a], "vpsllw zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0x4a, 0x01], "vpsllw zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf1, 0xca], "vpsllw zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0x0a], "vpsllq zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0x4a, 0x01], "vpsllq zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf3, 0xca], "vpsllq zmm1, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0x4a, 0x01], "vpmuludq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf4, 0xca], "vpmuludq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0x0a], "vpmaddwd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf5, 0xca], "vpmaddwd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x0a], "vpsadbw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0x4a, 0x01], "vpsadbw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf6, 0xca], "vpsadbw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0x0a], "vpsubb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0x4a, 0x01], "vpsubb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf8, 0xca], "vpsubb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0x0a], "vpsubw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0x4a, 0x01], "vpsubw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xf9, 0xca], "vpsubw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0x0a], "vpsubq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0x4a, 0x01], "vpsubq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfb, 0xca], "vpsubq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0x0a], "vpaddb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0x4a, 0x01], "vpaddb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfc, 0xca], "vpaddb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0x0a], "vpaddw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0x4a, 0x01], "vpaddw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x48, 0xfd, 0xca], "vpaddw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0x0a], "vmovupd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0x4a, 0x01], "vmovupd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x10, 0xca], "vmovupd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0x0a], "vmovupd zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0x4a, 0x01], "vmovupd zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x11, 0xca], "vmovupd zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x14, 0xca], "vunpcklpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x15, 0xca], "vunpckhpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0x0a], "vmovapd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0x4a, 0x01], "vmovapd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x28, 0xca], "vmovapd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0x0a], "vmovapd zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0x4a, 0x01], "vmovapd zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x29, 0xca], "vmovapd zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x51, 0xca], "vsqrtpd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x54, 0xca], "vandpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x55, 0xca], "vandnpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x56, 0xca], "vorpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x57, 0xca], "vxorpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x58, 0xca], "vaddpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x59, 0xca], "vmulpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5c, 0xca], "vsubpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5d, 0xca], "vminpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5e, 0xca], "vdivpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x5f, 0xca], "vmaxpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0x0a], "vpunpcklbw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x60, 0xca], "vpunpcklbw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0x0a], "vpunpcklwd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x61, 0xca], "vpunpcklwd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0x0a], "vpacksswb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0x4a, 0x01], "vpacksswb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x63, 0xca], "vpacksswb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0x0a], "vpcmpgtb k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0x4a, 0x01], "vpcmpgtb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x64, 0xca], "vpcmpgtb k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0x0a], "vpcmpgtw k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0x4a, 0x01], "vpcmpgtw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x65, 0xca], "vpcmpgtw k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0x0a], "vpackuswb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0x4a, 0x01], "vpackuswb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x67, 0xca], "vpackuswb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0x0a], "vpunpckhbw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x68, 0xca], "vpunpckhbw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0x0a], "vpunpckhwd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x69, 0xca], "vpunpckhwd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x6f, 0xca], "vmovdqa64 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0x0a], "vpcmpeqb k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0x4a, 0x01], "vpcmpeqb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x74, 0xca], "vpcmpeqb k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0x0a], "vpcmpeqw k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0x4a, 0x01], "vpcmpeqw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x75, 0xca], "vpcmpeqw k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0x0a], "vmovdqa64 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqa64 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0x7f, 0xca], "vmovdqa64 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0x0a], "vpsrlw zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0x4a, 0x01], "vpsrlw zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd1, 0xca], "vpsrlw zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0x0a], "vpsrlq zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0x4a, 0x01], "vpsrlq zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd3, 0xca], "vpsrlq zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd4, 0xca], "vpaddq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0x0a], "vpmullw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0x4a, 0x01], "vpmullw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd5, 0xca], "vpmullw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0x0a], "vpsubusb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0x4a, 0x01], "vpsubusb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd8, 0xca], "vpsubusb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0x0a], "vpsubusw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0x4a, 0x01], "vpsubusw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xd9, 0xca], "vpsubusw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0x0a], "vpminub zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0x4a, 0x01], "vpminub zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xda, 0xca], "vpminub zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdb, 0xca], "vpandq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0x0a], "vpaddusb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0x4a, 0x01], "vpaddusb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdc, 0xca], "vpaddusb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0x0a], "vpaddusw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0x4a, 0x01], "vpaddusw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdd, 0xca], "vpaddusw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0x0a], "vpmaxub zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0x4a, 0x01], "vpmaxub zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xde, 0xca], "vpmaxub zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xdf, 0xca], "vpandnq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0x0a], "vpavgb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0x4a, 0x01], "vpavgb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe0, 0xca], "vpavgb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0x0a], "vpsraw zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0x4a, 0x01], "vpsraw zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe1, 0xca], "vpsraw zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0x0a], "vpsraq zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0x4a, 0x01], "vpsraq zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe2, 0xca], "vpsraq zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0x0a], "vpavgw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0x4a, 0x01], "vpavgw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe3, 0xca], "vpavgw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0x0a], "vpmulhuw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe4, 0xca], "vpmulhuw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0x0a], "vpmulhw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0x4a, 0x01], "vpmulhw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe5, 0xca], "vpmulhw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0x0a], "vpsubsb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0x4a, 0x01], "vpsubsb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe8, 0xca], "vpsubsb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0x0a], "vpsubsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0x4a, 0x01], "vpsubsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xe9, 0xca], "vpsubsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0x0a], "vpminsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0x4a, 0x01], "vpminsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xea, 0xca], "vpminsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xeb, 0xca], "vporq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0x0a], "vpaddsb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0x4a, 0x01], "vpaddsb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xec, 0xca], "vpaddsb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0x0a], "vpaddsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0x4a, 0x01], "vpaddsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xed, 0xca], "vpaddsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0x0a], "vpmaxsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0x4a, 0x01], "vpmaxsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xee, 0xca], "vpmaxsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xef, 0xca], "vpxorq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0x0a], "vpsllw zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0x4a, 0x01], "vpsllw zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf1, 0xca], "vpsllw zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0x0a], "vpsllq zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0x4a, 0x01], "vpsllq zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf3, 0xca], "vpsllq zmm1{k5}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf4, 0xca], "vpmuludq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0x0a], "vpmaddwd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf5, 0xca], "vpmaddwd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0x0a], "vpsubb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0x4a, 0x01], "vpsubb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf8, 0xca], "vpsubb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0x0a], "vpsubw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0x4a, 0x01], "vpsubw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xf9, 0xca], "vpsubw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfb, 0xca], "vpsubq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0x0a], "vpaddb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0x4a, 0x01], "vpaddb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfc, 0xca], "vpaddb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0x0a], "vpaddw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0x4a, 0x01], "vpaddw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0x4d, 0xfd, 0xca], "vpaddw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x14, 0x0a], "vunpcklpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x14, 0x4a, 0x01], "vunpcklpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x15, 0x0a], "vunpckhpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x15, 0x4a, 0x01], "vunpckhpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0x0a], "vsqrtpd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0x4a, 0x01], "vsqrtpd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x51, 0xca], "vsqrtpd zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x54, 0x0a], "vandpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x54, 0x4a, 0x01], "vandpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x55, 0x0a], "vandnpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x55, 0x4a, 0x01], "vandnpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x56, 0x0a], "vorpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x56, 0x4a, 0x01], "vorpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x57, 0x0a], "vxorpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x57, 0x4a, 0x01], "vxorpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0x0a], "vaddpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0x4a, 0x01], "vaddpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x58, 0xca], "vaddpd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0x0a], "vmulpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0x4a, 0x01], "vmulpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x59, 0xca], "vmulpd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0x0a], "vcvtpd2ps ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5a, 0xca], "vcvtpd2ps ymm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0x0a], "vsubpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0x4a, 0x01], "vsubpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5c, 0xca], "vsubpd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5d, 0x0a], "vminpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5d, 0x4a, 0x01], "vminpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0x0a], "vdivpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0x4a, 0x01], "vdivpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5e, 0xca], "vdivpd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5f, 0x0a], "vmaxpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x5f, 0x4a, 0x01], "vmaxpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x6c, 0x0a], "vpunpcklqdq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x6d, 0x0a], "vpunpckhqdq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x72, 0x0a, 0xcc], "vprolq zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x78, 0x0a], "vcvttpd2uqq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0x0a], "vcvtpd2uqq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x79, 0xca], "vcvtpd2uqq zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x7a, 0x0a], "vcvttpd2qq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0x0a], "vcvtpd2qq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0x7b, 0xca], "vcvtpd2qq zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xc2, 0x0a, 0xcc], "vcmppd k1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xc6, 0x0a, 0xcc], "vshufpd zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xd4, 0x0a], "vpaddq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xd4, 0x4a, 0x01], "vpaddq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xdb, 0x0a], "vpandq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xdb, 0x4a, 0x01], "vpandq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xdf, 0x0a], "vpandnq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xdf, 0x4a, 0x01], "vpandnq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xe6, 0x0a], "vcvttpd2dq ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xeb, 0x0a], "vporq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xeb, 0x4a, 0x01], "vporq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xef, 0x0a], "vpxorq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xef, 0x4a, 0x01], "vpxorq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xf4, 0x0a], "vpmuludq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xf4, 0x4a, 0x01], "vpmuludq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xfb, 0x0a], "vpsubq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x58, 0xfb, 0x4a, 0x01], "vpsubq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x14, 0x0a], "vunpcklpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x15, 0x0a], "vunpckhpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0x0a], "vsqrtpd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x51, 0xca], "vsqrtpd zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x54, 0x0a], "vandpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x55, 0x0a], "vandnpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x56, 0x0a], "vorpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x57, 0x0a], "vxorpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0x0a], "vaddpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x58, 0xca], "vaddpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0x0a], "vmulpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x59, 0xca], "vmulpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0x0a], "vsubpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5c, 0xca], "vsubpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5d, 0x0a], "vminpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0x0a], "vdivpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5e, 0xca], "vdivpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5f, 0x0a], "vmaxpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xc2, 0x0a, 0xcc], "vcmppd k1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xc2, 0x4a, 0x01, 0xcc], "vcmppd k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xd4, 0x0a], "vpaddq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xdb, 0x0a], "vpandq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xdf, 0x0a], "vpandnq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xeb, 0x0a], "vporq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xef, 0x0a], "vpxorq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xf4, 0x0a], "vpmuludq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xfb, 0x0a], "vpsubq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x5d, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x2e, 0xca], "vucomisd xmm1{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x2f, 0xca], "vcomisd xmm1{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x51, 0xca], "vsqrtpd zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x58, 0xca], "vaddpd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x59, 0xca], "vmulpd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x5a, 0xca], "vcvtpd2ps ymm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x5c, 0xca], "vsubpd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x5d, 0xca], "vminpd zmm1{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x5e, 0xca], "vdivpd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x5f, 0xca], "vmaxpd zmm1{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x78, 0xca], "vcvttpd2uqq zmm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x79, 0xca], "vcvtpd2uqq zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x7a, 0xca], "vcvttpd2qq zmm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0x7b, 0xca], "vcvtpd2qq zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0xc2, 0xca, 0xcc], "vcmppd k1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x78, 0xe6, 0xca], "vcvttpd2dq ymm1{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x51, 0xca], "vsqrtpd zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x58, 0xca], "vaddpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x59, 0xca], "vmulpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x5c, 0xca], "vsubpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x5d, 0xca], "vminpd zmm1{k5}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x5e, 0xca], "vdivpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x5f, 0xca], "vmaxpd zmm1{k5}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0xc2, 0xca, 0xcc], "vcmppd k1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x7d, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0x0a], "vmovupd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0x4a, 0x01], "vmovupd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x10, 0xca], "vmovupd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x11, 0xca], "vmovupd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x14, 0xca], "vunpcklpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x15, 0xca], "vunpckhpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0x0a], "vmovapd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0x4a, 0x01], "vmovapd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x28, 0xca], "vmovapd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x29, 0xca], "vmovapd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x51, 0xca], "vsqrtpd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x54, 0xca], "vandpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x55, 0xca], "vandnpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x56, 0xca], "vorpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x57, 0xca], "vxorpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x58, 0xca], "vaddpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x59, 0xca], "vmulpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5c, 0xca], "vsubpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5d, 0xca], "vminpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5e, 0xca], "vdivpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x5f, 0xca], "vmaxpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0x0a], "vpunpcklbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0x4a, 0x01], "vpunpcklbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x60, 0xca], "vpunpcklbw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0x0a], "vpunpcklwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0x4a, 0x01], "vpunpcklwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x61, 0xca], "vpunpcklwd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0x0a], "vpacksswb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0x4a, 0x01], "vpacksswb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x63, 0xca], "vpacksswb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0x0a], "vpackuswb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0x4a, 0x01], "vpackuswb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x67, 0xca], "vpackuswb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0x0a], "vpunpckhbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0x4a, 0x01], "vpunpckhbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x68, 0xca], "vpunpckhbw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0x0a], "vpunpckhwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0x4a, 0x01], "vpunpckhwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x69, 0xca], "vpunpckhwd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6c, 0xca], "vpunpcklqdq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6d, 0xca], "vpunpckhqdq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0x0a], "vmovdqa64 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqa64 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x6f, 0xca], "vmovdqa64 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vprolq xmm0{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x78, 0xca], "vcvttpd2uqq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x79, 0xca], "vcvtpd2uqq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7a, 0xca], "vcvttpd2qq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7b, 0xca], "vcvtpd2qq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0x7f, 0xca], "vmovdqa64 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xc6, 0xca, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0x0a], "vpsrlw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0x4a, 0x01], "vpsrlw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd1, 0xca], "vpsrlw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0x0a], "vpsrlq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0x4a, 0x01], "vpsrlq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd3, 0xca], "vpsrlq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd4, 0xca], "vpaddq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0x0a], "vpmullw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0x4a, 0x01], "vpmullw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd5, 0xca], "vpmullw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0x0a], "vpsubusb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0x4a, 0x01], "vpsubusb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd8, 0xca], "vpsubusb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0x0a], "vpsubusw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0x4a, 0x01], "vpsubusw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xd9, 0xca], "vpsubusw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0x0a], "vpminub xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0x4a, 0x01], "vpminub xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xda, 0xca], "vpminub xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdb, 0xca], "vpandq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0x0a], "vpaddusb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0x4a, 0x01], "vpaddusb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdc, 0xca], "vpaddusb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0x0a], "vpaddusw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0x4a, 0x01], "vpaddusw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdd, 0xca], "vpaddusw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0x0a], "vpmaxub xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0x4a, 0x01], "vpmaxub xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xde, 0xca], "vpmaxub xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xdf, 0xca], "vpandnq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0x0a], "vpavgb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0x4a, 0x01], "vpavgb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe0, 0xca], "vpavgb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0x0a], "vpsraw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0x4a, 0x01], "vpsraw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe1, 0xca], "vpsraw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0x0a], "vpsraq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0x4a, 0x01], "vpsraq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe2, 0xca], "vpsraq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0x0a], "vpavgw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0x4a, 0x01], "vpavgw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe3, 0xca], "vpavgw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0x0a], "vpmulhuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0x4a, 0x01], "vpmulhuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe4, 0xca], "vpmulhuw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0x0a], "vpmulhw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0x4a, 0x01], "vpmulhw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe5, 0xca], "vpmulhw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0x0a], "vpsubsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0x4a, 0x01], "vpsubsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe8, 0xca], "vpsubsb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0x0a], "vpsubsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0x4a, 0x01], "vpsubsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xe9, 0xca], "vpsubsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0x0a], "vpminsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0x4a, 0x01], "vpminsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xea, 0xca], "vpminsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xeb, 0xca], "vporq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0x0a], "vpaddsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0x4a, 0x01], "vpaddsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xec, 0xca], "vpaddsb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0x0a], "vpaddsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0x4a, 0x01], "vpaddsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xed, 0xca], "vpaddsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0x0a], "vpmaxsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0x4a, 0x01], "vpmaxsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xee, 0xca], "vpmaxsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xef, 0xca], "vpxorq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0x0a], "vpsllw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0x4a, 0x01], "vpsllw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf1, 0xca], "vpsllw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0x0a], "vpsllq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0x4a, 0x01], "vpsllq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf3, 0xca], "vpsllq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf4, 0xca], "vpmuludq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0x0a], "vpmaddwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0x4a, 0x01], "vpmaddwd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf5, 0xca], "vpmaddwd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0x0a], "vpsubb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0x4a, 0x01], "vpsubb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf8, 0xca], "vpsubb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0x0a], "vpsubw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0x4a, 0x01], "vpsubw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xf9, 0xca], "vpsubw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfb, 0xca], "vpsubq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0x0a], "vpaddb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0x4a, 0x01], "vpaddb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfc, 0xca], "vpaddb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0x0a], "vpaddw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0x4a, 0x01], "vpaddw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0x8d, 0xfd, 0xca], "vpaddw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x14, 0x0a], "vunpcklpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x14, 0x4a, 0x01], "vunpcklpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x15, 0x0a], "vunpckhpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x15, 0x4a, 0x01], "vunpckhpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0x0a], "vsqrtpd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0x4a, 0x01], "vsqrtpd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x54, 0x0a], "vandpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x54, 0x4a, 0x01], "vandpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x55, 0x0a], "vandnpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x55, 0x4a, 0x01], "vandnpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x56, 0x0a], "vorpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x56, 0x4a, 0x01], "vorpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x57, 0x0a], "vxorpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x57, 0x4a, 0x01], "vxorpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0x0a], "vaddpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0x4a, 0x01], "vaddpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0x0a], "vmulpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0x4a, 0x01], "vmulpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0x0a], "vsubpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0x4a, 0x01], "vsubpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5d, 0x0a], "vminpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5d, 0x4a, 0x01], "vminpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0x0a], "vdivpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0x4a, 0x01], "vdivpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5f, 0x0a], "vmaxpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x5f, 0x4a, 0x01], "vmaxpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x6c, 0x0a], "vpunpcklqdq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x6c, 0x4a, 0x01], "vpunpcklqdq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x6d, 0x0a], "vpunpckhqdq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x6d, 0x4a, 0x01], "vpunpckhqdq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x72, 0x0a, 0xcc], "vprolq xmm0{k5}{z}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x72, 0x4a, 0x01, 0xcc], "vprolq xmm0{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x78, 0x0a], "vcvttpd2uqq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x78, 0x4a, 0x01], "vcvttpd2uqq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0x0a], "vcvtpd2uqq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0x4a, 0x01], "vcvtpd2uqq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x7a, 0x0a], "vcvttpd2qq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x7a, 0x4a, 0x01], "vcvttpd2qq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0x0a], "vcvtpd2qq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0x4a, 0x01], "vcvtpd2qq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xc6, 0x0a, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xd4, 0x0a], "vpaddq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xd4, 0x4a, 0x01], "vpaddq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xdb, 0x0a], "vpandq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xdb, 0x4a, 0x01], "vpandq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xdf, 0x0a], "vpandnq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xdf, 0x4a, 0x01], "vpandnq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xeb, 0x0a], "vporq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xeb, 0x4a, 0x01], "vporq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xef, 0x0a], "vpxorq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xef, 0x4a, 0x01], "vpxorq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xf4, 0x0a], "vpmuludq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xf4, 0x4a, 0x01], "vpmuludq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xfb, 0x0a], "vpsubq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0x9d, 0xfb, 0x4a, 0x01], "vpsubq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0x0a], "vmovupd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0x4a, 0x01], "vmovupd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x10, 0xca], "vmovupd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x11, 0xca], "vmovupd ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x14, 0xca], "vunpcklpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x15, 0xca], "vunpckhpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0x0a], "vmovapd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0x4a, 0x01], "vmovapd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x28, 0xca], "vmovapd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x29, 0xca], "vmovapd ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x51, 0xca], "vsqrtpd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x54, 0xca], "vandpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x55, 0xca], "vandnpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x56, 0xca], "vorpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x57, 0xca], "vxorpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x58, 0xca], "vaddpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x59, 0xca], "vmulpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5a, 0xca], "vcvtpd2ps xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5c, 0xca], "vsubpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5d, 0xca], "vminpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5e, 0xca], "vdivpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x5f, 0xca], "vmaxpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0x0a], "vpunpcklbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0x4a, 0x01], "vpunpcklbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x60, 0xca], "vpunpcklbw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0x0a], "vpunpcklwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0x4a, 0x01], "vpunpcklwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x61, 0xca], "vpunpcklwd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0x0a], "vpacksswb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0x4a, 0x01], "vpacksswb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x63, 0xca], "vpacksswb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0x0a], "vpackuswb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0x4a, 0x01], "vpackuswb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x67, 0xca], "vpackuswb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0x0a], "vpunpckhbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0x4a, 0x01], "vpunpckhbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x68, 0xca], "vpunpckhbw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0x0a], "vpunpckhwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0x4a, 0x01], "vpunpckhwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x69, 0xca], "vpunpckhwd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6c, 0xca], "vpunpcklqdq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6d, 0xca], "vpunpckhqdq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x0a], "vmovdqa64 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0x4a, 0x01], "vmovdqa64 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x6f, 0xca], "vmovdqa64 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vprolq ymm0{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x78, 0xca], "vcvttpd2uqq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x79, 0xca], "vcvtpd2uqq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7a, 0xca], "vcvttpd2qq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7b, 0xca], "vcvtpd2qq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0x7f, 0xca], "vmovdqa64 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xc6, 0xca, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0x0a], "vpsrlw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0x4a, 0x01], "vpsrlw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd1, 0xca], "vpsrlw ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0x0a], "vpsrlq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0x4a, 0x01], "vpsrlq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd3, 0xca], "vpsrlq ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd4, 0xca], "vpaddq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0x0a], "vpmullw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0x4a, 0x01], "vpmullw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd5, 0xca], "vpmullw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0x0a], "vpsubusb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0x4a, 0x01], "vpsubusb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd8, 0xca], "vpsubusb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0x0a], "vpsubusw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0x4a, 0x01], "vpsubusw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xd9, 0xca], "vpsubusw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0x0a], "vpminub ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0x4a, 0x01], "vpminub ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xda, 0xca], "vpminub ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdb, 0xca], "vpandq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0x0a], "vpaddusb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0x4a, 0x01], "vpaddusb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdc, 0xca], "vpaddusb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0x0a], "vpaddusw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0x4a, 0x01], "vpaddusw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdd, 0xca], "vpaddusw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0x0a], "vpmaxub ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0x4a, 0x01], "vpmaxub ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xde, 0xca], "vpmaxub ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xdf, 0xca], "vpandnq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0x0a], "vpavgb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0x4a, 0x01], "vpavgb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe0, 0xca], "vpavgb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0x0a], "vpsraw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0x4a, 0x01], "vpsraw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe1, 0xca], "vpsraw ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0x0a], "vpsraq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0x4a, 0x01], "vpsraq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe2, 0xca], "vpsraq ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0x0a], "vpavgw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0x4a, 0x01], "vpavgw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe3, 0xca], "vpavgw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0x0a], "vpmulhuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0x4a, 0x01], "vpmulhuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe4, 0xca], "vpmulhuw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0x0a], "vpmulhw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0x4a, 0x01], "vpmulhw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe5, 0xca], "vpmulhw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe6, 0xca], "vcvttpd2dq xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x0a], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0x4a, 0x01], "vpsubsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe8, 0xca], "vpsubsb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0x0a], "vpsubsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0x4a, 0x01], "vpsubsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xe9, 0xca], "vpsubsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0x0a], "vpminsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0x4a, 0x01], "vpminsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xea, 0xca], "vpminsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xeb, 0xca], "vporq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0x0a], "vpaddsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0x4a, 0x01], "vpaddsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xec, 0xca], "vpaddsb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0x0a], "vpaddsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0x4a, 0x01], "vpaddsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xed, 0xca], "vpaddsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0x0a], "vpmaxsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0x4a, 0x01], "vpmaxsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xee, 0xca], "vpmaxsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xef, 0xca], "vpxorq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0x0a], "vpsllw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0x4a, 0x01], "vpsllw ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf1, 0xca], "vpsllw ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0x0a], "vpsllq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0x4a, 0x01], "vpsllq ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf3, 0xca], "vpsllq ymm1{k5}{z}, ymm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf4, 0xca], "vpmuludq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0x0a], "vpmaddwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0x4a, 0x01], "vpmaddwd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf5, 0xca], "vpmaddwd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0x0a], "vpsubb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0x4a, 0x01], "vpsubb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf8, 0xca], "vpsubb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0x0a], "vpsubw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0x4a, 0x01], "vpsubw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xf9, 0xca], "vpsubw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfb, 0xca], "vpsubq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0x0a], "vpaddb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0x4a, 0x01], "vpaddb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfc, 0xca], "vpaddb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0x0a], "vpaddw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0x4a, 0x01], "vpaddw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfd, 0xad, 0xfd, 0xca], "vpaddw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0x0a], "vunpcklpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x14, 0x4a, 0x01], "vunpcklpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0x0a], "vunpckhpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x15, 0x4a, 0x01], "vunpckhpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0x0a], "vsqrtpd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0x4a, 0x01], "vsqrtpd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x54, 0x0a], "vandpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x54, 0x4a, 0x01], "vandpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x55, 0x0a], "vandnpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x55, 0x4a, 0x01], "vandnpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x56, 0x0a], "vorpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x56, 0x4a, 0x01], "vorpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x57, 0x0a], "vxorpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x57, 0x4a, 0x01], "vxorpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0x0a], "vaddpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0x4a, 0x01], "vaddpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0x0a], "vmulpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0x4a, 0x01], "vmulpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0x0a], "vcvtpd2ps xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0x4a, 0x01], "vcvtpd2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0x0a], "vsubpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0x4a, 0x01], "vsubpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5d, 0x0a], "vminpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5d, 0x4a, 0x01], "vminpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0x0a], "vdivpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0x4a, 0x01], "vdivpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5f, 0x0a], "vmaxpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x5f, 0x4a, 0x01], "vmaxpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x6c, 0x0a], "vpunpcklqdq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x6c, 0x4a, 0x01], "vpunpcklqdq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x6d, 0x0a], "vpunpckhqdq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x6d, 0x4a, 0x01], "vpunpckhqdq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x72, 0x0a, 0xcc], "vprolq ymm0{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x72, 0x4a, 0x01, 0xcc], "vprolq ymm0{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x78, 0x0a], "vcvttpd2uqq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x78, 0x4a, 0x01], "vcvttpd2uqq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0x0a], "vcvtpd2uqq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0x4a, 0x01], "vcvtpd2uqq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x7a, 0x0a], "vcvttpd2qq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x7a, 0x4a, 0x01], "vcvttpd2qq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0x0a], "vcvtpd2qq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0x4a, 0x01], "vcvtpd2qq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xc6, 0x0a, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xd4, 0x0a], "vpaddq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xd4, 0x4a, 0x01], "vpaddq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xdb, 0x0a], "vpandq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xdb, 0x4a, 0x01], "vpandq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xdf, 0x0a], "vpandnq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xdf, 0x4a, 0x01], "vpandnq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x0a], "vcvttpd2dq xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xe6, 0x4a, 0x01], "vcvttpd2dq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xeb, 0x0a], "vporq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xeb, 0x4a, 0x01], "vporq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xef, 0x0a], "vpxorq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xef, 0x4a, 0x01], "vpxorq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xf4, 0x0a], "vpmuludq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xf4, 0x4a, 0x01], "vpmuludq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xfb, 0x0a], "vpsubq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xbd, 0xfb, 0x4a, 0x01], "vpsubq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x0a], "vmovupd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0x4a, 0x01], "vmovupd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x10, 0xca], "vmovupd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x11, 0xca], "vmovupd zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x14, 0xca], "vunpcklpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x15, 0xca], "vunpckhpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x0a], "vmovapd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0x4a, 0x01], "vmovapd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x28, 0xca], "vmovapd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x29, 0xca], "vmovapd zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x54, 0xca], "vandpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x55, 0xca], "vandnpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x56, 0xca], "vorpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x57, 0xca], "vxorpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x58, 0xca], "vaddpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x59, 0xca], "vmulpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5d, 0xca], "vminpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0x0a], "vpunpcklbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0x4a, 0x01], "vpunpcklbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x60, 0xca], "vpunpcklbw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0x0a], "vpunpcklwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0x4a, 0x01], "vpunpcklwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x61, 0xca], "vpunpcklwd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0x0a], "vpacksswb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0x4a, 0x01], "vpacksswb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x63, 0xca], "vpacksswb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0x0a], "vpackuswb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0x4a, 0x01], "vpackuswb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x67, 0xca], "vpackuswb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0x0a], "vpunpckhbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0x4a, 0x01], "vpunpckhbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x68, 0xca], "vpunpckhbw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0x0a], "vpunpckhwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0x4a, 0x01], "vpunpckhwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x69, 0xca], "vpunpckhwd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6c, 0xca], "vpunpcklqdq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6d, 0xca], "vpunpckhqdq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0x0a], "vmovdqa64 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqa64 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x6f, 0xca], "vmovdqa64 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vprolq zmm0{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0x7f, 0xca], "vmovdqa64 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xc6, 0xca, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0x0a], "vpsrlw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0x4a, 0x01], "vpsrlw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd1, 0xca], "vpsrlw zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0x0a], "vpsrlq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0x4a, 0x01], "vpsrlq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd3, 0xca], "vpsrlq zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd4, 0xca], "vpaddq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0x0a], "vpmullw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0x4a, 0x01], "vpmullw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd5, 0xca], "vpmullw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0x0a], "vpsubusb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0x4a, 0x01], "vpsubusb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd8, 0xca], "vpsubusb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0x0a], "vpsubusw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0x4a, 0x01], "vpsubusw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xd9, 0xca], "vpsubusw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0x0a], "vpminub zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0x4a, 0x01], "vpminub zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xda, 0xca], "vpminub zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdb, 0xca], "vpandq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0x0a], "vpaddusb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0x4a, 0x01], "vpaddusb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdc, 0xca], "vpaddusb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0x0a], "vpaddusw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0x4a, 0x01], "vpaddusw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdd, 0xca], "vpaddusw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0x0a], "vpmaxub zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0x4a, 0x01], "vpmaxub zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xde, 0xca], "vpmaxub zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xdf, 0xca], "vpandnq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0x0a], "vpavgb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0x4a, 0x01], "vpavgb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe0, 0xca], "vpavgb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0x0a], "vpsraw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0x4a, 0x01], "vpsraw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe1, 0xca], "vpsraw zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0x0a], "vpsraq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0x4a, 0x01], "vpsraq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe2, 0xca], "vpsraq zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0x0a], "vpavgw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0x4a, 0x01], "vpavgw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe3, 0xca], "vpavgw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0x0a], "vpmulhuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0x4a, 0x01], "vpmulhuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe4, 0xca], "vpmulhuw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0x0a], "vpmulhw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0x4a, 0x01], "vpmulhw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe5, 0xca], "vpmulhw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0x0a], "vpsubsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0x4a, 0x01], "vpsubsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe8, 0xca], "vpsubsb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0x0a], "vpsubsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0x4a, 0x01], "vpsubsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xe9, 0xca], "vpsubsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0x0a], "vpminsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0x4a, 0x01], "vpminsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xea, 0xca], "vpminsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xeb, 0xca], "vporq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0x0a], "vpaddsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0x4a, 0x01], "vpaddsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xec, 0xca], "vpaddsb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0x0a], "vpaddsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0x4a, 0x01], "vpaddsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xed, 0xca], "vpaddsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0x0a], "vpmaxsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0x4a, 0x01], "vpmaxsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xee, 0xca], "vpmaxsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xef, 0xca], "vpxorq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0x0a], "vpsllw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0x4a, 0x01], "vpsllw zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf1, 0xca], "vpsllw zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0x0a], "vpsllq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0x4a, 0x01], "vpsllq zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf3, 0xca], "vpsllq zmm1{k5}{z}, zmm0, xmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf4, 0xca], "vpmuludq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0x0a], "vpmaddwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0x4a, 0x01], "vpmaddwd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf5, 0xca], "vpmaddwd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0x0a], "vpsubb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0x4a, 0x01], "vpsubb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf8, 0xca], "vpsubb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0x0a], "vpsubw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0x4a, 0x01], "vpsubw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xf9, 0xca], "vpsubw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfb, 0xca], "vpsubq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0x0a], "vpaddb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0x4a, 0x01], "vpaddb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfc, 0xca], "vpaddb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0x0a], "vpaddw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0x4a, 0x01], "vpaddw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfd, 0xcd, 0xfd, 0xca], "vpaddw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x14, 0x0a], "vunpcklpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x14, 0x4a, 0x01], "vunpcklpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x15, 0x0a], "vunpckhpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x15, 0x4a, 0x01], "vunpckhpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0x0a], "vsqrtpd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0x4a, 0x01], "vsqrtpd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x54, 0x0a], "vandpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x54, 0x4a, 0x01], "vandpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x55, 0x0a], "vandnpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x55, 0x4a, 0x01], "vandnpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x56, 0x0a], "vorpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x56, 0x4a, 0x01], "vorpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x57, 0x0a], "vxorpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x57, 0x4a, 0x01], "vxorpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0x0a], "vaddpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0x4a, 0x01], "vaddpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0x0a], "vmulpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0x4a, 0x01], "vmulpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0x0a], "vcvtpd2ps ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0x4a, 0x01], "vcvtpd2ps ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0x0a], "vsubpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0x4a, 0x01], "vsubpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5d, 0x0a], "vminpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5d, 0x4a, 0x01], "vminpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0x0a], "vdivpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0x4a, 0x01], "vdivpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5f, 0x0a], "vmaxpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x5f, 0x4a, 0x01], "vmaxpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x6c, 0x0a], "vpunpcklqdq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x6c, 0x4a, 0x01], "vpunpcklqdq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x6d, 0x0a], "vpunpckhqdq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x6d, 0x4a, 0x01], "vpunpckhqdq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x72, 0x0a, 0xcc], "vprolq zmm0{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x72, 0x4a, 0x01, 0xcc], "vprolq zmm0{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x78, 0x0a], "vcvttpd2uqq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x78, 0x4a, 0x01], "vcvttpd2uqq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0x0a], "vcvtpd2uqq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0x4a, 0x01], "vcvtpd2uqq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x7a, 0x0a], "vcvttpd2qq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x7a, 0x4a, 0x01], "vcvttpd2qq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0x0a], "vcvtpd2qq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0x4a, 0x01], "vcvtpd2qq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xc6, 0x0a, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xc6, 0x4a, 0x01, 0xcc], "vshufpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xd4, 0x0a], "vpaddq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xd4, 0x4a, 0x01], "vpaddq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xdb, 0x0a], "vpandq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xdb, 0x4a, 0x01], "vpandq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xdf, 0x0a], "vpandnq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xdf, 0x4a, 0x01], "vpandnq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xe6, 0x0a], "vcvttpd2dq ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xe6, 0x4a, 0x01], "vcvttpd2dq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xeb, 0x0a], "vporq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xeb, 0x4a, 0x01], "vporq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xef, 0x0a], "vpxorq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xef, 0x4a, 0x01], "vpxorq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xf4, 0x0a], "vpmuludq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xf4, 0x4a, 0x01], "vpmuludq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xfb, 0x0a], "vpsubq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xdd, 0xfb, 0x4a, 0x01], "vpsubq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x51, 0xca], "vsqrtpd zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x58, 0xca], "vaddpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x59, 0xca], "vmulpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x5a, 0xca], "vcvtpd2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x5c, 0xca], "vsubpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x5d, 0xca], "vminpd zmm1{k5}{z}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x5e, 0xca], "vdivpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x5f, 0xca], "vmaxpd zmm1{k5}{z}{sae}, zmm0, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x78, 0xca], "vcvttpd2uqq zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x79, 0xca], "vcvtpd2uqq zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x7a, 0xca], "vcvttpd2qq zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0x7b, 0xca], "vcvtpd2qq zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfd, 0xfd, 0xe6, 0xca], "vcvttpd2dq ymm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0x0a], "vmovdqu64 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x6f, 0xca], "vmovdqu64 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0x0a, 0xcc], "vpshufhw xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x70, 0xca, 0xcc], "vpshufhw xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0x0a], "vcvtuqq2pd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7a, 0xca], "vcvtuqq2pd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x0a], "vmovq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0x4a, 0x01], "vmovq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7e, 0xca], "vmovq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0x0a], "vmovdqu64 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu64 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0x7f, 0xca], "vmovdqu64 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0x0a], "vcvtqq2pd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x08, 0xe6, 0xca], "vcvtqq2pd xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0x0a], "vmovdqu64 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu64 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x0d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x2a, 0xca], "vcvtsi2ss xmm1{rne-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x2d, 0xca], "vcvtss2si ecx{rne-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x79, 0xca], "vcvtss2usi ecx{rne-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0x0a], "vcvtuqq2pd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x7a, 0xca], "vcvtuqq2pd zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0x7b, 0xca], "vcvtusi2ss xmm1{rne-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0x0a], "vcvtqq2pd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x18, 0xe6, 0xca], "vcvtqq2pd zmm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x1d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0x4a, 0x01], "vcvtsi2ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x0a], "vcvttss2si ecx, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0x4a, 0x01], "vcvttss2si ecx, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x0a], "vcvtss2si ecx, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0x4a, 0x01], "vcvtss2si ecx, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0x0a], "vmovdqu64 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x6f, 0xca], "vmovdqu64 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0x0a, 0xcc], "vpshufhw ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x70, 0xca, 0xcc], "vpshufhw ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0x0a], "vcvttss2usi ecx, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0x4a, 0x01], "vcvttss2usi ecx, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x78, 0xca], "vcvttss2usi ecx, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0x0a], "vcvtss2usi ecx, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0x4a, 0x01], "vcvtss2usi ecx, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x79, 0xca], "vcvtss2usi ecx, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0x0a], "vcvtuqq2pd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7a, 0xca], "vcvtuqq2pd ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x0a], "vcvtusi2ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0x4a, 0x01], "vcvtusi2ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7b, 0xca], "vcvtusi2ss xmm1, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0x0a], "vmovdqu64 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu64 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0x7f, 0xca], "vmovdqu64 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0x0a], "vcvtqq2pd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x28, 0xe6, 0xca], "vcvtqq2pd ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x6f, 0xca], "vmovdqu64 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0x0a], "vmovdqu64 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu64 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0x7f, 0xca], "vmovdqu64 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0x2d, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x2a, 0xca], "vcvtsi2ss xmm1{rd-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x2d, 0xca], "vcvtss2si ecx{rd-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x79, 0xca], "vcvtss2usi ecx{rd-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0x0a], "vcvtuqq2pd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x7a, 0xca], "vcvtuqq2pd zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0x7b, 0xca], "vcvtusi2ss xmm1{rd-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0x0a], "vcvtqq2pd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x38, 0xe6, 0xca], "vcvtqq2pd zmm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0x3d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0x0a], "vmovdqu64 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x6f, 0xca], "vmovdqu64 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0x0a, 0xcc], "vpshufhw zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x70, 0xca, 0xcc], "vpshufhw zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0x0a], "vcvtuqq2pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7a, 0xca], "vcvtuqq2pd zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0x0a], "vmovdqu64 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu64 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0x7f, 0xca], "vmovdqu64 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0x0a], "vcvtqq2pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x48, 0xe6, 0xca], "vcvtqq2pd zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x6f, 0xca], "vmovdqu64 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0x0a], "vmovdqu64 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu64 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0x7f, 0xca], "vmovdqu64 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0x4d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x2a, 0xca], "vcvtsi2ss xmm1{ru-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x2d, 0xca], "vcvtss2si ecx{ru-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x79, 0xca], "vcvtss2usi ecx{ru-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0x0a], "vcvtuqq2pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x7a, 0xca], "vcvtuqq2pd zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0x7b, 0xca], "vcvtusi2ss xmm1{ru-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0x0a], "vcvtqq2pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x58, 0xe6, 0xca], "vcvtqq2pd zmm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0x5d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x2a, 0xca], "vcvtsi2ss xmm1{rz-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x2c, 0xca], "vcvttss2si ecx{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x2d, 0xca], "vcvtss2si ecx{rz-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x78, 0xca], "vcvttss2usi ecx{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x79, 0xca], "vcvtss2usi ecx{rz-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x7a, 0xca], "vcvtuqq2pd zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0x7b, 0xca], "vcvtusi2ss xmm1{rz-sae}, xmm0, edx"); test_display(&[0x62, 0xf1, 0xfe, 0x78, 0xe6, 0xca], "vcvtqq2pd zmm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x7d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x7d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0x0a], "vmovdqu64 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu64 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x6f, 0xca], "vmovdqu64 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0x0a, 0xcc], "vpshufhw xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x70, 0xca, 0xcc], "vpshufhw xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x7a, 0xca], "vcvtuqq2pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0x7f, 0xca], "vmovdqu64 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xfe, 0x8d, 0xe6, 0xca], "vcvtqq2pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0x0a], "vcvtuqq2pd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0x4a, 0x01], "vcvtuqq2pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0x0a], "vcvtqq2pd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0x4a, 0x01], "vcvtqq2pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xfe, 0x9d, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0x0a], "vmovdqu64 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu64 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x6f, 0xca], "vmovdqu64 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0x0a, 0xcc], "vpshufhw ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x70, 0xca, 0xcc], "vpshufhw ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x7a, 0xca], "vcvtuqq2pd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0x7f, 0xca], "vmovdqu64 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xfe, 0xad, 0xe6, 0xca], "vcvtqq2pd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0x0a], "vcvtuqq2pd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0x0a], "vcvtqq2pd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0x4a, 0x01], "vcvtqq2pd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xfe, 0xbd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0x0a], "vmovdqu64 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu64 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x6f, 0xca], "vmovdqu64 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0x0a, 0xcc], "vpshufhw zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshufhw zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x70, 0xca, 0xcc], "vpshufhw zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0x7f, 0xca], "vmovdqu64 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xfe, 0xcd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0x0a], "vcvtuqq2pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0x4a, 0x01], "vcvtuqq2pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0x0a], "vcvtqq2pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0x4a, 0x01], "vcvtqq2pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xfe, 0xdd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xfd, 0x7a, 0xca], "vcvtuqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xfe, 0xfd, 0xe6, 0xca], "vcvtqq2pd zmm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0x0a], "vmovddup xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0x4a, 0x01], "vmovddup xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x12, 0xca], "vmovddup xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0x0a], "vmovdqu16 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x6f, 0xca], "vmovdqu16 xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0x0a, 0xcc], "vpshuflw xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x70, 0xca, 0xcc], "vpshuflw xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0x0a], "vcvtuqq2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7a, 0xca], "vcvtuqq2ps xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0x0a], "vmovdqu16 xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0x4a, 0x01], "vmovdqu16 xmmword [bp + si * 1 + 0x10], xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0x7f, 0xca], "vmovdqu16 xmm2, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0x0a], "vcvtpd2dq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x08, 0xe6, 0xca], "vcvtpd2dq xmm1, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0x0a], "vmovddup xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0x4a, 0x01], "vmovddup xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x12, 0xca], "vmovddup xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0x0a], "vmovdqu16 xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0x4a, 0x01], "vmovdqu16 xmmword [bp + si * 1 + 0x10]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x0d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x2d, 0xca], "vcvtsd2si ecx{rne-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x51, 0xca], "vsqrtsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x58, 0xca], "vaddsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x59, 0xca], "vmulsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x5a, 0xca], "vcvtsd2ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x5c, 0xca], "vsubsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x5e, 0xca], "vdivsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x79, 0xca], "vcvtsd2usi ecx{rne-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0x7a, 0xca], "vcvtuqq2ps ymm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x18, 0xe6, 0xca], "vcvtpd2dq ymm1{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x58, 0xca], "vaddsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x59, 0xca], "vmulsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x5c, 0xca], "vsubsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x5e, 0xca], "vdivsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x1d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x0a], "vmovsd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0x4a, 0x01], "vmovsd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x10, 0xca], "vmovsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x0a], "vmovsd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0x4a, 0x01], "vmovsd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x0a], "vmovddup ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0x4a, 0x01], "vmovddup ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x12, 0xca], "vmovddup ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2a, 0x4a, 0x01], "vcvtsi2sd xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0x0a], "vcvttsd2si ecx, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0x4a, 0x01], "vcvttsd2si ecx, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0x0a], "vcvtsd2si ecx, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0x4a, 0x01], "vcvtsd2si ecx, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0x4a, 0x01], "vsqrtsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x51, 0xca], "vsqrtsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0x0a], "vaddsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0x4a, 0x01], "vaddsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x58, 0xca], "vaddsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0x0a], "vmulsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0x4a, 0x01], "vmulsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x59, 0xca], "vmulsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0x0a], "vsubsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0x4a, 0x01], "vsubsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5c, 0xca], "vsubsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0x0a], "vminsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0x4a, 0x01], "vminsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5d, 0xca], "vminsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0x0a], "vdivsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0x4a, 0x01], "vdivsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5e, 0xca], "vdivsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0x0a], "vmaxsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0x4a, 0x01], "vmaxsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x5f, 0xca], "vmaxsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0x0a], "vmovdqu16 ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x6f, 0xca], "vmovdqu16 ymm1, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0x0a, 0xcc], "vpshuflw ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x70, 0xca, 0xcc], "vpshuflw ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0x0a], "vcvttsd2usi ecx, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0x4a, 0x01], "vcvttsd2usi ecx, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x78, 0xca], "vcvttsd2usi ecx, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0x0a], "vcvtsd2usi ecx, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0x4a, 0x01], "vcvtsd2usi ecx, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x79, 0xca], "vcvtsd2usi ecx, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0x0a], "vcvtuqq2ps xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7a, 0xca], "vcvtuqq2ps xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x0a], "vcvtusi2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7b, 0x4a, 0x01], "vcvtusi2sd xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0x0a], "vmovdqu16 ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0x4a, 0x01], "vmovdqu16 ymmword [bp + si * 1 + 0x20], ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0x7f, 0xca], "vmovdqu16 ymm2, ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x0a, 0xcc], "vcmpsd k1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0x4a, 0x01, 0xcc], "vcmpsd k1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xc2, 0xca, 0xcc], "vcmpsd k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0x0a], "vcvtpd2dq xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x28, 0xe6, 0xca], "vcvtpd2dq xmm1, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0x0a], "vmovsd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0x4a, 0x01], "vmovsd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x10, 0xca], "vmovsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x0a], "vmovsd qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0x4a, 0x01], "vmovsd qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x11, 0xca], "vmovsd xmm2{k5}, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0x0a], "vmovddup ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0x4a, 0x01], "vmovddup ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x12, 0xca], "vmovddup ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x0a], "vsqrtsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0x4a, 0x01], "vsqrtsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x51, 0xca], "vsqrtsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0x0a], "vaddsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0x4a, 0x01], "vaddsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x58, 0xca], "vaddsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0x0a], "vmulsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0x4a, 0x01], "vmulsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x59, 0xca], "vmulsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0x0a], "vsubsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0x4a, 0x01], "vsubsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5c, 0xca], "vsubsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0x0a], "vminsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0x4a, 0x01], "vminsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5d, 0xca], "vminsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0x0a], "vdivsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0x4a, 0x01], "vdivsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5e, 0xca], "vdivsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0x0a], "vmaxsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0x4a, 0x01], "vmaxsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x5f, 0xca], "vmaxsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x6f, 0xca], "vmovdqu16 ymm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0x0a], "vmovdqu16 ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0x4a, 0x01], "vmovdqu16 ymmword [bp + si * 1 + 0x20]{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0x7f, 0xca], "vmovdqu16 ymm2{k5}, ymm1"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x0a, 0xcc], "vcmpsd k1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0x4a, 0x01, 0xcc], "vcmpsd k1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0x2d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x2d, 0xca], "vcvtsd2si ecx{rd-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x51, 0xca], "vsqrtsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x58, 0xca], "vaddsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x59, 0xca], "vmulsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x5a, 0xca], "vcvtsd2ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x5c, 0xca], "vsubsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x5e, 0xca], "vdivsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x79, 0xca], "vcvtsd2usi ecx{rd-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0x0a], "vcvtuqq2ps xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0x7a, 0xca], "vcvtuqq2ps ymm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0x0a], "vcvtpd2dq xmm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x38, 0xe6, 0xca], "vcvtpd2dq ymm1{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x58, 0xca], "vaddsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x59, 0xca], "vmulsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x5c, 0xca], "vsubsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x5e, 0xca], "vdivsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0x3d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0x0a], "vmovddup zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0x4a, 0x01], "vmovddup zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x12, 0xca], "vmovddup zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0x0a], "vmovdqu16 zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x6f, 0xca], "vmovdqu16 zmm1, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0x0a, 0xcc], "vpshuflw zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x70, 0xca, 0xcc], "vpshuflw zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0x0a], "vcvtuqq2ps ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7a, 0xca], "vcvtuqq2ps ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0x0a], "vmovdqu16 zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0x4a, 0x01], "vmovdqu16 zmmword [bp + si * 1 + 0x40], zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0x7f, 0xca], "vmovdqu16 zmm2, zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0x0a], "vcvtpd2dq ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x48, 0xe6, 0xca], "vcvtpd2dq ymm1, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0x0a], "vmovddup zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0x4a, 0x01], "vmovddup zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x12, 0xca], "vmovddup zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x6f, 0xca], "vmovdqu16 zmm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0x0a], "vmovdqu16 zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0x4a, 0x01], "vmovdqu16 zmmword [bp + si * 1 + 0x40]{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0x7f, 0xca], "vmovdqu16 zmm2{k5}, zmm1"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0x4d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x2d, 0xca], "vcvtsd2si ecx{ru-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x51, 0xca], "vsqrtsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x58, 0xca], "vaddsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x59, 0xca], "vmulsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x5a, 0xca], "vcvtsd2ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x5c, 0xca], "vsubsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x5e, 0xca], "vdivsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x79, 0xca], "vcvtsd2usi ecx{ru-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0x0a], "vcvtuqq2ps ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0x7a, 0xca], "vcvtuqq2ps ymm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0x0a], "vcvtpd2dq ymm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x58, 0xe6, 0xca], "vcvtpd2dq ymm1{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x51, 0xca], "vsqrtsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x58, 0xca], "vaddsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x59, 0xca], "vmulsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x5c, 0xca], "vsubsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x5e, 0xca], "vdivsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0x5d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x2c, 0xca], "vcvttsd2si ecx{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x2d, 0xca], "vcvtsd2si ecx{rz-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x51, 0xca], "vsqrtsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x58, 0xca], "vaddsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x59, 0xca], "vmulsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x5a, 0xca], "vcvtsd2ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x5c, 0xca], "vsubsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x5d, 0xca], "vminsd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x5e, 0xca], "vdivsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x5f, 0xca], "vmaxsd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x78, 0xca], "vcvttsd2usi ecx{sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x79, 0xca], "vcvtsd2usi ecx{rz-sae}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x7a, 0xca], "vcvtuqq2ps ymm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0x7b, 0xca], "vcvtusi2sd xmm1, xmm0, edx"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0xc2, 0xca, 0xcc], "vcmpsd k1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x78, 0xe6, 0xca], "vcvtpd2dq ymm1{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x51, 0xca], "vsqrtsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x58, 0xca], "vaddsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x59, 0xca], "vmulsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x5c, 0xca], "vsubsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x5d, 0xca], "vminsd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x5e, 0xca], "vdivsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x5f, 0xca], "vmaxsd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0xc2, 0xca, 0xcc], "vcmpsd k1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x7d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0x0a], "vmovddup xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0x4a, 0x01], "vmovddup xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x12, 0xca], "vmovddup xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0x0a], "vmovdqu16 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0x4a, 0x01], "vmovdqu16 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x6f, 0xca], "vmovdqu16 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0x0a, 0xcc], "vpshuflw xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x70, 0xca, 0xcc], "vpshuflw xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0x7f, 0xca], "vmovdqu16 xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf1, 0xff, 0x8d, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf1, 0xff, 0x9d, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rne-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x0a], "vmovsd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0x4a, 0x01], "vmovsd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x10, 0xca], "vmovsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x11, 0xca], "vmovsd xmm2{k5}{z}, xmm0, xmm1"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x0a], "vmovddup ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0x4a, 0x01], "vmovddup ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x12, 0xca], "vmovddup ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0x0a], "vsqrtsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0x4a, 0x01], "vsqrtsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0x0a], "vaddsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0x4a, 0x01], "vaddsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x58, 0xca], "vaddsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0x0a], "vmulsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0x4a, 0x01], "vmulsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x59, 0xca], "vmulsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x0a], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0x4a, 0x01], "vcvtsd2ss xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0x0a], "vsubsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0x4a, 0x01], "vsubsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5c, 0xca], "vsubsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0x0a], "vminsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0x4a, 0x01], "vminsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5d, 0xca], "vminsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0x0a], "vdivsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0x4a, 0x01], "vdivsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5e, 0xca], "vdivsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x0a], "vmaxsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0x4a, 0x01], "vmaxsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0x0a], "vmovdqu16 ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0x4a, 0x01], "vmovdqu16 ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x6f, 0xca], "vmovdqu16 ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0x0a, 0xcc], "vpshuflw ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x70, 0xca, 0xcc], "vpshuflw ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x7a, 0xca], "vcvtuqq2ps xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0x7f, 0xca], "vmovdqu16 ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf1, 0xff, 0xad, 0xe6, 0xca], "vcvtpd2dq xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0x0a], "vcvtuqq2ps xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0x0a], "vcvtpd2dq xmm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0x4a, 0x01], "vcvtpd2dq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf1, 0xff, 0xbd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rd-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0x0a], "vmovddup zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0x4a, 0x01], "vmovddup zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x12, 0xca], "vmovddup zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0x0a], "vmovdqu16 zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0x4a, 0x01], "vmovdqu16 zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x6f, 0xca], "vmovdqu16 zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0x0a, 0xcc], "vpshuflw zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshuflw zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x70, 0xca, 0xcc], "vpshuflw zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0x7f, 0xca], "vmovdqu16 zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf1, 0xff, 0xcd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0x0a], "vcvtuqq2ps ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0x4a, 0x01], "vcvtuqq2ps ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0x0a], "vcvtpd2dq ymm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0x4a, 0x01], "vcvtpd2dq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf1, 0xff, 0xdd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{ru-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x51, 0xca], "vsqrtsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x58, 0xca], "vaddsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x59, 0xca], "vmulsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x5a, 0xca], "vcvtsd2ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x5c, 0xca], "vsubsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x5d, 0xca], "vminsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x5e, 0xca], "vdivsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x5f, 0xca], "vmaxsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0x7a, 0xca], "vcvtuqq2ps ymm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf1, 0xff, 0xfd, 0xe6, 0xca], "vcvtpd2dq ymm1{k5}{z}{rz-sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0x0a], "vpermilps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0x4a, 0x01], "vpermilps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x0c, 0xca], "vpermilps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0x0a], "vcvtph2ps xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x13, 0xca], "vcvtph2ps xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0x0a], "vprorvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0x4a, 0x01], "vprorvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x14, 0xca], "vprorvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0x0a], "vprolvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0x4a, 0x01], "vprolvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x15, 0xca], "vprolvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0x0a], "vbroadcastss xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0x4a, 0x01], "vbroadcastss xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x18, 0xca], "vbroadcastss xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0x0a], "vpabsd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0x4a, 0x01], "vpabsd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x1e, 0xca], "vpabsd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0x0a], "vpmovsxdq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x25, 0xca], "vpmovsxdq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0x0a], "vptestmb k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0x4a, 0x01], "vptestmb k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x26, 0xca], "vptestmb k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0x0a], "vptestmd k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0x4a, 0x01], "vptestmd k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x27, 0xca], "vptestmd k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2a, 0x4a, 0x01], "vmovntdqa xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0x4a, 0x01], "vpackusdw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2b, 0xca], "vpackusdw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0x0a], "vscalefps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0x4a, 0x01], "vscalefps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x2c, 0xca], "vscalefps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0x0a], "vpmovzxdq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x35, 0xca], "vpmovzxdq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0x0a], "vpminsd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0x4a, 0x01], "vpminsd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x39, 0xca], "vpminsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0x0a], "vpminud xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0x4a, 0x01], "vpminud xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3b, 0xca], "vpminud xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3d, 0xca], "vpmaxsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0x4a, 0x01], "vpmaxud xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x3f, 0xca], "vpmaxud xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0x0a], "vpmulld xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0x4a, 0x01], "vpmulld xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x40, 0xca], "vpmulld xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0x0a], "vgetexpps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0x4a, 0x01], "vgetexpps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x42, 0xca], "vgetexpps xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0x0a], "vplzcntd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0x4a, 0x01], "vplzcntd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x44, 0xca], "vplzcntd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0x4a, 0x01], "vpsrlvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x45, 0xca], "vpsrlvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0x0a], "vpsravd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0x4a, 0x01], "vpsravd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x46, 0xca], "vpsravd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0x0a], "vpsllvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0x4a, 0x01], "vpsllvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x47, 0xca], "vpsllvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0x0a], "vrcp14ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4c, 0xca], "vrcp14ps xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0x0a], "vrsqrt14ps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x4e, 0xca], "vrsqrt14ps xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0x4a, 0x01], "vpdpbusd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x50, 0xca], "vpdpbusd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0x4a, 0x01], "vpdpbusds xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x51, 0xca], "vpdpbusds xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0x4a, 0x01], "vpdpwssd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x52, 0xca], "vpdpwssd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0x4a, 0x01], "vpdpwssds xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x53, 0xca], "vpdpwssds xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0x0a], "vpopcntb xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0x4a, 0x01], "vpopcntb xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x54, 0xca], "vpopcntb xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0x0a], "vpopcntd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0x4a, 0x01], "vpopcntd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x55, 0xca], "vpopcntd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0x0a], "vpbroadcastd xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x58, 0xca], "vpbroadcastd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0x0a], "vbroadcasti32x2 xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x59, 0xca], "vbroadcasti32x2 xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0x0a], "vpexpandb xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0x4a, 0x01], "vpexpandb xmm1, xmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x62, 0xca], "vpexpandb xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0x0a], "vpcompressb xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0x4a, 0x01], "vpcompressb xmmword [bp + si * 1 + 0x1], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x63, 0xca], "vpcompressb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0x0a], "vpblendmd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0x4a, 0x01], "vpblendmd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x64, 0xca], "vpblendmd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0x0a], "vblendmps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0x4a, 0x01], "vblendmps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x65, 0xca], "vblendmps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0x0a], "vpblendmb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0x4a, 0x01], "vpblendmb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x66, 0xca], "vpblendmb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0x0a], "vpshldvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0x4a, 0x01], "vpshldvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x71, 0xca], "vpshldvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0x4a, 0x01], "vpshrdvd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x73, 0xca], "vpshrdvd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0x0a], "vpermi2b xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0x4a, 0x01], "vpermi2b xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x75, 0xca], "vpermi2b xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0x0a], "vpermi2d xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0x4a, 0x01], "vpermi2d xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x76, 0xca], "vpermi2d xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0x4a, 0x01], "vpermi2ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x77, 0xca], "vpermi2ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0x0a], "vpbroadcastb xmm1, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x78, 0xca], "vpbroadcastb xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0x0a], "vpbroadcastw xmm1, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x79, 0xca], "vpbroadcastw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7a, 0xca], "vpbroadcastb xmm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7b, 0xca], "vpbroadcastw xmm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0x0a], "vpermt2b xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0x4a, 0x01], "vpermt2b xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7d, 0xca], "vpermt2b xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0x4a, 0x01], "vpermt2d xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7e, 0xca], "vpermt2d xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x7f, 0xca], "vpermt2ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0x0a], "vexpandps xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0x4a, 0x01], "vexpandps xmm1, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x88, 0xca], "vexpandps xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0x0a], "vpexpandd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0x4a, 0x01], "vpexpandd xmm1, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x89, 0xca], "vpexpandd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0x0a], "vcompressps xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0x4a, 0x01], "vcompressps xmmword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8a, 0xca], "vcompressps xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0x0a], "vpcompressd xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0x4a, 0x01], "vpcompressd xmmword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8b, 0xca], "vpcompressd xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0x0a], "vpermb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0x4a, 0x01], "vpermb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8d, 0xca], "vpermb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0x0a], "vpshufbitqmb k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x8f, 0xca], "vpshufbitqmb k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x96, 0xca], "vfmaddsub132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x97, 0xca], "vfmsubadd132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x98, 0xca], "vfmadd132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9a, 0xca], "vfmsub132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9c, 0xca], "vfnmadd132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0x9e, 0xca], "vfnmsub132ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa6, 0xca], "vfmaddsub213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa7, 0xca], "vfmsubadd213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xa8, 0xca], "vfmadd213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xaa, 0xca], "vfmsub213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xac, 0xca], "vfnmadd213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xae, 0xca], "vfnmsub213ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb6, 0xca], "vfmaddsub231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb7, 0xca], "vfmsubadd231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xb8, 0xca], "vfmadd231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xba, 0xca], "vfmsub231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbc, 0xca], "vfnmadd231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xbe, 0xca], "vfnmsub231ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0x0a], "vpconflictd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0x4a, 0x01], "vpconflictd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xc4, 0xca], "vpconflictd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0x0a], "vgf2p8mulb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x08, 0xcf, 0xca], "vgf2p8mulb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x0c, 0xca], "vpermilps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x13, 0xca], "vcvtph2ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x14, 0xca], "vprorvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x15, 0xca], "vprolvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0x0a], "vbroadcastss xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0x4a, 0x01], "vbroadcastss xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x18, 0xca], "vbroadcastss xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0x0a], "vpabsd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x1e, 0xca], "vpabsd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x25, 0xca], "vpmovsxdq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0x0a], "vptestmb k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x26, 0xca], "vptestmb k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x27, 0xca], "vptestmd k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2b, 0xca], "vpackusdw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x2c, 0xca], "vscalefps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x35, 0xca], "vpmovzxdq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x39, 0xca], "vpminsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3b, 0xca], "vpminud xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3d, 0xca], "vpmaxsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x3f, 0xca], "vpmaxud xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x40, 0xca], "vpmulld xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0x0a], "vgetexpps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x42, 0xca], "vgetexpps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0x0a], "vplzcntd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x44, 0xca], "vplzcntd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x45, 0xca], "vpsrlvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x46, 0xca], "vpsravd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x47, 0xca], "vpsllvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4c, 0xca], "vrcp14ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x50, 0xca], "vpdpbusd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x51, 0xca], "vpdpbusds xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x52, 0xca], "vpdpwssd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x53, 0xca], "vpdpwssds xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0x0a], "vpopcntb xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0x4a, 0x01], "vpopcntb xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x54, 0xca], "vpopcntb xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0x0a], "vpopcntd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x55, 0xca], "vpopcntd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x58, 0xca], "vpbroadcastd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0x0a], "vpexpandb xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0x4a, 0x01], "vpexpandb xmm1{k5}, xmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x62, 0xca], "vpexpandb xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0x0a], "vpcompressb xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0x4a, 0x01], "vpcompressb xmmword [bp + si * 1 + 0x1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x63, 0xca], "vpcompressb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x64, 0xca], "vpblendmd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x65, 0xca], "vblendmps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0x0a], "vpblendmb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0x4a, 0x01], "vpblendmb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x66, 0xca], "vpblendmb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x71, 0xca], "vpshldvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x73, 0xca], "vpshrdvd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0x0a], "vpermi2b xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0x4a, 0x01], "vpermi2b xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x75, 0xca], "vpermi2b xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x76, 0xca], "vpermi2d xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x77, 0xca], "vpermi2ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1{k5}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x78, 0xca], "vpbroadcastb xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1{k5}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x79, 0xca], "vpbroadcastw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0x0a], "vpermt2b xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0x4a, 0x01], "vpermt2b xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7d, 0xca], "vpermt2b xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7e, 0xca], "vpermt2d xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x7f, 0xca], "vpermt2ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0x0a], "vexpandps xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0x4a, 0x01], "vexpandps xmm1{k5}, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x88, 0xca], "vexpandps xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0x0a], "vpexpandd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0x4a, 0x01], "vpexpandd xmm1{k5}, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x89, 0xca], "vpexpandd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0x0a], "vcompressps xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0x4a, 0x01], "vcompressps xmmword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8a, 0xca], "vcompressps xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0x0a], "vpcompressd xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0x4a, 0x01], "vpcompressd xmmword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8b, 0xca], "vpcompressd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0x0a], "vpermb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0x4a, 0x01], "vpermb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8d, 0xca], "vpermb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x98, 0xca], "vfmadd132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xba, 0xca], "vfmsub231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xc4, 0xca], "vpconflictd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x0d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x0c, 0x0a], "vpermilps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x0c, 0x4a, 0x01], "vpermilps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x14, 0x0a], "vprorvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x14, 0x4a, 0x01], "vprorvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x15, 0x0a], "vprolvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x15, 0x4a, 0x01], "vprolvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x1e, 0x0a], "vpabsd xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x1e, 0x4a, 0x01], "vpabsd xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x27, 0x0a], "vptestmd k1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x27, 0x4a, 0x01], "vptestmd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2b, 0x0a], "vpackusdw xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2b, 0x4a, 0x01], "vpackusdw xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0x0a], "vscalefps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0x4a, 0x01], "vscalefps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2c, 0xca], "vscalefps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x2d, 0xca], "vscalefss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x39, 0x0a], "vpminsd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x39, 0x4a, 0x01], "vpminsd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3b, 0x0a], "vpminud xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3b, 0x4a, 0x01], "vpminud xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3d, 0x0a], "vpmaxsd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3f, 0x0a], "vpmaxud xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x3f, 0x4a, 0x01], "vpmaxud xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x40, 0x0a], "vpmulld xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x40, 0x4a, 0x01], "vpmulld xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x42, 0x0a], "vgetexpps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x42, 0x4a, 0x01], "vgetexpps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x44, 0x0a], "vplzcntd xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x44, 0x4a, 0x01], "vplzcntd xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x45, 0x4a, 0x01], "vpsrlvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x46, 0x0a], "vpsravd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x46, 0x4a, 0x01], "vpsravd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x47, 0x0a], "vpsllvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x47, 0x4a, 0x01], "vpsllvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x4c, 0x0a], "vrcp14ps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x4e, 0x0a], "vrsqrt14ps xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x50, 0x0a], "vpdpbusd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x50, 0x4a, 0x01], "vpdpbusd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x51, 0x0a], "vpdpbusds xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x51, 0x4a, 0x01], "vpdpbusds xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x52, 0x0a], "vpdpwssd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x52, 0x4a, 0x01], "vpdpwssd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x53, 0x0a], "vpdpwssds xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x53, 0x4a, 0x01], "vpdpwssds xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x55, 0x0a], "vpopcntd xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x55, 0x4a, 0x01], "vpopcntd xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x64, 0x0a], "vpblendmd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x64, 0x4a, 0x01], "vpblendmd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x65, 0x0a], "vblendmps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x65, 0x4a, 0x01], "vblendmps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x71, 0x0a], "vpshldvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x71, 0x4a, 0x01], "vpshldvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x73, 0x0a], "vpshrdvd xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x73, 0x4a, 0x01], "vpshrdvd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x76, 0x0a], "vpermi2d xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x76, 0x4a, 0x01], "vpermi2d xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x77, 0x0a], "vpermi2ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x77, 0x4a, 0x01], "vpermi2ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x7e, 0x0a], "vpermt2d xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x7e, 0x4a, 0x01], "vpermt2d xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x7f, 0x0a], "vpermt2ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0x0a], "vfmaddsub132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x96, 0xca], "vfmaddsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0x0a], "vfmsubadd132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x97, 0xca], "vfmsubadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0x0a], "vfmadd132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x98, 0xca], "vfmadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x99, 0xca], "vfmadd132ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0x0a], "vfmsub132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9a, 0xca], "vfmsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9b, 0xca], "vfmsub132ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0x0a], "vfnmadd132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9c, 0xca], "vfnmadd132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9d, 0xca], "vfnmadd132ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0x0a], "vfnmsub132ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9e, 0xca], "vfnmsub132ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0x9f, 0xca], "vfnmsub132ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0x0a], "vfmaddsub213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa6, 0xca], "vfmaddsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0x0a], "vfmsubadd213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa7, 0xca], "vfmsubadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0x0a], "vfmadd213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa8, 0xca], "vfmadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xa9, 0xca], "vfmadd213ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0x0a], "vfmsub213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xaa, 0xca], "vfmsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xab, 0xca], "vfmsub213ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0x0a], "vfnmadd213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xac, 0xca], "vfnmadd213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xad, 0xca], "vfnmadd213ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0x0a], "vfnmsub213ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xae, 0xca], "vfnmsub213ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xaf, 0xca], "vfnmsub213ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0x0a], "vfmaddsub231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb6, 0xca], "vfmaddsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0x0a], "vfmsubadd231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb7, 0xca], "vfmsubadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0x0a], "vfmadd231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb8, 0xca], "vfmadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xb9, 0xca], "vfmadd231ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0x0a], "vfmsub231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xba, 0xca], "vfmsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbb, 0xca], "vfmsub231ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0x0a], "vfnmadd231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbc, 0xca], "vfnmadd231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbd, 0xca], "vfnmadd231ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0x0a], "vfnmsub231ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbe, 0xca], "vfnmsub231ps zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xbf, 0xca], "vfnmsub231ss xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xc4, 0x0a], "vpconflictd xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x18, 0xc4, 0x4a, 0x01], "vpconflictd xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x0c, 0x0a], "vpermilps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x14, 0x0a], "vprorvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x15, 0x0a], "vprolvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x1e, 0x0a], "vpabsd xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x27, 0x0a], "vptestmd k1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2b, 0x0a], "vpackusdw xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0x0a], "vscalefps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2c, 0xca], "vscalefps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x2d, 0xca], "vscalefss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x39, 0x0a], "vpminsd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3b, 0x0a], "vpminud xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3f, 0x0a], "vpmaxud xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x40, 0x0a], "vpmulld xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x42, 0x0a], "vgetexpps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x44, 0x0a], "vplzcntd xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x45, 0x0a], "vpsrlvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x46, 0x0a], "vpsravd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x47, 0x0a], "vpsllvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x50, 0x0a], "vpdpbusd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x51, 0x0a], "vpdpbusds xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x52, 0x0a], "vpdpwssd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x53, 0x0a], "vpdpwssds xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x55, 0x0a], "vpopcntd xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x64, 0x0a], "vpblendmd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x65, 0x0a], "vblendmps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x71, 0x0a], "vpshldvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x73, 0x0a], "vpshrdvd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x76, 0x0a], "vpermi2d xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x77, 0x0a], "vpermi2ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x7e, 0x0a], "vpermt2d xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xc4, 0x0a], "vpconflictd xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x1d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0x0a], "vpermilps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0x4a, 0x01], "vpermilps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x0c, 0xca], "vpermilps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0x0a], "vcvtph2ps ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x13, 0xca], "vcvtph2ps ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0x0a], "vprorvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0x4a, 0x01], "vprorvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x14, 0xca], "vprorvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0x0a], "vprolvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0x4a, 0x01], "vprolvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x15, 0xca], "vprolvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0x0a], "vpermps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0x4a, 0x01], "vpermps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x16, 0xca], "vpermps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0x0a], "vbroadcastss ymm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0x4a, 0x01], "vbroadcastss ymm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x18, 0xca], "vbroadcastss ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0x0a], "vbroadcastf32x2 ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x19, 0xca], "vbroadcastf32x2 ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x1a, 0x0a], "vbroadcastf32x4 ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0x0a], "vpabsd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0x4a, 0x01], "vpabsd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x1e, 0xca], "vpabsd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x0a], "vpmovsxdq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x0a], "vptestmb k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0x4a, 0x01], "vptestmb k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x26, 0xca], "vptestmb k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x0a], "vptestmd k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0x4a, 0x01], "vptestmd k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x27, 0xca], "vptestmd k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2a, 0x4a, 0x01], "vmovntdqa ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0x4a, 0x01], "vpackusdw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2b, 0xca], "vpackusdw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0x0a], "vscalefps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0x4a, 0x01], "vscalefps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2c, 0xca], "vscalefps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0x0a], "vscalefss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0x4a, 0x01], "vscalefss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x2d, 0xca], "vscalefss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0x0a], "vpmovzxdq ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x35, 0xca], "vpmovzxdq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0x0a], "vpermd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0x4a, 0x01], "vpermd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x36, 0xca], "vpermd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0x0a], "vpminsd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0x4a, 0x01], "vpminsd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x39, 0xca], "vpminsd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0x0a], "vpminud ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0x4a, 0x01], "vpminud ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3b, 0xca], "vpminud ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3d, 0xca], "vpmaxsd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0x4a, 0x01], "vpmaxud ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x3f, 0xca], "vpmaxud ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0x0a], "vpmulld ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0x4a, 0x01], "vpmulld ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x40, 0xca], "vpmulld ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0x0a], "vgetexpps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0x4a, 0x01], "vgetexpps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x42, 0xca], "vgetexpps ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x0a], "vgetexpss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0x4a, 0x01], "vgetexpss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x43, 0xca], "vgetexpss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0x0a], "vplzcntd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0x4a, 0x01], "vplzcntd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x44, 0xca], "vplzcntd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0x4a, 0x01], "vpsrlvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x45, 0xca], "vpsrlvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0x0a], "vpsravd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0x4a, 0x01], "vpsravd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x46, 0xca], "vpsravd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0x0a], "vpsllvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0x4a, 0x01], "vpsllvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x47, 0xca], "vpsllvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0x0a], "vrcp14ps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4c, 0xca], "vrcp14ps ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x0a], "vrcp14ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4d, 0xca], "vrcp14ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x0a], "vrsqrt14ps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4e, 0xca], "vrsqrt14ps ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x0a], "vrsqrt14ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x4f, 0xca], "vrsqrt14ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0x4a, 0x01], "vpdpbusd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x50, 0xca], "vpdpbusd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0x4a, 0x01], "vpdpbusds ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x51, 0xca], "vpdpbusds ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0x4a, 0x01], "vpdpwssd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x52, 0xca], "vpdpwssd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0x4a, 0x01], "vpdpwssds ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x53, 0xca], "vpdpwssds ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0x0a], "vpopcntb ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0x4a, 0x01], "vpopcntb ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x54, 0xca], "vpopcntb ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0x0a], "vpopcntd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0x4a, 0x01], "vpopcntd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x55, 0xca], "vpopcntd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0x0a], "vpbroadcastd ymm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x58, 0xca], "vpbroadcastd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0x0a], "vbroadcasti32x2 ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x59, 0xca], "vbroadcasti32x2 ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x5a, 0x0a], "vbroadcasti32x4 ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0x0a], "vpexpandb ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0x4a, 0x01], "vpexpandb ymm1, ymmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x62, 0xca], "vpexpandb ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x0a], "vpcompressb ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0x4a, 0x01], "vpcompressb ymmword [bp + si * 1 + 0x1], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x63, 0xca], "vpcompressb ymm2, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0x0a], "vpblendmd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0x4a, 0x01], "vpblendmd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x64, 0xca], "vpblendmd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0x0a], "vblendmps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0x4a, 0x01], "vblendmps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x65, 0xca], "vblendmps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0x0a], "vpblendmb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0x4a, 0x01], "vpblendmb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x66, 0xca], "vpblendmb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0x0a], "vpshldvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0x4a, 0x01], "vpshldvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x71, 0xca], "vpshldvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0x4a, 0x01], "vpshrdvd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x73, 0xca], "vpshrdvd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0x0a], "vpermi2b ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0x4a, 0x01], "vpermi2b ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x75, 0xca], "vpermi2b ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0x0a], "vpermi2d ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0x4a, 0x01], "vpermi2d ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x76, 0xca], "vpermi2d ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0x4a, 0x01], "vpermi2ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x77, 0xca], "vpermi2ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x0a], "vpbroadcastb ymm1, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x78, 0xca], "vpbroadcastb ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0x0a], "vpbroadcastw ymm1, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x79, 0xca], "vpbroadcastw ymm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7a, 0xca], "vpbroadcastb ymm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7b, 0xca], "vpbroadcastw ymm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0x0a], "vpermt2b ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0x4a, 0x01], "vpermt2b ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7d, 0xca], "vpermt2b ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0x4a, 0x01], "vpermt2d ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7e, 0xca], "vpermt2d ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x7f, 0xca], "vpermt2ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0x0a], "vexpandps ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0x4a, 0x01], "vexpandps ymm1, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x88, 0xca], "vexpandps ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0x0a], "vpexpandd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0x4a, 0x01], "vpexpandd ymm1, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x89, 0xca], "vpexpandd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0x0a], "vcompressps ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0x4a, 0x01], "vcompressps ymmword [bp + si * 1 + 0x4], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8a, 0xca], "vcompressps ymm2, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0x0a], "vpcompressd ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0x4a, 0x01], "vpcompressd ymmword [bp + si * 1 + 0x4], ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8b, 0xca], "vpcompressd ymm2, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0x0a], "vpermb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0x4a, 0x01], "vpermb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8d, 0xca], "vpermb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0x0a], "vpshufbitqmb k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x8f, 0xca], "vpshufbitqmb k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x96, 0xca], "vfmaddsub132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x97, 0xca], "vfmsubadd132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x98, 0xca], "vfmadd132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x0a], "vfmadd132ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x99, 0xca], "vfmadd132ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9a, 0xca], "vfmsub132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0x0a], "vfmsub132ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9b, 0xca], "vfmsub132ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9c, 0xca], "vfnmadd132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0x0a], "vfnmadd132ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9d, 0xca], "vfnmadd132ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9e, 0xca], "vfnmsub132ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0x0a], "vfnmsub132ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0x9f, 0xca], "vfnmsub132ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa6, 0xca], "vfmaddsub213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa7, 0xca], "vfmsubadd213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa8, 0xca], "vfmadd213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0x0a], "vfmadd213ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xa9, 0xca], "vfmadd213ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaa, 0xca], "vfmsub213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0x0a], "vfmsub213ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xab, 0xca], "vfmsub213ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xac, 0xca], "vfnmadd213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0x0a], "vfnmadd213ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xad, 0xca], "vfnmadd213ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xae, 0xca], "vfnmsub213ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0x0a], "vfnmsub213ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xaf, 0xca], "vfnmsub213ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb6, 0xca], "vfmaddsub231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb7, 0xca], "vfmsubadd231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb8, 0xca], "vfmadd231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0x0a], "vfmadd231ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xb9, 0xca], "vfmadd231ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xba, 0xca], "vfmsub231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0x0a], "vfmsub231ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbb, 0xca], "vfmsub231ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbc, 0xca], "vfnmadd231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0x0a], "vfnmadd231ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbd, 0xca], "vfnmadd231ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbe, 0xca], "vfnmsub231ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0x0a], "vfnmsub231ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xbf, 0xca], "vfnmsub231ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0x0a], "vpconflictd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0x4a, 0x01], "vpconflictd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xc4, 0xca], "vpconflictd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0x0a], "vrcp28ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcb, 0xca], "vrcp28ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0x0a], "vrsqrt28ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcd, 0xca], "vrsqrt28ss xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0x0a], "vgf2p8mulb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x28, 0xcf, 0xca], "vgf2p8mulb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x0c, 0xca], "vpermilps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0x0a], "vcvtph2ps ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x13, 0xca], "vcvtph2ps ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x14, 0xca], "vprorvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x15, 0xca], "vprolvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x16, 0xca], "vpermps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0x0a], "vbroadcastss ymm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0x4a, 0x01], "vbroadcastss ymm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x18, 0xca], "vbroadcastss ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0x0a], "vpabsd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x1e, 0xca], "vpabsd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x0a], "vpmovsxdq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x25, 0xca], "vpmovsxdq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x0a], "vptestmb k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x26, 0xca], "vptestmb k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x27, 0xca], "vptestmd k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2b, 0xca], "vpackusdw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2c, 0xca], "vscalefps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0x0a], "vscalefss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0x4a, 0x01], "vscalefss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x2d, 0xca], "vscalefss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0x0a], "vpmovzxdq ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x35, 0xca], "vpmovzxdq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x36, 0xca], "vpermd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x39, 0xca], "vpminsd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3b, 0xca], "vpminud ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3d, 0xca], "vpmaxsd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x3f, 0xca], "vpmaxud ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x40, 0xca], "vpmulld ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0x0a], "vgetexpps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x42, 0xca], "vgetexpps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0x0a], "vgetexpss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0x4a, 0x01], "vgetexpss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x43, 0xca], "vgetexpss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0x0a], "vplzcntd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x44, 0xca], "vplzcntd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x45, 0xca], "vpsrlvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x46, 0xca], "vpsravd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x47, 0xca], "vpsllvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4c, 0xca], "vrcp14ps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x0a], "vrcp14ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4d, 0xca], "vrcp14ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x50, 0xca], "vpdpbusd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x51, 0xca], "vpdpbusds ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x52, 0xca], "vpdpwssd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x53, 0xca], "vpdpwssds ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0x0a], "vpopcntb ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0x4a, 0x01], "vpopcntb ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x54, 0xca], "vpopcntb ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0x0a], "vpopcntd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x55, 0xca], "vpopcntd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0x0a], "vpbroadcastd ymm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x58, 0xca], "vpbroadcastd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0x0a], "vpexpandb ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0x4a, 0x01], "vpexpandb ymm1{k5}, ymmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x62, 0xca], "vpexpandb ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x0a], "vpcompressb ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0x4a, 0x01], "vpcompressb ymmword [bp + si * 1 + 0x1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x63, 0xca], "vpcompressb ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x64, 0xca], "vpblendmd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x65, 0xca], "vblendmps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0x0a], "vpblendmb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0x4a, 0x01], "vpblendmb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x66, 0xca], "vpblendmb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x71, 0xca], "vpshldvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x73, 0xca], "vpshrdvd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0x0a], "vpermi2b ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0x4a, 0x01], "vpermi2b ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x75, 0xca], "vpermi2b ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x76, 0xca], "vpermi2d ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x77, 0xca], "vpermi2ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x0a], "vpbroadcastb ymm1{k5}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1{k5}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x78, 0xca], "vpbroadcastb ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0x0a], "vpbroadcastw ymm1{k5}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1{k5}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x79, 0xca], "vpbroadcastw ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7a, 0xca], "vpbroadcastb ymm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7b, 0xca], "vpbroadcastw ymm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0x0a], "vpermt2b ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0x4a, 0x01], "vpermt2b ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7d, 0xca], "vpermt2b ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7e, 0xca], "vpermt2d ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x7f, 0xca], "vpermt2ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0x0a], "vexpandps ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0x4a, 0x01], "vexpandps ymm1{k5}, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x88, 0xca], "vexpandps ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0x0a], "vpexpandd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0x4a, 0x01], "vpexpandd ymm1{k5}, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x89, 0xca], "vpexpandd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0x0a], "vcompressps ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0x4a, 0x01], "vcompressps ymmword [bp + si * 1 + 0x4]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8a, 0xca], "vcompressps ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0x0a], "vpcompressd ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0x4a, 0x01], "vpcompressd ymmword [bp + si * 1 + 0x4]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8b, 0xca], "vpcompressd ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0x0a], "vpermb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0x4a, 0x01], "vpermb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8d, 0xca], "vpermb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x98, 0xca], "vfmadd132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x0a], "vfmadd132ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x99, 0xca], "vfmadd132ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9a, 0xca], "vfmsub132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa8, 0xca], "vfmadd213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaa, 0xca], "vfmsub213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0x0a], "vfmsub213ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xab, 0xca], "vfmsub213ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xac, 0xca], "vfnmadd213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xae, 0xca], "vfnmsub213ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb8, 0xca], "vfmadd231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xba, 0xca], "vfmsub231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xc4, 0xca], "vpconflictd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0x0a], "vrcp28ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcb, 0xca], "vrcp28ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x2d, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x0c, 0x0a], "vpermilps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x0c, 0x4a, 0x01], "vpermilps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x0a], "vprorvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x14, 0x4a, 0x01], "vprorvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x15, 0x0a], "vprolvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x15, 0x4a, 0x01], "vprolvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x16, 0x0a], "vpermps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x16, 0x4a, 0x01], "vpermps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x1e, 0x0a], "vpabsd ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x1e, 0x4a, 0x01], "vpabsd ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x0a], "vptestmd k1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x27, 0x4a, 0x01], "vptestmd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2b, 0x4a, 0x01], "vpackusdw ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0x0a], "vscalefps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0x4a, 0x01], "vscalefps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2c, 0xca], "vscalefps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x2d, 0xca], "vscalefss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x36, 0x0a], "vpermd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x36, 0x4a, 0x01], "vpermd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x39, 0x0a], "vpminsd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x39, 0x4a, 0x01], "vpminsd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3b, 0x0a], "vpminud ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3b, 0x4a, 0x01], "vpminud ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3d, 0x0a], "vpmaxsd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3f, 0x0a], "vpmaxud ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x3f, 0x4a, 0x01], "vpmaxud ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x40, 0x0a], "vpmulld ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x40, 0x4a, 0x01], "vpmulld ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x42, 0x0a], "vgetexpps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x42, 0x4a, 0x01], "vgetexpps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x44, 0x0a], "vplzcntd ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x44, 0x4a, 0x01], "vplzcntd ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x45, 0x4a, 0x01], "vpsrlvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x46, 0x0a], "vpsravd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x46, 0x4a, 0x01], "vpsravd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x47, 0x0a], "vpsllvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x47, 0x4a, 0x01], "vpsllvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x4c, 0x0a], "vrcp14ps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x4e, 0x0a], "vrsqrt14ps ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x50, 0x0a], "vpdpbusd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x50, 0x4a, 0x01], "vpdpbusd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x51, 0x0a], "vpdpbusds ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x51, 0x4a, 0x01], "vpdpbusds ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x52, 0x0a], "vpdpwssd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x52, 0x4a, 0x01], "vpdpwssd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x53, 0x0a], "vpdpwssds ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x53, 0x4a, 0x01], "vpdpwssds ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x55, 0x0a], "vpopcntd ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x55, 0x4a, 0x01], "vpopcntd ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x64, 0x0a], "vpblendmd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x64, 0x4a, 0x01], "vpblendmd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x65, 0x0a], "vblendmps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x65, 0x4a, 0x01], "vblendmps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x71, 0x0a], "vpshldvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x71, 0x4a, 0x01], "vpshldvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x73, 0x0a], "vpshrdvd ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x73, 0x4a, 0x01], "vpshrdvd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x76, 0x0a], "vpermi2d ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x76, 0x4a, 0x01], "vpermi2d ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x77, 0x0a], "vpermi2ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x77, 0x4a, 0x01], "vpermi2ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x7e, 0x0a], "vpermt2d ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x7e, 0x4a, 0x01], "vpermt2d ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x7f, 0x0a], "vpermt2ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0x0a], "vfmaddsub132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x96, 0xca], "vfmaddsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0x0a], "vfmsubadd132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x97, 0xca], "vfmsubadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0x0a], "vfmadd132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x98, 0xca], "vfmadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x99, 0xca], "vfmadd132ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0x0a], "vfmsub132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9a, 0xca], "vfmsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9b, 0xca], "vfmsub132ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0x0a], "vfnmadd132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9c, 0xca], "vfnmadd132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9d, 0xca], "vfnmadd132ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0x0a], "vfnmsub132ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9e, 0xca], "vfnmsub132ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0x9f, 0xca], "vfnmsub132ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0x0a], "vfmaddsub213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa6, 0xca], "vfmaddsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0x0a], "vfmsubadd213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa7, 0xca], "vfmsubadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0x0a], "vfmadd213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa8, 0xca], "vfmadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xa9, 0xca], "vfmadd213ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0x0a], "vfmsub213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xaa, 0xca], "vfmsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xab, 0xca], "vfmsub213ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0x0a], "vfnmadd213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xac, 0xca], "vfnmadd213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xad, 0xca], "vfnmadd213ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0x0a], "vfnmsub213ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xae, 0xca], "vfnmsub213ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xaf, 0xca], "vfnmsub213ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0x0a], "vfmaddsub231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb6, 0xca], "vfmaddsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0x0a], "vfmsubadd231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb7, 0xca], "vfmsubadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0x0a], "vfmadd231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb8, 0xca], "vfmadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xb9, 0xca], "vfmadd231ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0x0a], "vfmsub231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xba, 0xca], "vfmsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbb, 0xca], "vfmsub231ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0x0a], "vfnmadd231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbc, 0xca], "vfnmadd231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbd, 0xca], "vfnmadd231ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0x0a], "vfnmsub231ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbe, 0xca], "vfnmsub231ps zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xbf, 0xca], "vfnmsub231ss xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xc4, 0x0a], "vpconflictd ymm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x38, 0xc4, 0x4a, 0x01], "vpconflictd ymm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x0c, 0x0a], "vpermilps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x0a], "vprorvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x15, 0x0a], "vprolvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x16, 0x0a], "vpermps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x1e, 0x0a], "vpabsd ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x0a], "vptestmd k1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2b, 0x0a], "vpackusdw ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0x0a], "vscalefps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2c, 0xca], "vscalefps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x2d, 0xca], "vscalefss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x36, 0x0a], "vpermd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x39, 0x0a], "vpminsd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3b, 0x0a], "vpminud ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3d, 0x0a], "vpmaxsd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3f, 0x0a], "vpmaxud ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x40, 0x0a], "vpmulld ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x42, 0x0a], "vgetexpps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x44, 0x0a], "vplzcntd ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x45, 0x0a], "vpsrlvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x46, 0x0a], "vpsravd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x47, 0x0a], "vpsllvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x4c, 0x0a], "vrcp14ps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x50, 0x0a], "vpdpbusd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x51, 0x0a], "vpdpbusds ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x52, 0x0a], "vpdpwssd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x53, 0x0a], "vpdpwssds ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x55, 0x0a], "vpopcntd ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x64, 0x0a], "vpblendmd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x65, 0x0a], "vblendmps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x71, 0x0a], "vpshldvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x73, 0x0a], "vpshrdvd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x76, 0x0a], "vpermi2d ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x77, 0x0a], "vpermi2ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x7e, 0x0a], "vpermt2d ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x7f, 0x0a], "vpermt2ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0x0a], "vfmadd132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0x0a], "vfmsub231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xc4, 0x0a], "vpconflictd ymm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x3d, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0x0a], "vpermilps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0x4a, 0x01], "vpermilps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x0c, 0xca], "vpermilps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0x0a], "vcvtph2ps zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x13, 0xca], "vcvtph2ps zmm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0x0a], "vprorvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0x4a, 0x01], "vprorvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x14, 0xca], "vprorvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0x0a], "vprolvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0x4a, 0x01], "vprolvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x15, 0xca], "vprolvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0x0a], "vpermps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0x4a, 0x01], "vpermps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x16, 0xca], "vpermps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0x0a], "vbroadcastss zmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0x4a, 0x01], "vbroadcastss zmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x18, 0xca], "vbroadcastss zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0x0a], "vbroadcastf32x2 zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x19, 0xca], "vbroadcastf32x2 zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x0a], "vbroadcastf32x4 zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x0a], "vbroadcastf32x8 zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0x0a], "vpabsd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0x4a, 0x01], "vpabsd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x1e, 0xca], "vpabsd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0x0a], "vpmovsxdq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x25, 0xca], "vpmovsxdq zmm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0x0a], "vptestmb k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0x4a, 0x01], "vptestmb k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x26, 0xca], "vptestmb k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0x0a], "vptestmd k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0x4a, 0x01], "vptestmd k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x27, 0xca], "vptestmd k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x0a], "vmovntdqa zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2a, 0x4a, 0x01], "vmovntdqa zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0x4a, 0x01], "vpackusdw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2b, 0xca], "vpackusdw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0x0a], "vscalefps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0x4a, 0x01], "vscalefps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x2c, 0xca], "vscalefps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0x0a], "vpmovzxdq zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x35, 0xca], "vpmovzxdq zmm1, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0x0a], "vpermd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0x4a, 0x01], "vpermd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x36, 0xca], "vpermd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0x0a], "vpminsd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0x4a, 0x01], "vpminsd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x39, 0xca], "vpminsd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0x0a], "vpminud zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0x4a, 0x01], "vpminud zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3b, 0xca], "vpminud zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3d, 0xca], "vpmaxsd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0x4a, 0x01], "vpmaxud zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x3f, 0xca], "vpmaxud zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0x0a], "vpmulld zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0x4a, 0x01], "vpmulld zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x40, 0xca], "vpmulld zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0x0a], "vgetexpps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0x4a, 0x01], "vgetexpps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x42, 0xca], "vgetexpps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0x0a], "vplzcntd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0x4a, 0x01], "vplzcntd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x44, 0xca], "vplzcntd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0x4a, 0x01], "vpsrlvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x45, 0xca], "vpsrlvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0x0a], "vpsravd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0x4a, 0x01], "vpsravd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x46, 0xca], "vpsravd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0x0a], "vpsllvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0x4a, 0x01], "vpsllvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x47, 0xca], "vpsllvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0x0a], "vrcp14ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4c, 0xca], "vrcp14ps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0x0a], "vrsqrt14ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x4e, 0xca], "vrsqrt14ps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0x4a, 0x01], "vpdpbusd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x50, 0xca], "vpdpbusd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0x4a, 0x01], "vpdpbusds zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x51, 0xca], "vpdpbusds zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0x4a, 0x01], "vpdpwssd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x52, 0xca], "vpdpwssd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0x4a, 0x01], "vpdpwssds zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x53, 0xca], "vpdpwssds zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0x0a], "vpopcntb zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0x4a, 0x01], "vpopcntb zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x54, 0xca], "vpopcntb zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0x0a], "vpopcntd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0x4a, 0x01], "vpopcntd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x55, 0xca], "vpopcntd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0x0a], "vpbroadcastd zmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x58, 0xca], "vpbroadcastd zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0x0a], "vbroadcasti32x2 zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x59, 0xca], "vbroadcasti32x2 zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x0a], "vbroadcasti32x4 zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x0a], "vbroadcasti32x8 zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0x0a], "vpexpandb zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0x4a, 0x01], "vpexpandb zmm1, zmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x62, 0xca], "vpexpandb zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0x0a], "vpcompressb zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0x4a, 0x01], "vpcompressb zmmword [bp + si * 1 + 0x1], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x63, 0xca], "vpcompressb zmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0x0a], "vpblendmd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0x4a, 0x01], "vpblendmd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x64, 0xca], "vpblendmd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0x0a], "vblendmps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0x4a, 0x01], "vblendmps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x65, 0xca], "vblendmps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0x0a], "vpblendmb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0x4a, 0x01], "vpblendmb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x66, 0xca], "vpblendmb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0x0a], "vpshldvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0x4a, 0x01], "vpshldvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x71, 0xca], "vpshldvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0x4a, 0x01], "vpshrdvd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x73, 0xca], "vpshrdvd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0x0a], "vpermi2b zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0x4a, 0x01], "vpermi2b zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x75, 0xca], "vpermi2b zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0x0a], "vpermi2d zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0x4a, 0x01], "vpermi2d zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x76, 0xca], "vpermi2d zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0x4a, 0x01], "vpermi2ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x77, 0xca], "vpermi2ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0x0a], "vpbroadcastb zmm1, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x78, 0xca], "vpbroadcastb zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0x0a], "vpbroadcastw zmm1, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x79, 0xca], "vpbroadcastw zmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7a, 0xca], "vpbroadcastb zmm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7b, 0xca], "vpbroadcastw zmm1, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0x0a], "vpermt2b zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0x4a, 0x01], "vpermt2b zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7d, 0xca], "vpermt2b zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0x4a, 0x01], "vpermt2d zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7e, 0xca], "vpermt2d zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x7f, 0xca], "vpermt2ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0x0a], "vexpandps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0x4a, 0x01], "vexpandps zmm1, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x88, 0xca], "vexpandps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0x0a], "vpexpandd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0x4a, 0x01], "vpexpandd zmm1, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x89, 0xca], "vpexpandd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x0a], "vcompressps zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0x4a, 0x01], "vcompressps zmmword [bp + si * 1 + 0x4], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8a, 0xca], "vcompressps zmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x0a], "vpcompressd zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0x4a, 0x01], "vpcompressd zmmword [bp + si * 1 + 0x4], zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8b, 0xca], "vpcompressd zmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0x0a], "vpermb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0x4a, 0x01], "vpermb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8d, 0xca], "vpermb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0x0a], "vpshufbitqmb k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x8f, 0xca], "vpshufbitqmb k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x96, 0xca], "vfmaddsub132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x97, 0xca], "vfmsubadd132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x98, 0xca], "vfmadd132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9a, 0xca], "vfmsub132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9c, 0xca], "vfnmadd132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0x9e, 0xca], "vfnmsub132ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa6, 0xca], "vfmaddsub213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa7, 0xca], "vfmsubadd213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xa8, 0xca], "vfmadd213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xaa, 0xca], "vfmsub213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xac, 0xca], "vfnmadd213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xae, 0xca], "vfnmsub213ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb6, 0xca], "vfmaddsub231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb7, 0xca], "vfmsubadd231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xb8, 0xca], "vfmadd231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xba, 0xca], "vfmsub231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbc, 0xca], "vfnmadd231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xbe, 0xca], "vfnmsub231ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0x0a], "vpconflictd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0x4a, 0x01], "vpconflictd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc4, 0xca], "vpconflictd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0x0a], "vexp2ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0x4a, 0x01], "vexp2ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xc8, 0xca], "vexp2ps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0x0a], "vrcp28ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0x4a, 0x01], "vrcp28ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xca, 0xca], "vrcp28ps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0x0a], "vrsqrt28ps zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcc, 0xca], "vrsqrt28ps zmm1, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0x0a], "vgf2p8mulb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x48, 0xcf, 0xca], "vgf2p8mulb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x0c, 0xca], "vpermilps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0x0a], "vcvtph2ps zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x13, 0xca], "vcvtph2ps zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x14, 0xca], "vprorvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x15, 0xca], "vprolvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x16, 0xca], "vpermps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0x0a], "vbroadcastss zmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0x4a, 0x01], "vbroadcastss zmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x18, 0xca], "vbroadcastss zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0x0a], "vpabsd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x1e, 0xca], "vpabsd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0x0a], "vpmovsxdq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x25, 0xca], "vpmovsxdq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0x0a], "vptestmb k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0x4a, 0x01], "vptestmb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x26, 0xca], "vptestmb k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x27, 0xca], "vptestmd k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2b, 0xca], "vpackusdw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x2c, 0xca], "vscalefps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0x0a], "vpmovzxdq zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x35, 0xca], "vpmovzxdq zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x36, 0xca], "vpermd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x39, 0xca], "vpminsd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3b, 0xca], "vpminud zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3d, 0xca], "vpmaxsd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x3f, 0xca], "vpmaxud zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x40, 0xca], "vpmulld zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0x0a], "vgetexpps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x42, 0xca], "vgetexpps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0x0a], "vplzcntd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x44, 0xca], "vplzcntd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x45, 0xca], "vpsrlvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x46, 0xca], "vpsravd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x47, 0xca], "vpsllvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4c, 0xca], "vrcp14ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x50, 0xca], "vpdpbusd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x51, 0xca], "vpdpbusds zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x52, 0xca], "vpdpwssd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x53, 0xca], "vpdpwssds zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0x0a], "vpopcntb zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0x4a, 0x01], "vpopcntb zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x54, 0xca], "vpopcntb zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0x0a], "vpopcntd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x55, 0xca], "vpopcntd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0x0a], "vpbroadcastd zmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x58, 0xca], "vpbroadcastd zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0x0a], "vpexpandb zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0x4a, 0x01], "vpexpandb zmm1{k5}, zmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x62, 0xca], "vpexpandb zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0x0a], "vpcompressb zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0x4a, 0x01], "vpcompressb zmmword [bp + si * 1 + 0x1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x63, 0xca], "vpcompressb zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x64, 0xca], "vpblendmd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x65, 0xca], "vblendmps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0x0a], "vpblendmb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0x4a, 0x01], "vpblendmb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x66, 0xca], "vpblendmb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x71, 0xca], "vpshldvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x73, 0xca], "vpshrdvd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0x0a], "vpermi2b zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0x4a, 0x01], "vpermi2b zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x75, 0xca], "vpermi2b zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x76, 0xca], "vpermi2d zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x77, 0xca], "vpermi2ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0x0a], "vpbroadcastb zmm1{k5}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1{k5}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x78, 0xca], "vpbroadcastb zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0x0a], "vpbroadcastw zmm1{k5}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1{k5}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x79, 0xca], "vpbroadcastw zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7a, 0xca], "vpbroadcastb zmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7b, 0xca], "vpbroadcastw zmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0x0a], "vpermt2b zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0x4a, 0x01], "vpermt2b zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7d, 0xca], "vpermt2b zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7e, 0xca], "vpermt2d zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x7f, 0xca], "vpermt2ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0x0a], "vexpandps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0x4a, 0x01], "vexpandps zmm1{k5}, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x88, 0xca], "vexpandps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0x0a], "vpexpandd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0x4a, 0x01], "vpexpandd zmm1{k5}, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x89, 0xca], "vpexpandd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0x0a], "vcompressps zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0x4a, 0x01], "vcompressps zmmword [bp + si * 1 + 0x4]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8a, 0xca], "vcompressps zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0x0a], "vpcompressd zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0x4a, 0x01], "vpcompressd zmmword [bp + si * 1 + 0x4]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8b, 0xca], "vpcompressd zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0x0a], "vpermb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0x4a, 0x01], "vpermb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8d, 0xca], "vpermb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0x0a], "vpshufbitqmb k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0x4a, 0x01], "vpshufbitqmb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x8f, 0xca], "vpshufbitqmb k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x98, 0xca], "vfmadd132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xba, 0xca], "vfmsub231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc4, 0xca], "vpconflictd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xc8, 0xca], "vexp2ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xca, 0xca], "vrcp28ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0x4d, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x0c, 0x0a], "vpermilps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x0c, 0x4a, 0x01], "vpermilps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x14, 0x0a], "vprorvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x14, 0x4a, 0x01], "vprorvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x15, 0x0a], "vprolvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x15, 0x4a, 0x01], "vprolvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x16, 0x0a], "vpermps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x16, 0x4a, 0x01], "vpermps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x1e, 0x0a], "vpabsd zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x1e, 0x4a, 0x01], "vpabsd zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x27, 0x0a], "vptestmd k1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x27, 0x4a, 0x01], "vptestmd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2b, 0x0a], "vpackusdw zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2b, 0x4a, 0x01], "vpackusdw zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0x0a], "vscalefps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0x4a, 0x01], "vscalefps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2c, 0xca], "vscalefps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x2d, 0xca], "vscalefss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x36, 0x0a], "vpermd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x36, 0x4a, 0x01], "vpermd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x39, 0x0a], "vpminsd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x39, 0x4a, 0x01], "vpminsd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3b, 0x0a], "vpminud zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3b, 0x4a, 0x01], "vpminud zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3d, 0x0a], "vpmaxsd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3f, 0x0a], "vpmaxud zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x3f, 0x4a, 0x01], "vpmaxud zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x40, 0x0a], "vpmulld zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x40, 0x4a, 0x01], "vpmulld zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x42, 0x0a], "vgetexpps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x42, 0x4a, 0x01], "vgetexpps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x44, 0x0a], "vplzcntd zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x44, 0x4a, 0x01], "vplzcntd zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x45, 0x0a], "vpsrlvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x45, 0x4a, 0x01], "vpsrlvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x46, 0x0a], "vpsravd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x46, 0x4a, 0x01], "vpsravd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x47, 0x0a], "vpsllvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x47, 0x4a, 0x01], "vpsllvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x4c, 0x0a], "vrcp14ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x4e, 0x0a], "vrsqrt14ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x50, 0x0a], "vpdpbusd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x50, 0x4a, 0x01], "vpdpbusd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x51, 0x0a], "vpdpbusds zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x51, 0x4a, 0x01], "vpdpbusds zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x52, 0x0a], "vpdpwssd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x52, 0x4a, 0x01], "vpdpwssd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x53, 0x0a], "vpdpwssds zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x53, 0x4a, 0x01], "vpdpwssds zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x55, 0x0a], "vpopcntd zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x55, 0x4a, 0x01], "vpopcntd zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x64, 0x0a], "vpblendmd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x64, 0x4a, 0x01], "vpblendmd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x65, 0x0a], "vblendmps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x65, 0x4a, 0x01], "vblendmps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x71, 0x0a], "vpshldvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x71, 0x4a, 0x01], "vpshldvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x73, 0x0a], "vpshrdvd zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x73, 0x4a, 0x01], "vpshrdvd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x76, 0x0a], "vpermi2d zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x76, 0x4a, 0x01], "vpermi2d zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x77, 0x0a], "vpermi2ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x77, 0x4a, 0x01], "vpermi2ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x7e, 0x0a], "vpermt2d zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x7e, 0x4a, 0x01], "vpermt2d zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x7f, 0x0a], "vpermt2ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0x0a], "vfmaddsub132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x96, 0xca], "vfmaddsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0x0a], "vfmsubadd132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x97, 0xca], "vfmsubadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0x0a], "vfmadd132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x98, 0xca], "vfmadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x99, 0xca], "vfmadd132ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0x0a], "vfmsub132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9a, 0xca], "vfmsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9b, 0xca], "vfmsub132ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0x0a], "vfnmadd132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9c, 0xca], "vfnmadd132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9d, 0xca], "vfnmadd132ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0x0a], "vfnmsub132ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9e, 0xca], "vfnmsub132ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0x9f, 0xca], "vfnmsub132ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0x0a], "vfmaddsub213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa6, 0xca], "vfmaddsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0x0a], "vfmsubadd213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa7, 0xca], "vfmsubadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0x0a], "vfmadd213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa8, 0xca], "vfmadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xa9, 0xca], "vfmadd213ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0x0a], "vfmsub213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xaa, 0xca], "vfmsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xab, 0xca], "vfmsub213ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0x0a], "vfnmadd213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xac, 0xca], "vfnmadd213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xad, 0xca], "vfnmadd213ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0x0a], "vfnmsub213ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xae, 0xca], "vfnmsub213ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xaf, 0xca], "vfnmsub213ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0x0a], "vfmaddsub231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb6, 0xca], "vfmaddsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0x0a], "vfmsubadd231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb7, 0xca], "vfmsubadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0x0a], "vfmadd231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb8, 0xca], "vfmadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xb9, 0xca], "vfmadd231ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0x0a], "vfmsub231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xba, 0xca], "vfmsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbb, 0xca], "vfmsub231ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0x0a], "vfnmadd231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbc, 0xca], "vfnmadd231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbd, 0xca], "vfnmadd231ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0x0a], "vfnmsub231ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbe, 0xca], "vfnmsub231ps zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xbf, 0xca], "vfnmsub231ss xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xc4, 0x0a], "vpconflictd zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xc4, 0x4a, 0x01], "vpconflictd zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xc8, 0x0a], "vexp2ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xc8, 0x4a, 0x01], "vexp2ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xca, 0x0a], "vrcp28ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xca, 0x4a, 0x01], "vrcp28ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xcc, 0x0a], "vrsqrt28ps zmm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x58, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x0c, 0x0a], "vpermilps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x14, 0x0a], "vprorvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x15, 0x0a], "vprolvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x16, 0x0a], "vpermps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x1e, 0x0a], "vpabsd zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x27, 0x0a], "vptestmd k1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x27, 0x4a, 0x01], "vptestmd k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2b, 0x0a], "vpackusdw zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0x0a], "vscalefps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2c, 0xca], "vscalefps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x2d, 0xca], "vscalefss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x36, 0x0a], "vpermd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x39, 0x0a], "vpminsd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3b, 0x0a], "vpminud zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3d, 0x0a], "vpmaxsd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3f, 0x0a], "vpmaxud zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x40, 0x0a], "vpmulld zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x42, 0x0a], "vgetexpps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x44, 0x0a], "vplzcntd zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x45, 0x0a], "vpsrlvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x46, 0x0a], "vpsravd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x47, 0x0a], "vpsllvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x4c, 0x0a], "vrcp14ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x50, 0x0a], "vpdpbusd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x51, 0x0a], "vpdpbusds zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x52, 0x0a], "vpdpwssd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x53, 0x0a], "vpdpwssds zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x55, 0x0a], "vpopcntd zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x64, 0x0a], "vpblendmd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x65, 0x0a], "vblendmps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x71, 0x0a], "vpshldvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x73, 0x0a], "vpshrdvd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x76, 0x0a], "vpermi2d zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x77, 0x0a], "vpermi2ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x7e, 0x0a], "vpermt2d zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x7f, 0x0a], "vpermt2ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0x0a], "vfmadd132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0x0a], "vfmsub231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xc4, 0x0a], "vpconflictd zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xc8, 0x0a], "vexp2ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xca, 0x0a], "vrcp28ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x5d, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x13, 0xca], "vcvtph2ps zmm1{sae}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x2c, 0xca], "vscalefps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x2d, 0xca], "vscalefss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x42, 0xca], "vgetexpps zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x43, 0xca], "vgetexpss xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x96, 0xca], "vfmaddsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x97, 0xca], "vfmsubadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x98, 0xca], "vfmadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x99, 0xca], "vfmadd132ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9a, 0xca], "vfmsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9b, 0xca], "vfmsub132ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9c, 0xca], "vfnmadd132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9d, 0xca], "vfnmadd132ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9e, 0xca], "vfnmsub132ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0x9f, 0xca], "vfnmsub132ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xa6, 0xca], "vfmaddsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xa7, 0xca], "vfmsubadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xa8, 0xca], "vfmadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xa9, 0xca], "vfmadd213ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xaa, 0xca], "vfmsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xab, 0xca], "vfmsub213ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xac, 0xca], "vfnmadd213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xad, 0xca], "vfnmadd213ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xae, 0xca], "vfnmsub213ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xaf, 0xca], "vfnmsub213ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xb6, 0xca], "vfmaddsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xb7, 0xca], "vfmsubadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xb8, 0xca], "vfmadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xb9, 0xca], "vfmadd231ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xba, 0xca], "vfmsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xbb, 0xca], "vfmsub231ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xbc, 0xca], "vfnmadd231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xbd, 0xca], "vfnmadd231ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xbe, 0xca], "vfnmsub231ps zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xbf, 0xca], "vfnmsub231ss xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xc8, 0xca], "vexp2ps zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xca, 0xca], "vrcp28ps zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xcb, 0xca], "vrcp28ss xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xcc, 0xca], "vrsqrt28ps zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x78, 0xcd, 0xca], "vrsqrt28ss xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x13, 0xca], "vcvtph2ps zmm1{k5}{sae}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x2c, 0xca], "vscalefps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x2d, 0xca], "vscalefss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x42, 0xca], "vgetexpps zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x43, 0xca], "vgetexpss xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xc8, 0xca], "vexp2ps zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xca, 0xca], "vrcp28ps zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xcb, 0xca], "vrcp28ss xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x7d, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x0c, 0xca], "vpermilps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0x0a], "vcvtph2ps xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0x4a, 0x01], "vcvtph2ps xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x13, 0xca], "vcvtph2ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x14, 0xca], "vprorvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x15, 0xca], "vprolvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0x0a], "vbroadcastss xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0x4a, 0x01], "vbroadcastss xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x18, 0xca], "vbroadcastss xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x1e, 0xca], "vpabsd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0x0a], "vpmovsxdq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0x4a, 0x01], "vpmovsxdq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x25, 0xca], "vpmovsxdq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2b, 0xca], "vpackusdw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x2c, 0xca], "vscalefps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0x0a], "vpmovzxdq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0x4a, 0x01], "vpmovzxdq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x35, 0xca], "vpmovzxdq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x39, 0xca], "vpminsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3b, 0xca], "vpminud xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3d, 0xca], "vpmaxsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x3f, 0xca], "vpmaxud xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x40, 0xca], "vpmulld xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x42, 0xca], "vgetexpps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x44, 0xca], "vplzcntd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x45, 0xca], "vpsrlvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x46, 0xca], "vpsravd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x47, 0xca], "vpsllvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4c, 0xca], "vrcp14ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x4e, 0xca], "vrsqrt14ps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x50, 0xca], "vpdpbusd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x51, 0xca], "vpdpbusds xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x52, 0xca], "vpdpwssd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x53, 0xca], "vpdpwssds xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0x0a], "vpopcntb xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0x4a, 0x01], "vpopcntb xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x54, 0xca], "vpopcntb xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x55, 0xca], "vpopcntd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0x0a], "vpbroadcastd xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0x4a, 0x01], "vpbroadcastd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x58, 0xca], "vpbroadcastd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0x0a], "vbroadcasti32x2 xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0x4a, 0x01], "vbroadcasti32x2 xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x59, 0xca], "vbroadcasti32x2 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0x0a], "vpexpandb xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0x4a, 0x01], "vpexpandb xmm1{k5}{z}, xmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x62, 0xca], "vpexpandb xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x63, 0xca], "vpcompressb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x64, 0xca], "vpblendmd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x65, 0xca], "vblendmps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0x0a], "vpblendmb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0x4a, 0x01], "vpblendmb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x66, 0xca], "vpblendmb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x71, 0xca], "vpshldvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x73, 0xca], "vpshrdvd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0x0a], "vpermi2b xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0x4a, 0x01], "vpermi2b xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x75, 0xca], "vpermi2b xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x76, 0xca], "vpermi2d xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x77, 0xca], "vpermi2ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0x0a], "vpbroadcastb xmm1{k5}{z}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0x4a, 0x01], "vpbroadcastb xmm1{k5}{z}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x78, 0xca], "vpbroadcastb xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0x0a], "vpbroadcastw xmm1{k5}{z}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0x4a, 0x01], "vpbroadcastw xmm1{k5}{z}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x79, 0xca], "vpbroadcastw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7a, 0xca], "vpbroadcastb xmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7b, 0xca], "vpbroadcastw xmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0x0a], "vpermt2b xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0x4a, 0x01], "vpermt2b xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7d, 0xca], "vpermt2b xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7e, 0xca], "vpermt2d xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x7f, 0xca], "vpermt2ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0x0a], "vexpandps xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0x4a, 0x01], "vexpandps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x88, 0xca], "vexpandps xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0x0a], "vpexpandd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0x4a, 0x01], "vpexpandd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x89, 0xca], "vpexpandd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x8a, 0xca], "vcompressps xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x8b, 0xca], "vpcompressd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0x0a], "vpermb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0x4a, 0x01], "vpermb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x8d, 0xca], "vpermb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x96, 0xca], "vfmaddsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x97, 0xca], "vfmsubadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x98, 0xca], "vfmadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9a, 0xca], "vfmsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9c, 0xca], "vfnmadd132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0x9e, 0xca], "vfnmsub132ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa6, 0xca], "vfmaddsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa7, 0xca], "vfmsubadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xa8, 0xca], "vfmadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xaa, 0xca], "vfmsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xac, 0xca], "vfnmadd213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xae, 0xca], "vfnmsub213ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb6, 0xca], "vfmaddsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb7, 0xca], "vfmsubadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xb8, 0xca], "vfmadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xba, 0xca], "vfmsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbc, 0xca], "vfnmadd231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xbe, 0xca], "vfnmsub231ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xc4, 0xca], "vpconflictd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0x0a], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0x4a, 0x01], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0x8d, 0xcf, 0xca], "vgf2p8mulb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x0c, 0x0a], "vpermilps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x0c, 0x4a, 0x01], "vpermilps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x14, 0x0a], "vprorvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x14, 0x4a, 0x01], "vprorvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x15, 0x0a], "vprolvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x15, 0x4a, 0x01], "vprolvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x1e, 0x0a], "vpabsd xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x1e, 0x4a, 0x01], "vpabsd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2b, 0x0a], "vpackusdw xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2b, 0x4a, 0x01], "vpackusdw xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0x0a], "vscalefps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0x4a, 0x01], "vscalefps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x39, 0x0a], "vpminsd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x39, 0x4a, 0x01], "vpminsd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3b, 0x0a], "vpminud xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3b, 0x4a, 0x01], "vpminud xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3d, 0x0a], "vpmaxsd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3d, 0x4a, 0x01], "vpmaxsd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3f, 0x0a], "vpmaxud xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x3f, 0x4a, 0x01], "vpmaxud xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x40, 0x0a], "vpmulld xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x40, 0x4a, 0x01], "vpmulld xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x42, 0x0a], "vgetexpps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x42, 0x4a, 0x01], "vgetexpps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x44, 0x0a], "vplzcntd xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x44, 0x4a, 0x01], "vplzcntd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x45, 0x0a], "vpsrlvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x45, 0x4a, 0x01], "vpsrlvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x46, 0x0a], "vpsravd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x46, 0x4a, 0x01], "vpsravd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x47, 0x0a], "vpsllvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x47, 0x4a, 0x01], "vpsllvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x4c, 0x0a], "vrcp14ps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x4c, 0x4a, 0x01], "vrcp14ps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x4e, 0x0a], "vrsqrt14ps xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x4e, 0x4a, 0x01], "vrsqrt14ps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x50, 0x0a], "vpdpbusd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x50, 0x4a, 0x01], "vpdpbusd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x51, 0x0a], "vpdpbusds xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x51, 0x4a, 0x01], "vpdpbusds xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x52, 0x0a], "vpdpwssd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x52, 0x4a, 0x01], "vpdpwssd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x53, 0x0a], "vpdpwssds xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x53, 0x4a, 0x01], "vpdpwssds xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x55, 0x0a], "vpopcntd xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x55, 0x4a, 0x01], "vpopcntd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x64, 0x0a], "vpblendmd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x64, 0x4a, 0x01], "vpblendmd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x65, 0x0a], "vblendmps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x65, 0x4a, 0x01], "vblendmps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x71, 0x0a], "vpshldvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x71, 0x4a, 0x01], "vpshldvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x73, 0x0a], "vpshrdvd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x73, 0x4a, 0x01], "vpshrdvd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x76, 0x0a], "vpermi2d xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x76, 0x4a, 0x01], "vpermi2d xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x77, 0x0a], "vpermi2ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x77, 0x4a, 0x01], "vpermi2ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x7e, 0x0a], "vpermt2d xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x7e, 0x4a, 0x01], "vpermt2d xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x7f, 0x0a], "vpermt2ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x7f, 0x4a, 0x01], "vpermt2ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0x0a], "vfmaddsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0x4a, 0x01], "vfmaddsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0x0a], "vfmsubadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0x4a, 0x01], "vfmsubadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0x0a], "vfmadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0x4a, 0x01], "vfmadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0x0a], "vfmsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0x4a, 0x01], "vfmsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0x0a], "vfnmadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0x4a, 0x01], "vfnmadd132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0x0a], "vfnmsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0x4a, 0x01], "vfnmsub132ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0x0a], "vfmaddsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0x4a, 0x01], "vfmaddsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0x0a], "vfmsubadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0x4a, 0x01], "vfmsubadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0x0a], "vfmadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0x4a, 0x01], "vfmadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0x0a], "vfmsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0x4a, 0x01], "vfmsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0x0a], "vfnmadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0x4a, 0x01], "vfnmadd213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0x0a], "vfnmsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0x4a, 0x01], "vfnmsub213ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0x0a], "vfmaddsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0x4a, 0x01], "vfmaddsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0x0a], "vfmsubadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0x4a, 0x01], "vfmsubadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0x0a], "vfmadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0x4a, 0x01], "vfmadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0x0a], "vfmsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0x4a, 0x01], "vfmsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0x0a], "vfnmadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0x4a, 0x01], "vfnmadd231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0x0a], "vfnmsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0x4a, 0x01], "vfnmsub231ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xc4, 0x0a], "vpconflictd xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0x9d, 0xc4, 0x4a, 0x01], "vpconflictd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x0c, 0xca], "vpermilps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x0a], "vcvtph2ps ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0x4a, 0x01], "vcvtph2ps ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x13, 0xca], "vcvtph2ps ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x14, 0xca], "vprorvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x15, 0xca], "vprolvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x16, 0xca], "vpermps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0x0a], "vbroadcastss ymm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0x4a, 0x01], "vbroadcastss ymm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x18, 0xca], "vbroadcastss ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0x0a], "vbroadcastf32x2 ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0x4a, 0x01], "vbroadcastf32x2 ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x19, 0xca], "vbroadcastf32x2 ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x1a, 0x0a], "vbroadcastf32x4 ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x1e, 0xca], "vpabsd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x0a], "vpmovsxdq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0x4a, 0x01], "vpmovsxdq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x25, 0xca], "vpmovsxdq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2b, 0xca], "vpackusdw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2c, 0xca], "vscalefps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0x0a], "vscalefss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0x4a, 0x01], "vscalefss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x2d, 0xca], "vscalefss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0x0a], "vpmovzxdq ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0x4a, 0x01], "vpmovzxdq ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x35, 0xca], "vpmovzxdq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x36, 0xca], "vpermd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x39, 0xca], "vpminsd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3b, 0xca], "vpminud ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3d, 0xca], "vpmaxsd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x3f, 0xca], "vpmaxud ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x40, 0xca], "vpmulld ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x42, 0xca], "vgetexpps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x0a], "vgetexpss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0x4a, 0x01], "vgetexpss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x43, 0xca], "vgetexpss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x44, 0xca], "vplzcntd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x45, 0xca], "vpsrlvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x46, 0xca], "vpsravd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x47, 0xca], "vpsllvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4c, 0xca], "vrcp14ps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x0a], "vrcp14ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0x4a, 0x01], "vrcp14ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4d, 0xca], "vrcp14ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4e, 0xca], "vrsqrt14ps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x0a], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0x4a, 0x01], "vrsqrt14ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x4f, 0xca], "vrsqrt14ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x50, 0xca], "vpdpbusd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x51, 0xca], "vpdpbusds ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x52, 0xca], "vpdpwssd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x53, 0xca], "vpdpwssds ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0x0a], "vpopcntb ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0x4a, 0x01], "vpopcntb ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x54, 0xca], "vpopcntb ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x55, 0xca], "vpopcntd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0x0a], "vpbroadcastd ymm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0x4a, 0x01], "vpbroadcastd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x58, 0xca], "vpbroadcastd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0x0a], "vbroadcasti32x2 ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0x4a, 0x01], "vbroadcasti32x2 ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x59, 0xca], "vbroadcasti32x2 ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x5a, 0x0a], "vbroadcasti32x4 ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0x0a], "vpexpandb ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0x4a, 0x01], "vpexpandb ymm1{k5}{z}, ymmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x62, 0xca], "vpexpandb ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x63, 0xca], "vpcompressb ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x64, 0xca], "vpblendmd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x65, 0xca], "vblendmps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0x0a], "vpblendmb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0x4a, 0x01], "vpblendmb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x66, 0xca], "vpblendmb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x71, 0xca], "vpshldvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x73, 0xca], "vpshrdvd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0x0a], "vpermi2b ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0x4a, 0x01], "vpermi2b ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x75, 0xca], "vpermi2b ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x76, 0xca], "vpermi2d ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x77, 0xca], "vpermi2ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x0a], "vpbroadcastb ymm1{k5}{z}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0x4a, 0x01], "vpbroadcastb ymm1{k5}{z}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x78, 0xca], "vpbroadcastb ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0x0a], "vpbroadcastw ymm1{k5}{z}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0x4a, 0x01], "vpbroadcastw ymm1{k5}{z}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x79, 0xca], "vpbroadcastw ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7a, 0xca], "vpbroadcastb ymm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7b, 0xca], "vpbroadcastw ymm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0x0a], "vpermt2b ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0x4a, 0x01], "vpermt2b ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7d, 0xca], "vpermt2b ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7e, 0xca], "vpermt2d ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x7f, 0xca], "vpermt2ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0x0a], "vexpandps ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0x4a, 0x01], "vexpandps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x88, 0xca], "vexpandps ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0x0a], "vpexpandd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0x4a, 0x01], "vpexpandd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x89, 0xca], "vpexpandd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x8a, 0xca], "vcompressps ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x8b, 0xca], "vpcompressd ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0x0a], "vpermb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0x4a, 0x01], "vpermb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x8d, 0xca], "vpermb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x96, 0xca], "vfmaddsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x97, 0xca], "vfmsubadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x98, 0xca], "vfmadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x0a], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0x4a, 0x01], "vfmadd132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9a, 0xca], "vfmsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0x0a], "vfmsub132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0x4a, 0x01], "vfmsub132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9c, 0xca], "vfnmadd132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0x0a], "vfnmadd132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0x4a, 0x01], "vfnmadd132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9e, 0xca], "vfnmsub132ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0x0a], "vfnmsub132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0x4a, 0x01], "vfnmsub132ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa6, 0xca], "vfmaddsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa7, 0xca], "vfmsubadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa8, 0xca], "vfmadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0x0a], "vfmadd213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0x4a, 0x01], "vfmadd213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaa, 0xca], "vfmsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0x0a], "vfmsub213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0x4a, 0x01], "vfmsub213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xac, 0xca], "vfnmadd213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0x0a], "vfnmadd213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0x4a, 0x01], "vfnmadd213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xae, 0xca], "vfnmsub213ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0x0a], "vfnmsub213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0x4a, 0x01], "vfnmsub213ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb6, 0xca], "vfmaddsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb7, 0xca], "vfmsubadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb8, 0xca], "vfmadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0x0a], "vfmadd231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0x4a, 0x01], "vfmadd231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xba, 0xca], "vfmsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0x0a], "vfmsub231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0x4a, 0x01], "vfmsub231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbc, 0xca], "vfnmadd231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0x0a], "vfnmadd231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0x4a, 0x01], "vfnmadd231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbe, 0xca], "vfnmsub231ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0x0a], "vfnmsub231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0x4a, 0x01], "vfnmsub231ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xc4, 0xca], "vpconflictd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0x0a], "vrcp28ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0x4a, 0x01], "vrcp28ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0x0a], "vrsqrt28ss xmm1{k5}{z}, xmm0, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0x4a, 0x01], "vrsqrt28ss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0x0a], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0x4a, 0x01], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xad, 0xcf, 0xca], "vgf2p8mulb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x0c, 0x0a], "vpermilps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x0c, 0x4a, 0x01], "vpermilps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0x0a], "vprorvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x14, 0x4a, 0x01], "vprorvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x15, 0x0a], "vprolvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x15, 0x4a, 0x01], "vprolvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x16, 0x0a], "vpermps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x16, 0x4a, 0x01], "vpermps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x1e, 0x0a], "vpabsd ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x1e, 0x4a, 0x01], "vpabsd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x0a], "vpackusdw ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2b, 0x4a, 0x01], "vpackusdw ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0x0a], "vscalefps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0x4a, 0x01], "vscalefps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x36, 0x0a], "vpermd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x36, 0x4a, 0x01], "vpermd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x39, 0x0a], "vpminsd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x39, 0x4a, 0x01], "vpminsd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3b, 0x0a], "vpminud ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3b, 0x4a, 0x01], "vpminud ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3d, 0x0a], "vpmaxsd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3d, 0x4a, 0x01], "vpmaxsd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3f, 0x0a], "vpmaxud ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x3f, 0x4a, 0x01], "vpmaxud ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x40, 0x0a], "vpmulld ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x40, 0x4a, 0x01], "vpmulld ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x42, 0x0a], "vgetexpps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x42, 0x4a, 0x01], "vgetexpps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x44, 0x0a], "vplzcntd ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x44, 0x4a, 0x01], "vplzcntd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x45, 0x0a], "vpsrlvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x45, 0x4a, 0x01], "vpsrlvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x46, 0x0a], "vpsravd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x46, 0x4a, 0x01], "vpsravd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x47, 0x0a], "vpsllvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x47, 0x4a, 0x01], "vpsllvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x4c, 0x0a], "vrcp14ps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x4c, 0x4a, 0x01], "vrcp14ps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x4e, 0x0a], "vrsqrt14ps ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x4e, 0x4a, 0x01], "vrsqrt14ps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x50, 0x0a], "vpdpbusd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x50, 0x4a, 0x01], "vpdpbusd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x51, 0x0a], "vpdpbusds ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x51, 0x4a, 0x01], "vpdpbusds ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x52, 0x0a], "vpdpwssd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x52, 0x4a, 0x01], "vpdpwssd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x53, 0x0a], "vpdpwssds ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x53, 0x4a, 0x01], "vpdpwssds ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x55, 0x0a], "vpopcntd ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x55, 0x4a, 0x01], "vpopcntd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x64, 0x0a], "vpblendmd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x64, 0x4a, 0x01], "vpblendmd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x65, 0x0a], "vblendmps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x65, 0x4a, 0x01], "vblendmps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x71, 0x0a], "vpshldvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x71, 0x4a, 0x01], "vpshldvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x73, 0x0a], "vpshrdvd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x73, 0x4a, 0x01], "vpshrdvd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x76, 0x0a], "vpermi2d ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x76, 0x4a, 0x01], "vpermi2d ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x77, 0x0a], "vpermi2ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x77, 0x4a, 0x01], "vpermi2ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x7e, 0x0a], "vpermt2d ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x7e, 0x4a, 0x01], "vpermt2d ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x7f, 0x0a], "vpermt2ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x7f, 0x4a, 0x01], "vpermt2ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0x0a], "vfmaddsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0x4a, 0x01], "vfmaddsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0x0a], "vfmsubadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0x4a, 0x01], "vfmsubadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0x0a], "vfmadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0x4a, 0x01], "vfmadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0x0a], "vfmsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0x4a, 0x01], "vfmsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0x0a], "vfnmadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0x4a, 0x01], "vfnmadd132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0x0a], "vfnmsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0x4a, 0x01], "vfnmsub132ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0x0a], "vfmaddsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0x0a], "vfmsubadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0x0a], "vfmadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0x4a, 0x01], "vfmadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0x0a], "vfmsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0x4a, 0x01], "vfmsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0x0a], "vfnmadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0x4a, 0x01], "vfnmadd213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0x0a], "vfnmsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0x4a, 0x01], "vfnmsub213ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0x0a], "vfmaddsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0x0a], "vfmsubadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0x0a], "vfmadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0x4a, 0x01], "vfmadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0x0a], "vfmsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0x4a, 0x01], "vfmsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0x0a], "vfnmadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0x4a, 0x01], "vfnmadd231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0x0a], "vfnmsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0x4a, 0x01], "vfnmsub231ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xc4, 0x0a], "vpconflictd ymm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xbd, 0xc4, 0x4a, 0x01], "vpconflictd ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x0c, 0xca], "vpermilps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0x0a], "vcvtph2ps zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0x4a, 0x01], "vcvtph2ps zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x14, 0xca], "vprorvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x15, 0xca], "vprolvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x16, 0xca], "vpermps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0x0a], "vbroadcastss zmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0x4a, 0x01], "vbroadcastss zmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x18, 0xca], "vbroadcastss zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0x0a], "vbroadcastf32x2 zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0x4a, 0x01], "vbroadcastf32x2 zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x19, 0xca], "vbroadcastf32x2 zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1a, 0x0a], "vbroadcastf32x4 zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1a, 0x4a, 0x01], "vbroadcastf32x4 zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1b, 0x0a], "vbroadcastf32x8 zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1b, 0x4a, 0x01], "vbroadcastf32x8 zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x1e, 0xca], "vpabsd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x0a], "vpmovsxdq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0x4a, 0x01], "vpmovsxdq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x25, 0xca], "vpmovsxdq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2b, 0xca], "vpackusdw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0x0a], "vpmovzxdq zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0x4a, 0x01], "vpmovzxdq zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x35, 0xca], "vpmovzxdq zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x36, 0xca], "vpermd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x39, 0xca], "vpminsd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3b, 0xca], "vpminud zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3d, 0xca], "vpmaxsd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x3f, 0xca], "vpmaxud zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x40, 0xca], "vpmulld zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x44, 0xca], "vplzcntd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x45, 0xca], "vpsrlvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x46, 0xca], "vpsravd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x47, 0xca], "vpsllvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4c, 0xca], "vrcp14ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x4e, 0xca], "vrsqrt14ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x50, 0xca], "vpdpbusd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x51, 0xca], "vpdpbusds zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x52, 0xca], "vpdpwssd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x53, 0xca], "vpdpwssds zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0x0a], "vpopcntb zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0x4a, 0x01], "vpopcntb zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x54, 0xca], "vpopcntb zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x55, 0xca], "vpopcntd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0x0a], "vpbroadcastd zmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0x4a, 0x01], "vpbroadcastd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x58, 0xca], "vpbroadcastd zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0x0a], "vbroadcasti32x2 zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0x4a, 0x01], "vbroadcasti32x2 zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x59, 0xca], "vbroadcasti32x2 zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x5a, 0x0a], "vbroadcasti32x4 zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x5a, 0x4a, 0x01], "vbroadcasti32x4 zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x5b, 0x0a], "vbroadcasti32x8 zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x5b, 0x4a, 0x01], "vbroadcasti32x8 zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0x0a], "vpexpandb zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0x4a, 0x01], "vpexpandb zmm1{k5}{z}, zmmword [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x62, 0xca], "vpexpandb zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x63, 0xca], "vpcompressb zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x64, 0xca], "vpblendmd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x65, 0xca], "vblendmps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0x0a], "vpblendmb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0x4a, 0x01], "vpblendmb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x66, 0xca], "vpblendmb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x71, 0xca], "vpshldvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x73, 0xca], "vpshrdvd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0x0a], "vpermi2b zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0x4a, 0x01], "vpermi2b zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x75, 0xca], "vpermi2b zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x76, 0xca], "vpermi2d zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x77, 0xca], "vpermi2ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0x0a], "vpbroadcastb zmm1{k5}{z}, byte [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0x4a, 0x01], "vpbroadcastb zmm1{k5}{z}, byte [bp + si * 1 + 0x1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x78, 0xca], "vpbroadcastb zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0x0a], "vpbroadcastw zmm1{k5}{z}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0x4a, 0x01], "vpbroadcastw zmm1{k5}{z}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x79, 0xca], "vpbroadcastw zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7a, 0xca], "vpbroadcastb zmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7b, 0xca], "vpbroadcastw zmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0x0a], "vpermt2b zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0x4a, 0x01], "vpermt2b zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7d, 0xca], "vpermt2b zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7e, 0xca], "vpermt2d zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x7f, 0xca], "vpermt2ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0x0a], "vexpandps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0x4a, 0x01], "vexpandps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x88, 0xca], "vexpandps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0x0a], "vpexpandd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0x4a, 0x01], "vpexpandd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x89, 0xca], "vpexpandd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x8a, 0xca], "vcompressps zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x8b, 0xca], "vpcompressd zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0x0a], "vpermb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0x4a, 0x01], "vpermb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x8d, 0xca], "vpermb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc4, 0xca], "vpconflictd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0x0a], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0x4a, 0x01], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7d, 0xcd, 0xcf, 0xca], "vgf2p8mulb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x0c, 0x0a], "vpermilps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x0c, 0x4a, 0x01], "vpermilps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x14, 0x0a], "vprorvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x14, 0x4a, 0x01], "vprorvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x15, 0x0a], "vprolvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x15, 0x4a, 0x01], "vprolvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x16, 0x0a], "vpermps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x16, 0x4a, 0x01], "vpermps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x1e, 0x0a], "vpabsd zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x1e, 0x4a, 0x01], "vpabsd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2b, 0x0a], "vpackusdw zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2b, 0x4a, 0x01], "vpackusdw zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0x0a], "vscalefps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0x4a, 0x01], "vscalefps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x36, 0x0a], "vpermd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x36, 0x4a, 0x01], "vpermd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x39, 0x0a], "vpminsd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x39, 0x4a, 0x01], "vpminsd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3b, 0x0a], "vpminud zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3b, 0x4a, 0x01], "vpminud zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3d, 0x0a], "vpmaxsd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3d, 0x4a, 0x01], "vpmaxsd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3f, 0x0a], "vpmaxud zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x3f, 0x4a, 0x01], "vpmaxud zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x40, 0x0a], "vpmulld zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x40, 0x4a, 0x01], "vpmulld zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x42, 0x0a], "vgetexpps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x42, 0x4a, 0x01], "vgetexpps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x44, 0x0a], "vplzcntd zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x44, 0x4a, 0x01], "vplzcntd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x45, 0x0a], "vpsrlvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x45, 0x4a, 0x01], "vpsrlvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x46, 0x0a], "vpsravd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x46, 0x4a, 0x01], "vpsravd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x47, 0x0a], "vpsllvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x47, 0x4a, 0x01], "vpsllvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x4c, 0x0a], "vrcp14ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x4c, 0x4a, 0x01], "vrcp14ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x4e, 0x0a], "vrsqrt14ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x4e, 0x4a, 0x01], "vrsqrt14ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x50, 0x0a], "vpdpbusd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x50, 0x4a, 0x01], "vpdpbusd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x51, 0x0a], "vpdpbusds zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x51, 0x4a, 0x01], "vpdpbusds zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x52, 0x0a], "vpdpwssd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x52, 0x4a, 0x01], "vpdpwssd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x53, 0x0a], "vpdpwssds zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x53, 0x4a, 0x01], "vpdpwssds zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x55, 0x0a], "vpopcntd zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x55, 0x4a, 0x01], "vpopcntd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x64, 0x0a], "vpblendmd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x64, 0x4a, 0x01], "vpblendmd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x65, 0x0a], "vblendmps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x65, 0x4a, 0x01], "vblendmps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x71, 0x0a], "vpshldvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x71, 0x4a, 0x01], "vpshldvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x73, 0x0a], "vpshrdvd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x73, 0x4a, 0x01], "vpshrdvd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x76, 0x0a], "vpermi2d zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x76, 0x4a, 0x01], "vpermi2d zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x77, 0x0a], "vpermi2ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x77, 0x4a, 0x01], "vpermi2ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x7e, 0x0a], "vpermt2d zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x7e, 0x4a, 0x01], "vpermt2d zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x7f, 0x0a], "vpermt2ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x7f, 0x4a, 0x01], "vpermt2ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0x0a], "vfmaddsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0x4a, 0x01], "vfmaddsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0x0a], "vfmsubadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0x4a, 0x01], "vfmsubadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0x0a], "vfmadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0x4a, 0x01], "vfmadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0x0a], "vfmsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0x4a, 0x01], "vfmsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0x0a], "vfnmadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0x4a, 0x01], "vfnmadd132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0x0a], "vfnmsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0x4a, 0x01], "vfnmsub132ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0x0a], "vfmaddsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0x4a, 0x01], "vfmaddsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0x0a], "vfmsubadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0x4a, 0x01], "vfmsubadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0x0a], "vfmadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0x4a, 0x01], "vfmadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0x0a], "vfmsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0x4a, 0x01], "vfmsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0x0a], "vfnmadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0x4a, 0x01], "vfnmadd213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0x0a], "vfnmsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0x4a, 0x01], "vfnmsub213ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0x0a], "vfmaddsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0x4a, 0x01], "vfmaddsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0x0a], "vfmsubadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0x4a, 0x01], "vfmsubadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0x0a], "vfmadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0x4a, 0x01], "vfmadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0x0a], "vfmsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0x4a, 0x01], "vfmsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0x0a], "vfnmadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0x4a, 0x01], "vfnmadd231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0x0a], "vfnmsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0x4a, 0x01], "vfnmsub231ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xc4, 0x0a], "vpconflictd zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xc4, 0x4a, 0x01], "vpconflictd zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xc8, 0x0a], "vexp2ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xc8, 0x4a, 0x01], "vexp2ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xca, 0x0a], "vrcp28ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xca, 0x4a, 0x01], "vrcp28ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xcc, 0x0a], "vrsqrt28ps zmm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xdd, 0xcc, 0x4a, 0x01], "vrsqrt28ps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x13, 0xca], "vcvtph2ps zmm1{k5}{z}{sae}, ymm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x2c, 0xca], "vscalefps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x2d, 0xca], "vscalefss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x42, 0xca], "vgetexpps zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x43, 0xca], "vgetexpss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x96, 0xca], "vfmaddsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x97, 0xca], "vfmsubadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x98, 0xca], "vfmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x99, 0xca], "vfmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9a, 0xca], "vfmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9b, 0xca], "vfmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9c, 0xca], "vfnmadd132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9d, 0xca], "vfnmadd132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9e, 0xca], "vfnmsub132ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0x9f, 0xca], "vfnmsub132ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xa6, 0xca], "vfmaddsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xa7, 0xca], "vfmsubadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xa8, 0xca], "vfmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xa9, 0xca], "vfmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xaa, 0xca], "vfmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xab, 0xca], "vfmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xac, 0xca], "vfnmadd213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xad, 0xca], "vfnmadd213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xae, 0xca], "vfnmsub213ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xaf, 0xca], "vfnmsub213ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xb6, 0xca], "vfmaddsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xb7, 0xca], "vfmsubadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xb8, 0xca], "vfmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xb9, 0xca], "vfmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xba, 0xca], "vfmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xbb, 0xca], "vfmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xbc, 0xca], "vfnmadd231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xbd, 0xca], "vfnmadd231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xbe, 0xca], "vfnmsub231ps zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xbf, 0xca], "vfnmsub231ss xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xc8, 0xca], "vexp2ps zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xca, 0xca], "vrcp28ps zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xcb, 0xca], "vrcp28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xcc, 0xca], "vrsqrt28ps zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0x7d, 0xfd, 0xcd, 0xca], "vrsqrt28ss xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0x0a], "vpmovuswb qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0x4a, 0x01], "vpmovuswb qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x10, 0xca], "vpmovuswb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0x0a], "vpmovusdb dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0x4a, 0x01], "vpmovusdb dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x11, 0xca], "vpmovusdb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0x0a], "vpmovusqb word [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0x4a, 0x01], "vpmovusqb word [bp + si * 1 + 0x2], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x12, 0xca], "vpmovusqb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0x0a], "vpmovusdw qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0x4a, 0x01], "vpmovusdw qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x13, 0xca], "vpmovusdw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0x0a], "vpmovusqw dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0x4a, 0x01], "vpmovusqw dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x14, 0xca], "vpmovusqw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0x0a], "vpmovusqd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0x4a, 0x01], "vpmovusqd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x15, 0xca], "vpmovusqd xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0x0a], "vpmovswb qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0x4a, 0x01], "vpmovswb qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x20, 0xca], "vpmovswb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0x0a], "vpmovsdb dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0x4a, 0x01], "vpmovsdb dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x21, 0xca], "vpmovsdb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0x0a], "vpmovsqb word [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0x4a, 0x01], "vpmovsqb word [bp + si * 1 + 0x2], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x22, 0xca], "vpmovsqb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0x0a], "vpmovsdw qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0x4a, 0x01], "vpmovsdw qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x23, 0xca], "vpmovsdw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0x0a], "vpmovsqw dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0x4a, 0x01], "vpmovsqw dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x24, 0xca], "vpmovsqw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0x0a], "vpmovsqd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0x4a, 0x01], "vpmovsqd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x25, 0xca], "vpmovsqd xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0x0a], "vptestnmb k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0x4a, 0x01], "vptestnmb k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x26, 0xca], "vptestnmb k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0x0a], "vptestnmd k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0x4a, 0x01], "vptestnmd k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x27, 0xca], "vptestnmd k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xca], "vpmovm2b xmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x29, 0xca], "vpmovb2m k1, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0x0a], "vpmovwb qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0x4a, 0x01], "vpmovwb qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x30, 0xca], "vpmovwb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0x0a], "vpmovdb dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0x4a, 0x01], "vpmovdb dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x31, 0xca], "vpmovdb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0x0a], "vpmovqb word [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0x4a, 0x01], "vpmovqb word [bp + si * 1 + 0x2], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x32, 0xca], "vpmovqb xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0x0a], "vpmovdw qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0x4a, 0x01], "vpmovdw qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x33, 0xca], "vpmovdw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0x0a], "vpmovqw dword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0x4a, 0x01], "vpmovqw dword [bp + si * 1 + 0x4], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x34, 0xca], "vpmovqw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0x0a], "vpmovqd qword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0x4a, 0x01], "vpmovqd qword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x35, 0xca], "vpmovqd xmm2, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x38, 0xca], "vpmovm2d xmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x39, 0xca], "vpmovd2m k1, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x3a, 0xca], "vpbroadcastmw2d xmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x52, 0xca], "vdpbf16ps xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0x0a], "vcvtneps2bf16 xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x72, 0xca], "vcvtneps2bf16 xmm1, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0x0a], "vpmovuswb qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0x4a, 0x01], "vpmovuswb qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x10, 0xca], "vpmovuswb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0x0a], "vpmovusdb dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0x4a, 0x01], "vpmovusdb dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x11, 0xca], "vpmovusdb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0x0a], "vpmovusqb word [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0x4a, 0x01], "vpmovusqb word [bp + si * 1 + 0x2]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x12, 0xca], "vpmovusqb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0x0a], "vpmovusdw qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0x4a, 0x01], "vpmovusdw qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x13, 0xca], "vpmovusdw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0x0a], "vpmovusqw dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0x4a, 0x01], "vpmovusqw dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x14, 0xca], "vpmovusqw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0x0a], "vpmovusqd qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0x4a, 0x01], "vpmovusqd qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x15, 0xca], "vpmovusqd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0x0a], "vpmovswb qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0x4a, 0x01], "vpmovswb qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x20, 0xca], "vpmovswb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0x0a], "vpmovsdb dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0x4a, 0x01], "vpmovsdb dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x21, 0xca], "vpmovsdb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0x0a], "vpmovsqb word [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0x4a, 0x01], "vpmovsqb word [bp + si * 1 + 0x2]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x22, 0xca], "vpmovsqb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0x0a], "vpmovsdw qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0x4a, 0x01], "vpmovsdw qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x23, 0xca], "vpmovsdw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0x0a], "vpmovsqw dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0x4a, 0x01], "vpmovsqw dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x24, 0xca], "vpmovsqw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0x0a], "vpmovsqd qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0x4a, 0x01], "vpmovsqd qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x25, 0xca], "vpmovsqd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0x0a], "vptestnmb k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x26, 0xca], "vptestnmb k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x27, 0xca], "vptestnmd k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0x0a], "vpmovwb qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0x4a, 0x01], "vpmovwb qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x30, 0xca], "vpmovwb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0x0a], "vpmovdb dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0x4a, 0x01], "vpmovdb dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x31, 0xca], "vpmovdb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0x0a], "vpmovqb word [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0x4a, 0x01], "vpmovqb word [bp + si * 1 + 0x2]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x32, 0xca], "vpmovqb xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0x0a], "vpmovdw qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0x4a, 0x01], "vpmovdw qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x33, 0xca], "vpmovdw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0x0a], "vpmovqw dword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0x4a, 0x01], "vpmovqw dword [bp + si * 1 + 0x4]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x34, 0xca], "vpmovqw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0x0a], "vpmovqd qword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0x4a, 0x01], "vpmovqd qword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x35, 0xca], "vpmovqd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x52, 0xca], "vdpbf16ps xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x0d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x27, 0x0a], "vptestnmd k1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x27, 0x4a, 0x01], "vptestnmd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x52, 0x0a], "vdpbf16ps xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x18, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x27, 0x0a], "vptestnmd k1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x1d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x0a], "vpmovuswb xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0x4a, 0x01], "vpmovuswb xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x10, 0xca], "vpmovuswb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0x0a], "vpmovusdb qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0x4a, 0x01], "vpmovusdb qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x11, 0xca], "vpmovusdb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0x0a], "vpmovusqb dword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0x4a, 0x01], "vpmovusqb dword [bp + si * 1 + 0x4], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x12, 0xca], "vpmovusqb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0x0a], "vpmovusdw xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0x4a, 0x01], "vpmovusdw xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x13, 0xca], "vpmovusdw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0x0a], "vpmovusqw qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0x4a, 0x01], "vpmovusqw qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x14, 0xca], "vpmovusqw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0x0a], "vpmovusqd xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0x4a, 0x01], "vpmovusqd xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x15, 0xca], "vpmovusqd xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0x0a], "vpmovswb xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0x4a, 0x01], "vpmovswb xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x20, 0xca], "vpmovswb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0x0a], "vpmovsdb qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0x4a, 0x01], "vpmovsdb qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x21, 0xca], "vpmovsdb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0x0a], "vpmovsqb dword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0x4a, 0x01], "vpmovsqb dword [bp + si * 1 + 0x4], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x22, 0xca], "vpmovsqb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0x0a], "vpmovsdw xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0x4a, 0x01], "vpmovsdw xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x23, 0xca], "vpmovsdw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0x0a], "vpmovsqw qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0x4a, 0x01], "vpmovsqw qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x24, 0xca], "vpmovsqw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0x0a], "vpmovsqd xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0x4a, 0x01], "vpmovsqd xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x25, 0xca], "vpmovsqd xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0x0a], "vptestnmb k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0x4a, 0x01], "vptestnmb k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x26, 0xca], "vptestnmb k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0x0a], "vptestnmd k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0x4a, 0x01], "vptestnmd k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x27, 0xca], "vptestnmd k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x28, 0xca], "vpmovm2b ymm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xca], "vpmovb2m k1, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0x0a], "vpmovwb xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0x4a, 0x01], "vpmovwb xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x30, 0xca], "vpmovwb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0x0a], "vpmovdb qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0x4a, 0x01], "vpmovdb qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x31, 0xca], "vpmovdb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0x0a], "vpmovqb dword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0x4a, 0x01], "vpmovqb dword [bp + si * 1 + 0x4], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x32, 0xca], "vpmovqb xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0x0a], "vpmovdw xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0x4a, 0x01], "vpmovdw xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x33, 0xca], "vpmovdw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0x0a], "vpmovqw qword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0x4a, 0x01], "vpmovqw qword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x34, 0xca], "vpmovqw xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0x0a], "vpmovqd xmmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0x4a, 0x01], "vpmovqd xmmword [bp + si * 1 + 0x10], ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x35, 0xca], "vpmovqd xmm2, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x38, 0xca], "vpmovm2d ymm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x39, 0xca], "vpmovd2m k1, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x52, 0xca], "vdpbf16ps ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0x0a], "vcvtneps2bf16 xmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x72, 0xca], "vcvtneps2bf16 xmm1, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x0a], "vpmovuswb xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0x4a, 0x01], "vpmovuswb xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x10, 0xca], "vpmovuswb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0x0a], "vpmovusdb qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0x4a, 0x01], "vpmovusdb qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x11, 0xca], "vpmovusdb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0x0a], "vpmovusqb dword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0x4a, 0x01], "vpmovusqb dword [bp + si * 1 + 0x4]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x12, 0xca], "vpmovusqb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0x0a], "vpmovusdw xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0x4a, 0x01], "vpmovusdw xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x13, 0xca], "vpmovusdw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0x0a], "vpmovusqw qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0x4a, 0x01], "vpmovusqw qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x14, 0xca], "vpmovusqw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0x0a], "vpmovusqd xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0x4a, 0x01], "vpmovusqd xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x15, 0xca], "vpmovusqd xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0x0a], "vpmovswb xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0x4a, 0x01], "vpmovswb xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x20, 0xca], "vpmovswb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0x0a], "vpmovsdb qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0x4a, 0x01], "vpmovsdb qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x21, 0xca], "vpmovsdb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0x0a], "vpmovsqb dword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0x4a, 0x01], "vpmovsqb dword [bp + si * 1 + 0x4]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x22, 0xca], "vpmovsqb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0x0a], "vpmovsdw xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0x4a, 0x01], "vpmovsdw xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x23, 0xca], "vpmovsdw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0x0a], "vpmovsqw qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0x4a, 0x01], "vpmovsqw qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x24, 0xca], "vpmovsqw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0x0a], "vpmovsqd xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0x4a, 0x01], "vpmovsqd xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x25, 0xca], "vpmovsqd xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0x0a], "vptestnmb k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x26, 0xca], "vptestnmb k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x27, 0xca], "vptestnmd k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0x0a], "vpmovwb xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0x4a, 0x01], "vpmovwb xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x30, 0xca], "vpmovwb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0x0a], "vpmovdb qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0x4a, 0x01], "vpmovdb qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x31, 0xca], "vpmovdb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0x0a], "vpmovqb dword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0x4a, 0x01], "vpmovqb dword [bp + si * 1 + 0x4]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x32, 0xca], "vpmovqb xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0x0a], "vpmovdw xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0x4a, 0x01], "vpmovdw xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x33, 0xca], "vpmovdw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0x0a], "vpmovqw qword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0x4a, 0x01], "vpmovqw qword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x34, 0xca], "vpmovqw xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0x0a], "vpmovqd xmmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0x4a, 0x01], "vpmovqd xmmword [bp + si * 1 + 0x10]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x35, 0xca], "vpmovqd xmm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x52, 0xca], "vdpbf16ps ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0x2d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x27, 0x0a], "vptestnmd k1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x27, 0x4a, 0x01], "vptestnmd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x0a], "vdpbf16ps ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x0a], "vcvtneps2bf16 xmm1, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x38, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x27, 0x0a], "vptestnmd k1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x0a], "vdpbf16ps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x3d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0x0a], "vpmovuswb ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0x4a, 0x01], "vpmovuswb ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x10, 0xca], "vpmovuswb ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0x0a], "vpmovusdb xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0x4a, 0x01], "vpmovusdb xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x11, 0xca], "vpmovusdb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x0a], "vpmovusqb qword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0x4a, 0x01], "vpmovusqb qword [bp + si * 1 + 0x8], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x12, 0xca], "vpmovusqb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0x0a], "vpmovusdw ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0x4a, 0x01], "vpmovusdw ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x13, 0xca], "vpmovusdw ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0x0a], "vpmovusqw xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0x4a, 0x01], "vpmovusqw xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x14, 0xca], "vpmovusqw xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0x0a], "vpmovusqd ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0x4a, 0x01], "vpmovusqd ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x15, 0xca], "vpmovusqd ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0x0a], "vpmovswb ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0x4a, 0x01], "vpmovswb ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x20, 0xca], "vpmovswb ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0x0a], "vpmovsdb xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0x4a, 0x01], "vpmovsdb xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x21, 0xca], "vpmovsdb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0x0a], "vpmovsqb qword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0x4a, 0x01], "vpmovsqb qword [bp + si * 1 + 0x8], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x22, 0xca], "vpmovsqb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0x0a], "vpmovsdw ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0x4a, 0x01], "vpmovsdw ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x23, 0xca], "vpmovsdw ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0x0a], "vpmovsqw xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0x4a, 0x01], "vpmovsqw xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x24, 0xca], "vpmovsqw xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0x0a], "vpmovsqd ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0x4a, 0x01], "vpmovsqd ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x25, 0xca], "vpmovsqd ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0x0a], "vptestnmb k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0x4a, 0x01], "vptestnmb k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x26, 0xca], "vptestnmb k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0x0a], "vptestnmd k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0x4a, 0x01], "vptestnmd k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x27, 0xca], "vptestnmd k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x28, 0xca], "vpmovm2b zmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x29, 0xca], "vpmovb2m k1, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0x0a], "vpmovwb ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0x4a, 0x01], "vpmovwb ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x30, 0xca], "vpmovwb ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0x0a], "vpmovdb xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0x4a, 0x01], "vpmovdb xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x31, 0xca], "vpmovdb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0x0a], "vpmovqb qword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0x4a, 0x01], "vpmovqb qword [bp + si * 1 + 0x8], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x32, 0xca], "vpmovqb xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0x0a], "vpmovdw ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0x4a, 0x01], "vpmovdw ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x33, 0xca], "vpmovdw ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0x0a], "vpmovqw xmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0x4a, 0x01], "vpmovqw xmmword [bp + si * 1 + 0x10], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x34, 0xca], "vpmovqw xmm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0x0a], "vpmovqd ymmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0x4a, 0x01], "vpmovqd ymmword [bp + si * 1 + 0x20], zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x35, 0xca], "vpmovqd ymm2, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x38, 0xca], "vpmovm2d zmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x39, 0xca], "vpmovd2m k1, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x3a, 0xca], "vpbroadcastmw2d zmm1, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x52, 0xca], "vdpbf16ps zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0x0a], "vcvtneps2bf16 ymm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x48, 0x72, 0xca], "vcvtneps2bf16 ymm1, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0x0a], "vpmovuswb ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0x4a, 0x01], "vpmovuswb ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x10, 0xca], "vpmovuswb ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0x0a], "vpmovusdb xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0x4a, 0x01], "vpmovusdb xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x11, 0xca], "vpmovusdb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x0a], "vpmovusqb qword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0x4a, 0x01], "vpmovusqb qword [bp + si * 1 + 0x8]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x12, 0xca], "vpmovusqb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0x0a], "vpmovusdw ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0x4a, 0x01], "vpmovusdw ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x13, 0xca], "vpmovusdw ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0x0a], "vpmovusqw xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0x4a, 0x01], "vpmovusqw xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x14, 0xca], "vpmovusqw xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0x0a], "vpmovusqd ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0x4a, 0x01], "vpmovusqd ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x15, 0xca], "vpmovusqd ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0x0a], "vpmovswb ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0x4a, 0x01], "vpmovswb ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x20, 0xca], "vpmovswb ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0x0a], "vpmovsdb xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0x4a, 0x01], "vpmovsdb xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x21, 0xca], "vpmovsdb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0x0a], "vpmovsqb qword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0x4a, 0x01], "vpmovsqb qword [bp + si * 1 + 0x8]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x22, 0xca], "vpmovsqb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0x0a], "vpmovsdw ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0x4a, 0x01], "vpmovsdw ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x23, 0xca], "vpmovsdw ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0x0a], "vpmovsqw xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0x4a, 0x01], "vpmovsqw xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x24, 0xca], "vpmovsqw xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0x0a], "vpmovsqd ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0x4a, 0x01], "vpmovsqd ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x25, 0xca], "vpmovsqd ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0x0a], "vptestnmb k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0x4a, 0x01], "vptestnmb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x26, 0xca], "vptestnmb k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x27, 0xca], "vptestnmd k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0x0a], "vpmovwb ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0x4a, 0x01], "vpmovwb ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x30, 0xca], "vpmovwb ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0x0a], "vpmovdb xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0x4a, 0x01], "vpmovdb xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x31, 0xca], "vpmovdb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0x0a], "vpmovqb qword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0x4a, 0x01], "vpmovqb qword [bp + si * 1 + 0x8]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x32, 0xca], "vpmovqb xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0x0a], "vpmovdw ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0x4a, 0x01], "vpmovdw ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x33, 0xca], "vpmovdw ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0x0a], "vpmovqw xmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0x4a, 0x01], "vpmovqw xmmword [bp + si * 1 + 0x10]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x34, 0xca], "vpmovqw xmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0x0a], "vpmovqd ymmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0x4a, 0x01], "vpmovqd ymmword [bp + si * 1 + 0x20]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x35, 0xca], "vpmovqd ymm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x52, 0xca], "vdpbf16ps zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0x4d, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x27, 0x0a], "vptestnmd k1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x27, 0x4a, 0x01], "vptestnmd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x52, 0x0a], "vdpbf16ps zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x72, 0x0a], "vcvtneps2bf16 ymm1, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x58, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x27, 0x0a], "vptestnmd k1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x27, 0x4a, 0x01], "vptestnmd k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x52, 0x0a], "vdpbf16ps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x5d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x52, 0xca], "vdpbf16ps xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7e, 0x8d, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0x7e, 0x9d, 0x52, 0x0a], "vdpbf16ps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x9d, 0x52, 0x4a, 0x01], "vdpbf16ps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x9d, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0x9d, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x10, 0xca], "vpmovuswb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x13, 0xca], "vpmovusdw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x15, 0xca], "vpmovusqd xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x20, 0xca], "vpmovswb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x23, 0xca], "vpmovsdw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x25, 0xca], "vpmovsqd xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x30, 0xca], "vpmovwb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x33, 0xca], "vpmovdw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x35, 0xca], "vpmovqd xmm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x52, 0xca], "vdpbf16ps ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7e, 0xad, 0x72, 0xca], "vcvtneps2bf16 xmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x0a], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0xbd, 0x52, 0x4a, 0x01], "vdpbf16ps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0x0a], "vcvtneps2bf16 xmm1{k5}{z}, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0xbd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x10, 0xca], "vpmovuswb ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x11, 0xca], "vpmovusdb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x12, 0xca], "vpmovusqb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x13, 0xca], "vpmovusdw ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x14, 0xca], "vpmovusqw xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x15, 0xca], "vpmovusqd ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x20, 0xca], "vpmovswb ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x21, 0xca], "vpmovsdb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x22, 0xca], "vpmovsqb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x23, 0xca], "vpmovsdw ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x24, 0xca], "vpmovsqw xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x25, 0xca], "vpmovsqd ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x30, 0xca], "vpmovwb ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x31, 0xca], "vpmovdb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x32, 0xca], "vpmovqb xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x33, 0xca], "vpmovdw ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x34, 0xca], "vpmovqw xmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x35, 0xca], "vpmovqd ymm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x52, 0xca], "vdpbf16ps zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7e, 0xcd, 0x72, 0xca], "vcvtneps2bf16 ymm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0x7e, 0xdd, 0x52, 0x0a], "vdpbf16ps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0xdd, 0x52, 0x4a, 0x01], "vdpbf16ps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0xdd, 0x72, 0x0a], "vcvtneps2bf16 ymm1{k5}{z}, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7e, 0xdd, 0x72, 0x4a, 0x01], "vcvtneps2bf16 ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x0a], "vp2intersectd k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0x4a, 0x01], "vp2intersectd k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x68, 0xca], "vp2intersectd k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x08, 0x72, 0xca], "vcvtne2ps2bf16 xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x0d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x18, 0x68, 0x0a], "vp2intersectd k1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x18, 0x68, 0x4a, 0x01], "vp2intersectd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x18, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x18, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x1d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x1d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0x0a], "vp2intersectd k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0x4a, 0x01], "vp2intersectd k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x68, 0xca], "vp2intersectd k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x72, 0xca], "vcvtne2ps2bf16 ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x9b, 0x0a], "v4fmaddss xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x0a], "v4fnmaddss xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x28, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0x9b, 0x0a], "v4fmaddss xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x0a], "v4fnmaddss xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x2d, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x38, 0x68, 0x0a], "vp2intersectd k1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x38, 0x68, 0x4a, 0x01], "vp2intersectd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x38, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x38, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x3d, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x3d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x52, 0x0a], "vp4dpwssd zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x53, 0x0a], "vp4dpwssds zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0x0a], "vp2intersectd k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0x4a, 0x01], "vp2intersectd k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x68, 0xca], "vp2intersectd k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x72, 0xca], "vcvtne2ps2bf16 zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x0a], "v4fmaddps zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x0a], "v4fnmaddps zmm1, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x48, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x52, 0x0a], "vp4dpwssd zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x53, 0x0a], "vp4dpwssds zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x9a, 0x0a], "v4fmaddps zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x4d, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x58, 0x68, 0x0a], "vp2intersectd k1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x58, 0x68, 0x4a, 0x01], "vp2intersectd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x58, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x58, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x5d, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x5d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0x8d, 0x72, 0xca], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0x7f, 0x9d, 0x72, 0x0a], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0x9d, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0x72, 0xca], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0x9b, 0x0a], "v4fmaddss xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0x9b, 0x4a, 0x01], "v4fmaddss xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0xab, 0x0a], "v4fnmaddss xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xad, 0xab, 0x4a, 0x01], "v4fnmaddss xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xbd, 0x72, 0x0a], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0xbd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x52, 0x0a], "vp4dpwssd zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x52, 0x4a, 0x01], "vp4dpwssd zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x53, 0x0a], "vp4dpwssds zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x53, 0x4a, 0x01], "vp4dpwssds zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x72, 0xca], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x9a, 0x0a], "v4fmaddps zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0x9a, 0x4a, 0x01], "v4fmaddps zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0xaa, 0x0a], "v4fnmaddps zmm1{k5}{z}, zmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0x7f, 0xcd, 0xaa, 0x4a, 0x01], "v4fnmaddps zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x0a], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}"); test_display(&[0x62, 0xf2, 0x7f, 0xdd, 0x72, 0x4a, 0x01], "vcvtne2ps2bf16 zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0x0a], "vpshufb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0x4a, 0x01], "vpshufb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x00, 0xca], "vpshufb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0x0a], "vpmaddubsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x04, 0xca], "vpmaddubsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0x0a], "vpmulhrsw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0b, 0xca], "vpmulhrsw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0x4a, 0x01], "vpermilpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x0d, 0xca], "vpermilpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0x0a], "vpsrlvw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0x4a, 0x01], "vpsrlvw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x10, 0xca], "vpsrlvw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0x0a], "vpsravw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0x4a, 0x01], "vpsravw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x11, 0xca], "vpsravw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0x0a], "vpsllvw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0x4a, 0x01], "vpsllvw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x12, 0xca], "vpsllvw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0x0a], "vprorvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0x4a, 0x01], "vprorvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x14, 0xca], "vprorvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0x0a], "vprolvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0x4a, 0x01], "vprolvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x15, 0xca], "vprolvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0x0a], "vpabsb xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0x4a, 0x01], "vpabsb xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1c, 0xca], "vpabsb xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0x0a], "vpabsw xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0x4a, 0x01], "vpabsw xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1d, 0xca], "vpabsw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0x0a], "vpabsq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0x4a, 0x01], "vpabsq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x1f, 0xca], "vpabsq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0x0a], "vpmovsxbw xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x20, 0xca], "vpmovsxbw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0x0a], "vpmovsxbd xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x21, 0xca], "vpmovsxbd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0x0a], "vpmovsxbq xmm1, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x22, 0xca], "vpmovsxbq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0x0a], "vpmovsxwd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x23, 0xca], "vpmovsxwd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x0a], "vpmovsxwq xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x24, 0xca], "vpmovsxwq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0x0a], "vptestmw k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0x4a, 0x01], "vptestmw k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x26, 0xca], "vptestmw k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0x0a], "vptestmq k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0x4a, 0x01], "vptestmq k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x27, 0xca], "vptestmq k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0x0a], "vpmuldq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0x4a, 0x01], "vpmuldq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x28, 0xca], "vpmuldq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x0a], "vpcmpeqq k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0x4a, 0x01], "vpcmpeqq k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x29, 0xca], "vpcmpeqq k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0x4a, 0x01], "vscalefpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x2c, 0xca], "vscalefpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0x0a], "vpmovzxbw xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x30, 0xca], "vpmovzxbw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0x0a], "vpmovzxbd xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x31, 0xca], "vpmovzxbd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0x0a], "vpmovzxbq xmm1, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x32, 0xca], "vpmovzxbq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0x0a], "vpmovzxwd xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x33, 0xca], "vpmovzxwd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0x0a], "vpmovzxwq xmm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x34, 0xca], "vpmovzxwq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0x0a], "vpcmpgtq k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0x4a, 0x01], "vpcmpgtq k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x37, 0xca], "vpcmpgtq k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0x0a], "vpminsb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0x4a, 0x01], "vpminsb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x38, 0xca], "vpminsb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0x0a], "vpminsq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0x4a, 0x01], "vpminsq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x39, 0xca], "vpminsq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0x0a], "vpminuw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0x4a, 0x01], "vpminuw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3a, 0xca], "vpminuw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0x0a], "vpminuq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0x4a, 0x01], "vpminuq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3b, 0xca], "vpminuq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0x0a], "vpmaxsb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3c, 0xca], "vpmaxsb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3d, 0xca], "vpmaxsq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0x0a], "vpmaxuw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3e, 0xca], "vpmaxuw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x3f, 0xca], "vpmaxuq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0x0a], "vpmullq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0x4a, 0x01], "vpmullq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x40, 0xca], "vpmullq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0x0a], "vgetexppd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0x4a, 0x01], "vgetexppd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x42, 0xca], "vgetexppd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0x0a], "vplzcntq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0x4a, 0x01], "vplzcntq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x44, 0xca], "vplzcntq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0x4a, 0x01], "vpsrlvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x45, 0xca], "vpsrlvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0x0a], "vpsravq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0x4a, 0x01], "vpsravq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x46, 0xca], "vpsravq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0x0a], "vpsllvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0x4a, 0x01], "vpsllvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x47, 0xca], "vpsllvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0x0a], "vrcp14pd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4c, 0xca], "vrcp14pd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0x0a], "vrsqrt14pd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x4e, 0xca], "vrsqrt14pd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0x0a], "vpopcntw xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0x4a, 0x01], "vpopcntw xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x54, 0xca], "vpopcntw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0x0a], "vpopcntq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0x4a, 0x01], "vpopcntq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x55, 0xca], "vpopcntq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0x0a], "vpbroadcastq xmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x59, 0xca], "vpbroadcastq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0x0a], "vpexpandw xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0x4a, 0x01], "vpexpandw xmm1, xmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x62, 0xca], "vpexpandw xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0x0a], "vpcompressw xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0x4a, 0x01], "vpcompressw xmmword [bp + si * 1 + 0x2], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x63, 0xca], "vpcompressw xmm2, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0x0a], "vpblendmq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0x4a, 0x01], "vpblendmq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x64, 0xca], "vpblendmq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0x0a], "vblendmpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0x4a, 0x01], "vblendmpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x65, 0xca], "vblendmpd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0x0a], "vpblendmw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0x4a, 0x01], "vpblendmw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x66, 0xca], "vpblendmw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0x0a], "vpshldvw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0x4a, 0x01], "vpshldvw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x70, 0xca], "vpshldvw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0x0a], "vpshldvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0x4a, 0x01], "vpshldvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x71, 0xca], "vpshldvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0x0a], "vpshrdvw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0x4a, 0x01], "vpshrdvw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x72, 0xca], "vpshrdvw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0x4a, 0x01], "vpshrdvq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x73, 0xca], "vpshrdvq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0x0a], "vpermi2w xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0x4a, 0x01], "vpermi2w xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x75, 0xca], "vpermi2w xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0x0a], "vpermi2q xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0x4a, 0x01], "vpermi2q xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x76, 0xca], "vpermi2q xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0x4a, 0x01], "vpermi2pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x77, 0xca], "vpermi2pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7c, 0xca], "vpbroadcastd xmm1, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0x0a], "vpermt2w xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0x4a, 0x01], "vpermt2w xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7d, 0xca], "vpermt2w xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0x4a, 0x01], "vpermt2q xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7e, 0xca], "vpermt2q xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x7f, 0xca], "vpermt2pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x83, 0xca], "vpmultishiftqb xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0x0a], "vexpandpd xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0x4a, 0x01], "vexpandpd xmm1, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x88, 0xca], "vexpandpd xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0x0a], "vpexpandq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0x4a, 0x01], "vpexpandq xmm1, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x89, 0xca], "vpexpandq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0x0a], "vcompresspd xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0x4a, 0x01], "vcompresspd xmmword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8a, 0xca], "vcompresspd xmm2, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0x0a], "vpcompressq xmmword [bp + si * 1], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0x4a, 0x01], "vpcompressq xmmword [bp + si * 1 + 0x8], xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8b, 0xca], "vpcompressq xmm2, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0x0a], "vpermw xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0x4a, 0x01], "vpermw xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x8d, 0xca], "vpermw xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x96, 0xca], "vfmaddsub132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x97, 0xca], "vfmsubadd132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x98, 0xca], "vfmadd132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9a, 0xca], "vfmsub132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9c, 0xca], "vfnmadd132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0x9e, 0xca], "vfnmsub132pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa6, 0xca], "vfmaddsub213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa7, 0xca], "vfmsubadd213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xa8, 0xca], "vfmadd213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xaa, 0xca], "vfmsub213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xac, 0xca], "vfnmadd213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xae, 0xca], "vfnmsub213pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb4, 0xca], "vpmadd52luq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb5, 0xca], "vpmadd52huq xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb6, 0xca], "vfmaddsub231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb7, 0xca], "vfmsubadd231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xb8, 0xca], "vfmadd231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xba, 0xca], "vfmsub231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbc, 0xca], "vfnmadd231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xbe, 0xca], "vfnmsub231pd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0x0a], "vpconflictq xmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0x4a, 0x01], "vpconflictq xmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xc4, 0xca], "vpconflictq xmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0x0a], "vaesenc xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0x4a, 0x01], "vaesenc xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0x0a], "vaesenclast xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0x4a, 0x01], "vaesenclast xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdd, 0xca], "vaesenclast xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0x0a], "vaesdec xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0x4a, 0x01], "vaesdec xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xde, 0xca], "vaesdec xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0x0a], "vaesdeclast xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0x4a, 0x01], "vaesdeclast xmm1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x08, 0xdf, 0xca], "vaesdeclast xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0x0a], "vpshufb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0x4a, 0x01], "vpshufb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x00, 0xca], "vpshufb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x04, 0xca], "vpmaddubsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x0d, 0xca], "vpermilpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0x0a], "vpsrlvw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0x4a, 0x01], "vpsrlvw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x10, 0xca], "vpsrlvw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0x0a], "vpsravw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0x4a, 0x01], "vpsravw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x11, 0xca], "vpsravw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x0a], "vpsllvw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0x4a, 0x01], "vpsllvw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x12, 0xca], "vpsllvw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x14, 0xca], "vprorvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x15, 0xca], "vprolvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0x0a], "vpabsb xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0x4a, 0x01], "vpabsb xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1c, 0xca], "vpabsb xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0x0a], "vpabsw xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0x4a, 0x01], "vpabsw xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1d, 0xca], "vpabsw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0x0a], "vpabsq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x1f, 0xca], "vpabsq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x20, 0xca], "vpmovsxbw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x21, 0xca], "vpmovsxbd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1{k5}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x22, 0xca], "vpmovsxbq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x23, 0xca], "vpmovsxwd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x24, 0xca], "vpmovsxwq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0x0a], "vptestmw k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x26, 0xca], "vptestmw k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x27, 0xca], "vptestmq k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x28, 0xca], "vpmuldq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x29, 0xca], "vpcmpeqq k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x2c, 0xca], "vscalefpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x30, 0xca], "vpmovzxbw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x31, 0xca], "vpmovzxbd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1{k5}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x32, 0xca], "vpmovzxbq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x33, 0xca], "vpmovzxwd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x34, 0xca], "vpmovzxwq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x37, 0xca], "vpcmpgtq k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0x0a], "vpminsb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0x4a, 0x01], "vpminsb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x38, 0xca], "vpminsb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x39, 0xca], "vpminsq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0x0a], "vpminuw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0x4a, 0x01], "vpminuw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3a, 0xca], "vpminuw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3b, 0xca], "vpminuq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3c, 0xca], "vpmaxsb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3d, 0xca], "vpmaxsq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3e, 0xca], "vpmaxuw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x3f, 0xca], "vpmaxuq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x40, 0xca], "vpmullq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0x0a], "vgetexppd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x42, 0xca], "vgetexppd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0x0a], "vplzcntq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x44, 0xca], "vplzcntq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x45, 0xca], "vpsrlvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x46, 0xca], "vpsravq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x47, 0xca], "vpsllvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4c, 0xca], "vrcp14pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0x0a], "vpopcntw xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0x4a, 0x01], "vpopcntw xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x54, 0xca], "vpopcntw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0x0a], "vpopcntq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x55, 0xca], "vpopcntq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x59, 0xca], "vpbroadcastq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0x0a], "vpexpandw xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0x4a, 0x01], "vpexpandw xmm1{k5}, xmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x62, 0xca], "vpexpandw xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0x0a], "vpcompressw xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0x4a, 0x01], "vpcompressw xmmword [bp + si * 1 + 0x2]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x63, 0xca], "vpcompressw xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x64, 0xca], "vpblendmq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x65, 0xca], "vblendmpd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0x0a], "vpblendmw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0x4a, 0x01], "vpblendmw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x66, 0xca], "vpblendmw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0x0a], "vpshldvw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0x4a, 0x01], "vpshldvw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x70, 0xca], "vpshldvw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x71, 0xca], "vpshldvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0x0a], "vpshrdvw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0x4a, 0x01], "vpshrdvw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x72, 0xca], "vpshrdvw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x73, 0xca], "vpshrdvq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0x0a], "vpermi2w xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0x4a, 0x01], "vpermi2w xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x75, 0xca], "vpermi2w xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x76, 0xca], "vpermi2q xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x77, 0xca], "vpermi2pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0x0a], "vpermt2w xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0x4a, 0x01], "vpermt2w xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7d, 0xca], "vpermt2w xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7e, 0xca], "vpermt2q xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x7f, 0xca], "vpermt2pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0x0a], "vexpandpd xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0x4a, 0x01], "vexpandpd xmm1{k5}, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x88, 0xca], "vexpandpd xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0x0a], "vpexpandq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0x4a, 0x01], "vpexpandq xmm1{k5}, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x89, 0xca], "vpexpandq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0x0a], "vcompresspd xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0x4a, 0x01], "vcompresspd xmmword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8a, 0xca], "vcompresspd xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0x0a], "vpcompressq xmmword [bp + si * 1]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0x4a, 0x01], "vpcompressq xmmword [bp + si * 1 + 0x8]{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8b, 0xca], "vpcompressq xmm2{k5}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0x0a], "vpermw xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0x4a, 0x01], "vpermw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x8d, 0xca], "vpermw xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x98, 0xca], "vfmadd132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xba, 0xca], "vfmsub231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x0d, 0xc4, 0xca], "vpconflictq xmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x0d, 0x0a], "vpermilpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x0d, 0x4a, 0x01], "vpermilpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x14, 0x0a], "vprorvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x14, 0x4a, 0x01], "vprorvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x15, 0x0a], "vprolvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x15, 0x4a, 0x01], "vprolvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x1f, 0x0a], "vpabsq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x1f, 0x4a, 0x01], "vpabsq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x0a], "vptestmq k1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x27, 0x4a, 0x01], "vptestmq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x28, 0x0a], "vpmuldq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x28, 0x4a, 0x01], "vpmuldq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x29, 0x0a], "vpcmpeqq k1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x29, 0x4a, 0x01], "vpcmpeqq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0x0a], "vscalefpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0x4a, 0x01], "vscalefpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x2c, 0xca], "vscalefpd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x2d, 0xca], "vscalefsd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x37, 0x0a], "vpcmpgtq k1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x37, 0x4a, 0x01], "vpcmpgtq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x39, 0x0a], "vpminsq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x39, 0x4a, 0x01], "vpminsq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3b, 0x0a], "vpminuq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3b, 0x4a, 0x01], "vpminuq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3d, 0x0a], "vpmaxsq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3f, 0x0a], "vpmaxuq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x40, 0x0a], "vpmullq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x40, 0x4a, 0x01], "vpmullq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x42, 0x0a], "vgetexppd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x42, 0x4a, 0x01], "vgetexppd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x44, 0x0a], "vplzcntq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x44, 0x4a, 0x01], "vplzcntq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x45, 0x4a, 0x01], "vpsrlvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x46, 0x0a], "vpsravq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x46, 0x4a, 0x01], "vpsravq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x47, 0x0a], "vpsllvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x47, 0x4a, 0x01], "vpsllvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x4c, 0x0a], "vrcp14pd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x4e, 0x0a], "vrsqrt14pd xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x55, 0x0a], "vpopcntq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x55, 0x4a, 0x01], "vpopcntq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x64, 0x0a], "vpblendmq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x64, 0x4a, 0x01], "vpblendmq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x65, 0x0a], "vblendmpd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x65, 0x4a, 0x01], "vblendmpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x71, 0x0a], "vpshldvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x71, 0x4a, 0x01], "vpshldvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x73, 0x0a], "vpshrdvq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x73, 0x4a, 0x01], "vpshrdvq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x76, 0x0a], "vpermi2q xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x76, 0x4a, 0x01], "vpermi2q xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x77, 0x0a], "vpermi2pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x77, 0x4a, 0x01], "vpermi2pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x7e, 0x0a], "vpermt2q xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x7e, 0x4a, 0x01], "vpermt2q xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x7f, 0x0a], "vpermt2pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x83, 0x0a], "vpmultishiftqb xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0x0a], "vfmaddsub132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x96, 0xca], "vfmaddsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0x0a], "vfmsubadd132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x97, 0xca], "vfmsubadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0x0a], "vfmadd132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x98, 0xca], "vfmadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x99, 0xca], "vfmadd132sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0x0a], "vfmsub132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9a, 0xca], "vfmsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9b, 0xca], "vfmsub132sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0x0a], "vfnmadd132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9c, 0xca], "vfnmadd132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9d, 0xca], "vfnmadd132sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0x0a], "vfnmsub132pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9e, 0xca], "vfnmsub132pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0x9f, 0xca], "vfnmsub132sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0x0a], "vfmaddsub213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa6, 0xca], "vfmaddsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0x0a], "vfmsubadd213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa7, 0xca], "vfmsubadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0x0a], "vfmadd213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa8, 0xca], "vfmadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xa9, 0xca], "vfmadd213sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0x0a], "vfmsub213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xaa, 0xca], "vfmsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xab, 0xca], "vfmsub213sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0x0a], "vfnmadd213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xac, 0xca], "vfnmadd213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xad, 0xca], "vfnmadd213sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0x0a], "vfnmsub213pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xae, 0xca], "vfnmsub213pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xaf, 0xca], "vfnmsub213sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb4, 0x0a], "vpmadd52luq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb5, 0x0a], "vpmadd52huq xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0x0a], "vfmaddsub231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb6, 0xca], "vfmaddsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0x0a], "vfmsubadd231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb7, 0xca], "vfmsubadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0x0a], "vfmadd231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb8, 0xca], "vfmadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xb9, 0xca], "vfmadd231sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0x0a], "vfmsub231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xba, 0xca], "vfmsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbb, 0xca], "vfmsub231sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0x0a], "vfnmadd231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbc, 0xca], "vfnmadd231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbd, 0xca], "vfnmadd231sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0x0a], "vfnmsub231pd xmm1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbe, 0xca], "vfnmsub231pd zmm1{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xbf, 0xca], "vfnmsub231sd xmm1{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xc4, 0x0a], "vpconflictq xmm1, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x18, 0xc4, 0x4a, 0x01], "vpconflictq xmm1, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x0d, 0x0a], "vpermilpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x14, 0x0a], "vprorvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x15, 0x0a], "vprolvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x1f, 0x0a], "vpabsq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x0a], "vptestmq k1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x28, 0x0a], "vpmuldq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x29, 0x0a], "vpcmpeqq k1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0x0a], "vscalefpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x37, 0x0a], "vpcmpgtq k1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x39, 0x0a], "vpminsq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3b, 0x0a], "vpminuq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x40, 0x0a], "vpmullq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x42, 0x0a], "vgetexppd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x44, 0x0a], "vplzcntq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x45, 0x0a], "vpsrlvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x46, 0x0a], "vpsravq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x47, 0x0a], "vpsllvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x55, 0x0a], "vpopcntq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x64, 0x0a], "vpblendmq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x65, 0x0a], "vblendmpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x71, 0x0a], "vpshldvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x73, 0x0a], "vpshrdvq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x76, 0x0a], "vpermi2q xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x77, 0x0a], "vpermi2pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x7e, 0x0a], "vpermt2q xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xc4, 0x0a], "vpconflictq xmm1{k5}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x1d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0x0a], "vpshufb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0x4a, 0x01], "vpshufb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x00, 0xca], "vpshufb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0x0a], "vpmaddubsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x04, 0xca], "vpmaddubsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0x0a], "vpmulhrsw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0b, 0xca], "vpmulhrsw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0x4a, 0x01], "vpermilpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x0d, 0xca], "vpermilpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0x0a], "vpsrlvw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0x4a, 0x01], "vpsrlvw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x10, 0xca], "vpsrlvw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0x0a], "vpsravw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0x4a, 0x01], "vpsravw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x11, 0xca], "vpsravw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0x0a], "vpsllvw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0x4a, 0x01], "vpsllvw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x12, 0xca], "vpsllvw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0x0a], "vprorvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0x4a, 0x01], "vprorvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x14, 0xca], "vprorvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0x0a], "vprolvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0x4a, 0x01], "vprolvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x15, 0xca], "vprolvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0x0a], "vpermpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0x4a, 0x01], "vpermpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x16, 0xca], "vpermpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0x0a], "vbroadcastsd ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x19, 0xca], "vbroadcastsd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1a, 0x0a], "vbroadcastf64x2 ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0x0a], "vpabsb ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0x4a, 0x01], "vpabsb ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1c, 0xca], "vpabsb ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0x0a], "vpabsw ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0x4a, 0x01], "vpabsw ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1d, 0xca], "vpabsw ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0x0a], "vpabsq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0x4a, 0x01], "vpabsq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x1f, 0xca], "vpabsq ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0x0a], "vpmovsxbw ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x20, 0xca], "vpmovsxbw ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0x0a], "vpmovsxbd ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x21, 0xca], "vpmovsxbd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0x0a], "vpmovsxbq ymm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x22, 0xca], "vpmovsxbq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0x0a], "vpmovsxwd ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x23, 0xca], "vpmovsxwd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0x0a], "vpmovsxwq ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x24, 0xca], "vpmovsxwq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x0a], "vptestmw k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0x4a, 0x01], "vptestmw k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x26, 0xca], "vptestmw k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0x0a], "vptestmq k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0x4a, 0x01], "vptestmq k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x27, 0xca], "vptestmq k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0x0a], "vpmuldq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0x4a, 0x01], "vpmuldq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x0a], "vpcmpeqq k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0x4a, 0x01], "vpcmpeqq k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x29, 0xca], "vpcmpeqq k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0x4a, 0x01], "vscalefpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2c, 0xca], "vscalefpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x0a], "vscalefsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0x4a, 0x01], "vscalefsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x2d, 0xca], "vscalefsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0x0a], "vpmovzxbw ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x30, 0xca], "vpmovzxbw ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0x0a], "vpmovzxbd ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x31, 0xca], "vpmovzxbd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0x0a], "vpmovzxbq ymm1, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x32, 0xca], "vpmovzxbq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0x0a], "vpmovzxwd ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x33, 0xca], "vpmovzxwd ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0x0a], "vpmovzxwq ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x34, 0xca], "vpmovzxwq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0x0a], "vpermq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0x4a, 0x01], "vpermq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x36, 0xca], "vpermq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0x0a], "vpcmpgtq k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0x4a, 0x01], "vpcmpgtq k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x37, 0xca], "vpcmpgtq k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0x0a], "vpminsb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0x4a, 0x01], "vpminsb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x38, 0xca], "vpminsb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0x0a], "vpminsq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0x4a, 0x01], "vpminsq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x39, 0xca], "vpminsq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0x0a], "vpminuw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0x4a, 0x01], "vpminuw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3a, 0xca], "vpminuw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0x0a], "vpminuq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0x4a, 0x01], "vpminuq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3b, 0xca], "vpminuq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0x0a], "vpmaxsb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3c, 0xca], "vpmaxsb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3d, 0xca], "vpmaxsq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0x0a], "vpmaxuw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3e, 0xca], "vpmaxuw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x3f, 0xca], "vpmaxuq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0x0a], "vpmullq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0x4a, 0x01], "vpmullq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x40, 0xca], "vpmullq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0x0a], "vgetexppd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0x4a, 0x01], "vgetexppd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x42, 0xca], "vgetexppd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0x0a], "vgetexpsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0x4a, 0x01], "vgetexpsd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x43, 0xca], "vgetexpsd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0x0a], "vplzcntq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0x4a, 0x01], "vplzcntq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x44, 0xca], "vplzcntq ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0x4a, 0x01], "vpsrlvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x45, 0xca], "vpsrlvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0x0a], "vpsravq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0x4a, 0x01], "vpsravq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x46, 0xca], "vpsravq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0x0a], "vpsllvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0x4a, 0x01], "vpsllvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x47, 0xca], "vpsllvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0x0a], "vrcp14pd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4c, 0xca], "vrcp14pd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0x0a], "vrcp14sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4d, 0xca], "vrcp14sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0x0a], "vrsqrt14pd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4e, 0xca], "vrsqrt14pd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0x0a], "vrsqrt14sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x4f, 0xca], "vrsqrt14sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0x0a], "vpopcntw ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0x4a, 0x01], "vpopcntw ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x54, 0xca], "vpopcntw ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0x0a], "vpopcntq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0x4a, 0x01], "vpopcntq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x55, 0xca], "vpopcntq ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0x0a], "vpbroadcastq ymm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x59, 0xca], "vpbroadcastq ymm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x5a, 0x0a], "vbroadcasti64x2 ymm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0x0a], "vpexpandw ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0x4a, 0x01], "vpexpandw ymm1, ymmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x62, 0xca], "vpexpandw ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0x0a], "vpcompressw ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0x4a, 0x01], "vpcompressw ymmword [bp + si * 1 + 0x2], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x63, 0xca], "vpcompressw ymm2, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0x0a], "vpblendmq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0x4a, 0x01], "vpblendmq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x64, 0xca], "vpblendmq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0x0a], "vblendmpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0x4a, 0x01], "vblendmpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x65, 0xca], "vblendmpd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0x0a], "vpblendmw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0x4a, 0x01], "vpblendmw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x66, 0xca], "vpblendmw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0x0a], "vpshldvw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0x4a, 0x01], "vpshldvw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x70, 0xca], "vpshldvw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0x0a], "vpshldvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0x4a, 0x01], "vpshldvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x71, 0xca], "vpshldvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0x0a], "vpshrdvw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0x4a, 0x01], "vpshrdvw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x72, 0xca], "vpshrdvw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0x4a, 0x01], "vpshrdvq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x73, 0xca], "vpshrdvq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0x0a], "vpermi2w ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0x4a, 0x01], "vpermi2w ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x75, 0xca], "vpermi2w ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0x0a], "vpermi2q ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0x4a, 0x01], "vpermi2q ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x76, 0xca], "vpermi2q ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0x4a, 0x01], "vpermi2pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x77, 0xca], "vpermi2pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7c, 0xca], "vpbroadcastd ymm1, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0x0a], "vpermt2w ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0x4a, 0x01], "vpermt2w ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7d, 0xca], "vpermt2w ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0x4a, 0x01], "vpermt2q ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7e, 0xca], "vpermt2q ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x7f, 0xca], "vpermt2pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x83, 0xca], "vpmultishiftqb ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0x0a], "vexpandpd ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0x4a, 0x01], "vexpandpd ymm1, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x88, 0xca], "vexpandpd ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0x0a], "vpexpandq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0x4a, 0x01], "vpexpandq ymm1, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x89, 0xca], "vpexpandq ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0x0a], "vcompresspd ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0x4a, 0x01], "vcompresspd ymmword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8a, 0xca], "vcompresspd ymm2, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0x0a], "vpcompressq ymmword [bp + si * 1], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0x4a, 0x01], "vpcompressq ymmword [bp + si * 1 + 0x8], ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8b, 0xca], "vpcompressq ymm2, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0x0a], "vpermw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0x4a, 0x01], "vpermw ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x8d, 0xca], "vpermw ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x96, 0xca], "vfmaddsub132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x97, 0xca], "vfmsubadd132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x98, 0xca], "vfmadd132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0x0a], "vfmadd132sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x99, 0xca], "vfmadd132sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9a, 0xca], "vfmsub132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0x0a], "vfmsub132sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9b, 0xca], "vfmsub132sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9c, 0xca], "vfnmadd132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0x0a], "vfnmadd132sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9d, 0xca], "vfnmadd132sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9e, 0xca], "vfnmsub132pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0x0a], "vfnmsub132sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0x9f, 0xca], "vfnmsub132sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa6, 0xca], "vfmaddsub213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa7, 0xca], "vfmsubadd213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa8, 0xca], "vfmadd213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0x0a], "vfmadd213sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xa9, 0xca], "vfmadd213sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaa, 0xca], "vfmsub213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0x0a], "vfmsub213sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xab, 0xca], "vfmsub213sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xac, 0xca], "vfnmadd213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0x0a], "vfnmadd213sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xad, 0xca], "vfnmadd213sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xae, 0xca], "vfnmsub213pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0x0a], "vfnmsub213sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xaf, 0xca], "vfnmsub213sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb4, 0xca], "vpmadd52luq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb5, 0xca], "vpmadd52huq ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb6, 0xca], "vfmaddsub231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb7, 0xca], "vfmsubadd231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb8, 0xca], "vfmadd231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0x0a], "vfmadd231sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xb9, 0xca], "vfmadd231sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xba, 0xca], "vfmsub231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0x0a], "vfmsub231sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbb, 0xca], "vfmsub231sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbc, 0xca], "vfnmadd231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0x0a], "vfnmadd231sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbd, 0xca], "vfnmadd231sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbe, 0xca], "vfnmsub231pd ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0x0a], "vfnmsub231sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xbf, 0xca], "vfnmsub231sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0x0a], "vpconflictq ymm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0x4a, 0x01], "vpconflictq ymm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xc4, 0xca], "vpconflictq ymm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0x0a], "vrcp28sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcb, 0xca], "vrcp28sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0x0a], "vrsqrt28sd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xcd, 0xca], "vrsqrt28sd xmm1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x0a], "vaesenc ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0x4a, 0x01], "vaesenc ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0x0a], "vaesenclast ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0x4a, 0x01], "vaesenclast ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdd, 0xca], "vaesenclast ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0x0a], "vaesdec ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0x4a, 0x01], "vaesdec ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xde, 0xca], "vaesdec ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0x0a], "vaesdeclast ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0x4a, 0x01], "vaesdeclast ymm1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x28, 0xdf, 0xca], "vaesdeclast ymm1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0x0a], "vpshufb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0x4a, 0x01], "vpshufb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x00, 0xca], "vpshufb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0x0a], "vpmaddubsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x04, 0xca], "vpmaddubsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0b, 0xca], "vpmulhrsw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x0d, 0xca], "vpermilpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0x0a], "vpsrlvw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0x4a, 0x01], "vpsrlvw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x10, 0xca], "vpsrlvw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0x0a], "vpsravw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0x4a, 0x01], "vpsravw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x11, 0xca], "vpsravw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0x0a], "vpsllvw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0x4a, 0x01], "vpsllvw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x12, 0xca], "vpsllvw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x14, 0xca], "vprorvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x15, 0xca], "vprolvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x16, 0xca], "vpermpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0x0a], "vbroadcastsd ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x19, 0xca], "vbroadcastsd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0x0a], "vpabsb ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0x4a, 0x01], "vpabsb ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1c, 0xca], "vpabsb ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0x0a], "vpabsw ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0x4a, 0x01], "vpabsw ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1d, 0xca], "vpabsw ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0x0a], "vpabsq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x1f, 0xca], "vpabsq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0x0a], "vpmovsxbw ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x20, 0xca], "vpmovsxbw ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0x0a], "vpmovsxbd ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x21, 0xca], "vpmovsxbd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0x0a], "vpmovsxbq ymm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x22, 0xca], "vpmovsxbq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0x0a], "vpmovsxwd ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x23, 0xca], "vpmovsxwd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0x0a], "vpmovsxwq ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x24, 0xca], "vpmovsxwq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x0a], "vptestmw k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x26, 0xca], "vptestmw k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x27, 0xca], "vptestmq k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x28, 0xca], "vpmuldq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x29, 0xca], "vpcmpeqq k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2c, 0xca], "vscalefpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x0a], "vscalefsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0x4a, 0x01], "vscalefsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x2d, 0xca], "vscalefsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0x0a], "vpmovzxbw ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x30, 0xca], "vpmovzxbw ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0x0a], "vpmovzxbd ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x31, 0xca], "vpmovzxbd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0x0a], "vpmovzxbq ymm1{k5}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1{k5}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x32, 0xca], "vpmovzxbq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0x0a], "vpmovzxwd ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x33, 0xca], "vpmovzxwd ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0x0a], "vpmovzxwq ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x34, 0xca], "vpmovzxwq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x36, 0xca], "vpermq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x37, 0xca], "vpcmpgtq k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0x0a], "vpminsb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0x4a, 0x01], "vpminsb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x38, 0xca], "vpminsb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x39, 0xca], "vpminsq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0x0a], "vpminuw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0x4a, 0x01], "vpminuw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3a, 0xca], "vpminuw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3b, 0xca], "vpminuq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0x0a], "vpmaxsb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3c, 0xca], "vpmaxsb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3d, 0xca], "vpmaxsq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0x0a], "vpmaxuw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3e, 0xca], "vpmaxuw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x3f, 0xca], "vpmaxuq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x40, 0xca], "vpmullq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0x0a], "vgetexppd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x42, 0xca], "vgetexppd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0x0a], "vgetexpsd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0x4a, 0x01], "vgetexpsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x43, 0xca], "vgetexpsd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0x0a], "vplzcntq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x44, 0xca], "vplzcntq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x45, 0xca], "vpsrlvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x46, 0xca], "vpsravq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x47, 0xca], "vpsllvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4c, 0xca], "vrcp14pd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0x0a], "vrcp14sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4d, 0xca], "vrcp14sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0x0a], "vpopcntw ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0x4a, 0x01], "vpopcntw ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x54, 0xca], "vpopcntw ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0x0a], "vpopcntq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x55, 0xca], "vpopcntq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0x0a], "vpbroadcastq ymm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x59, 0xca], "vpbroadcastq ymm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0x0a], "vpexpandw ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0x4a, 0x01], "vpexpandw ymm1{k5}, ymmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x62, 0xca], "vpexpandw ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0x0a], "vpcompressw ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0x4a, 0x01], "vpcompressw ymmword [bp + si * 1 + 0x2]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x63, 0xca], "vpcompressw ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x64, 0xca], "vpblendmq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x65, 0xca], "vblendmpd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0x0a], "vpblendmw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0x4a, 0x01], "vpblendmw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x66, 0xca], "vpblendmw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0x0a], "vpshldvw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0x4a, 0x01], "vpshldvw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x70, 0xca], "vpshldvw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x71, 0xca], "vpshldvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0x0a], "vpshrdvw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0x4a, 0x01], "vpshrdvw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x72, 0xca], "vpshrdvw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x73, 0xca], "vpshrdvq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0x0a], "vpermi2w ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0x4a, 0x01], "vpermi2w ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x75, 0xca], "vpermi2w ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x76, 0xca], "vpermi2q ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x77, 0xca], "vpermi2pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7c, 0xca], "vpbroadcastd ymm1{k5}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0x0a], "vpermt2w ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0x4a, 0x01], "vpermt2w ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7d, 0xca], "vpermt2w ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7e, 0xca], "vpermt2q ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x7f, 0xca], "vpermt2pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x83, 0xca], "vpmultishiftqb ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0x0a], "vexpandpd ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0x4a, 0x01], "vexpandpd ymm1{k5}, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x88, 0xca], "vexpandpd ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0x0a], "vpexpandq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0x4a, 0x01], "vpexpandq ymm1{k5}, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x89, 0xca], "vpexpandq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0x0a], "vcompresspd ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0x4a, 0x01], "vcompresspd ymmword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8a, 0xca], "vcompresspd ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0x0a], "vpcompressq ymmword [bp + si * 1]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0x4a, 0x01], "vpcompressq ymmword [bp + si * 1 + 0x8]{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8b, 0xca], "vpcompressq ymm2{k5}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0x0a], "vpermw ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0x4a, 0x01], "vpermw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x8d, 0xca], "vpermw ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x98, 0xca], "vfmadd132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0x0a], "vfmadd132sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x99, 0xca], "vfmadd132sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9a, 0xca], "vfmsub132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa8, 0xca], "vfmadd213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaa, 0xca], "vfmsub213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0x0a], "vfmsub213sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xab, 0xca], "vfmsub213sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xac, 0xca], "vfnmadd213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xae, 0xca], "vfnmsub213pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb4, 0xca], "vpmadd52luq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb5, 0xca], "vpmadd52huq ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb8, 0xca], "vfmadd231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xba, 0xca], "vfmsub231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xc4, 0xca], "vpconflictq ymm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0x0a], "vrcp28sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcb, 0xca], "vrcp28sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x2d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x0d, 0x0a], "vpermilpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x0d, 0x4a, 0x01], "vpermilpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x14, 0x0a], "vprorvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x14, 0x4a, 0x01], "vprorvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x15, 0x0a], "vprolvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x15, 0x4a, 0x01], "vprolvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x16, 0x0a], "vpermpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x16, 0x4a, 0x01], "vpermpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x1f, 0x0a], "vpabsq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x1f, 0x4a, 0x01], "vpabsq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x27, 0x0a], "vptestmq k1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x27, 0x4a, 0x01], "vptestmq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x0a], "vpmuldq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x28, 0x4a, 0x01], "vpmuldq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x29, 0x0a], "vpcmpeqq k1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x29, 0x4a, 0x01], "vpcmpeqq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0x0a], "vscalefpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0x4a, 0x01], "vscalefpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x2c, 0xca], "vscalefpd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x2d, 0xca], "vscalefsd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x36, 0x0a], "vpermq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x36, 0x4a, 0x01], "vpermq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x37, 0x0a], "vpcmpgtq k1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x37, 0x4a, 0x01], "vpcmpgtq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x39, 0x0a], "vpminsq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x39, 0x4a, 0x01], "vpminsq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3b, 0x0a], "vpminuq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3b, 0x4a, 0x01], "vpminuq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3d, 0x0a], "vpmaxsq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3f, 0x0a], "vpmaxuq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x40, 0x0a], "vpmullq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x40, 0x4a, 0x01], "vpmullq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x42, 0x0a], "vgetexppd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x42, 0x4a, 0x01], "vgetexppd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x44, 0x0a], "vplzcntq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x44, 0x4a, 0x01], "vplzcntq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x45, 0x4a, 0x01], "vpsrlvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x46, 0x0a], "vpsravq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x46, 0x4a, 0x01], "vpsravq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x47, 0x0a], "vpsllvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x47, 0x4a, 0x01], "vpsllvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x4c, 0x0a], "vrcp14pd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x4e, 0x0a], "vrsqrt14pd ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x55, 0x0a], "vpopcntq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x55, 0x4a, 0x01], "vpopcntq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x64, 0x0a], "vpblendmq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x64, 0x4a, 0x01], "vpblendmq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x65, 0x0a], "vblendmpd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x65, 0x4a, 0x01], "vblendmpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x71, 0x0a], "vpshldvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x71, 0x4a, 0x01], "vpshldvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x73, 0x0a], "vpshrdvq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x73, 0x4a, 0x01], "vpshrdvq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x76, 0x0a], "vpermi2q ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x76, 0x4a, 0x01], "vpermi2q ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x77, 0x0a], "vpermi2pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x77, 0x4a, 0x01], "vpermi2pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x7e, 0x0a], "vpermt2q ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x7e, 0x4a, 0x01], "vpermt2q ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x7f, 0x0a], "vpermt2pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x83, 0x0a], "vpmultishiftqb ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0x0a], "vfmaddsub132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x96, 0xca], "vfmaddsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0x0a], "vfmsubadd132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x97, 0xca], "vfmsubadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0x0a], "vfmadd132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x98, 0xca], "vfmadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x99, 0xca], "vfmadd132sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0x0a], "vfmsub132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9a, 0xca], "vfmsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9b, 0xca], "vfmsub132sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0x0a], "vfnmadd132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9c, 0xca], "vfnmadd132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9d, 0xca], "vfnmadd132sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0x0a], "vfnmsub132pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9e, 0xca], "vfnmsub132pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0x9f, 0xca], "vfnmsub132sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0x0a], "vfmaddsub213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa6, 0xca], "vfmaddsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0x0a], "vfmsubadd213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa7, 0xca], "vfmsubadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0x0a], "vfmadd213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa8, 0xca], "vfmadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xa9, 0xca], "vfmadd213sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0x0a], "vfmsub213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xaa, 0xca], "vfmsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xab, 0xca], "vfmsub213sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0x0a], "vfnmadd213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xac, 0xca], "vfnmadd213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xad, 0xca], "vfnmadd213sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0x0a], "vfnmsub213pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xae, 0xca], "vfnmsub213pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xaf, 0xca], "vfnmsub213sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb4, 0x0a], "vpmadd52luq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb5, 0x0a], "vpmadd52huq ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0x0a], "vfmaddsub231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb6, 0xca], "vfmaddsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0x0a], "vfmsubadd231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb7, 0xca], "vfmsubadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0x0a], "vfmadd231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb8, 0xca], "vfmadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xb9, 0xca], "vfmadd231sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0x0a], "vfmsub231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xba, 0xca], "vfmsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbb, 0xca], "vfmsub231sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0x0a], "vfnmadd231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbc, 0xca], "vfnmadd231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbd, 0xca], "vfnmadd231sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0x0a], "vfnmsub231pd ymm1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbe, 0xca], "vfnmsub231pd zmm1{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xbf, 0xca], "vfnmsub231sd xmm1{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xc4, 0x0a], "vpconflictq ymm1, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x38, 0xc4, 0x4a, 0x01], "vpconflictq ymm1, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x0d, 0x0a], "vpermilpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x14, 0x0a], "vprorvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x15, 0x0a], "vprolvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x16, 0x0a], "vpermpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x1f, 0x0a], "vpabsq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x27, 0x0a], "vptestmq k1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x0a], "vpmuldq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x0a], "vpcmpeqq k1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0x0a], "vscalefpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x36, 0x0a], "vpermq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x37, 0x0a], "vpcmpgtq k1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x39, 0x0a], "vpminsq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3b, 0x0a], "vpminuq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3d, 0x0a], "vpmaxsq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3f, 0x0a], "vpmaxuq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x40, 0x0a], "vpmullq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x42, 0x0a], "vgetexppd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x44, 0x0a], "vplzcntq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x45, 0x0a], "vpsrlvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x46, 0x0a], "vpsravq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x47, 0x0a], "vpsllvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x4c, 0x0a], "vrcp14pd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x55, 0x0a], "vpopcntq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x64, 0x0a], "vpblendmq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x65, 0x0a], "vblendmpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x71, 0x0a], "vpshldvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x73, 0x0a], "vpshrdvq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x76, 0x0a], "vpermi2q ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x77, 0x0a], "vpermi2pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x7e, 0x0a], "vpermt2q ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x7f, 0x0a], "vpermt2pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0x0a], "vfmadd132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0x0a], "vfmsub231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xc4, 0x0a], "vpconflictq ymm1{k5}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x3d, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0x0a], "vpshufb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0x4a, 0x01], "vpshufb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x00, 0xca], "vpshufb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0x0a], "vpmaddubsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x04, 0xca], "vpmaddubsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0x0a], "vpmulhrsw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0b, 0xca], "vpmulhrsw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0x4a, 0x01], "vpermilpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x0d, 0xca], "vpermilpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0x0a], "vpsrlvw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0x4a, 0x01], "vpsrlvw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x10, 0xca], "vpsrlvw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0x0a], "vpsravw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0x4a, 0x01], "vpsravw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x11, 0xca], "vpsravw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0x0a], "vpsllvw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0x4a, 0x01], "vpsllvw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x12, 0xca], "vpsllvw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0x0a], "vprorvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0x4a, 0x01], "vprorvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x14, 0xca], "vprorvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0x0a], "vprolvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0x4a, 0x01], "vprolvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x15, 0xca], "vprolvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0x0a], "vpermpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0x4a, 0x01], "vpermpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x16, 0xca], "vpermpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0x0a], "vbroadcastsd zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x19, 0xca], "vbroadcastsd zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x0a], "vbroadcastf64x2 zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x0a], "vbroadcastf64x4 zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0x0a], "vpabsb zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0x4a, 0x01], "vpabsb zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1c, 0xca], "vpabsb zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0x0a], "vpabsw zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0x4a, 0x01], "vpabsw zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1d, 0xca], "vpabsw zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0x0a], "vpabsq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0x4a, 0x01], "vpabsq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x1f, 0xca], "vpabsq zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0x0a], "vpmovsxbw zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x20, 0xca], "vpmovsxbw zmm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0x0a], "vpmovsxbd zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x21, 0xca], "vpmovsxbd zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0x0a], "vpmovsxbq zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x22, 0xca], "vpmovsxbq zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0x0a], "vpmovsxwd zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x23, 0xca], "vpmovsxwd zmm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0x0a], "vpmovsxwq zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x24, 0xca], "vpmovsxwq zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x0a], "vptestmw k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0x4a, 0x01], "vptestmw k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x26, 0xca], "vptestmw k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0x0a], "vptestmq k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0x4a, 0x01], "vptestmq k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x27, 0xca], "vptestmq k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0x0a], "vpmuldq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0x4a, 0x01], "vpmuldq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x28, 0xca], "vpmuldq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0x0a], "vpcmpeqq k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0x4a, 0x01], "vpcmpeqq k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x29, 0xca], "vpcmpeqq k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0x4a, 0x01], "vscalefpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x2c, 0xca], "vscalefpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0x0a], "vpmovzxbw zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x30, 0xca], "vpmovzxbw zmm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0x0a], "vpmovzxbd zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x31, 0xca], "vpmovzxbd zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0x0a], "vpmovzxbq zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x32, 0xca], "vpmovzxbq zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0x0a], "vpmovzxwd zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x33, 0xca], "vpmovzxwd zmm1, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0x0a], "vpmovzxwq zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x34, 0xca], "vpmovzxwq zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0x0a], "vpermq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0x4a, 0x01], "vpermq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x36, 0xca], "vpermq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0x0a], "vpcmpgtq k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0x4a, 0x01], "vpcmpgtq k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x37, 0xca], "vpcmpgtq k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0x0a], "vpminsb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0x4a, 0x01], "vpminsb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x38, 0xca], "vpminsb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0x0a], "vpminsq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0x4a, 0x01], "vpminsq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x39, 0xca], "vpminsq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0x0a], "vpminuw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0x4a, 0x01], "vpminuw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3a, 0xca], "vpminuw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0x0a], "vpminuq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0x4a, 0x01], "vpminuq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3b, 0xca], "vpminuq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0x0a], "vpmaxsb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3c, 0xca], "vpmaxsb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3d, 0xca], "vpmaxsq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0x0a], "vpmaxuw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3e, 0xca], "vpmaxuw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x3f, 0xca], "vpmaxuq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0x0a], "vpmullq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0x4a, 0x01], "vpmullq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x40, 0xca], "vpmullq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0x0a], "vgetexppd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0x4a, 0x01], "vgetexppd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x42, 0xca], "vgetexppd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0x0a], "vplzcntq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0x4a, 0x01], "vplzcntq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x44, 0xca], "vplzcntq zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0x4a, 0x01], "vpsrlvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x45, 0xca], "vpsrlvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0x0a], "vpsravq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0x4a, 0x01], "vpsravq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x46, 0xca], "vpsravq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0x0a], "vpsllvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0x4a, 0x01], "vpsllvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x47, 0xca], "vpsllvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0x0a], "vrcp14pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4c, 0xca], "vrcp14pd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0x0a], "vrsqrt14pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x4e, 0xca], "vrsqrt14pd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0x0a], "vpopcntw zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0x4a, 0x01], "vpopcntw zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x54, 0xca], "vpopcntw zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0x0a], "vpopcntq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0x4a, 0x01], "vpopcntq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x55, 0xca], "vpopcntq zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0x0a], "vpbroadcastq zmm1, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x59, 0xca], "vpbroadcastq zmm1, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x0a], "vbroadcasti64x2 zmm1, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x0a], "vbroadcasti64x4 zmm1, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0x0a], "vpexpandw zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0x4a, 0x01], "vpexpandw zmm1, zmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x62, 0xca], "vpexpandw zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0x0a], "vpcompressw zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0x4a, 0x01], "vpcompressw zmmword [bp + si * 1 + 0x2], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x63, 0xca], "vpcompressw zmm2, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0x0a], "vpblendmq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0x4a, 0x01], "vpblendmq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x64, 0xca], "vpblendmq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0x0a], "vblendmpd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0x4a, 0x01], "vblendmpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x65, 0xca], "vblendmpd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0x0a], "vpblendmw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0x4a, 0x01], "vpblendmw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x66, 0xca], "vpblendmw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0x0a], "vpshldvw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0x4a, 0x01], "vpshldvw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x70, 0xca], "vpshldvw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0x0a], "vpshldvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0x4a, 0x01], "vpshldvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x71, 0xca], "vpshldvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0x0a], "vpshrdvw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0x4a, 0x01], "vpshrdvw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x72, 0xca], "vpshrdvw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0x4a, 0x01], "vpshrdvq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x73, 0xca], "vpshrdvq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0x0a], "vpermi2w zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0x4a, 0x01], "vpermi2w zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x75, 0xca], "vpermi2w zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0x0a], "vpermi2q zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0x4a, 0x01], "vpermi2q zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x76, 0xca], "vpermi2q zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0x4a, 0x01], "vpermi2pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x77, 0xca], "vpermi2pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7c, 0xca], "vpbroadcastd zmm1, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0x0a], "vpermt2w zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0x4a, 0x01], "vpermt2w zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7d, 0xca], "vpermt2w zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0x4a, 0x01], "vpermt2q zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7e, 0xca], "vpermt2q zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x7f, 0xca], "vpermt2pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x83, 0xca], "vpmultishiftqb zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0x0a], "vexpandpd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0x4a, 0x01], "vexpandpd zmm1, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x88, 0xca], "vexpandpd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0x0a], "vpexpandq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0x4a, 0x01], "vpexpandq zmm1, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x89, 0xca], "vpexpandq zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x0a], "vcompresspd zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0x4a, 0x01], "vcompresspd zmmword [bp + si * 1 + 0x8], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8a, 0xca], "vcompresspd zmm2, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x0a], "vpcompressq zmmword [bp + si * 1], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0x4a, 0x01], "vpcompressq zmmword [bp + si * 1 + 0x8], zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8b, 0xca], "vpcompressq zmm2, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0x0a], "vpermw zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0x4a, 0x01], "vpermw zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x8d, 0xca], "vpermw zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x96, 0xca], "vfmaddsub132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x97, 0xca], "vfmsubadd132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x98, 0xca], "vfmadd132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9a, 0xca], "vfmsub132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9c, 0xca], "vfnmadd132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0x9e, 0xca], "vfnmsub132pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa6, 0xca], "vfmaddsub213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa7, 0xca], "vfmsubadd213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xa8, 0xca], "vfmadd213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xaa, 0xca], "vfmsub213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xac, 0xca], "vfnmadd213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xae, 0xca], "vfnmsub213pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb4, 0xca], "vpmadd52luq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb5, 0xca], "vpmadd52huq zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb6, 0xca], "vfmaddsub231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb7, 0xca], "vfmsubadd231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xb8, 0xca], "vfmadd231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xba, 0xca], "vfmsub231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbc, 0xca], "vfnmadd231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xbe, 0xca], "vfnmsub231pd zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0x0a], "vpconflictq zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0x4a, 0x01], "vpconflictq zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc4, 0xca], "vpconflictq zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0x0a], "vexp2pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0x4a, 0x01], "vexp2pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xc8, 0xca], "vexp2pd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0x0a], "vrcp28pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0x4a, 0x01], "vrcp28pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xca, 0xca], "vrcp28pd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0x0a], "vrsqrt28pd zmm1, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xcc, 0xca], "vrsqrt28pd zmm1, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x0a], "vaesenc zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0x4a, 0x01], "vaesenc zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdc, 0xca], "vaesenc zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0x0a], "vaesenclast zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0x4a, 0x01], "vaesenclast zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdd, 0xca], "vaesenclast zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0x0a], "vaesdec zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0x4a, 0x01], "vaesdec zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xde, 0xca], "vaesdec zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0x0a], "vaesdeclast zmm1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0x4a, 0x01], "vaesdeclast zmm1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x48, 0xdf, 0xca], "vaesdeclast zmm1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0x0a], "vpshufb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0x4a, 0x01], "vpshufb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x00, 0xca], "vpshufb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0x0a], "vpmaddubsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x04, 0xca], "vpmaddubsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0b, 0xca], "vpmulhrsw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x0d, 0xca], "vpermilpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0x0a], "vpsrlvw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0x4a, 0x01], "vpsrlvw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x10, 0xca], "vpsrlvw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0x0a], "vpsravw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0x4a, 0x01], "vpsravw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x11, 0xca], "vpsravw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0x0a], "vpsllvw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0x4a, 0x01], "vpsllvw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x12, 0xca], "vpsllvw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x14, 0xca], "vprorvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x15, 0xca], "vprolvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x16, 0xca], "vpermpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0x0a], "vbroadcastsd zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x19, 0xca], "vbroadcastsd zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0x0a], "vpabsb zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0x4a, 0x01], "vpabsb zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1c, 0xca], "vpabsb zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0x0a], "vpabsw zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0x4a, 0x01], "vpabsw zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1d, 0xca], "vpabsw zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0x0a], "vpabsq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x1f, 0xca], "vpabsq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0x0a], "vpmovsxbw zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x20, 0xca], "vpmovsxbw zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0x0a], "vpmovsxbd zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x21, 0xca], "vpmovsxbd zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0x0a], "vpmovsxbq zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x22, 0xca], "vpmovsxbq zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0x0a], "vpmovsxwd zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x23, 0xca], "vpmovsxwd zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0x0a], "vpmovsxwq zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x24, 0xca], "vpmovsxwq zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0x0a], "vptestmw k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0x4a, 0x01], "vptestmw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x26, 0xca], "vptestmw k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x27, 0xca], "vptestmq k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x28, 0xca], "vpmuldq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x29, 0xca], "vpcmpeqq k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x2c, 0xca], "vscalefpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0x0a], "vpmovzxbw zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x30, 0xca], "vpmovzxbw zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0x0a], "vpmovzxbd zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x31, 0xca], "vpmovzxbd zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0x0a], "vpmovzxbq zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x32, 0xca], "vpmovzxbq zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0x0a], "vpmovzxwd zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x33, 0xca], "vpmovzxwd zmm1{k5}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0x0a], "vpmovzxwq zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x34, 0xca], "vpmovzxwq zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x36, 0xca], "vpermq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x37, 0xca], "vpcmpgtq k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0x0a], "vpminsb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0x4a, 0x01], "vpminsb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x38, 0xca], "vpminsb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x39, 0xca], "vpminsq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0x0a], "vpminuw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0x4a, 0x01], "vpminuw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3a, 0xca], "vpminuw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3b, 0xca], "vpminuq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0x0a], "vpmaxsb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3c, 0xca], "vpmaxsb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3d, 0xca], "vpmaxsq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0x0a], "vpmaxuw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3e, 0xca], "vpmaxuw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x3f, 0xca], "vpmaxuq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x40, 0xca], "vpmullq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0x0a], "vgetexppd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x42, 0xca], "vgetexppd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0x0a], "vplzcntq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x44, 0xca], "vplzcntq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x45, 0xca], "vpsrlvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x46, 0xca], "vpsravq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x47, 0xca], "vpsllvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4c, 0xca], "vrcp14pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0x0a], "vpopcntw zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0x4a, 0x01], "vpopcntw zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x54, 0xca], "vpopcntw zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0x0a], "vpopcntq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x55, 0xca], "vpopcntq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0x0a], "vpbroadcastq zmm1{k5}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1{k5}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x59, 0xca], "vpbroadcastq zmm1{k5}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1{k5}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1{k5}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0x0a], "vpexpandw zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0x4a, 0x01], "vpexpandw zmm1{k5}, zmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x62, 0xca], "vpexpandw zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0x0a], "vpcompressw zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0x4a, 0x01], "vpcompressw zmmword [bp + si * 1 + 0x2]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x63, 0xca], "vpcompressw zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x64, 0xca], "vpblendmq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x65, 0xca], "vblendmpd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0x0a], "vpblendmw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0x4a, 0x01], "vpblendmw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x66, 0xca], "vpblendmw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0x0a], "vpshldvw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0x4a, 0x01], "vpshldvw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x70, 0xca], "vpshldvw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x71, 0xca], "vpshldvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0x0a], "vpshrdvw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0x4a, 0x01], "vpshrdvw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x72, 0xca], "vpshrdvw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x73, 0xca], "vpshrdvq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0x0a], "vpermi2w zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0x4a, 0x01], "vpermi2w zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x75, 0xca], "vpermi2w zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x76, 0xca], "vpermi2q zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x77, 0xca], "vpermi2pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7c, 0xca], "vpbroadcastd zmm1{k5}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0x0a], "vpermt2w zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0x4a, 0x01], "vpermt2w zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7d, 0xca], "vpermt2w zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7e, 0xca], "vpermt2q zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x7f, 0xca], "vpermt2pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x83, 0xca], "vpmultishiftqb zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0x0a], "vexpandpd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0x4a, 0x01], "vexpandpd zmm1{k5}, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x88, 0xca], "vexpandpd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0x0a], "vpexpandq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0x4a, 0x01], "vpexpandq zmm1{k5}, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x89, 0xca], "vpexpandq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0x0a], "vcompresspd zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0x4a, 0x01], "vcompresspd zmmword [bp + si * 1 + 0x8]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8a, 0xca], "vcompresspd zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0x0a], "vpcompressq zmmword [bp + si * 1]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0x4a, 0x01], "vpcompressq zmmword [bp + si * 1 + 0x8]{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8b, 0xca], "vpcompressq zmm2{k5}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0x0a], "vpermw zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0x4a, 0x01], "vpermw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x8d, 0xca], "vpermw zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x98, 0xca], "vfmadd132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb4, 0xca], "vpmadd52luq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb5, 0xca], "vpmadd52huq zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xba, 0xca], "vfmsub231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc4, 0xca], "vpconflictq zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xc8, 0xca], "vexp2pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xca, 0xca], "vrcp28pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0x4d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x0d, 0x0a], "vpermilpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x0d, 0x4a, 0x01], "vpermilpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x14, 0x0a], "vprorvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x14, 0x4a, 0x01], "vprorvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x15, 0x0a], "vprolvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x15, 0x4a, 0x01], "vprolvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x16, 0x0a], "vpermpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x16, 0x4a, 0x01], "vpermpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x1f, 0x0a], "vpabsq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x1f, 0x4a, 0x01], "vpabsq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x0a], "vptestmq k1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x27, 0x4a, 0x01], "vptestmq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x28, 0x0a], "vpmuldq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x28, 0x4a, 0x01], "vpmuldq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x0a], "vpcmpeqq k1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x29, 0x4a, 0x01], "vpcmpeqq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0x0a], "vscalefpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0x4a, 0x01], "vscalefpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x2c, 0xca], "vscalefpd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x2d, 0xca], "vscalefsd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x36, 0x0a], "vpermq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x36, 0x4a, 0x01], "vpermq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x37, 0x0a], "vpcmpgtq k1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x37, 0x4a, 0x01], "vpcmpgtq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x39, 0x0a], "vpminsq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x39, 0x4a, 0x01], "vpminsq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3b, 0x0a], "vpminuq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3b, 0x4a, 0x01], "vpminuq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3d, 0x0a], "vpmaxsq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3f, 0x0a], "vpmaxuq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x40, 0x0a], "vpmullq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x40, 0x4a, 0x01], "vpmullq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x42, 0x0a], "vgetexppd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x42, 0x4a, 0x01], "vgetexppd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x44, 0x0a], "vplzcntq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x44, 0x4a, 0x01], "vplzcntq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x45, 0x0a], "vpsrlvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x45, 0x4a, 0x01], "vpsrlvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x46, 0x0a], "vpsravq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x46, 0x4a, 0x01], "vpsravq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x47, 0x0a], "vpsllvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x47, 0x4a, 0x01], "vpsllvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x4c, 0x0a], "vrcp14pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x4e, 0x0a], "vrsqrt14pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x55, 0x0a], "vpopcntq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x55, 0x4a, 0x01], "vpopcntq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x64, 0x0a], "vpblendmq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x64, 0x4a, 0x01], "vpblendmq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x65, 0x0a], "vblendmpd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x65, 0x4a, 0x01], "vblendmpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x71, 0x0a], "vpshldvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x71, 0x4a, 0x01], "vpshldvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x73, 0x0a], "vpshrdvq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x73, 0x4a, 0x01], "vpshrdvq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x76, 0x0a], "vpermi2q zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x76, 0x4a, 0x01], "vpermi2q zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x77, 0x0a], "vpermi2pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x77, 0x4a, 0x01], "vpermi2pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x7e, 0x0a], "vpermt2q zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x7e, 0x4a, 0x01], "vpermt2q zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x7f, 0x0a], "vpermt2pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x83, 0x0a], "vpmultishiftqb zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0x0a], "vfmaddsub132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x96, 0xca], "vfmaddsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0x0a], "vfmsubadd132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x97, 0xca], "vfmsubadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0x0a], "vfmadd132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x98, 0xca], "vfmadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x99, 0xca], "vfmadd132sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0x0a], "vfmsub132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9a, 0xca], "vfmsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9b, 0xca], "vfmsub132sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0x0a], "vfnmadd132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9c, 0xca], "vfnmadd132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9d, 0xca], "vfnmadd132sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0x0a], "vfnmsub132pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9e, 0xca], "vfnmsub132pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0x9f, 0xca], "vfnmsub132sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0x0a], "vfmaddsub213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa6, 0xca], "vfmaddsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0x0a], "vfmsubadd213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa7, 0xca], "vfmsubadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0x0a], "vfmadd213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa8, 0xca], "vfmadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xa9, 0xca], "vfmadd213sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0x0a], "vfmsub213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xaa, 0xca], "vfmsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xab, 0xca], "vfmsub213sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0x0a], "vfnmadd213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xac, 0xca], "vfnmadd213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xad, 0xca], "vfnmadd213sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0x0a], "vfnmsub213pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xae, 0xca], "vfnmsub213pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xaf, 0xca], "vfnmsub213sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb4, 0x0a], "vpmadd52luq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb5, 0x0a], "vpmadd52huq zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0x0a], "vfmaddsub231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb6, 0xca], "vfmaddsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0x0a], "vfmsubadd231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb7, 0xca], "vfmsubadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0x0a], "vfmadd231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb8, 0xca], "vfmadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xb9, 0xca], "vfmadd231sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0x0a], "vfmsub231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xba, 0xca], "vfmsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbb, 0xca], "vfmsub231sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0x0a], "vfnmadd231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbc, 0xca], "vfnmadd231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbd, 0xca], "vfnmadd231sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0x0a], "vfnmsub231pd zmm1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbe, 0xca], "vfnmsub231pd zmm1{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xbf, 0xca], "vfnmsub231sd xmm1{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xc4, 0x0a], "vpconflictq zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xc4, 0x4a, 0x01], "vpconflictq zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xc8, 0x0a], "vexp2pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xc8, 0x4a, 0x01], "vexp2pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xca, 0x0a], "vrcp28pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xca, 0x4a, 0x01], "vrcp28pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xcc, 0x0a], "vrsqrt28pd zmm1, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x58, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x0d, 0x0a], "vpermilpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x14, 0x0a], "vprorvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x15, 0x0a], "vprolvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x16, 0x0a], "vpermpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x1f, 0x0a], "vpabsq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x0a], "vptestmq k1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x27, 0x4a, 0x01], "vptestmq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x28, 0x0a], "vpmuldq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x29, 0x0a], "vpcmpeqq k1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x29, 0x4a, 0x01], "vpcmpeqq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0x0a], "vscalefpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x2c, 0xca], "vscalefpd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x2d, 0xca], "vscalefsd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x36, 0x0a], "vpermq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x37, 0x0a], "vpcmpgtq k1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x37, 0x4a, 0x01], "vpcmpgtq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x39, 0x0a], "vpminsq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3b, 0x0a], "vpminuq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3d, 0x0a], "vpmaxsq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3f, 0x0a], "vpmaxuq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x40, 0x0a], "vpmullq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x42, 0x0a], "vgetexppd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x44, 0x0a], "vplzcntq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x45, 0x0a], "vpsrlvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x46, 0x0a], "vpsravq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x47, 0x0a], "vpsllvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x4c, 0x0a], "vrcp14pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x55, 0x0a], "vpopcntq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x64, 0x0a], "vpblendmq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x65, 0x0a], "vblendmpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x71, 0x0a], "vpshldvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x73, 0x0a], "vpshrdvq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x76, 0x0a], "vpermi2q zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x77, 0x0a], "vpermi2pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x7e, 0x0a], "vpermt2q zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x7f, 0x0a], "vpermt2pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0x0a], "vfmadd132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0x0a], "vfmsub231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xc4, 0x0a], "vpconflictq zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xc8, 0x0a], "vexp2pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xca, 0x0a], "vrcp28pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x5d, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x2c, 0xca], "vscalefpd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x2d, 0xca], "vscalefsd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x42, 0xca], "vgetexppd zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x43, 0xca], "vgetexpsd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x96, 0xca], "vfmaddsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x97, 0xca], "vfmsubadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x98, 0xca], "vfmadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x99, 0xca], "vfmadd132sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9a, 0xca], "vfmsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9b, 0xca], "vfmsub132sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9c, 0xca], "vfnmadd132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9d, 0xca], "vfnmadd132sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9e, 0xca], "vfnmsub132pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0x9f, 0xca], "vfnmsub132sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xa6, 0xca], "vfmaddsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xa7, 0xca], "vfmsubadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xa8, 0xca], "vfmadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xa9, 0xca], "vfmadd213sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xaa, 0xca], "vfmsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xab, 0xca], "vfmsub213sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xac, 0xca], "vfnmadd213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xad, 0xca], "vfnmadd213sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xae, 0xca], "vfnmsub213pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xaf, 0xca], "vfnmsub213sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xb6, 0xca], "vfmaddsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xb7, 0xca], "vfmsubadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xb8, 0xca], "vfmadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xb9, 0xca], "vfmadd231sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xba, 0xca], "vfmsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xbb, 0xca], "vfmsub231sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xbc, 0xca], "vfnmadd231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xbd, 0xca], "vfnmadd231sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xbe, 0xca], "vfnmsub231pd zmm1{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xbf, 0xca], "vfnmsub231sd xmm1{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xc8, 0xca], "vexp2pd zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xca, 0xca], "vrcp28pd zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xcb, 0xca], "vrcp28sd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xcc, 0xca], "vrsqrt28pd zmm1{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x78, 0xcd, 0xca], "vrsqrt28sd xmm1{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x2c, 0xca], "vscalefpd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x2d, 0xca], "vscalefsd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x42, 0xca], "vgetexppd zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x43, 0xca], "vgetexpsd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xc8, 0xca], "vexp2pd zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xca, 0xca], "vrcp28pd zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xcb, 0xca], "vrcp28sd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x7d, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0x0a], "vpshufb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0x4a, 0x01], "vpshufb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x00, 0xca], "vpshufb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0x0a], "vpmaddubsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0x4a, 0x01], "vpmaddubsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x04, 0xca], "vpmaddubsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0x0a], "vpmulhrsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0x4a, 0x01], "vpmulhrsw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0b, 0xca], "vpmulhrsw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x0d, 0xca], "vpermilpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0x0a], "vpsrlvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0x4a, 0x01], "vpsrlvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x10, 0xca], "vpsrlvw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0x0a], "vpsravw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0x4a, 0x01], "vpsravw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x11, 0xca], "vpsravw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0x0a], "vpsllvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0x4a, 0x01], "vpsllvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x12, 0xca], "vpsllvw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x14, 0xca], "vprorvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x15, 0xca], "vprolvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0x0a], "vpabsb xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0x4a, 0x01], "vpabsb xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1c, 0xca], "vpabsb xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0x0a], "vpabsw xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0x4a, 0x01], "vpabsw xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1d, 0xca], "vpabsw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x1f, 0xca], "vpabsq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0x0a], "vpmovsxbw xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0x4a, 0x01], "vpmovsxbw xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x20, 0xca], "vpmovsxbw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0x0a], "vpmovsxbd xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0x4a, 0x01], "vpmovsxbd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x21, 0xca], "vpmovsxbd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0x0a], "vpmovsxbq xmm1{k5}{z}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0x4a, 0x01], "vpmovsxbq xmm1{k5}{z}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x22, 0xca], "vpmovsxbq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0x0a], "vpmovsxwd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0x4a, 0x01], "vpmovsxwd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x23, 0xca], "vpmovsxwd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0x0a], "vpmovsxwq xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0x4a, 0x01], "vpmovsxwq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x24, 0xca], "vpmovsxwq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x28, 0xca], "vpmuldq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x2c, 0xca], "vscalefpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0x0a], "vpmovzxbw xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0x4a, 0x01], "vpmovzxbw xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x30, 0xca], "vpmovzxbw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0x0a], "vpmovzxbd xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0x4a, 0x01], "vpmovzxbd xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x31, 0xca], "vpmovzxbd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0x0a], "vpmovzxbq xmm1{k5}{z}, word [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0x4a, 0x01], "vpmovzxbq xmm1{k5}{z}, word [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x32, 0xca], "vpmovzxbq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0x0a], "vpmovzxwd xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0x4a, 0x01], "vpmovzxwd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x33, 0xca], "vpmovzxwd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0x0a], "vpmovzxwq xmm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0x4a, 0x01], "vpmovzxwq xmm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x34, 0xca], "vpmovzxwq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0x0a], "vpminsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0x4a, 0x01], "vpminsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x38, 0xca], "vpminsb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x39, 0xca], "vpminsq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0x0a], "vpminuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0x4a, 0x01], "vpminuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3a, 0xca], "vpminuw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3b, 0xca], "vpminuq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0x0a], "vpmaxsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0x4a, 0x01], "vpmaxsb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3c, 0xca], "vpmaxsb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3d, 0xca], "vpmaxsq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0x0a], "vpmaxuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0x4a, 0x01], "vpmaxuw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3e, 0xca], "vpmaxuw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x3f, 0xca], "vpmaxuq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x40, 0xca], "vpmullq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x42, 0xca], "vgetexppd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x44, 0xca], "vplzcntq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x45, 0xca], "vpsrlvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x46, 0xca], "vpsravq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x47, 0xca], "vpsllvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4c, 0xca], "vrcp14pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x4e, 0xca], "vrsqrt14pd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0x0a], "vpopcntw xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0x4a, 0x01], "vpopcntw xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x54, 0xca], "vpopcntw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x55, 0xca], "vpopcntq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0x0a], "vpbroadcastq xmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0x4a, 0x01], "vpbroadcastq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x59, 0xca], "vpbroadcastq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0x0a], "vpexpandw xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0x4a, 0x01], "vpexpandw xmm1{k5}{z}, xmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x62, 0xca], "vpexpandw xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x63, 0xca], "vpcompressw xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x64, 0xca], "vpblendmq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x65, 0xca], "vblendmpd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0x0a], "vpblendmw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0x4a, 0x01], "vpblendmw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x66, 0xca], "vpblendmw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0x0a], "vpshldvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0x4a, 0x01], "vpshldvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x70, 0xca], "vpshldvw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x71, 0xca], "vpshldvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0x0a], "vpshrdvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0x4a, 0x01], "vpshrdvw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x72, 0xca], "vpshrdvw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x73, 0xca], "vpshrdvq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0x0a], "vpermi2w xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0x4a, 0x01], "vpermi2w xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x75, 0xca], "vpermi2w xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x76, 0xca], "vpermi2q xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x77, 0xca], "vpermi2pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7c, 0xca], "vpbroadcastd xmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0x0a], "vpermt2w xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0x4a, 0x01], "vpermt2w xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7d, 0xca], "vpermt2w xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7e, 0xca], "vpermt2q xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x7f, 0xca], "vpermt2pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x83, 0xca], "vpmultishiftqb xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0x0a], "vexpandpd xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0x4a, 0x01], "vexpandpd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x88, 0xca], "vexpandpd xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0x0a], "vpexpandq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0x4a, 0x01], "vpexpandq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x89, 0xca], "vpexpandq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x8a, 0xca], "vcompresspd xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x8b, 0xca], "vpcompressq xmm2{k5}{z}, xmm1"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0x0a], "vpermw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0x4a, 0x01], "vpermw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x8d, 0xca], "vpermw xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x96, 0xca], "vfmaddsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x97, 0xca], "vfmsubadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x98, 0xca], "vfmadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9a, 0xca], "vfmsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9c, 0xca], "vfnmadd132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0x9e, 0xca], "vfnmsub132pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa6, 0xca], "vfmaddsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa7, 0xca], "vfmsubadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xa8, 0xca], "vfmadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xaa, 0xca], "vfmsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xac, 0xca], "vfnmadd213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xae, 0xca], "vfnmsub213pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb4, 0xca], "vpmadd52luq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb5, 0xca], "vpmadd52huq xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb6, 0xca], "vfmaddsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb7, 0xca], "vfmsubadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xb8, 0xca], "vfmadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xba, 0xca], "vfmsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbc, 0xca], "vfnmadd231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xbe, 0xca], "vfnmsub231pd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0x8d, 0xc4, 0xca], "vpconflictq xmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x0d, 0x0a], "vpermilpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x0d, 0x4a, 0x01], "vpermilpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x14, 0x0a], "vprorvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x14, 0x4a, 0x01], "vprorvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x15, 0x0a], "vprolvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x15, 0x4a, 0x01], "vprolvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x1f, 0x0a], "vpabsq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x1f, 0x4a, 0x01], "vpabsq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x28, 0x0a], "vpmuldq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x28, 0x4a, 0x01], "vpmuldq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0x0a], "vscalefpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0x4a, 0x01], "vscalefpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x39, 0x0a], "vpminsq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x39, 0x4a, 0x01], "vpminsq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3b, 0x0a], "vpminuq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3b, 0x4a, 0x01], "vpminuq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3d, 0x0a], "vpmaxsq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3d, 0x4a, 0x01], "vpmaxsq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3f, 0x0a], "vpmaxuq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x3f, 0x4a, 0x01], "vpmaxuq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x40, 0x0a], "vpmullq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x40, 0x4a, 0x01], "vpmullq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x42, 0x0a], "vgetexppd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x42, 0x4a, 0x01], "vgetexppd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x44, 0x0a], "vplzcntq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x44, 0x4a, 0x01], "vplzcntq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x45, 0x0a], "vpsrlvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x45, 0x4a, 0x01], "vpsrlvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x46, 0x0a], "vpsravq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x46, 0x4a, 0x01], "vpsravq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x47, 0x0a], "vpsllvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x47, 0x4a, 0x01], "vpsllvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x4c, 0x0a], "vrcp14pd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x4c, 0x4a, 0x01], "vrcp14pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x4e, 0x0a], "vrsqrt14pd xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x4e, 0x4a, 0x01], "vrsqrt14pd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x55, 0x0a], "vpopcntq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x55, 0x4a, 0x01], "vpopcntq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x64, 0x0a], "vpblendmq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x64, 0x4a, 0x01], "vpblendmq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x65, 0x0a], "vblendmpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x65, 0x4a, 0x01], "vblendmpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x71, 0x0a], "vpshldvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x71, 0x4a, 0x01], "vpshldvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x73, 0x0a], "vpshrdvq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x73, 0x4a, 0x01], "vpshrdvq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x76, 0x0a], "vpermi2q xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x76, 0x4a, 0x01], "vpermi2q xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x77, 0x0a], "vpermi2pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x77, 0x4a, 0x01], "vpermi2pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x7e, 0x0a], "vpermt2q xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x7e, 0x4a, 0x01], "vpermt2q xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x7f, 0x0a], "vpermt2pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x7f, 0x4a, 0x01], "vpermt2pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x83, 0x0a], "vpmultishiftqb xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x83, 0x4a, 0x01], "vpmultishiftqb xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0x0a], "vfmaddsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0x4a, 0x01], "vfmaddsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0x0a], "vfmsubadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0x4a, 0x01], "vfmsubadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0x0a], "vfmadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0x4a, 0x01], "vfmadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0x0a], "vfmsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0x4a, 0x01], "vfmsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0x0a], "vfnmadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0x4a, 0x01], "vfnmadd132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0x0a], "vfnmsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0x4a, 0x01], "vfnmsub132pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0x0a], "vfmaddsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0x4a, 0x01], "vfmaddsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0x0a], "vfmsubadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0x4a, 0x01], "vfmsubadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0x0a], "vfmadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0x4a, 0x01], "vfmadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0x0a], "vfmsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0x4a, 0x01], "vfmsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0x0a], "vfnmadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0x4a, 0x01], "vfnmadd213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0x0a], "vfnmsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0x4a, 0x01], "vfnmsub213pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb4, 0x0a], "vpmadd52luq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb4, 0x4a, 0x01], "vpmadd52luq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb5, 0x0a], "vpmadd52huq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb5, 0x4a, 0x01], "vpmadd52huq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0x0a], "vfmaddsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0x4a, 0x01], "vfmaddsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0x0a], "vfmsubadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0x4a, 0x01], "vfmsubadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0x0a], "vfmadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0x4a, 0x01], "vfmadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0x0a], "vfmsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0x4a, 0x01], "vfmsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0x0a], "vfnmadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0x4a, 0x01], "vfnmadd231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0x0a], "vfnmsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0x4a, 0x01], "vfnmsub231pd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rne-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rne-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xc4, 0x0a], "vpconflictq xmm1{k5}{z}, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0x9d, 0xc4, 0x4a, 0x01], "vpconflictq xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0x0a], "vpshufb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0x4a, 0x01], "vpshufb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x00, 0xca], "vpshufb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0x0a], "vpmaddubsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0x4a, 0x01], "vpmaddubsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x04, 0xca], "vpmaddubsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0x0a], "vpmulhrsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0x4a, 0x01], "vpmulhrsw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0b, 0xca], "vpmulhrsw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x0d, 0xca], "vpermilpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0x0a], "vpsrlvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0x4a, 0x01], "vpsrlvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x10, 0xca], "vpsrlvw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0x0a], "vpsravw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0x4a, 0x01], "vpsravw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x11, 0xca], "vpsravw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0x0a], "vpsllvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0x4a, 0x01], "vpsllvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x12, 0xca], "vpsllvw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x14, 0xca], "vprorvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x15, 0xca], "vprolvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x16, 0xca], "vpermpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0x0a], "vbroadcastsd ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0x4a, 0x01], "vbroadcastsd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x19, 0xca], "vbroadcastsd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1a, 0x0a], "vbroadcastf64x2 ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0x0a], "vpabsb ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0x4a, 0x01], "vpabsb ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1c, 0xca], "vpabsb ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0x0a], "vpabsw ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0x4a, 0x01], "vpabsw ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1d, 0xca], "vpabsw ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x1f, 0xca], "vpabsq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0x0a], "vpmovsxbw ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0x4a, 0x01], "vpmovsxbw ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x20, 0xca], "vpmovsxbw ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0x0a], "vpmovsxbd ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0x4a, 0x01], "vpmovsxbd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x21, 0xca], "vpmovsxbd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0x0a], "vpmovsxbq ymm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0x4a, 0x01], "vpmovsxbq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x22, 0xca], "vpmovsxbq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0x0a], "vpmovsxwd ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0x4a, 0x01], "vpmovsxwd ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x23, 0xca], "vpmovsxwd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0x0a], "vpmovsxwq ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0x4a, 0x01], "vpmovsxwq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x24, 0xca], "vpmovsxwq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x28, 0xca], "vpmuldq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2c, 0xca], "vscalefpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0x0a], "vscalefsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0x4a, 0x01], "vscalefsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0x0a], "vpmovzxbw ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0x4a, 0x01], "vpmovzxbw ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x30, 0xca], "vpmovzxbw ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0x0a], "vpmovzxbd ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0x4a, 0x01], "vpmovzxbd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x31, 0xca], "vpmovzxbd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0x0a], "vpmovzxbq ymm1{k5}{z}, dword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0x4a, 0x01], "vpmovzxbq ymm1{k5}{z}, dword [bp + si * 1 + 0x4]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x32, 0xca], "vpmovzxbq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0x0a], "vpmovzxwd ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0x4a, 0x01], "vpmovzxwd ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x33, 0xca], "vpmovzxwd ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0x0a], "vpmovzxwq ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0x4a, 0x01], "vpmovzxwq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x34, 0xca], "vpmovzxwq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x36, 0xca], "vpermq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0x0a], "vpminsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0x4a, 0x01], "vpminsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x38, 0xca], "vpminsb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x39, 0xca], "vpminsq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0x0a], "vpminuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0x4a, 0x01], "vpminuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3a, 0xca], "vpminuw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3b, 0xca], "vpminuq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0x0a], "vpmaxsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0x4a, 0x01], "vpmaxsb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3c, 0xca], "vpmaxsb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3d, 0xca], "vpmaxsq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0x0a], "vpmaxuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0x4a, 0x01], "vpmaxuw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3e, 0xca], "vpmaxuw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x3f, 0xca], "vpmaxuq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x40, 0xca], "vpmullq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x42, 0xca], "vgetexppd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0x0a], "vgetexpsd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0x4a, 0x01], "vgetexpsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x44, 0xca], "vplzcntq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x45, 0xca], "vpsrlvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x46, 0xca], "vpsravq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x47, 0xca], "vpsllvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4c, 0xca], "vrcp14pd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0x0a], "vrcp14sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0x4a, 0x01], "vrcp14sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4d, 0xca], "vrcp14sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4e, 0xca], "vrsqrt14pd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0x0a], "vrsqrt14sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0x4a, 0x01], "vrsqrt14sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x4f, 0xca], "vrsqrt14sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0x0a], "vpopcntw ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0x4a, 0x01], "vpopcntw ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x54, 0xca], "vpopcntw ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x55, 0xca], "vpopcntq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0x0a], "vpbroadcastq ymm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0x4a, 0x01], "vpbroadcastq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x59, 0xca], "vpbroadcastq ymm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x5a, 0x0a], "vbroadcasti64x2 ymm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 ymm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0x0a], "vpexpandw ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0x4a, 0x01], "vpexpandw ymm1{k5}{z}, ymmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x62, 0xca], "vpexpandw ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x63, 0xca], "vpcompressw ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x64, 0xca], "vpblendmq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x65, 0xca], "vblendmpd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0x0a], "vpblendmw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0x4a, 0x01], "vpblendmw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x66, 0xca], "vpblendmw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0x0a], "vpshldvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0x4a, 0x01], "vpshldvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x70, 0xca], "vpshldvw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x71, 0xca], "vpshldvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0x0a], "vpshrdvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0x4a, 0x01], "vpshrdvw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x72, 0xca], "vpshrdvw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x73, 0xca], "vpshrdvq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0x0a], "vpermi2w ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0x4a, 0x01], "vpermi2w ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x75, 0xca], "vpermi2w ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x76, 0xca], "vpermi2q ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x77, 0xca], "vpermi2pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7c, 0xca], "vpbroadcastd ymm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0x0a], "vpermt2w ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0x4a, 0x01], "vpermt2w ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7d, 0xca], "vpermt2w ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7e, 0xca], "vpermt2q ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x7f, 0xca], "vpermt2pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x83, 0xca], "vpmultishiftqb ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0x0a], "vexpandpd ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0x4a, 0x01], "vexpandpd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x88, 0xca], "vexpandpd ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0x0a], "vpexpandq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0x4a, 0x01], "vpexpandq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x89, 0xca], "vpexpandq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x8a, 0xca], "vcompresspd ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x8b, 0xca], "vpcompressq ymm2{k5}{z}, ymm1"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0x0a], "vpermw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0x4a, 0x01], "vpermw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x8d, 0xca], "vpermw ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x96, 0xca], "vfmaddsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x97, 0xca], "vfmsubadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x98, 0xca], "vfmadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0x0a], "vfmadd132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0x4a, 0x01], "vfmadd132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9a, 0xca], "vfmsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0x0a], "vfmsub132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0x4a, 0x01], "vfmsub132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9c, 0xca], "vfnmadd132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0x0a], "vfnmadd132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0x4a, 0x01], "vfnmadd132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9e, 0xca], "vfnmsub132pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0x0a], "vfnmsub132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0x4a, 0x01], "vfnmsub132sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa6, 0xca], "vfmaddsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa7, 0xca], "vfmsubadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa8, 0xca], "vfmadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0x0a], "vfmadd213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0x4a, 0x01], "vfmadd213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaa, 0xca], "vfmsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0x0a], "vfmsub213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0x4a, 0x01], "vfmsub213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xac, 0xca], "vfnmadd213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0x0a], "vfnmadd213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0x4a, 0x01], "vfnmadd213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xae, 0xca], "vfnmsub213pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0x0a], "vfnmsub213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0x4a, 0x01], "vfnmsub213sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb4, 0xca], "vpmadd52luq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb5, 0xca], "vpmadd52huq ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb6, 0xca], "vfmaddsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb7, 0xca], "vfmsubadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb8, 0xca], "vfmadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0x0a], "vfmadd231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0x4a, 0x01], "vfmadd231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xba, 0xca], "vfmsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0x0a], "vfmsub231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0x4a, 0x01], "vfmsub231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbc, 0xca], "vfnmadd231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0x0a], "vfnmadd231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0x4a, 0x01], "vfnmadd231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbe, 0xca], "vfnmsub231pd ymm1{k5}{z}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0x0a], "vfnmsub231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0x4a, 0x01], "vfnmsub231sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xc4, 0xca], "vpconflictq ymm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0x0a], "vrcp28sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0x4a, 0x01], "vrcp28sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0x0a], "vrsqrt28sd xmm1{k5}{z}, xmm0, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0x4a, 0x01], "vrsqrt28sd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xad, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x0d, 0x0a], "vpermilpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x0d, 0x4a, 0x01], "vpermilpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x14, 0x0a], "vprorvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x14, 0x4a, 0x01], "vprorvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x15, 0x0a], "vprolvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x15, 0x4a, 0x01], "vprolvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x16, 0x0a], "vpermpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x16, 0x4a, 0x01], "vpermpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x1f, 0x0a], "vpabsq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x1f, 0x4a, 0x01], "vpabsq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0x0a], "vpmuldq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x28, 0x4a, 0x01], "vpmuldq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0x0a], "vscalefpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0x4a, 0x01], "vscalefpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x36, 0x0a], "vpermq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x36, 0x4a, 0x01], "vpermq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x39, 0x0a], "vpminsq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x39, 0x4a, 0x01], "vpminsq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3b, 0x0a], "vpminuq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3b, 0x4a, 0x01], "vpminuq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3d, 0x0a], "vpmaxsq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3d, 0x4a, 0x01], "vpmaxsq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3f, 0x0a], "vpmaxuq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x3f, 0x4a, 0x01], "vpmaxuq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x40, 0x0a], "vpmullq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x40, 0x4a, 0x01], "vpmullq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x42, 0x0a], "vgetexppd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x42, 0x4a, 0x01], "vgetexppd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x44, 0x0a], "vplzcntq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x44, 0x4a, 0x01], "vplzcntq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x45, 0x0a], "vpsrlvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x45, 0x4a, 0x01], "vpsrlvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x46, 0x0a], "vpsravq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x46, 0x4a, 0x01], "vpsravq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x47, 0x0a], "vpsllvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x47, 0x4a, 0x01], "vpsllvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x4c, 0x0a], "vrcp14pd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x4c, 0x4a, 0x01], "vrcp14pd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x0a], "vrsqrt14pd ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x4e, 0x4a, 0x01], "vrsqrt14pd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x55, 0x0a], "vpopcntq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x55, 0x4a, 0x01], "vpopcntq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x64, 0x0a], "vpblendmq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x64, 0x4a, 0x01], "vpblendmq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x65, 0x0a], "vblendmpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x65, 0x4a, 0x01], "vblendmpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x71, 0x0a], "vpshldvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x71, 0x4a, 0x01], "vpshldvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x73, 0x0a], "vpshrdvq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x73, 0x4a, 0x01], "vpshrdvq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x76, 0x0a], "vpermi2q ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x76, 0x4a, 0x01], "vpermi2q ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x77, 0x0a], "vpermi2pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x77, 0x4a, 0x01], "vpermi2pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x7e, 0x0a], "vpermt2q ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x7e, 0x4a, 0x01], "vpermt2q ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x7f, 0x0a], "vpermt2pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x7f, 0x4a, 0x01], "vpermt2pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x83, 0x0a], "vpmultishiftqb ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x83, 0x4a, 0x01], "vpmultishiftqb ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0x0a], "vfmaddsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0x4a, 0x01], "vfmaddsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0x0a], "vfmsubadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0x4a, 0x01], "vfmsubadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0x0a], "vfmadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0x4a, 0x01], "vfmadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0x0a], "vfmsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0x4a, 0x01], "vfmsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0x0a], "vfnmadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0x4a, 0x01], "vfnmadd132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0x0a], "vfnmsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0x4a, 0x01], "vfnmsub132pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0x0a], "vfmaddsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0x0a], "vfmsubadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0x0a], "vfmadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0x4a, 0x01], "vfmadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0x0a], "vfmsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0x4a, 0x01], "vfmsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0x0a], "vfnmadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0x4a, 0x01], "vfnmadd213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0x0a], "vfnmsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0x4a, 0x01], "vfnmsub213pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb4, 0x0a], "vpmadd52luq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb4, 0x4a, 0x01], "vpmadd52luq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb5, 0x0a], "vpmadd52huq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb5, 0x4a, 0x01], "vpmadd52huq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0x0a], "vfmaddsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0x0a], "vfmsubadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0x0a], "vfmadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0x4a, 0x01], "vfmadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0x0a], "vfmsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0x4a, 0x01], "vfmsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0x0a], "vfnmadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0x4a, 0x01], "vfnmadd231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0x0a], "vfnmsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0x4a, 0x01], "vfnmsub231pd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rd-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rd-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xc4, 0x0a], "vpconflictq ymm1{k5}{z}, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xbd, 0xc4, 0x4a, 0x01], "vpconflictq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0x0a], "vpshufb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0x4a, 0x01], "vpshufb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x00, 0xca], "vpshufb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0x0a], "vpmaddubsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0x4a, 0x01], "vpmaddubsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x04, 0xca], "vpmaddubsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0x0a], "vpmulhrsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0x4a, 0x01], "vpmulhrsw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0b, 0xca], "vpmulhrsw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x0d, 0xca], "vpermilpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0x0a], "vpsrlvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0x4a, 0x01], "vpsrlvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x10, 0xca], "vpsrlvw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0x0a], "vpsravw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0x4a, 0x01], "vpsravw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x11, 0xca], "vpsravw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0x0a], "vpsllvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0x4a, 0x01], "vpsllvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x12, 0xca], "vpsllvw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x14, 0xca], "vprorvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x15, 0xca], "vprolvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x16, 0xca], "vpermpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0x0a], "vbroadcastsd zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0x4a, 0x01], "vbroadcastsd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x19, 0xca], "vbroadcastsd zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1a, 0x0a], "vbroadcastf64x2 zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1a, 0x4a, 0x01], "vbroadcastf64x2 zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1b, 0x0a], "vbroadcastf64x4 zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1b, 0x4a, 0x01], "vbroadcastf64x4 zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0x0a], "vpabsb zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0x4a, 0x01], "vpabsb zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1c, 0xca], "vpabsb zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0x0a], "vpabsw zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0x4a, 0x01], "vpabsw zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1d, 0xca], "vpabsw zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x1f, 0xca], "vpabsq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0x0a], "vpmovsxbw zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0x4a, 0x01], "vpmovsxbw zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x20, 0xca], "vpmovsxbw zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0x0a], "vpmovsxbd zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0x4a, 0x01], "vpmovsxbd zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x21, 0xca], "vpmovsxbd zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0x0a], "vpmovsxbq zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0x4a, 0x01], "vpmovsxbq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x22, 0xca], "vpmovsxbq zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0x0a], "vpmovsxwd zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0x4a, 0x01], "vpmovsxwd zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x23, 0xca], "vpmovsxwd zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0x0a], "vpmovsxwq zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0x4a, 0x01], "vpmovsxwq zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x24, 0xca], "vpmovsxwq zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x28, 0xca], "vpmuldq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0x0a], "vpmovzxbw zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0x4a, 0x01], "vpmovzxbw zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x30, 0xca], "vpmovzxbw zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0x0a], "vpmovzxbd zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0x4a, 0x01], "vpmovzxbd zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x31, 0xca], "vpmovzxbd zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0x0a], "vpmovzxbq zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0x4a, 0x01], "vpmovzxbq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x32, 0xca], "vpmovzxbq zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0x0a], "vpmovzxwd zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0x4a, 0x01], "vpmovzxwd zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x33, 0xca], "vpmovzxwd zmm1{k5}{z}, ymm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0x0a], "vpmovzxwq zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0x4a, 0x01], "vpmovzxwq zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x34, 0xca], "vpmovzxwq zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x36, 0xca], "vpermq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0x0a], "vpminsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0x4a, 0x01], "vpminsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x38, 0xca], "vpminsb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x39, 0xca], "vpminsq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0x0a], "vpminuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0x4a, 0x01], "vpminuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3a, 0xca], "vpminuw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3b, 0xca], "vpminuq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0x0a], "vpmaxsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0x4a, 0x01], "vpmaxsb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3c, 0xca], "vpmaxsb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3d, 0xca], "vpmaxsq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0x0a], "vpmaxuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0x4a, 0x01], "vpmaxuw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3e, 0xca], "vpmaxuw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x3f, 0xca], "vpmaxuq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x40, 0xca], "vpmullq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x44, 0xca], "vplzcntq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x45, 0xca], "vpsrlvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x46, 0xca], "vpsravq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x47, 0xca], "vpsllvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4c, 0xca], "vrcp14pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x4e, 0xca], "vrsqrt14pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0x0a], "vpopcntw zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0x4a, 0x01], "vpopcntw zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x54, 0xca], "vpopcntw zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x55, 0xca], "vpopcntq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0x0a], "vpbroadcastq zmm1{k5}{z}, qword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0x4a, 0x01], "vpbroadcastq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x59, 0xca], "vpbroadcastq zmm1{k5}{z}, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x5a, 0x0a], "vbroadcasti64x2 zmm1{k5}{z}, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x5a, 0x4a, 0x01], "vbroadcasti64x2 zmm1{k5}{z}, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x5b, 0x0a], "vbroadcasti64x4 zmm1{k5}{z}, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x5b, 0x4a, 0x01], "vbroadcasti64x4 zmm1{k5}{z}, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0x0a], "vpexpandw zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0x4a, 0x01], "vpexpandw zmm1{k5}{z}, zmmword [bp + si * 1 + 0x2]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x62, 0xca], "vpexpandw zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x63, 0xca], "vpcompressw zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x64, 0xca], "vpblendmq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x65, 0xca], "vblendmpd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0x0a], "vpblendmw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0x4a, 0x01], "vpblendmw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x66, 0xca], "vpblendmw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0x0a], "vpshldvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0x4a, 0x01], "vpshldvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x70, 0xca], "vpshldvw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x71, 0xca], "vpshldvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0x0a], "vpshrdvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0x4a, 0x01], "vpshrdvw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x72, 0xca], "vpshrdvw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x73, 0xca], "vpshrdvq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0x0a], "vpermi2w zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0x4a, 0x01], "vpermi2w zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x75, 0xca], "vpermi2w zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x76, 0xca], "vpermi2q zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x77, 0xca], "vpermi2pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7c, 0xca], "vpbroadcastd zmm1{k5}{z}, edx"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0x0a], "vpermt2w zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0x4a, 0x01], "vpermt2w zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7d, 0xca], "vpermt2w zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7e, 0xca], "vpermt2q zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x7f, 0xca], "vpermt2pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x83, 0xca], "vpmultishiftqb zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0x0a], "vexpandpd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0x4a, 0x01], "vexpandpd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x88, 0xca], "vexpandpd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0x0a], "vpexpandq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0x4a, 0x01], "vpexpandq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x8]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x89, 0xca], "vpexpandq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x8a, 0xca], "vcompresspd zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x8b, 0xca], "vpcompressq zmm2{k5}{z}, zmm1"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0x0a], "vpermw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0x4a, 0x01], "vpermw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x8d, 0xca], "vpermw zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb4, 0xca], "vpmadd52luq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb5, 0xca], "vpmadd52huq zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc4, 0xca], "vpconflictq zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfd, 0xcd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x0d, 0x0a], "vpermilpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x0d, 0x4a, 0x01], "vpermilpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x14, 0x0a], "vprorvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x14, 0x4a, 0x01], "vprorvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x15, 0x0a], "vprolvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x15, 0x4a, 0x01], "vprolvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x16, 0x0a], "vpermpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x16, 0x4a, 0x01], "vpermpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x1f, 0x0a], "vpabsq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x1f, 0x4a, 0x01], "vpabsq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x28, 0x0a], "vpmuldq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x28, 0x4a, 0x01], "vpmuldq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0x0a], "vscalefpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0x4a, 0x01], "vscalefpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x36, 0x0a], "vpermq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x36, 0x4a, 0x01], "vpermq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x39, 0x0a], "vpminsq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x39, 0x4a, 0x01], "vpminsq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3b, 0x0a], "vpminuq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3b, 0x4a, 0x01], "vpminuq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3d, 0x0a], "vpmaxsq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3d, 0x4a, 0x01], "vpmaxsq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3f, 0x0a], "vpmaxuq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x3f, 0x4a, 0x01], "vpmaxuq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x40, 0x0a], "vpmullq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x40, 0x4a, 0x01], "vpmullq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x42, 0x0a], "vgetexppd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x42, 0x4a, 0x01], "vgetexppd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x44, 0x0a], "vplzcntq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x44, 0x4a, 0x01], "vplzcntq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x45, 0x0a], "vpsrlvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x45, 0x4a, 0x01], "vpsrlvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x46, 0x0a], "vpsravq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x46, 0x4a, 0x01], "vpsravq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x47, 0x0a], "vpsllvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x47, 0x4a, 0x01], "vpsllvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x4c, 0x0a], "vrcp14pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x4c, 0x4a, 0x01], "vrcp14pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x0a], "vrsqrt14pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x4e, 0x4a, 0x01], "vrsqrt14pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x55, 0x0a], "vpopcntq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x55, 0x4a, 0x01], "vpopcntq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x64, 0x0a], "vpblendmq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x64, 0x4a, 0x01], "vpblendmq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x65, 0x0a], "vblendmpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x65, 0x4a, 0x01], "vblendmpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x71, 0x0a], "vpshldvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x71, 0x4a, 0x01], "vpshldvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x73, 0x0a], "vpshrdvq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x73, 0x4a, 0x01], "vpshrdvq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x76, 0x0a], "vpermi2q zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x76, 0x4a, 0x01], "vpermi2q zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x77, 0x0a], "vpermi2pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x77, 0x4a, 0x01], "vpermi2pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x7e, 0x0a], "vpermt2q zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x7e, 0x4a, 0x01], "vpermt2q zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x7f, 0x0a], "vpermt2pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x7f, 0x4a, 0x01], "vpermt2pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x83, 0x0a], "vpmultishiftqb zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x83, 0x4a, 0x01], "vpmultishiftqb zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0x0a], "vfmaddsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0x4a, 0x01], "vfmaddsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0x0a], "vfmsubadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0x4a, 0x01], "vfmsubadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0x0a], "vfmadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0x4a, 0x01], "vfmadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0x0a], "vfmsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0x4a, 0x01], "vfmsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0x0a], "vfnmadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0x4a, 0x01], "vfnmadd132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0x0a], "vfnmsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0x4a, 0x01], "vfnmsub132pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0x0a], "vfmaddsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0x4a, 0x01], "vfmaddsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0x0a], "vfmsubadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0x4a, 0x01], "vfmsubadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0x0a], "vfmadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0x4a, 0x01], "vfmadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0x0a], "vfmsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0x4a, 0x01], "vfmsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0x0a], "vfnmadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0x4a, 0x01], "vfnmadd213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0x0a], "vfnmsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0x4a, 0x01], "vfnmsub213pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb4, 0x0a], "vpmadd52luq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb4, 0x4a, 0x01], "vpmadd52luq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb5, 0x0a], "vpmadd52huq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb5, 0x4a, 0x01], "vpmadd52huq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0x0a], "vfmaddsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0x4a, 0x01], "vfmaddsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0x0a], "vfmsubadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0x4a, 0x01], "vfmsubadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0x0a], "vfmadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0x4a, 0x01], "vfmadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0x0a], "vfmsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0x4a, 0x01], "vfmsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0x0a], "vfnmadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0x4a, 0x01], "vfnmadd231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0x0a], "vfnmsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0x4a, 0x01], "vfnmsub231pd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{ru-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{ru-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xc4, 0x0a], "vpconflictq zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xc4, 0x4a, 0x01], "vpconflictq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xc8, 0x0a], "vexp2pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xc8, 0x4a, 0x01], "vexp2pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xca, 0x0a], "vrcp28pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xca, 0x4a, 0x01], "vrcp28pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xcc, 0x0a], "vrsqrt28pd zmm1{k5}{z}, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xdd, 0xcc, 0x4a, 0x01], "vrsqrt28pd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x2c, 0xca], "vscalefpd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x2d, 0xca], "vscalefsd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x42, 0xca], "vgetexppd zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x43, 0xca], "vgetexpsd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x96, 0xca], "vfmaddsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x97, 0xca], "vfmsubadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x98, 0xca], "vfmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x99, 0xca], "vfmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9a, 0xca], "vfmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9b, 0xca], "vfmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9c, 0xca], "vfnmadd132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9d, 0xca], "vfnmadd132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9e, 0xca], "vfnmsub132pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0x9f, 0xca], "vfnmsub132sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xa6, 0xca], "vfmaddsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xa7, 0xca], "vfmsubadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xa8, 0xca], "vfmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xa9, 0xca], "vfmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xaa, 0xca], "vfmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xab, 0xca], "vfmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xac, 0xca], "vfnmadd213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xad, 0xca], "vfnmadd213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xae, 0xca], "vfnmsub213pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xaf, 0xca], "vfnmsub213sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xb6, 0xca], "vfmaddsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xb7, 0xca], "vfmsubadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xb8, 0xca], "vfmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xb9, 0xca], "vfmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xba, 0xca], "vfmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xbb, 0xca], "vfmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xbc, 0xca], "vfnmadd231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xbd, 0xca], "vfnmadd231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xbe, 0xca], "vfnmsub231pd zmm1{k5}{z}{rz-sae}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xbf, 0xca], "vfnmsub231sd xmm1{k5}{z}{rz-sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xc8, 0xca], "vexp2pd zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xca, 0xca], "vrcp28pd zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xcb, 0xca], "vrcp28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xcc, 0xca], "vrsqrt28pd zmm1{k5}{z}{sae}, zmm2"); test_display(&[0x62, 0xf2, 0xfd, 0xfd, 0xcd, 0xca], "vrsqrt28sd xmm1{k5}{z}{sae}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0x0a], "vptestnmw k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0x4a, 0x01], "vptestnmw k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x26, 0xca], "vptestnmw k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0x0a], "vptestnmq k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0x4a, 0x01], "vptestnmq k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x27, 0xca], "vptestnmq k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x28, 0xca], "vpmovm2w xmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x29, 0xca], "vpmovw2m k1, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x2a, 0xca], "vpbroadcastmb2q xmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x38, 0xca], "vpmovm2q xmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x08, 0x39, 0xca], "vpmovq2m k1, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0x0a], "vptestnmw k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x26, 0xca], "vptestnmw k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xfe, 0x0d, 0x27, 0xca], "vptestnmq k1{k5}, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x18, 0x27, 0x0a], "vptestnmq k1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfe, 0x18, 0x27, 0x4a, 0x01], "vptestnmq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfe, 0x1d, 0x27, 0x0a], "vptestnmq k1{k5}, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xfe, 0x1d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0x0a], "vptestnmw k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0x4a, 0x01], "vptestnmw k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x26, 0xca], "vptestnmw k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0x0a], "vptestnmq k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0x4a, 0x01], "vptestnmq k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x27, 0xca], "vptestnmq k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x28, 0xca], "vpmovm2w ymm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x29, 0xca], "vpmovw2m k1, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x2a, 0xca], "vpbroadcastmb2q ymm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x38, 0xca], "vpmovm2q ymm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x28, 0x39, 0xca], "vpmovq2m k1, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0x0a], "vptestnmw k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x26, 0xca], "vptestnmw k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xfe, 0x2d, 0x27, 0xca], "vptestnmq k1{k5}, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xfe, 0x38, 0x27, 0x0a], "vptestnmq k1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfe, 0x38, 0x27, 0x4a, 0x01], "vptestnmq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfe, 0x3d, 0x27, 0x0a], "vptestnmq k1{k5}, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xfe, 0x3d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0x0a], "vptestnmw k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0x4a, 0x01], "vptestnmw k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x26, 0xca], "vptestnmw k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0x0a], "vptestnmq k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0x4a, 0x01], "vptestnmq k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x27, 0xca], "vptestnmq k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x28, 0xca], "vpmovm2w zmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x29, 0xca], "vpmovw2m k1, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x2a, 0xca], "vpbroadcastmb2q zmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x38, 0xca], "vpmovm2q zmm1, k2"); test_display(&[0x62, 0xf2, 0xfe, 0x48, 0x39, 0xca], "vpmovq2m k1, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0x0a], "vptestnmw k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0x4a, 0x01], "vptestnmw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x26, 0xca], "vptestnmw k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xfe, 0x4d, 0x27, 0xca], "vptestnmq k1{k5}, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xfe, 0x58, 0x27, 0x0a], "vptestnmq k1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfe, 0x58, 0x27, 0x4a, 0x01], "vptestnmq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xfe, 0x5d, 0x27, 0x0a], "vptestnmq k1{k5}, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xfe, 0x5d, 0x27, 0x4a, 0x01], "vptestnmq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x0a], "vp2intersectq k1, xmm0, xmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0x4a, 0x01], "vp2intersectq k1, xmm0, xmmword [bp + si * 1 + 0x10]"); test_display(&[0x62, 0xf2, 0xff, 0x08, 0x68, 0xca], "vp2intersectq k1, xmm0, xmm2"); test_display(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x0a], "vp2intersectq k1, xmm0, qword [bp + si * 1]{1to2}"); test_display(&[0x62, 0xf2, 0xff, 0x18, 0x68, 0x4a, 0x01], "vp2intersectq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}"); test_display(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x0a], "vp2intersectq k1, ymm0, ymmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0x4a, 0x01], "vp2intersectq k1, ymm0, ymmword [bp + si * 1 + 0x20]"); test_display(&[0x62, 0xf2, 0xff, 0x28, 0x68, 0xca], "vp2intersectq k1, ymm0, ymm2"); test_display(&[0x62, 0xf2, 0xff, 0x38, 0x68, 0x0a], "vp2intersectq k1, ymm0, qword [bp + si * 1]{1to4}"); test_display(&[0x62, 0xf2, 0xff, 0x38, 0x68, 0x4a, 0x01], "vp2intersectq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}"); test_display(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0x0a], "vp2intersectq k1, zmm0, zmmword [bp + si * 1]"); test_display(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0x4a, 0x01], "vp2intersectq k1, zmm0, zmmword [bp + si * 1 + 0x40]"); test_display(&[0x62, 0xf2, 0xff, 0x48, 0x68, 0xca], "vp2intersectq k1, zmm0, zmm2"); test_display(&[0x62, 0xf2, 0xff, 0x58, 0x68, 0x0a], "vp2intersectq k1, zmm0, qword [bp + si * 1]{1to8}"); test_display(&[0x62, 0xf2, 0xff, 0x58, 0x68, 0x4a, 0x01], "vp2intersectq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x03, 0xca, 0xcc], "valignd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0x0a, 0xcc], "vpermilps xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x04, 0xca, 0xcc], "vpermilps xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x08, 0xca, 0xcc], "vrndscaleps xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [bp + si * 1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph qword [bp + si * 1 + 0x8], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1e, 0xca, 0xcc], "vpcmpud k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x1f, 0xca, 0xcc], "vpcmpd k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x0a, 0xcc], "vinsertps xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0x4a, 0x01, 0xcc], "vinsertps xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x21, 0xca, 0xcc], "vinsertps xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x25, 0xca, 0xcc], "vpternlogd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x26, 0xca, 0xcc], "vgetmantps xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpub k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3e, 0xca, 0xcc], "vpcmpub k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpb k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x3f, 0xca, 0xcc], "vpcmpb k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x50, 0xca, 0xcc], "vrangeps xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x54, 0xca, 0xcc], "vfixupimmps xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0x0a, 0xcc], "vreduceps xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x56, 0xca, 0xcc], "vreduceps xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0x0a, 0xcc], "vfpclassps k1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x66, 0xca, 0xcc], "vfpclassps k1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x71, 0xca, 0xcc], "vpshldd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x08, 0x73, 0xca, 0xcc], "vpshrdd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0x0a, 0xcc], "vcvtps2ph qword [bp + si * 1]{k5}, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph qword [bp + si * 1 + 0x8]{k5}, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x0d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x03, 0x0a, 0xcc], "valignd xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x04, 0x0a, 0xcc], "vpermilps xmm1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpud k1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpd k1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x25, 0x0a, 0xcc], "vpternlogd xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x26, 0x0a, 0xcc], "vgetmantps xmm1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x50, 0x0a, 0xcc], "vrangeps xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x56, 0x0a, 0xcc], "vreduceps xmm1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x71, 0x0a, 0xcc], "vpshldd xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x73, 0x0a, 0xcc], "vpshrdd xmm1, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x18, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x1d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x03, 0xca, 0xcc], "valignd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0x0a, 0xcc], "vpermilps ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x04, 0xca, 0xcc], "vpermilps ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x08, 0xca, 0xcc], "vrndscaleps ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x0a, 0xca, 0xcc], "vrndscaless xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [bp + si * 1], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [bp + si * 1 + 0x10], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [bp + si * 1], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph xmmword [bp + si * 1 + 0x10], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1e, 0xca, 0xcc], "vpcmpud k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x1f, 0xca, 0xcc], "vpcmpd k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x25, 0xca, 0xcc], "vpternlogd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x26, 0xca, 0xcc], "vgetmantps ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0x0a, 0xcc], "vgetmantss xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x27, 0xca, 0xcc], "vgetmantss xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [bp + si * 1], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [bp + si * 1 + 0x10], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpub k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3e, 0xca, 0xcc], "vpcmpub k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpb k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x3f, 0xca, 0xcc], "vpcmpb k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x50, 0xca, 0xcc], "vrangeps ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0x0a, 0xcc], "vrangess xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x51, 0xca, 0xcc], "vrangess xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x54, 0xca, 0xcc], "vfixupimmps ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x55, 0xca, 0xcc], "vfixupimmss xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0x0a, 0xcc], "vreduceps ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x56, 0xca, 0xcc], "vreduceps ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0x0a, 0xcc], "vreducess xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x57, 0xca, 0xcc], "vreducess xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0x0a, 0xcc], "vfpclassps k1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x66, 0xca, 0xcc], "vfpclassps k1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0x0a, 0xcc], "vfpclassss k1, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0x4a, 0x01, 0xcc], "vfpclassss k1, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x67, 0xca, 0xcc], "vfpclassss k1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x71, 0xca, 0xcc], "vpshldd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x28, 0x73, 0xca, 0xcc], "vpshrdd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x03, 0xca, 0xcc], "valignd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [bp + si * 1]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [bp + si * 1 + 0x10]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x0a, 0xcc], "vcvtps2ph xmmword [bp + si * 1]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph xmmword [bp + si * 1 + 0x10]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [bp + si * 1]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [bp + si * 1 + 0x10]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1{k5}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0x0a, 0xcc], "vfpclassss k1{k5}, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0x4a, 0x01, 0xcc], "vfpclassss k1{k5}, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x67, 0xca, 0xcc], "vfpclassss k1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x2d, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x03, 0x0a, 0xcc], "valignd ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x0a, 0xcc], "vpermilps ymm1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpud k1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpd k1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x25, 0x0a, 0xcc], "vpternlogd ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x26, 0x0a, 0xcc], "vgetmantps ymm1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x50, 0x0a, 0xcc], "vrangeps ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x56, 0x0a, 0xcc], "vreduceps ymm1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x71, 0x0a, 0xcc], "vpshldd ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x73, 0x0a, 0xcc], "vpshrdd ymm1, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x38, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x3d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x03, 0xca, 0xcc], "valignd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0x0a, 0xcc], "vpermilps zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x04, 0xca, 0xcc], "vpermilps zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x08, 0xca, 0xcc], "vrndscaleps zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [bp + si * 1 + 0x10], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0x4a, 0x01, 0xcc], "vextractf32x8 ymmword [bp + si * 1 + 0x20], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph ymmword [bp + si * 1 + 0x20], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1e, 0xca, 0xcc], "vpcmpud k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x1f, 0xca, 0xcc], "vpcmpd k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x25, 0xca, 0xcc], "vpternlogd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x26, 0xca, 0xcc], "vgetmantps zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [bp + si * 1 + 0x10], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0x4a, 0x01, 0xcc], "vextracti32x8 ymmword [bp + si * 1 + 0x20], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpub k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3e, 0xca, 0xcc], "vpcmpub k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpb k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x3f, 0xca, 0xcc], "vpcmpb k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x50, 0xca, 0xcc], "vrangeps zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x54, 0xca, 0xcc], "vfixupimmps zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0x0a, 0xcc], "vreduceps zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x56, 0xca, 0xcc], "vreduceps zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0x0a, 0xcc], "vfpclassps k1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x66, 0xca, 0xcc], "vfpclassps k1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x71, 0xca, 0xcc], "vpshldd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x48, 0x73, 0xca, 0xcc], "vpshrdd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x03, 0xca, 0xcc], "valignd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0x0a, 0xcc], "vextractf32x4 xmmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0x4a, 0x01, 0xcc], "vextractf32x4 xmmword [bp + si * 1 + 0x10]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf32x8 ymmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0x4a, 0x01, 0xcc], "vextractf32x8 ymmword [bp + si * 1 + 0x20]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0x0a, 0xcc], "vcvtps2ph ymmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0x4a, 0x01, 0xcc], "vcvtps2ph ymmword [bp + si * 1 + 0x20]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpud k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpd k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0x0a, 0xcc], "vextracti32x4 xmmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0x4a, 0x01, 0xcc], "vextracti32x4 xmmword [bp + si * 1 + 0x10]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti32x8 ymmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0x4a, 0x01, 0xcc], "vextracti32x8 ymmword [bp + si * 1 + 0x20]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpub k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpub k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpub k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpb k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpb k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpb k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x66, 0xca, 0xcc], "vfpclassps k1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x4d, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x03, 0x0a, 0xcc], "valignd zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x04, 0x0a, 0xcc], "vpermilps zmm1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpud k1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpd k1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x25, 0x0a, 0xcc], "vpternlogd zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x26, 0x0a, 0xcc], "vgetmantps zmm1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x50, 0x0a, 0xcc], "vrangeps zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x56, 0x0a, 0xcc], "vreduceps zmm1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x66, 0x0a, 0xcc], "vfpclassps k1, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x71, 0x0a, 0xcc], "vpshldd zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x73, 0x0a, 0xcc], "vpshrdd zmm1, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x58, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpud k1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpud k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpd k1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpd k1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x66, 0x0a, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x66, 0x4a, 0x01, 0xcc], "vfpclassps k1{k5}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x5d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{sae}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x26, 0xca, 0xcc], "vgetmantps zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x27, 0xca, 0xcc], "vgetmantss xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x50, 0xca, 0xcc], "vrangeps zmm1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x51, 0xca, 0xcc], "vrangess xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x56, 0xca, 0xcc], "vreduceps zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x78, 0x57, 0xca, 0xcc], "vreducess xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{sae}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x7d, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x03, 0xca, 0xcc], "valignd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x04, 0xca, 0xcc], "vpermilps xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x08, 0xca, 0xcc], "vrndscaleps xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x25, 0xca, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x26, 0xca, 0xcc], "vgetmantps xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0x0a, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x42, 0xca, 0xcc], "vdbpsadbw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x50, 0xca, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x56, 0xca, 0xcc], "vreduceps xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x71, 0xca, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x8d, 0x73, 0xca, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x03, 0x0a, 0xcc], "valignd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x03, 0x4a, 0x01, 0xcc], "valignd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x04, 0x0a, 0xcc], "vpermilps xmm1{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x04, 0x4a, 0x01, 0xcc], "vpermilps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x08, 0x0a, 0xcc], "vrndscaleps xmm1{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantps xmm1{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x50, 0x0a, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x50, 0x4a, 0x01, 0xcc], "vrangeps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x56, 0x0a, 0xcc], "vreduceps xmm1{k5}{z}, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x56, 0x4a, 0x01, 0xcc], "vreduceps xmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x71, 0x0a, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x71, 0x4a, 0x01, 0xcc], "vpshldd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, dword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0x9d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x03, 0xca, 0xcc], "valignd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x04, 0xca, 0xcc], "vpermilps ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x08, 0xca, 0xcc], "vrndscaleps ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x0a, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0x4a, 0x01, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0x0a, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x18, 0xca, 0xcc], "vinsertf32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x1d, 0xca, 0xcc], "vcvtps2ph xmm2{k5}{z}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x23, 0xca, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x25, 0xca, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x26, 0xca, 0xcc], "vgetmantps ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0x0a, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0x4a, 0x01, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0x0a, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x38, 0xca, 0xcc], "vinserti32x4 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0x0a, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x42, 0xca, 0xcc], "vdbpsadbw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x43, 0xca, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x50, 0xca, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0x0a, 0xcc], "vrangess xmm1{k5}{z}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0x4a, 0x01, 0xcc], "vrangess xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x54, 0xca, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x56, 0xca, 0xcc], "vreduceps ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0x0a, 0xcc], "vreducess xmm1{k5}{z}, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0x4a, 0x01, 0xcc], "vreducess xmm1{k5}{z}, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x71, 0xca, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xad, 0x73, 0xca, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x03, 0x0a, 0xcc], "valignd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x03, 0x4a, 0x01, 0xcc], "valignd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0x0a, 0xcc], "vpermilps ymm1{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x08, 0x0a, 0xcc], "vrndscaleps ymm1{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x23, 0x0a, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantps ymm1{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x43, 0x0a, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x50, 0x0a, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x56, 0x0a, 0xcc], "vreduceps ymm1{k5}{z}, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps ymm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x71, 0x0a, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, dword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xbd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd ymm1{k5}{z}, ymm0, dword [bp + si * 1 + 0x4]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x03, 0xca, 0xcc], "valignd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x04, 0xca, 0xcc], "vpermilps zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0x4a, 0x01, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x18, 0xca, 0xcc], "vinsertf32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x19, 0xca, 0xcc], "vextractf32x4 xmm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x1b, 0xca, 0xcc], "vextractf32x8 ymm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x23, 0xca, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x25, 0xca, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0x0a, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0x4a, 0x01, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x38, 0xca, 0xcc], "vinserti32x4 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x39, 0xca, 0xcc], "vextracti32x4 xmm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0x4a, 0x01, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x3a, 0xca, 0xcc], "vinserti32x8 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x3b, 0xca, 0xcc], "vextracti32x8 ymm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x0a, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0x4a, 0x01, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x42, 0xca, 0xcc], "vdbpsadbw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x43, 0xca, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x71, 0xca, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xcd, 0x73, 0xca, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x03, 0x0a, 0xcc], "valignd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x03, 0x4a, 0x01, 0xcc], "valignd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x04, 0x0a, 0xcc], "vpermilps zmm1{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x04, 0x4a, 0x01, 0xcc], "vpermilps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x08, 0x0a, 0xcc], "vrndscaleps zmm1{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x08, 0x4a, 0x01, 0xcc], "vrndscaleps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x23, 0x0a, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x23, 0x4a, 0x01, 0xcc], "vshuff32x4 zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantps zmm1{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x43, 0x0a, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x43, 0x4a, 0x01, 0xcc], "vshufi32x4 zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x50, 0x0a, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x50, 0x4a, 0x01, 0xcc], "vrangeps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmps zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x56, 0x0a, 0xcc], "vreduceps zmm1{k5}{z}, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x56, 0x4a, 0x01, 0xcc], "vreduceps zmm1{k5}{z}, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x71, 0x0a, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x71, 0x4a, 0x01, 0xcc], "vpshldd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, dword [bp + si * 1]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xdd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdd zmm1{k5}{z}, zmm0, dword [bp + si * 1 + 0x4]{1to16}, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x08, 0xca, 0xcc], "vrndscaleps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x0a, 0xca, 0xcc], "vrndscaless xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x1d, 0xca, 0xcc], "vcvtps2ph ymm2{k5}{z}{sae}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x26, 0xca, 0xcc], "vgetmantps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x27, 0xca, 0xcc], "vgetmantss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x50, 0xca, 0xcc], "vrangeps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x51, 0xca, 0xcc], "vrangess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmps zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmss xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x56, 0xca, 0xcc], "vreduceps zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0x7d, 0xfd, 0x57, 0xca, 0xcc], "vreducess xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x03, 0xca, 0xcc], "valignq xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x05, 0xca, 0xcc], "vpermilpd xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x09, 0xca, 0xcc], "vrndscalepd xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x0a, 0xcc], "vpalignr xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x0f, 0xca, 0xcc], "vpalignr xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x0a, 0xcc], "vpextrb byte [bp + si * 1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0x4a, 0x01, 0xcc], "vpextrb byte [bp + si * 1 + 0x1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x14, 0xca, 0xcc], "vpextrb edx, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x0a, 0xcc], "vpextrw word [bp + si * 1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0x4a, 0x01, 0xcc], "vpextrw word [bp + si * 1 + 0x2], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x15, 0xca, 0xcc], "vpextrw edx, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x0a, 0xcc], "vpextrd dword [bp + si * 1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0x4a, 0x01, 0xcc], "vpextrd dword [bp + si * 1 + 0x4], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x16, 0xca, 0xcc], "vpextrd edx, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x0a, 0xcc], "vextractps dword [bp + si * 1], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0x4a, 0x01, 0xcc], "vextractps dword [bp + si * 1 + 0x4], xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x17, 0xca, 0xcc], "vextractps edx, xmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1e, 0xca, 0xcc], "vpcmpuq k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x1f, 0xca, 0xcc], "vpcmpq k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x0a, 0xcc], "vpinsrb xmm1, xmm0, byte [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0x4a, 0x01, 0xcc], "vpinsrb xmm1, xmm0, byte [bp + si * 1 + 0x1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x20, 0xca, 0xcc], "vpinsrb xmm1, xmm0, edx, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x0a, 0xcc], "vpinsrd xmm1, xmm0, dword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0x4a, 0x01, 0xcc], "vpinsrd xmm1, xmm0, dword [bp + si * 1 + 0x4], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x22, 0xca, 0xcc], "vpinsrd xmm1, xmm0, edx, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x25, 0xca, 0xcc], "vpternlogq xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x26, 0xca, 0xcc], "vgetmantpd xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3e, 0xca, 0xcc], "vpcmpuw k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0x0a, 0xcc], "vpcmpw k1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x3f, 0xca, 0xcc], "vpcmpw k1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x0a, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x44, 0xca, 0xcc], "vpclmulqdq xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x50, 0xca, 0xcc], "vrangepd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0x0a, 0xcc], "vreducepd xmm1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x56, 0xca, 0xcc], "vreducepd xmm1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0x0a, 0xcc], "vfpclasspd k1, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x66, 0xca, 0xcc], "vfpclasspd k1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0x0a, 0xcc], "vpshldw xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x70, 0xca, 0xcc], "vpshldw xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x71, 0xca, 0xcc], "vpshldq xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0x0a, 0xcc], "vpshrdw xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x72, 0xca, 0xcc], "vpshrdw xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0x73, 0xca, 0xcc], "vpshrdq xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x08, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x0d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x03, 0x0a, 0xcc], "valignq xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x05, 0x0a, 0xcc], "vpermilpd xmm1, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x1f, 0x0a, 0xcc], "vpcmpq k1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x25, 0x0a, 0xcc], "vpternlogq xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x50, 0x0a, 0xcc], "vrangepd xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x56, 0x0a, 0xcc], "vreducepd xmm1, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x71, 0x0a, 0xcc], "vpshldq xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x73, 0x0a, 0xcc], "vpshrdq xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x18, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x1d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0x0a, 0xcc], "vpermq ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x00, 0xca, 0xcc], "vpermq ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0x0a, 0xcc], "vpermpd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x01, 0xca, 0xcc], "vpermpd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x03, 0xca, 0xcc], "valignq ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x05, 0xca, 0xcc], "vpermilpd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x09, 0xca, 0xcc], "vrndscalepd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x0a, 0xcc], "vpalignr ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x0f, 0xca, 0xcc], "vpalignr ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [bp + si * 1], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [bp + si * 1 + 0x10], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1e, 0xca, 0xcc], "vpcmpuq k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x1f, 0xca, 0xcc], "vpcmpq k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x25, 0xca, 0xcc], "vpternlogq ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x26, 0xca, 0xcc], "vgetmantpd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x27, 0xca, 0xcc], "vgetmantsd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [bp + si * 1], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [bp + si * 1 + 0x10], ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3e, 0xca, 0xcc], "vpcmpuw k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0x0a, 0xcc], "vpcmpw k1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x3f, 0xca, 0xcc], "vpcmpw k1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x0a, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x44, 0xca, 0xcc], "vpclmulqdq ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x50, 0xca, 0xcc], "vrangepd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0x0a, 0xcc], "vrangesd xmm1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x51, 0xca, 0xcc], "vrangesd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0x0a, 0xcc], "vreducepd ymm1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x56, 0xca, 0xcc], "vreducepd ymm1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0x0a, 0xcc], "vreducesd xmm1, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x57, 0xca, 0xcc], "vreducesd xmm1, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x0a, 0xcc], "vfpclasspd k1, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x66, 0xca, 0xcc], "vfpclasspd k1, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0x0a, 0xcc], "vfpclasssd k1, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0x4a, 0x01, 0xcc], "vfpclasssd k1, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x67, 0xca, 0xcc], "vfpclasssd k1, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0x0a, 0xcc], "vpshldw ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x70, 0xca, 0xcc], "vpshldw ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x71, 0xca, 0xcc], "vpshldq ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0x0a, 0xcc], "vpshrdw ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x72, 0xca, 0xcc], "vpshrdw ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0x73, 0xca, 0xcc], "vpshrdq ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x28, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x03, 0xca, 0xcc], "valignq ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [bp + si * 1]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [bp + si * 1 + 0x10]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [bp + si * 1]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [bp + si * 1 + 0x10]{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1{k5}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0x0a, 0xcc], "vfpclasssd k1{k5}, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0x4a, 0x01, 0xcc], "vfpclasssd k1{k5}, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x67, 0xca, 0xcc], "vfpclasssd k1{k5}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x2d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x0a, 0xcc], "vpermq ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x01, 0x0a, 0xcc], "vpermpd ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x03, 0x0a, 0xcc], "valignq ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x05, 0x0a, 0xcc], "vpermilpd ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x1f, 0x0a, 0xcc], "vpcmpq k1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x25, 0x0a, 0xcc], "vpternlogq ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x50, 0x0a, 0xcc], "vrangepd ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x56, 0x0a, 0xcc], "vreducepd ymm1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x71, 0x0a, 0xcc], "vpshldq ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x73, 0x0a, 0xcc], "vpshrdq ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x38, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x3d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0x0a, 0xcc], "vpermq zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x00, 0xca, 0xcc], "vpermq zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0x0a, 0xcc], "vpermpd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x01, 0xca, 0xcc], "vpermpd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x03, 0xca, 0xcc], "valignq zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x05, 0xca, 0xcc], "vpermilpd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x09, 0xca, 0xcc], "vrndscalepd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0x0a, 0xcc], "vpalignr zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x0f, 0xca, 0xcc], "vpalignr zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [bp + si * 1 + 0x10], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0x4a, 0x01, 0xcc], "vextractf64x4 ymmword [bp + si * 1 + 0x20], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1e, 0xca, 0xcc], "vpcmpuq k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x1f, 0xca, 0xcc], "vpcmpq k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x25, 0xca, 0xcc], "vpternlogq zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x26, 0xca, 0xcc], "vgetmantpd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [bp + si * 1 + 0x10], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [bp + si * 1], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0x4a, 0x01, 0xcc], "vextracti64x4 ymmword [bp + si * 1 + 0x20], zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0x0a, 0xcc], "vpcmpuw k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3e, 0xca, 0xcc], "vpcmpuw k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0x0a, 0xcc], "vpcmpw k1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x3f, 0xca, 0xcc], "vpcmpw k1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x0a, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0x4a, 0x01, 0xcc], "vpclmulqdq zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x44, 0xca, 0xcc], "vpclmulqdq zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x50, 0xca, 0xcc], "vrangepd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0x0a, 0xcc], "vreducepd zmm1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x56, 0xca, 0xcc], "vreducepd zmm1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0x0a, 0xcc], "vfpclasspd k1, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x66, 0xca, 0xcc], "vfpclasspd k1, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0x0a, 0xcc], "vpshldw zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x70, 0xca, 0xcc], "vpshldw zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x71, 0xca, 0xcc], "vpshldq zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0x0a, 0xcc], "vpshrdw zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x72, 0xca, 0xcc], "vpshrdw zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0x73, 0xca, 0xcc], "vpshrdq zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x48, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x03, 0xca, 0xcc], "valignq zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0x0a, 0xcc], "vextractf64x2 xmmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0x4a, 0x01, 0xcc], "vextractf64x2 xmmword [bp + si * 1 + 0x10]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0x0a, 0xcc], "vextractf64x4 ymmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0x4a, 0x01, 0xcc], "vextractf64x4 ymmword [bp + si * 1 + 0x20]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1e, 0xca, 0xcc], "vpcmpuq k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x1f, 0xca, 0xcc], "vpcmpq k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0x0a, 0xcc], "vextracti64x2 xmmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0x4a, 0x01, 0xcc], "vextracti64x2 xmmword [bp + si * 1 + 0x10]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0x0a, 0xcc], "vextracti64x4 ymmword [bp + si * 1]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0x4a, 0x01, 0xcc], "vextracti64x4 ymmword [bp + si * 1 + 0x20]{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0x0a, 0xcc], "vpcmpuw k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0x4a, 0x01, 0xcc], "vpcmpuw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3e, 0xca, 0xcc], "vpcmpuw k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0x0a, 0xcc], "vpcmpw k1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0x4a, 0x01, 0xcc], "vpcmpw k1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x3f, 0xca, 0xcc], "vpcmpw k1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x66, 0xca, 0xcc], "vfpclasspd k1{k5}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x4d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x00, 0x0a, 0xcc], "vpermq zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x01, 0x0a, 0xcc], "vpermpd zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x03, 0x0a, 0xcc], "valignq zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x05, 0x0a, 0xcc], "vpermilpd zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x1e, 0x0a, 0xcc], "vpcmpuq k1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x1f, 0x0a, 0xcc], "vpcmpq k1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x25, 0x0a, 0xcc], "vpternlogq zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x50, 0x0a, 0xcc], "vrangepd zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x56, 0x0a, 0xcc], "vreducepd zmm1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x66, 0x0a, 0xcc], "vfpclasspd k1, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x71, 0x0a, 0xcc], "vpshldq zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x73, 0x0a, 0xcc], "vpshrdq zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x58, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x1e, 0x0a, 0xcc], "vpcmpuq k1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x1e, 0x4a, 0x01, 0xcc], "vpcmpuq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x1f, 0x0a, 0xcc], "vpcmpq k1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x1f, 0x4a, 0x01, 0xcc], "vpcmpq k1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x66, 0x0a, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x66, 0x4a, 0x01, 0xcc], "vfpclasspd k1{k5}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x5d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x50, 0xca, 0xcc], "vrangepd zmm1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x51, 0xca, 0xcc], "vrangesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x56, 0xca, 0xcc], "vreducepd zmm1{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x78, 0x57, 0xca, 0xcc], "vreducesd xmm1{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x7d, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x03, 0xca, 0xcc], "valignq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x05, 0xca, 0xcc], "vpermilpd xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x09, 0xca, 0xcc], "vrndscalepd xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0x0a, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x0f, 0xca, 0xcc], "vpalignr xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x25, 0xca, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x26, 0xca, 0xcc], "vgetmantpd xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x50, 0xca, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x54, 0xca, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}{z}, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x56, 0xca, 0xcc], "vreducepd xmm1{k5}{z}, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0x0a, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0x4a, 0x01, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x70, 0xca, 0xcc], "vpshldw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x71, 0xca, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0x0a, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x72, 0xca, 0xcc], "vpshrdw xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0x73, 0xca, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xce, 0xca, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x8d, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x03, 0x0a, 0xcc], "valignq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x03, 0x4a, 0x01, 0xcc], "valignq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x05, 0x0a, 0xcc], "vpermilpd xmm1{k5}{z}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x09, 0x0a, 0xcc], "vrndscalepd xmm1{k5}{z}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x25, 0x0a, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x26, 0x0a, 0xcc], "vgetmantpd xmm1{k5}{z}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x50, 0x0a, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x50, 0x4a, 0x01, 0xcc], "vrangepd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x54, 0x0a, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x56, 0x0a, 0xcc], "vreducepd xmm1{k5}{z}, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x56, 0x4a, 0x01, 0xcc], "vreducepd xmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x71, 0x0a, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x71, 0x4a, 0x01, 0xcc], "vpshldq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x73, 0x0a, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0xce, 0x0a, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, qword [bp + si * 1]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0x9d, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8]{1to2}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x00, 0xca, 0xcc], "vpermq ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x01, 0xca, 0xcc], "vpermpd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x03, 0xca, 0xcc], "valignq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x05, 0xca, 0xcc], "vpermilpd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x09, 0xca, 0xcc], "vrndscalepd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x0a, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0x4a, 0x01, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x0a, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x0f, 0xca, 0xcc], "vpalignr ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x0a, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x18, 0xca, 0xcc], "vinsertf64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x23, 0xca, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x25, 0xca, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x26, 0xca, 0xcc], "vgetmantpd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0x0a, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0x4a, 0x01, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0x0a, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x38, 0xca, 0xcc], "vinserti64x2 ymm1{k5}{z}, ymm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, ymm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x43, 0xca, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x50, 0xca, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0x0a, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0x4a, 0x01, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x54, 0xca, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0x0a, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0x4a, 0x01, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}{z}, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x56, 0xca, 0xcc], "vreducepd ymm1{k5}{z}, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0x0a, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, qword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0x4a, 0x01, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, qword [bp + si * 1 + 0x8], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0x0a, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0x4a, 0x01, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x70, 0xca, 0xcc], "vpshldw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x71, 0xca, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0x0a, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x72, 0xca, 0xcc], "vpshrdw ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0x73, 0xca, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xce, 0xca, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xad, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0x0a, 0xcc], "vpermq ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x00, 0x4a, 0x01, 0xcc], "vpermq ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x01, 0x0a, 0xcc], "vpermpd ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x03, 0x0a, 0xcc], "valignq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x03, 0x4a, 0x01, 0xcc], "valignq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x05, 0x0a, 0xcc], "vpermilpd ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x09, 0x0a, 0xcc], "vrndscalepd ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x23, 0x0a, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x25, 0x0a, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x26, 0x0a, 0xcc], "vgetmantpd ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x43, 0x0a, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x50, 0x0a, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x54, 0x0a, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x56, 0x0a, 0xcc], "vreducepd ymm1{k5}{z}, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd ymm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x71, 0x0a, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x73, 0x0a, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, qword [bp + si * 1]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xbd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb ymm1{k5}{z}, ymm0, qword [bp + si * 1 + 0x8]{1to4}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x00, 0xca, 0xcc], "vpermq zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x01, 0xca, 0xcc], "vpermpd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x03, 0xca, 0xcc], "valignq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x05, 0xca, 0xcc], "vpermilpd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x0a, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0x4a, 0x01, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x0f, 0xca, 0xcc], "vpalignr zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0x0a, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0x4a, 0x01, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x18, 0xca, 0xcc], "vinsertf64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x19, 0xca, 0xcc], "vextractf64x2 xmm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0x0a, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0x4a, 0x01, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x1a, 0xca, 0xcc], "vinsertf64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x1b, 0xca, 0xcc], "vextractf64x4 ymm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x23, 0xca, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x25, 0xca, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0x0a, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0x4a, 0x01, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmmword [bp + si * 1 + 0x10], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x38, 0xca, 0xcc], "vinserti64x2 zmm1{k5}{z}, zmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x39, 0xca, 0xcc], "vextracti64x2 xmm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0x0a, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0x4a, 0x01, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymmword [bp + si * 1 + 0x20], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x3a, 0xca, 0xcc], "vinserti64x4 zmm1{k5}{z}, zmm0, ymm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x3b, 0xca, 0xcc], "vextracti64x4 ymm2{k5}{z}, zmm1, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x43, 0xca, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}{z}, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0x0a, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0x4a, 0x01, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x70, 0xca, 0xcc], "vpshldw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x71, 0xca, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0x0a, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0x4a, 0x01, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x72, 0xca, 0xcc], "vpshrdw zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0x73, 0xca, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xce, 0xca, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmmword [bp + si * 1 + 0x40], 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xcd, 0xcf, 0xca, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x00, 0x0a, 0xcc], "vpermq zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x00, 0x4a, 0x01, 0xcc], "vpermq zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x01, 0x0a, 0xcc], "vpermpd zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x01, 0x4a, 0x01, 0xcc], "vpermpd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x03, 0x0a, 0xcc], "valignq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x03, 0x4a, 0x01, 0xcc], "valignq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x05, 0x0a, 0xcc], "vpermilpd zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x05, 0x4a, 0x01, 0xcc], "vpermilpd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x09, 0x0a, 0xcc], "vrndscalepd zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x09, 0x4a, 0x01, 0xcc], "vrndscalepd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x23, 0x0a, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x23, 0x4a, 0x01, 0xcc], "vshuff64x2 zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x25, 0x0a, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x25, 0x4a, 0x01, 0xcc], "vpternlogq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x26, 0x0a, 0xcc], "vgetmantpd zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x26, 0x4a, 0x01, 0xcc], "vgetmantpd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x43, 0x0a, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x43, 0x4a, 0x01, 0xcc], "vshufi64x2 zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x50, 0x0a, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x50, 0x4a, 0x01, 0xcc], "vrangepd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x54, 0x0a, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x54, 0x4a, 0x01, 0xcc], "vfixupimmpd zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x56, 0x0a, 0xcc], "vreducepd zmm1{k5}{z}, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x56, 0x4a, 0x01, 0xcc], "vreducepd zmm1{k5}{z}, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x71, 0x0a, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x71, 0x4a, 0x01, 0xcc], "vpshldq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x73, 0x0a, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0x73, 0x4a, 0x01, 0xcc], "vpshrdq zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0xce, 0x0a, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0xce, 0x4a, 0x01, 0xcc], "vgf2p8affineqb zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0xcf, 0x0a, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, qword [bp + si * 1]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xdd, 0xcf, 0x4a, 0x01, 0xcc], "vgf2p8affineinvqb zmm1{k5}{z}, zmm0, qword [bp + si * 1 + 0x8]{1to8}, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x09, 0xca, 0xcc], "vrndscalepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x0b, 0xca, 0xcc], "vrndscalesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x26, 0xca, 0xcc], "vgetmantpd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x27, 0xca, 0xcc], "vgetmantsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x50, 0xca, 0xcc], "vrangepd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x51, 0xca, 0xcc], "vrangesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x54, 0xca, 0xcc], "vfixupimmpd zmm1{k5}{z}{sae}, zmm0, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x55, 0xca, 0xcc], "vfixupimmsd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x56, 0xca, 0xcc], "vreducepd zmm1{k5}{z}{sae}, zmm2, 0xcc"); test_display(&[0x62, 0xf3, 0xfd, 0xfd, 0x57, 0xca, 0xcc], "vreducesd xmm1{k5}{z}{sae}, xmm0, xmm2, 0xcc"); test_display(&[0x63, 0xc1], "arpl cx, ax"); test_display(&[0x65, 0x66, 0x0f, 0x01, 0xdc], "stgi"); test_display(&[0x65, 0x66, 0x66, 0x64, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword fs:[bx]"); test_display(&[0x65, 0x67, 0x65, 0x65, 0x0f, 0x0e], "femms"); test_display(&[0x65, 0x89, 0x04], "mov word gs:[si], ax"); test_display(&[0x65, 0xf0, 0x87, 0x0f], "lock xchg word gs:[bx], cx"); test_display(&[0x66, 0x0f, 0x01, 0xd8], "vmrun ax"); test_display(&[0x66, 0x0f, 0x02, 0x01], "lar eax, word [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x02, 0xc1], "lar eax, ecx"); test_display(&[0x66, 0x0f, 0x03, 0x01], "lsl eax, word [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x03, 0xc1], "lsl eax, ecx"); test_display(&[0x66, 0x0f, 0x05], "syscall"); test_display(&[0x66, 0x0f, 0x0f, 0xc6, 0xb7], "pmulhrw mm0, mm6"); test_display(&[0x66, 0x0f, 0x10, 0xc0], "movupd xmm0, xmm0"); test_display(&[0x66, 0x0f, 0x12, 0x03], "movlpd xmm0, qword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0x13, 0x03], "movlpd qword [bp + di * 1], xmm0"); test_display(&[0x66, 0x0f, 0x14, 0x03], "unpcklpd xmm0, xmmword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0x14, 0xc3], "unpcklpd xmm0, xmm3"); test_display(&[0x66, 0x0f, 0x15, 0x03], "unpckhpd xmm0, xmmword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0x15, 0xc3], "unpckhpd xmm0, xmm3"); test_display(&[0x66, 0x0f, 0x16, 0x03], "movhpd xmm0, qword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0x17, 0x03], "movhpd qword [bp + di * 1], xmm0"); test_display(&[0x66, 0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [bx + si * 1]"); test_display(&[0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [bx + si * 1]"); test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x28, 0xd0], "movapd xmm2, xmm0"); test_display(&[0x66, 0x0f, 0x29, 0x00], "movapd xmmword [bx + si * 1], xmm0"); test_display(&[0x66, 0x0f, 0x2a, 0x00], "cvtpi2pd xmm0, qword [bx + si * 1]"); test_display(&[0x66, 0x0f, 0x2a, 0x0f], "cvtpi2pd xmm1, qword [bx]"); test_display(&[0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_display(&[0x66, 0x0f, 0x2a, 0xcf], "cvtpi2pd xmm1, mm7"); test_display(&[0x66, 0x0f, 0x2b, 0x0f], "movntpd xmmword [bx], xmm1"); test_display(&[0x66, 0x0f, 0x2c, 0x0f], "cvttpd2pi mm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x2c, 0xcf], "cvttpd2pi mm1, xmm7"); test_display(&[0x66, 0x0f, 0x2d, 0x0f], "cvtpd2pi mm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x2d, 0xcf], "cvtpd2pi mm1, xmm7"); test_display(&[0x66, 0x0f, 0x2e, 0x0f], "ucomisd xmm1, qword [bx]"); test_display(&[0x66, 0x0f, 0x2e, 0xcf], "ucomisd xmm1, xmm7"); test_display(&[0x66, 0x0f, 0x2f, 0x0f], "comisd xmm1, qword [bx]"); test_display(&[0x66, 0x0f, 0x2f, 0xcf], "comisd xmm1, xmm7"); test_display(&[0x66, 0x0f, 0x38, 0x00, 0xda], "pshufb xmm3, xmm2"); test_display(&[0x66, 0x0f, 0x38, 0x37, 0x03], "pcmpgtq xmm0, xmmword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0x38, 0x37, 0xc3], "pcmpgtq xmm0, xmm3"); test_display(&[0x66, 0x0f, 0x38, 0x80, 0x2f], "invept ebp, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0x81, 0x2f], "invvpid ebp, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0x82, 0x2f], "invpcid ebp, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xcf, 0x1c], "gf2p8mulb xmm3, xmmword [si]"); test_display(&[0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x38, 0xf5, 0x47, 0xe9], "wruss dword [bx - 0x17], eax"); test_display(&[0x66, 0x0f, 0x38, 0xf6, 0x01], "adcx eax, dword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x38, 0xf6, 0xc1], "adcx eax, ecx"); test_display(&[0x66, 0x0f, 0x3a, 0x0c, 0x11, 0x22], "blendps xmm2, xmmword [bx + di * 1], 0x22"); test_display(&[0x66, 0x0f, 0x3a, 0x0c, 0xc1, 0x22], "blendps xmm0, xmm1, 0x22"); test_display(&[0x66, 0x0f, 0x3a, 0x0d, 0x11, 0x22], "blendpd xmm2, xmmword [bx + di * 1], 0x22"); test_display(&[0x66, 0x0f, 0x3a, 0x0d, 0xc1, 0x22], "blendpd xmm0, xmm1, 0x22"); test_display(&[0x66, 0x0f, 0x3a, 0x60, 0xc6, 0x54], "pcmpestrm xmm0, xmm6, 0x54"); test_display(&[0x66, 0x0f, 0x3a, 0x61, 0xc6, 0x54], "pcmpestri xmm0, xmm6, 0x54"); test_display(&[0x66, 0x0f, 0x3a, 0x62, 0xc6, 0x54], "pcmpistrm xmm0, xmm6, 0x54"); test_display(&[0x66, 0x0f, 0x3a, 0x63, 0xc6, 0x54], "pcmpistri xmm0, xmm6, 0x54"); test_display(&[0x66, 0x0f, 0x3a, 0xdf, 0x0f, 0xaa], "aeskeygenassist xmm1, xmmword [bx], 0xaa"); test_display(&[0x66, 0x0f, 0x50, 0xc1], "movmskpd eax, xmm1"); test_display(&[0x66, 0x0f, 0x51, 0x01], "sqrtpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x54, 0x01], "andpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x55, 0x01], "andnpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x56, 0x01], "orpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x57, 0x01], "xorpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x58, 0x01], "addpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x59, 0x01], "mulpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5a, 0x01], "cvtpd2ps xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5b, 0x01], "cvtps2dq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5c, 0x01], "subpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5d, 0x01], "minpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5e, 0x01], "divpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x5f, 0x01], "maxpd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0x6e, 0xc0], "movd xmm0, eax"); test_display(&[0x66, 0x0f, 0x70, 0xc0, 0x4e], "pshufd xmm0, xmm0, 0x4e"); test_display(&[0x66, 0x0f, 0x71, 0xd0, 0x8f], "psrlw xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x71, 0xe0, 0x8f], "psraw xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x71, 0xf0, 0x8f], "psllw xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x72, 0xd0, 0x8f], "psrld xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x72, 0xe0, 0x8f], "psrad xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x72, 0xf0, 0x8f], "pslld xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x73, 0xd0, 0x8f], "psrlq xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x73, 0xd8, 0x8f], "psrldq xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x73, 0xf0, 0x8f], "psllq xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x73, 0xf8, 0x8f], "pslldq xmm0, 0x8f"); test_display(&[0x66, 0x0f, 0x74, 0x12], "pcmpeqb xmm2, xmmword [bp + si * 1]"); test_display(&[0x66, 0x0f, 0x74, 0xc1], "pcmpeqb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0x78, 0xc1, 0x4e, 0x76], "extrq xmm1, 0x4e, 0x76"); test_display(&[0x66, 0x0f, 0x79, 0xcf], "extrq xmm1, xmm7"); test_display(&[0x66, 0x0f, 0x7c, 0x0f], "haddpd xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x7c, 0xcf], "haddpd xmm1, xmm7"); test_display(&[0x66, 0x0f, 0x7d, 0x0f], "hsubpd xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0x7d, 0xcf], "hsubpd xmm1, xmm7"); test_display(&[0x66, 0x0f, 0x7e, 0x01], "movd dword [bx + di * 1], xmm0"); test_display(&[0x66, 0x0f, 0x7e, 0xc1], "movd ecx, xmm0"); test_display(&[0x66, 0x0f, 0xa4, 0xcf, 0x11], "shld edi, ecx, 0x11"); test_display(&[0x66, 0x0f, 0xac, 0xcf, 0x11], "shrd edi, ecx, 0x11"); test_display(&[0x66, 0x0f, 0xae, 0x37], "clwb zmmword [bx]"); test_display(&[0x66, 0x0f, 0xae, 0x3f], "clflushopt zmmword [bx]"); test_display(&[0x66, 0x0f, 0xae, 0xf1], "tpause ecx"); test_display(&[0x66, 0x0f, 0xae, 0xf7], "tpause edi"); test_display(&[0x66, 0x0f, 0xaf, 0xd1], "imul edx, ecx"); test_display(&[0x66, 0x0f, 0xb3, 0xc0], "btr eax, eax"); test_display(&[0x66, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0x66, 0x0f, 0xc1, 0xcc], "xadd esp, ecx"); test_display(&[0x66, 0x0f, 0xc2, 0x03, 0x08], "cmppd xmm0, xmmword [bp + di * 1], 0x8"); test_display(&[0x66, 0x0f, 0xc2, 0xc3, 0x08], "cmppd xmm0, xmm3, 0x8"); test_display(&[0x66, 0x0f, 0xc4, 0x03, 0x08], "pinsrw xmm0, word [bp + di * 1], 0x8"); test_display(&[0x66, 0x0f, 0xc4, 0xc3, 0x08], "pinsrw xmm0, ebx, 0x8"); test_display(&[0x66, 0x0f, 0xc5, 0xd8, 0xff], "pextrw ebx, xmm0, 0xff"); test_display(&[0x66, 0x0f, 0xc6, 0x03, 0x08], "shufpd xmm0, xmmword [bp + di * 1], 0x8"); test_display(&[0x66, 0x0f, 0xc6, 0xc3, 0x08], "shufpd xmm0, xmm3, 0x8"); test_display(&[0x66, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [bx]"); test_display(&[0x66, 0x0f, 0xc7, 0x33], "vmclear qword [bp + di * 1]"); test_display(&[0x66, 0x0f, 0xc7, 0x37], "vmclear qword [bx]"); test_display(&[0x66, 0x0f, 0xc7, 0xf5], "rdrand ebp"); test_display(&[0x66, 0x0f, 0xc7, 0xf7], "rdrand edi"); test_display(&[0x66, 0x0f, 0xc7, 0xfd], "rdseed ebp"); test_display(&[0x66, 0x0f, 0xd0, 0x0f], "addsubpd xmm1, xmmword [bx]"); test_display(&[0x66, 0x0f, 0xd0, 0xcf], "addsubpd xmm1, xmm7"); test_display(&[0x66, 0x0f, 0xd1, 0x01], "psrlw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd1, 0xc1], "psrlw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd2, 0x01], "psrld xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd2, 0xc1], "psrld xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd3, 0x01], "psrlq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd3, 0xc1], "psrlq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd4, 0x01], "paddq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd4, 0xc1], "paddq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd5, 0x01], "pmullw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd5, 0xc1], "pmullw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd6, 0x01], "movq qword [bx + di * 1], xmm0"); test_display(&[0x66, 0x0f, 0xd6, 0xc1], "movq xmm1, xmm0"); test_display(&[0x66, 0x0f, 0xd7, 0xc1], "pmovmskb eax, xmm1"); test_display(&[0x66, 0x0f, 0xd8, 0x01], "psubusb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd8, 0xc1], "psubusb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xd9, 0x01], "psubusw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xd9, 0xc1], "psubusw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xda, 0x01], "pminub xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xda, 0xc1], "pminub xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xdb, 0x01], "pand xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xdb, 0xc1], "pand xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xdc, 0x01], "paddusb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xdc, 0xc1], "paddusb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xdd, 0x01], "paddusw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xdd, 0xc1], "paddusw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xde, 0x01], "pmaxub xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xde, 0xc1], "pmaxub xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xdf, 0x01], "pandn xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xdf, 0xc1], "pandn xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe0, 0x01], "pavgb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe0, 0xc1], "pavgb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe1, 0x01], "psraw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe1, 0xc1], "psraw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe2, 0x01], "psrad xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe2, 0xc1], "psrad xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe3, 0x01], "pavgw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe3, 0xc1], "pavgw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe4, 0x01], "pmulhuw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe4, 0xc1], "pmulhuw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe5, 0x01], "pmulhw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe5, 0xc1], "pmulhw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe6, 0x01], "cvttpd2dq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe6, 0xc1], "cvttpd2dq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe7, 0x01], "movntdq xmmword [bx + di * 1], xmm0"); test_display(&[0x66, 0x0f, 0xe8, 0x01], "psubsb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe8, 0xc1], "psubsb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xe9, 0x01], "psubsw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xe9, 0xc1], "psubsw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xea, 0x01], "pminsw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xea, 0xc1], "pminsw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xeb, 0x01], "por xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xeb, 0x12], "por xmm2, xmmword [bp + si * 1]"); test_display(&[0x66, 0x0f, 0xeb, 0xc1], "por xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xeb, 0xc3], "por xmm0, xmm3"); test_display(&[0x66, 0x0f, 0xeb, 0xc4], "por xmm0, xmm4"); test_display(&[0x66, 0x0f, 0xeb, 0xd3], "por xmm2, xmm3"); test_display(&[0x66, 0x0f, 0xec, 0x01], "paddsb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xec, 0xc1], "paddsb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xed, 0x01], "paddsw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xed, 0xc1], "paddsw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xee, 0x01], "pmaxsw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xee, 0xc1], "pmaxsw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xef, 0x01], "pxor xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xef, 0xc0], "pxor xmm0, xmm0"); test_display(&[0x66, 0x0f, 0xef, 0xc1], "pxor xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf1, 0x01], "psllw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf1, 0xc1], "psllw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf2, 0x01], "pslld xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf2, 0xc1], "pslld xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf3, 0x01], "psllq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf3, 0xc1], "psllq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf4, 0x01], "pmuludq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf4, 0xc1], "pmuludq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf5, 0x01], "pmaddwd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf5, 0xc1], "pmaddwd xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf6, 0x01], "psadbw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf6, 0xc1], "psadbw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf7, 0xc1], "maskmovdqu xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf8, 0x01], "psubb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf8, 0x12], "psubb xmm2, xmmword [bp + si * 1]"); test_display(&[0x66, 0x0f, 0xf8, 0xc1], "psubb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xf8, 0xc8], "psubb xmm1, xmm0"); test_display(&[0x66, 0x0f, 0xf8, 0xd0], "psubb xmm2, xmm0"); test_display(&[0x66, 0x0f, 0xf9, 0x01], "psubw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xf9, 0xc1], "psubw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xfa, 0x01], "psubd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xfa, 0xc1], "psubd xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xfb, 0x01], "psubq xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xfb, 0xc1], "psubq xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xfc, 0x01], "paddb xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xfc, 0xc1], "paddb xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xfd, 0x01], "paddw xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xfd, 0xc1], "paddw xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xfe, 0x01], "paddd xmm0, xmmword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xfe, 0xc1], "paddd xmm0, xmm1"); test_display(&[0x66, 0x0f, 0xff, 0x01], "ud0 eax, dword [bx + di * 1]"); test_display(&[0x66, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_display(&[0x66, 0x2e, 0xf2, 0xf0, 0x0f, 0xbb, 0x13], "xacquire lock btc dword cs:[bp + di * 1], edx"); test_display(&[0x66, 0x31, 0xc0], "xor eax, eax"); test_display(&[0x66, 0x32, 0xc0], "xor al, al"); test_display(&[0x66, 0x32, 0xc5], "xor al, ch"); test_display(&[0x66, 0x3e, 0x26, 0x2e, 0x2e, 0x0f, 0x38, 0x2a, 0x2b], "movntdqa xmm5, xmmword cs:[bp + di * 1]"); test_display(&[0x66, 0x50], "push eax"); test_display(&[0x66, 0x66, 0x64, 0x3e, 0x0f, 0x38, 0x23, 0x9d, 0x69, 0x0f], "pmovsxwd xmm3, qword [di + 0xf69]"); test_display(&[0x66, 0x8f, 0x00], "pop dword [bx + si * 1]"); test_display(&[0x66, 0x91], "xchg eax, ecx"); test_display(&[0x66, 0x99], "cdq"); test_display(&[0x66, 0xc5, 0x78, 0x10], "lds edi, far [bx + si * 1 + 0x10]"); test_display(&[0x66, 0xcf], "iretd"); test_display(&[0x66, 0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, esi"); test_display(&[0x66, 0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0x66, 0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0x66, 0xf3, 0x0f, 0xbd, 0xc1], "lzcnt eax, ecx"); test_display(&[0x66, 0xff, 0xe0], "jmp eax"); test_display(&[0x67, 0x0f, 0x5b, 0x01], "cvtdq2ps xmm0, xmmword [ecx]"); test_display(&[0x67, 0x66, 0x0f, 0x28, 0x00], "movapd xmm0, xmmword [eax]"); test_display(&[0x67, 0x66, 0x0f, 0x38, 0xdb, 0x0f], "aesimc xmm1, xmmword [edi]"); test_display(&[0x67, 0x66, 0x0f, 0x38, 0xdc, 0x0f], "aesenc xmm1, xmmword [edi]"); test_display(&[0x67, 0x66, 0x0f, 0x38, 0xdd, 0x0f], "aesenclast xmm1, xmmword [edi]"); test_display(&[0x67, 0x66, 0x0f, 0x38, 0xde, 0x0f], "aesdec xmm1, xmmword [edi]"); test_display(&[0x67, 0x66, 0x0f, 0x38, 0xdf, 0x0f], "aesdeclast xmm1, xmmword [edi]"); test_display(&[0x67, 0x66, 0x65, 0x3e, 0x0f, 0x6d, 0xd1], "punpckhqdq xmm2, xmm1"); test_display(&[0x67, 0xe5, 0x99], "in ax, 0x99"); test_display(&[0x67, 0xff, 0xe0], "jmp ax"); test_display(&[0x68, 0x7f, 0x63], "push 0x637f"); test_display(&[0x6b, 0x43, 0x6f, 0x6d], "imul ax, word [bp + di * 1 + 0x6f], 0x6d"); test_display(&[0x72, 0x5a], "jb $+0x5a"); test_display(&[0x72, 0xf0], "jb $-0x10"); test_display(&[0x73, 0x31], "jnb $+0x31"); test_display(&[0x74, 0x47], "jz $+0x47"); test_display(&[0x81, 0xec, 0x10, 0x03], "sub sp, 0x310"); test_display(&[0x66, 0x81, 0xec, 0x10, 0x03, 0x00, 0x00], "sub esp, 0x310"); test_display(&[0x83, 0xf8, 0xff], "cmp ax, -0x1"); test_display(&[0x66, 0x83, 0xf8, 0xff], "cmp eax, -0x1"); test_display(&[0x89, 0x43, 0x18], "mov word [bp + di * 1 + 0x18], ax"); test_display(&[0x89, 0x46, 0x10], "mov word [bp + 0x10], ax"); test_display(&[0x89, 0x4e, 0x08], "mov word [bp + 0x8], cx"); test_display(&[0x89, 0x55, 0x94], "mov word [di - 0x6c], dx"); test_display(&[0x8b, 0x32], "mov si, word [bp + si * 1]"); test_display(&[0x8b, 0x4c, 0x10], "mov cx, word [si + 0x10]"); test_display(&[0x8d, 0x53, 0x08], "lea dx, word [bp + di * 1 + 0x8]"); test_display(&[0x8e, 0x00], "mov es, word [bx + si * 1]"); test_display(&[0x8e, 0x10], "mov ss, word [bx + si * 1]"); test_display(&[0x8e, 0x18], "mov ds, word [bx + si * 1]"); test_display(&[0x8e, 0x20], "mov fs, word [bx + si * 1]"); test_display(&[0x8e, 0x28], "mov gs, word [bx + si * 1]"); test_display(&[0x8f, 0x00], "pop word [bx + si * 1]"); test_display(&[0x90], "nop"); test_display(&[0x91], "xchg ax, cx"); test_display(&[0x98], "cbw"); test_display(&[0x9c], "pushf"); test_display(&[0xa0, 0x93, 0x62], "mov al, byte [0x6293]"); test_display(&[0xa1, 0x93, 0x62], "mov ax, word [0x6293]"); test_display(&[0xa2, 0x93, 0x62], "mov byte [0x6293], al"); test_display(&[0xa3, 0x93, 0x62], "mov word [0x6293], ax"); test_display(&[0xba, 0x01, 0x00], "mov dx, 0x1"); test_display(&[0xc3], "ret"); test_display(&[0xc4, 0x02], "les ax, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x38, 0x14, 0x0a], "vunpcklps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x38, 0x15, 0x0a], "vunpckhps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x38, 0xc6, 0xca, 0x77], "vshufps xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0x39, 0x14, 0x0a], "vunpcklpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x39, 0x15, 0x0a], "vunpckhpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x39, 0x60, 0xca], "vpunpcklbw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x61, 0xca], "vpunpcklwd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x62, 0xca], "vpunpckldq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x63, 0xca], "vpacksswb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x64, 0xca], "vpcmpgtb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x65, 0xca], "vpcmpgtw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x66, 0xca], "vpcmpgtd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x67, 0xca], "vpackuswb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x68, 0xca], "vpunpckhbw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x69, 0xca], "vpunpckhwd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x6a, 0xca], "vpunpckhdq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0x6b, 0xca], "vpackssdw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xc6, 0xca, 0x77], "vshufpd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0x39, 0xd5, 0xca], "vpmullw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xda, 0xca], "vpminub xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xde, 0xca], "vpmaxub xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xea, 0xca], "vpminsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xeb, 0xca], "vpor xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xec, 0xca], "vpaddsb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xed, 0xca], "vpaddsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xee, 0xca], "vpmaxsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x39, 0xef, 0xca], "vpxor xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0x3a, 0x5c, 0x0a], "vsubss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3b, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3b, 0x5c, 0x0a], "vsubsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3c, 0x14, 0x0a], "vunpcklps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3c, 0x15, 0x0a], "vunpckhps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3c, 0xc6, 0xca, 0x77], "vshufps ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0x3d, 0x14, 0x0a], "vunpcklpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3d, 0x15, 0x0a], "vunpckhpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3d, 0x60, 0xca], "vpunpcklbw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x61, 0xca], "vpunpcklwd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x62, 0xca], "vpunpckldq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x63, 0xca], "vpacksswb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x64, 0xca], "vpcmpgtb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x65, 0xca], "vpcmpgtw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x66, 0xca], "vpcmpgtd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x67, 0xca], "vpackuswb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x68, 0xca], "vpunpckhbw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x69, 0xca], "vpunpckhwd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x6a, 0xca], "vpunpckhdq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0x6b, 0xca], "vpackssdw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xc6, 0xca, 0x77], "vshufpd ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0x3d, 0xd5, 0xca], "vpmullw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xda, 0xca], "vpminub ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xde, 0xca], "vpmaxub ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xea, 0xca], "vpminsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xeb, 0xca], "vpor ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xec, 0xca], "vpaddsb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xed, 0xca], "vpaddsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xee, 0xca], "vpmaxsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3d, 0xef, 0xca], "vpxor ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0x3e, 0x5c, 0x0a], "vsubss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3f, 0x51, 0x0a], "vsqrtsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x3f, 0x5c, 0x0a], "vsubsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x78, 0x28, 0xca], "vmovaps xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x78, 0x29, 0xca], "vmovaps xmm2, xmm1"); test_display(&[0xc4, 0xc1, 0x78, 0x2b, 0x0a], "vmovntps xmmword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0x78, 0x5c, 0x0a], "vsubps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x78, 0xae, 0x11], "vldmxcsr dword [bx + di * 1]"); test_display(&[0xc4, 0xc1, 0x78, 0xae, 0x19], "vstmxcsr dword [bx + di * 1]"); test_display(&[0xc4, 0xc1, 0x79, 0x28, 0xca], "vmovapd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x79, 0x29, 0xca], "vmovapd xmm2, xmm1"); test_display(&[0xc4, 0xc1, 0x79, 0x2b, 0x0a], "vmovntpd xmmword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0x79, 0x2e, 0x0a], "vucomisd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x79, 0x2e, 0xca], "vucomisd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x79, 0x2f, 0x0a], "vcomisd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x79, 0x2f, 0xca], "vcomisd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x79, 0x50, 0xca], "vmovmskpd ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x79, 0x51, 0x0a], "vsqrtpd xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x79, 0x5c, 0x0a], "vsubpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x79, 0x6f, 0xca], "vmovdqa xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x79, 0x7e, 0xca], "vmovd edx, xmm1"); test_display(&[0xc4, 0xc1, 0x79, 0x7f, 0xca], "vmovdqa xmm2, xmm1"); test_display(&[0xc4, 0xc1, 0x79, 0xc5, 0xca, 0x77], "vpextrw ecx, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0x79, 0xd7, 0xca], "vpmovmskb ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7a, 0x12, 0x0a], "vmovsldup xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7a, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7a, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0x7a, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7a, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7a, 0x6f, 0xca], "vmovdqu xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x7a, 0x7f, 0xca], "vmovdqu xmm2, xmm1"); test_display(&[0xc4, 0xc1, 0x7b, 0x12, 0x0a], "vmovddup xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7b, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7b, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0x7b, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7b, 0x2d, 0x0a], "vcvtsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7b, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7c, 0x5c, 0x0a], "vsubps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7d, 0x2e, 0x0a], "vucomisd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7d, 0x2e, 0xca], "vucomisd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x7d, 0x2f, 0x0a], "vcomisd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7d, 0x2f, 0xca], "vcomisd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0x7d, 0x50, 0xca], "vmovmskpd ecx, ymm2"); test_display(&[0xc4, 0xc1, 0x7d, 0x51, 0x0a], "vsqrtpd ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7d, 0x5c, 0x0a], "vsubpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7d, 0x6f, 0xca], "vmovdqa ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0x7d, 0x7f, 0xca], "vmovdqa ymm2, ymm1"); test_display(&[0xc4, 0xc1, 0x7d, 0xd7, 0xca], "vpmovmskb ecx, ymm2"); test_display(&[0xc4, 0xc1, 0x7e, 0x12, 0x0a], "vmovsldup ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7e, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7e, 0x2d, 0x0a], "vcvtss2si ecx, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7e, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7e, 0x6f, 0xca], "vmovdqu ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0x7e, 0x7f, 0xca], "vmovdqu ymm2, ymm1"); test_display(&[0xc4, 0xc1, 0x7f, 0x12, 0x0a], "vmovddup ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7f, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0x7f, 0x2c, 0x0a], "vcvttsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7f, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0x7f, 0x2d, 0x0a], "vcvtsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0x7f, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x12, 0x0a], "vmovlps xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x12, 0xca], "vmovhlps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x16, 0x0a], "vmovhps xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x54, 0xca], "vandps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x55, 0xca], "vandnps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x56, 0x0a], "vorps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x57, 0xca], "vxorps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x58, 0xca], "vaddps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb8, 0x59, 0x0a], "vmulps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x5d, 0x0a], "vminps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x5e, 0x0a], "vdivps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0x5f, 0x0a], "vmaxps xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb8, 0xc2, 0xca, 0x77], "vcmpps xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xb9, 0x12, 0x0a], "vmovlpd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x16, 0x0a], "vmovhpd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x54, 0x0a], "vandpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x55, 0x0a], "vandnpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x56, 0x0a], "vorpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x57, 0xca], "vxorpd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0x58, 0x0a], "vaddpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x59, 0x0a], "vmulpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x5d, 0x0a], "vminpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x5e, 0x0a], "vdivpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x5f, 0x0a], "vmaxpd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xb9, 0x71, 0xd2, 0x77], "vpsrlw xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xb9, 0x74, 0xca], "vpcmpeqb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0x75, 0xca], "vpcmpeqw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0x76, 0xca], "vpcmpeqd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0x7c, 0xca], "vhaddpd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0x7d, 0xca], "vhsubpd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xc2, 0xca, 0x77], "vcmppd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xb9, 0xc4, 0xca, 0x77], "vpinsrw xmm1, xmm0, edx, 0x77"); test_display(&[0xc4, 0xc1, 0xb9, 0xd0, 0xca], "vaddsubpd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd1, 0xca], "vpsrlw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd2, 0xca], "vpsrld xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd3, 0xca], "vpsrlq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd4, 0xca], "vpaddq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd8, 0xca], "vpsubusb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xd9, 0xca], "vpsubusw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xdb, 0xca], "vpand xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xdc, 0xca], "vpaddusb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xdd, 0xca], "vpaddusw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xdf, 0xca], "vpandn xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe0, 0xca], "vpavgb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe1, 0xca], "vpsraw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe2, 0xca], "vpsrad xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe3, 0xca], "vpavgw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe4, 0xca], "vpmulhuw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe5, 0xca], "vpmulhw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe8, 0xca], "vpsubsb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xe9, 0xca], "vpsubsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf1, 0xca], "vpsllw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf2, 0xca], "vpslld xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf3, 0xca], "vpsllq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf4, 0xca], "vpmuludq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf8, 0xca], "vpsubb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xf9, 0xca], "vpsubw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xfa, 0xca], "vpsubd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xfb, 0xca], "vpsubq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xfc, 0xca], "vpaddb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xfd, 0xca], "vpaddw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xb9, 0xfe, 0xca], "vpaddd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xba, 0x58, 0x0a], "vaddss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xba, 0x58, 0xca], "vaddss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xba, 0x59, 0x0a], "vmulss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xba, 0x5d, 0x0a], "vminss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xba, 0x5e, 0x0a], "vdivss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xba, 0x5f, 0x0a], "vmaxss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); test_display(&[0xc4, 0xc1, 0xbb, 0x58, 0x0a], "vaddsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x59, 0x0a], "vmulsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x5d, 0x0a], "vminsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x5e, 0x0a], "vdivsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x5f, 0x0a], "vmaxsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbb, 0x7c, 0xca], "vhaddps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbb, 0x7d, 0xca], "vhsubps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbb, 0xc2, 0xca, 0x77], "vcmpsd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xbb, 0xd0, 0xca], "vaddsubps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbc, 0x54, 0xca], "vandps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbc, 0x55, 0xca], "vandnps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbc, 0x56, 0x0a], "vorps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbc, 0x57, 0xca], "vxorps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbc, 0x58, 0xca], "vaddps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbc, 0x59, 0x0a], "vmulps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbc, 0x5d, 0x0a], "vminps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbc, 0x5e, 0x0a], "vdivps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbc, 0x5f, 0x0a], "vmaxps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbc, 0xc2, 0xca, 0x77], "vcmpps ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xbd, 0x54, 0x0a], "vandpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x55, 0x0a], "vandnpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x56, 0x0a], "vorpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x57, 0xca], "vxorpd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0x58, 0x0a], "vaddpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x59, 0x0a], "vmulpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x5d, 0x0a], "vminpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x5e, 0x0a], "vdivpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x5f, 0x0a], "vmaxpd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0x74, 0xca], "vpcmpeqb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0x75, 0xca], "vpcmpeqw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0x76, 0xca], "vpcmpeqd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0x7c, 0xca], "vhaddpd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0x7d, 0xca], "vhsubpd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xc2, 0xca, 0x77], "vcmppd ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xbd, 0xd0, 0xca], "vaddsubpd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd1, 0x0a], "vpsrlw ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0xd1, 0xca], "vpsrlw ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd2, 0x0a], "vpsrld ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0xd2, 0xca], "vpsrld ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd3, 0x0a], "vpsrlq ymm1, ymm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbd, 0xd3, 0xca], "vpsrlq ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd4, 0xca], "vpaddq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd8, 0xca], "vpsubusb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xd9, 0xca], "vpsubusw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xdb, 0xca], "vpand ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xdc, 0xca], "vpaddusb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xdd, 0xca], "vpaddusw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xdf, 0xca], "vpandn ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe0, 0xca], "vpavgb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe1, 0xca], "vpsraw ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe2, 0xca], "vpsrad ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe3, 0xca], "vpavgw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe4, 0xca], "vpmulhuw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe5, 0xca], "vpmulhw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe8, 0xca], "vpsubsb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xe9, 0xca], "vpsubsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf1, 0xca], "vpsllw ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf2, 0xca], "vpslld ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf3, 0xca], "vpsllq ymm1, ymm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf4, 0xca], "vpmuludq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf8, 0xca], "vpsubb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xf9, 0xca], "vpsubw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xfa, 0xca], "vpsubd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xfb, 0xca], "vpsubq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xfc, 0xca], "vpaddb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xfd, 0xca], "vpaddw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbd, 0xfe, 0xca], "vpaddd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbe, 0x58, 0x0a], "vaddss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbe, 0x58, 0xca], "vaddss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xbe, 0x59, 0x0a], "vmulss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbe, 0x5d, 0x0a], "vminss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbe, 0x5e, 0x0a], "vdivss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbe, 0x5f, 0x0a], "vmaxss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x11, 0xca], "vmovsd xmm2, xmm0, xmm1"); test_display(&[0xc4, 0xc1, 0xbf, 0x58, 0x0a], "vaddsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x59, 0x0a], "vmulsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x5d, 0x0a], "vminsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x5e, 0x0a], "vdivsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x5f, 0x0a], "vmaxsd xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xbf, 0x7c, 0xca], "vhaddps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbf, 0x7d, 0xca], "vhsubps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xbf, 0xc2, 0xca, 0x77], "vcmpsd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xbf, 0xd0, 0xca], "vaddsubps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xf8, 0x10, 0x0a], "vmovups xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf8, 0x11, 0x0a], "vmovups xmmword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xf8, 0x17, 0x0a], "vmovhps qword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xf8, 0x50, 0xca], "vmovmskps ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xf8, 0x51, 0x0a], "vsqrtps xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf8, 0x52, 0xca], "vrsqrtps xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf8, 0x53, 0xca], "vrcpps xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf8, 0x5a, 0x0a], "vcvtps2pd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf8, 0x5a, 0xca], "vcvtps2pd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf8, 0x5b, 0x0a], "vcvtdq2ps xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf8, 0x5b, 0xca], "vcvtdq2ps xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x10, 0x0a], "vmovupd xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf9, 0x13, 0x0a], "vmovlpd qword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xf9, 0x17, 0x0a], "vmovhpd qword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xf9, 0x50, 0xca], "vmovmskpd ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x5a, 0xca], "vcvtpd2ps xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x5b, 0xca], "vcvtps2dq xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x6c, 0xca], "vpunpcklqdq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x6d, 0xca], "vpunpckhqdq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0x6e, 0x0a], "vmovd xmm1, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xf9, 0x6e, 0xca], "vmovd xmm1, edx"); test_display(&[0xc4, 0xc1, 0xf9, 0x70, 0xca, 0x77], "vpshufd xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x71, 0xd2, 0x77], "vpsrlw xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x71, 0xe2, 0x77], "vpsraw xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x71, 0xf2, 0x77], "vpsllw xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x72, 0xd2, 0x77], "vpsrld xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x72, 0xe2, 0x77], "vpsrad xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x72, 0xf2, 0x77], "vpslld xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x73, 0xd2, 0x77], "vpsrlq xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x73, 0xda, 0x77], "vpsrldq xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x73, 0xf2, 0x77], "vpsllq xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x73, 0xfa, 0x77], "vpslldq xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xf9, 0x7e, 0xca], "vmovd edx, xmm1"); test_display(&[0xc4, 0xc1, 0xf9, 0xe6, 0xca], "vcvttpd2dq xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0xe7, 0x0a], "vmovntdq xmmword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xf9, 0xf5, 0xca], "vpmaddwd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0xf6, 0xca], "vpsadbw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xf9, 0xf7, 0xca], "vmaskmovdqu xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x10, 0x0a], "vmovss xmm1, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfa, 0x11, 0x0a], "vmovss dword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xfa, 0x12, 0x0a], "vmovsldup xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfa, 0x16, 0xca], "vmovshdup xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x2a, 0x0a], "vcvtsi2ss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfa, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0xfa, 0x51, 0x0a], "vsqrtss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfa, 0x52, 0xca], "vrsqrtss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x53, 0xca], "vrcpss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x5a, 0x0a], "vcvtss2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfa, 0x5a, 0xca], "vcvtss2sd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x5b, 0xca], "vcvttps2dq xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfa, 0x70, 0xca, 0x77], "vpshufhw xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfa, 0xe6, 0xca], "vcvtdq2pd xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfb, 0x10, 0x0a], "vmovsd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfb, 0x11, 0x0a], "vmovsd qword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xfb, 0x2a, 0x0a], "vcvtsi2sd xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfb, 0x2d, 0x0a], "vcvtsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfb, 0x5a, 0x0a], "vcvtsd2ss xmm1, xmm0, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfb, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfb, 0x70, 0xca, 0x77], "vpshuflw xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfb, 0xe6, 0xca], "vcvtpd2dq xmm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfb, 0xf0, 0x0a], "vlddqu xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfc, 0x10, 0x0a], "vmovups ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfc, 0x11, 0x0a], "vmovups ymmword [bp + si * 1], ymm1"); test_display(&[0xc4, 0xc1, 0xfc, 0x28, 0xca], "vmovaps ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfc, 0x29, 0xca], "vmovaps ymm2, ymm1"); test_display(&[0xc4, 0xc1, 0xfc, 0x2b, 0x0a], "vmovntps ymmword [bp + si * 1], ymm1"); test_display(&[0xc4, 0xc1, 0xfc, 0x50, 0xca], "vmovmskps ecx, ymm2"); test_display(&[0xc4, 0xc1, 0xfc, 0x51, 0x0a], "vsqrtps ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfc, 0x52, 0xca], "vrsqrtps ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfc, 0x53, 0xca], "vrcpps ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfc, 0x5a, 0x0a], "vcvtps2pd ymm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfc, 0x5a, 0xca], "vcvtps2pd ymm1, xmm2"); test_display(&[0xc4, 0xc1, 0xfc, 0x5b, 0x0a], "vcvtdq2ps ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfc, 0x5b, 0xca], "vcvtdq2ps ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x10, 0x0a], "vmovupd ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfd, 0x28, 0xca], "vmovapd ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x29, 0xca], "vmovapd ymm2, ymm1"); test_display(&[0xc4, 0xc1, 0xfd, 0x2b, 0x0a], "vmovntpd ymmword [bp + si * 1], ymm1"); test_display(&[0xc4, 0xc1, 0xfd, 0x50, 0xca], "vmovmskpd ecx, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x5a, 0xca], "vcvtpd2ps xmm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x5b, 0xca], "vcvtps2dq ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x6c, 0xca], "vpunpcklqdq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x6d, 0xca], "vpunpckhqdq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0x70, 0xca, 0x77], "vpshufd ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x71, 0xd2, 0x77], "vpsrlw ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x71, 0xe2, 0x77], "vpsraw ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x71, 0xf2, 0x77], "vpsllw ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x72, 0xd2, 0x77], "vpsrld ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x72, 0xe2, 0x77], "vpsrad ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x72, 0xf2, 0x77], "vpslld ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x73, 0xd2, 0x77], "vpsrlq ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x73, 0xda, 0x77], "vpsrldq ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x73, 0xf2, 0x77], "vpsllq ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0x73, 0xfa, 0x77], "vpslldq ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfd, 0xe6, 0xca], "vcvttpd2dq xmm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0xe7, 0x0a], "vmovntdq ymmword [bp + si * 1], ymm1"); test_display(&[0xc4, 0xc1, 0xfd, 0xf5, 0xca], "vpmaddwd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xfd, 0xf6, 0xca], "vpsadbw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x10, 0x0a], "vmovss xmm1, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfe, 0x11, 0x0a], "vmovss dword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xfe, 0x12, 0x0a], "vmovsldup ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfe, 0x16, 0xca], "vmovshdup ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x2a, 0xca], "vcvtsi2ss xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0xfe, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x2d, 0x0a], "vcvtss2si ecx, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfe, 0x51, 0x0a], "vsqrtss xmm1, xmm0, dword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xfe, 0x52, 0xca], "vrsqrtss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x53, 0xca], "vrcpss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x5a, 0xca], "vcvtss2sd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x5b, 0xca], "vcvttps2dq ymm1, ymm2"); test_display(&[0xc4, 0xc1, 0xfe, 0x70, 0xca, 0x77], "vpshufhw ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xfe, 0xe6, 0xca], "vcvtdq2pd ymm1, xmm2"); test_display(&[0xc4, 0xc1, 0xff, 0x10, 0x0a], "vmovsd xmm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xff, 0x11, 0x0a], "vmovsd qword [bp + si * 1], xmm1"); test_display(&[0xc4, 0xc1, 0xff, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0xc4, 0xc1, 0xff, 0x2c, 0x0a], "vcvttsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc4, 0xc1, 0xff, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xff, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0xc4, 0xc1, 0xff, 0x5a, 0xca], "vcvtsd2ss xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc1, 0xff, 0x70, 0xca, 0x77], "vpshuflw ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc1, 0xff, 0xe6, 0xca], "vcvtpd2dq xmm1, ymm2"); test_display(&[0xc4, 0xc1, 0xff, 0xf0, 0x0a], "vlddqu ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x39, 0x0c, 0xca], "vpermilps xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x0d, 0xca], "vpermilpd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x28, 0xca], "vpmuldq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x29, 0xca], "vpcmpeqq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x2b, 0xca], "vpackusdw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x37, 0xca], "vpcmpgtq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x38, 0xca], "vpminsb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x39, 0xca], "vpminsd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3a, 0xca], "vpminuw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3b, 0xca], "vpminud xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3c, 0xca], "vpmaxsb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3d, 0xca], "vpmaxsd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3e, 0xca], "vpmaxuw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x3f, 0xca], "vpmaxud xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x39, 0x40, 0xca], "vpmulld xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x0c, 0xca], "vpermilps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x0d, 0xca], "vpermilpd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x28, 0xca], "vpmuldq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x29, 0xca], "vpcmpeqq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x2b, 0x0a], "vpackusdw ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x3d, 0x2b, 0xca], "vpackusdw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x36, 0xca], "vpermd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x37, 0xca], "vpcmpgtq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x38, 0xca], "vpminsb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x39, 0xca], "vpminsd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3a, 0xca], "vpminuw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3b, 0xca], "vpminud ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3c, 0xca], "vpmaxsb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3d, 0xca], "vpmaxsd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3e, 0xca], "vpmaxuw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x3f, 0xca], "vpmaxud ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x3d, 0x40, 0xca], "vpmulld ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x79, 0x00, 0xca], "vpshufb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x01, 0xca], "vphaddw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x02, 0xca], "vphaddd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x03, 0xca], "vphaddsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x04, 0xca], "vpmaddubsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x05, 0xca], "vphsubw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x06, 0xca], "vphsubd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x07, 0xca], "vphsubsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x08, 0xca], "vpsignb xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x09, 0xca], "vpsignw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x0a, 0xca], "vpsignd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x0b, 0xca], "vpmulhrsw xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x0e, 0xca], "vtestps xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x0f, 0xca], "vtestpd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x17, 0xca], "vptest xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x18, 0x0a], "vbroadcastss xmm1, dword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x18, 0xca], "vbroadcastss xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x1c, 0xca], "vpabsb xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x1d, 0xca], "vpabsw xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x1e, 0xca], "vpabsd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x20, 0xca], "vpmovsxbw xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x21, 0xca], "vpmovsxbd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x22, 0xca], "vpmovsxbq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x23, 0xca], "vpmovsxwd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x24, 0xca], "vpmovsxwq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x25, 0xca], "vpmovsxdq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x2a, 0x0a], "vmovntdqa xmm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x30, 0xca], "vpmovzxbw xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x31, 0xca], "vpmovzxbd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x32, 0xca], "vpmovzxbq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x33, 0xca], "vpmovzxwd xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x34, 0xca], "vpmovzxwq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x35, 0xca], "vpmovzxdq xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x41, 0xca], "vphminposuw xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x45, 0x0a], "vpsrlvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x45, 0xca], "vpsrlvd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x46, 0x0a], "vpsravd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x47, 0x0a], "vpsllvd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x47, 0xca], "vpsllvd xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0x79, 0x8c, 0x0a], "vpmaskmovd xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x79, 0x8e, 0x0a], "vpmaskmovd xmmword [bp + si * 1], xmm0, xmm1"); test_display(&[0xc4, 0xc2, 0x79, 0xdb, 0xca], "vaesimc xmm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x00, 0xca], "vpshufb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x01, 0xca], "vphaddw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x02, 0xca], "vphaddd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x03, 0xca], "vphaddsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x04, 0xca], "vpmaddubsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x05, 0xca], "vphsubw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x06, 0xca], "vphsubd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x07, 0xca], "vphsubsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x08, 0xca], "vpsignb ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x09, 0xca], "vpsignw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x0a, 0xca], "vpsignd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x0b, 0xca], "vpmulhrsw ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x0e, 0xca], "vtestps ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x0f, 0xca], "vtestpd ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x16, 0x0a], "vpermps ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x16, 0xca], "vpermps ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x17, 0xca], "vptest ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x18, 0x0a], "vbroadcastss ymm1, dword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x18, 0xca], "vbroadcastss ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x19, 0x0a], "vbroadcastsd ymm1, qword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x19, 0xca], "vbroadcastsd ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x1a, 0x0a], "vbroadcastf128 ymm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x1c, 0xca], "vpabsb ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x1d, 0xca], "vpabsw ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x1e, 0xca], "vpabsd ymm1, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x20, 0xca], "vpmovsxbw ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x21, 0xca], "vpmovsxbd ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x22, 0xca], "vpmovsxbq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x23, 0xca], "vpmovsxwd ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x24, 0xca], "vpmovsxwq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x25, 0xca], "vpmovsxdq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x2a, 0x0a], "vmovntdqa ymm1, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x30, 0xca], "vpmovzxbw ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x31, 0xca], "vpmovzxbd ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x32, 0xca], "vpmovzxbq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x33, 0xca], "vpmovzxwd ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x34, 0xca], "vpmovzxwq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x35, 0xca], "vpmovzxdq ymm1, xmm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x45, 0x0a], "vpsrlvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x45, 0xca], "vpsrlvd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x46, 0x0a], "vpsravd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x47, 0x0a], "vpsllvd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x47, 0xca], "vpsllvd ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0x7d, 0x5a, 0x0a], "vbroadcasti128 ymm1, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x8c, 0x0a], "vpmaskmovd ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0x7d, 0x8e, 0x0a], "vpmaskmovd ymmword [bp + si * 1], ymm0, ymm1"); test_display(&[0xc4, 0xc2, 0xb9, 0xdc, 0xca], "vaesenc xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xb9, 0xdd, 0xca], "vaesenclast xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xb9, 0xde, 0xca], "vaesdec xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xb9, 0xdf, 0xca], "vaesdeclast xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xbd, 0xdc, 0xca], "vaesenc ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xbd, 0xdd, 0xca], "vaesenclast ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xbd, 0xde, 0xca], "vaesdec ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xbd, 0xdf, 0xca], "vaesdeclast ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xf9, 0x45, 0x0a], "vpsrlvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xf9, 0x45, 0xca], "vpsrlvq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xf9, 0x47, 0x0a], "vpsllvq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xf9, 0x47, 0xca], "vpsllvq xmm1, xmm0, xmm2"); test_display(&[0xc4, 0xc2, 0xf9, 0x8c, 0x0a], "vpmaskmovq xmm1, xmm0, xmmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xf9, 0x8e, 0x0a], "vpmaskmovq xmmword [bp + si * 1], xmm0, xmm1"); test_display(&[0xc4, 0xc2, 0xfd, 0x45, 0x0a], "vpsrlvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xfd, 0x45, 0xca], "vpsrlvq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xfd, 0x47, 0x0a], "vpsllvq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xfd, 0x47, 0xca], "vpsllvq ymm1, ymm0, ymm2"); test_display(&[0xc4, 0xc2, 0xfd, 0x8c, 0x0a], "vpmaskmovq ymm1, ymm0, ymmword [bp + si * 1]"); test_display(&[0xc4, 0xc2, 0xfd, 0x8e, 0x0a], "vpmaskmovq ymmword [bp + si * 1], ymm0, ymm1"); test_display(&[0xc4, 0xc3, 0x39, 0x0a, 0xca, 0x77], "vroundss xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x0b, 0xca, 0x77], "vroundsd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x0c, 0xca, 0x77], "vblendps xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x0d, 0xca, 0x77], "vblendpd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x0e, 0xca, 0x77], "vpblendw xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x20, 0x0a, 0x77], "vpinsrb xmm1, xmm0, byte [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x20, 0xca, 0x77], "vpinsrb xmm1, xmm0, edx, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x21, 0xca, 0x77], "vinsertps xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x22, 0x0a, 0x77], "vpinsrd xmm1, xmm0, dword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x22, 0xca, 0x77], "vpinsrd xmm1, xmm0, edx, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x40, 0xca, 0x77], "vdpps xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x41, 0xca, 0x77], "vdppd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x42, 0xca, 0x77], "vmpsadbw xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x39, 0x4c, 0xca, 0x77], "vpblendvb xmm1, xmm0, xmm2, xmm7"); test_display(&[0xc4, 0xc3, 0x3d, 0x0a, 0xca, 0x77], "vroundss xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x0b, 0xca, 0x77], "vroundsd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x0c, 0xca, 0x77], "vblendps ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x0d, 0xca, 0x77], "vblendpd ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x0e, 0xca, 0x77], "vpblendw ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x18, 0xca, 0x77], "vinsertf128 ymm1, ymm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x38, 0xca, 0x77], "vinserti128 ymm1, ymm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x40, 0xca, 0x77], "vdpps ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x42, 0xca, 0x77], "vmpsadbw ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x3d, 0x4c, 0xca, 0x77], "vpblendvb ymm1, ymm0, ymm2, ymm7"); test_display(&[0xc4, 0xc3, 0x79, 0x02, 0x0a, 0x77], "vpblendd xmm1, xmm0, xmmword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x02, 0xca, 0x77], "vpblendd xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x04, 0xca, 0x77], "vpermilps xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x05, 0xca, 0x77], "vpermilpd xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x08, 0xca, 0x77], "vroundps xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x09, 0xca, 0x77], "vroundpd xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x14, 0x0a, 0x77], "vpextrb byte [bp + si * 1], xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x14, 0xca, 0x77], "vpextrb edx, xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x15, 0x0a, 0x77], "vpextrw word [bp + si * 1], xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x15, 0xca, 0x77], "vpextrw edx, xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x16, 0x0a, 0x77], "vpextrd dword [bp + si * 1], xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x16, 0xca, 0x77], "vpextrd edx, xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x17, 0x0a, 0x77], "vextractps dword [bp + si * 1], xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x17, 0xca, 0x77], "vextractps edx, xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x60, 0xca, 0x77], "vpcmpestrm xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x61, 0xca, 0x77], "vpcmpestri xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x62, 0xca, 0x77], "vpcmpistrm xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x79, 0x63, 0xca, 0x77], "vpcmpistri xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x02, 0x0a, 0x77], "vpblendd ymm1, ymm0, ymmword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x02, 0xca, 0x77], "vpblendd ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x04, 0xca, 0x77], "vpermilps ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x05, 0xca, 0x77], "vpermilpd ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x06, 0x0a, 0x77], "vperm2f128 ymm1, ymm0, ymmword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x06, 0xca, 0x77], "vperm2f128 ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x08, 0xca, 0x77], "vroundps ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x09, 0xca, 0x77], "vroundpd ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x19, 0xca, 0x77], "vextractf128 xmm2, ymm1, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x39, 0xca, 0x77], "vextracti128 xmm2, ymm1, 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x46, 0x0a, 0x77], "vperm2i128 ymm1, ymm0, ymmword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0x7d, 0x46, 0xca, 0x77], "vperm2i128 ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0xb9, 0x0f, 0xca, 0x77], "vpalignr xmm1, xmm0, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0xb9, 0x22, 0x0a, 0x77], "vpinsrd xmm1, xmm0, dword [bp + si * 1], 0x77"); test_display(&[0xc4, 0xc3, 0xb9, 0x22, 0xca, 0x77], "vpinsrd xmm1, xmm0, edx, 0x77"); test_display(&[0xc4, 0xc3, 0xbd, 0x0f, 0xca, 0x77], "vpalignr ymm1, ymm0, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0xf9, 0x16, 0x0a, 0x77], "vpextrd dword [bp + si * 1], xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0xf9, 0x16, 0xca, 0x77], "vpextrd edx, xmm1, 0x77"); test_display(&[0xc4, 0xc3, 0xf9, 0xdf, 0xca, 0x77], "vaeskeygenassist xmm1, xmm2, 0x77"); test_display(&[0xc4, 0xc3, 0xfd, 0x00, 0xca, 0x77], "vpermq ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xc3, 0xfd, 0x01, 0xca, 0x77], "vpermpd ymm1, ymm2, 0x77"); test_display(&[0xc4, 0xe2, 0x60, 0xf2, 0x01], "andn eax, ebx, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0x60, 0xf5, 0x07], "bzhi eax, dword [bx], ebx"); test_display(&[0xc4, 0xe2, 0x60, 0xf7, 0x01], "bextr eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0x61, 0xf7, 0x01], "shlx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0x62, 0xf5, 0x07], "pext eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0x62, 0xf7, 0x01], "sarx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0x63, 0xf5, 0x07], "pdep eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0x63, 0xf6, 0x07], "mulx eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0x63, 0xf7, 0x01], "shrx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0x78, 0xf3, 0x09], "blsr eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0x78, 0xf3, 0x11], "blsmsk eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0x78, 0xf3, 0x19], "blsi eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0xe0, 0xf2, 0x01], "andn eax, ebx, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0xe0, 0xf5, 0x07], "bzhi eax, dword [bx], ebx"); test_display(&[0xc4, 0xe2, 0xe0, 0xf7, 0x01], "bextr eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0xe1, 0xf7, 0x01], "shlx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0xe2, 0xf5, 0x07], "pext eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0xe2, 0xf7, 0x01], "sarx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0xe3, 0xf5, 0x07], "pdep eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0xe3, 0xf6, 0x07], "mulx eax, ebx, dword [bx]"); test_display(&[0xc4, 0xe2, 0xe3, 0xf7, 0x01], "shrx eax, dword [bx + di * 1], ebx"); test_display(&[0xc4, 0xe2, 0xf8, 0xf3, 0x09], "blsr eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0xf8, 0xf3, 0x11], "blsmsk eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe2, 0xf8, 0xf3, 0x19], "blsi eax, dword [bx + di * 1]"); test_display(&[0xc4, 0xe3, 0x7b, 0xf0, 0x01, 0x05], "rorx eax, dword [bx + di * 1], 0x5"); test_display(&[0xc4, 0xe3, 0xfb, 0xf0, 0x01, 0x05], "rorx eax, dword [bx + di * 1], 0x5"); test_display(&[0xc5, 0x78, 0x10], "lds di, dword [bx + si * 1 + 0x10]"); test_display(&[0xc5, 0xf8, 0x10, 0x00], "vmovups xmm0, xmmword [bx + si * 1]"); test_display(&[0xc5, 0xf8, 0x10, 0x01], "vmovups xmm0, xmmword [bx + di * 1]"); test_display(&[0xc5, 0xf8, 0x2e, 0xca], "vucomiss xmm1, xmm2"); test_display(&[0xc5, 0xf8, 0x2f, 0xca], "vcomiss xmm1, xmm2"); test_display(&[0xc5, 0xfa, 0x2c, 0x0a], "vcvttss2si ecx, dword [bp + si * 1]"); test_display(&[0xc5, 0xfa, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0xc5, 0xfa, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_display(&[0xc5, 0xfb, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0xc5, 0xfb, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0xc5, 0xfb, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0xc5, 0xfc, 0x2e, 0x0a], "vucomiss xmm1, dword [bp + si * 1]"); test_display(&[0xc5, 0xfc, 0x2f, 0x0a], "vcomiss xmm1, dword [bp + si * 1]"); test_display(&[0xc5, 0xfe, 0x2c, 0xca], "vcvttss2si ecx, xmm2"); test_display(&[0xc5, 0xfe, 0x2d, 0xca], "vcvtss2si ecx, xmm2"); test_display(&[0xc5, 0xff, 0x2a, 0xca], "vcvtsi2sd xmm1, xmm0, edx"); test_display(&[0xc5, 0xff, 0x2c, 0x0a], "vcvttsd2si ecx, qword [bp + si * 1]"); test_display(&[0xc5, 0xff, 0x2c, 0xca], "vcvttsd2si ecx, xmm2"); test_display(&[0xc5, 0xff, 0x2d, 0xca], "vcvtsd2si ecx, xmm2"); test_display(&[0xc6, 0xf8, 0x10], "xabort 0x10"); test_display(&[0xc7, 0x43, 0x10, 0x00, 0x00], "mov word [bp + di * 1 + 0x10], 0x0"); test_display(&[0xc7, 0xf8, 0x10, 0x12], "xbegin $+0x1210"); test_display(&[0xc8, 0x01, 0x02, 0x03], "enter 0x201, 0x3"); test_display(&[0xc9], "leave"); test_display(&[0xca, 0x12, 0x34], "retf 0x3412"); test_display(&[0xcb], "retf"); test_display(&[0xcd, 0x00], "int 0x0"); test_display(&[0xcd, 0xff], "int 0xff"); test_display(&[0xce], "into"); test_display(&[0xcf], "iret"); test_display(&[0xd2, 0xe0], "shl al, cl"); test_display(&[0xd4, 0x01], "aam 0x1"); test_display(&[0xd4, 0x0a], "aam 0xa"); test_display(&[0xd5, 0x01], "aad 0x1"); test_display(&[0xd5, 0x0a], "aad 0xa"); test_display(&[0xd8, 0x03], "fadd st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x0b], "fmul st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x13], "fcom st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x1b], "fcomp st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x23], "fsub st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x2b], "fsubr st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x33], "fdiv st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0x3b], "fdivr st(0), dword [bp + di * 1]"); test_display(&[0xd8, 0xc3], "fadd st(0), st(3)"); test_display(&[0xd8, 0xcb], "fmul st(0), st(3)"); test_display(&[0xd8, 0xd3], "fcom st(0), st(3)"); test_display(&[0xd8, 0xdb], "fcomp st(0), st(3)"); test_display(&[0xd8, 0xe3], "fsub st(0), st(3)"); test_display(&[0xd8, 0xeb], "fsubr st(0), st(3)"); test_display(&[0xd8, 0xf3], "fdiv st(0), st(3)"); test_display(&[0xd8, 0xfb], "fdivr st(0), st(3)"); test_display(&[0xd9, 0x03], "fld st(0), dword [bp + di * 1]"); test_display(&[0xd9, 0x13], "fst dword [bp + di * 1], st(0)"); test_display(&[0xd9, 0x1b], "fstp dword [bp + di * 1], st(0)"); test_display(&[0xd9, 0x23], "fldenv ptr [bp + di * 1]"); test_display(&[0xd9, 0x2b], "fldcw word [bp + di * 1]"); test_display(&[0xd9, 0x33], "fnstenv ptr [bp + di * 1]"); test_display(&[0xd9, 0x3b], "fnstcw word [bp + di * 1]"); test_display(&[0xd9, 0xc3], "fld st(0), st(3)"); test_display(&[0xd9, 0xcb], "fxch st(0), st(3)"); test_display(&[0xd9, 0xd0], "fnop"); test_display(&[0xd9, 0xdb], "fstpnce st(3), st(0)"); test_display(&[0xd9, 0xe0], "fchs"); test_display(&[0xd9, 0xe1], "fabs"); test_display(&[0xd9, 0xe4], "ftst"); test_display(&[0xd9, 0xe5], "fxam"); test_display(&[0xd9, 0xe8], "fld1"); test_display(&[0xd9, 0xe9], "fldl2t"); test_display(&[0xd9, 0xea], "fldl2e"); test_display(&[0xd9, 0xeb], "fldpi"); test_display(&[0xd9, 0xec], "fldlg2"); test_display(&[0xd9, 0xed], "fldln2"); test_display(&[0xd9, 0xee], "fldz"); test_display(&[0xd9, 0xf0], "f2xm1"); test_display(&[0xd9, 0xf1], "fyl2x"); test_display(&[0xd9, 0xf2], "fptan"); test_display(&[0xd9, 0xf3], "fpatan"); test_display(&[0xd9, 0xf4], "fxtract"); test_display(&[0xd9, 0xf5], "fprem1"); test_display(&[0xd9, 0xf6], "fdecstp"); test_display(&[0xd9, 0xf7], "fincstp"); test_display(&[0xd9, 0xf8], "fprem"); test_display(&[0xd9, 0xf9], "fyl2xp1"); test_display(&[0xd9, 0xfa], "fsqrt"); test_display(&[0xd9, 0xfb], "fsincos"); test_display(&[0xd9, 0xfc], "frndint"); test_display(&[0xd9, 0xfd], "fscale"); test_display(&[0xd9, 0xfe], "fsin"); test_display(&[0xd9, 0xff], "fcos"); test_display(&[0xda, 0x03], "fiadd st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x0b], "fimul st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x13], "ficom st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x1b], "ficomp st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x23], "fisub st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x2b], "fisubr st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x33], "fidiv st(0), dword [bp + di * 1]"); test_display(&[0xda, 0x3b], "fidivr st(0), dword [bp + di * 1]"); test_display(&[0xda, 0xc3], "fcmovb st(0), st(3)"); test_display(&[0xda, 0xcb], "fcmove st(0), st(3)"); test_display(&[0xda, 0xd3], "fcmovbe st(0), st(3)"); test_display(&[0xda, 0xdb], "fcmovu st(0), st(3)"); test_display(&[0xda, 0xe9], "fucompp"); test_display(&[0xdb, 0x03], "fild st(0), dword [bp + di * 1]"); test_display(&[0xdb, 0x0b], "fisttp dword [bp + di * 1], st(0)"); test_display(&[0xdb, 0x13], "fist dword [bp + di * 1], st(0)"); test_display(&[0xdb, 0x1b], "fistp dword [bp + di * 1], st(0)"); test_display(&[0xdb, 0x2b], "fld st(0), mword [bp + di * 1]"); test_display(&[0xdb, 0x3b], "fstp mword [bp + di * 1], st(0)"); test_display(&[0xdb, 0xc3], "fcmovnb st(0), st(3)"); test_display(&[0xdb, 0xcb], "fcmovne st(0), st(3)"); test_display(&[0xdb, 0xd3], "fcmovnbe st(0), st(3)"); test_display(&[0xdb, 0xdb], "fcmovnu st(0), st(3)"); test_display(&[0xdb, 0xe0], "feni8087_nop"); test_display(&[0xdb, 0xe1], "fdisi8087_nop"); test_display(&[0xdb, 0xe2], "fnclex"); test_display(&[0xdb, 0xe3], "fninit"); test_display(&[0xdb, 0xe4], "fsetpm287_nop"); test_display(&[0xdb, 0xeb], "fucomi st(0), st(3)"); test_display(&[0xdb, 0xf3], "fcomi st(0), st(3)"); test_display(&[0xdc, 0x03], "fadd st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x0b], "fmul st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x13], "fcom st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x1b], "fcomp st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x23], "fsub st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x2b], "fsubr st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x33], "fdiv st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0x3b], "fdivr st(0), qword [bp + di * 1]"); test_display(&[0xdc, 0xc3], "fadd st(3), st(0)"); test_display(&[0xdc, 0xcb], "fmul st(3), st(0)"); test_display(&[0xdc, 0xd3], "fcom st(0), st(3)"); test_display(&[0xdc, 0xdb], "fcomp st(0), st(3)"); test_display(&[0xdc, 0xe3], "fsubr st(3), st(0)"); test_display(&[0xdc, 0xeb], "fsub st(3), st(0)"); test_display(&[0xdc, 0xf3], "fdivr st(3), st(0)"); test_display(&[0xdc, 0xfb], "fdiv st(3), st(0)"); test_display(&[0xdd, 0x03], "fld st(0), qword [bp + di * 1]"); test_display(&[0xdd, 0x0b], "fisttp qword [bp + di * 1], st(0)"); test_display(&[0xdd, 0x13], "fst qword [bp + di * 1], st(0)"); test_display(&[0xdd, 0x1b], "fstp qword [bp + di * 1], st(0)"); test_display(&[0xdd, 0x23], "frstor ptr [bp + di * 1]"); test_display(&[0xdd, 0x33], "fnsave ptr [bp + di * 1]"); test_display(&[0xdd, 0x3b], "fnstsw word [bp + di * 1]"); test_display(&[0xdd, 0xc3], "ffree st(3)"); test_display(&[0xdd, 0xcb], "fxch st(0), st(3)"); test_display(&[0xdd, 0xd3], "fst st(3), st(0)"); test_display(&[0xdd, 0xdb], "fstp st(3), st(0)"); test_display(&[0xdd, 0xe3], "fucom st(0), st(3)"); test_display(&[0xdd, 0xeb], "fucomp st(0), st(3)"); test_display(&[0xde, 0x03], "fiadd st(0), word [bp + di * 1]"); test_display(&[0xde, 0x0b], "fimul st(0), word [bp + di * 1]"); test_display(&[0xde, 0x13], "ficom st(0), word [bp + di * 1]"); test_display(&[0xde, 0x1b], "ficomp st(0), word [bp + di * 1]"); test_display(&[0xde, 0x23], "fisub st(0), word [bp + di * 1]"); test_display(&[0xde, 0x2b], "fisubr st(0), word [bp + di * 1]"); test_display(&[0xde, 0x33], "fidiv st(0), word [bp + di * 1]"); test_display(&[0xde, 0x3b], "fidivr st(0), word [bp + di * 1]"); test_display(&[0xde, 0xc3], "faddp st(3), st(0)"); test_display(&[0xde, 0xcb], "fmulp st(3), st(0)"); test_display(&[0xde, 0xd3], "fcomp st(0), st(3)"); test_display(&[0xde, 0xd9], "fcompp"); test_display(&[0xde, 0xe3], "fsubrp st(3), st(0)"); test_display(&[0xde, 0xeb], "fsubp st(3), st(0)"); test_display(&[0xde, 0xf3], "fdivrp st(3), st(0)"); test_display(&[0xde, 0xfb], "fdivp st(3), st(0)"); test_display(&[0xdf, 0x03], "fild st(0), word [bp + di * 1]"); test_display(&[0xdf, 0x0b], "fisttp word [bp + di * 1], st(0)"); test_display(&[0xdf, 0x13], "fist word [bp + di * 1], st(0)"); test_display(&[0xdf, 0x1b], "fistp word [bp + di * 1], st(0)"); test_display(&[0xdf, 0x23], "fbld st(0), mword [bp + di * 1]"); test_display(&[0xdf, 0x2b], "fild st(0), qword [bp + di * 1]"); test_display(&[0xdf, 0x33], "fbstp mword [bp + di * 1], st(0)"); test_display(&[0xdf, 0x3b], "fistp qword [bp + di * 1], st(0)"); test_display(&[0xdf, 0xc3], "ffreep st(3)"); test_display(&[0xdf, 0xcb], "fxch st(0), st(3)"); test_display(&[0xdf, 0xd3], "fstp st(3), st(0)"); test_display(&[0xdf, 0xdb], "fstp st(3), st(0)"); test_display(&[0xdf, 0xe0], "fnstsw ax"); test_display(&[0xdf, 0xeb], "fucomip st(0), st(3)"); test_display(&[0xdf, 0xf3], "fcomip st(0), st(3)"); test_display(&[0xe0, 0x12], "loopnz $+0x12"); test_display(&[0xe1, 0x12], "loopz $+0x12"); test_display(&[0xe2, 0x12], "loop $+0x12"); test_display(&[0xe3, 0x12], "jcxz $+0x12"); test_display(&[0xe3, 0xf0], "jcxz $-0x10"); test_display(&[0xe4, 0x99], "in al, 0x99"); test_display(&[0xe5, 0x99], "in ax, 0x99"); test_display(&[0xe6, 0x99], "out 0x99, al"); test_display(&[0xe7, 0x99], "out 0x99, ax"); test_display(&[0xec], "in al, dx"); test_display(&[0xed], "in ax, dx"); test_display(&[0xee], "out dx, al"); test_display(&[0xef], "out dx, ax"); test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc word [bx], dx"); test_display(&[0xf0, 0x0f, 0xbb, 0x17], "lock btc word [bx], dx"); test_display(&[0xf0, 0x31, 0x00], "lock xor word [bx + si * 1], ax"); test_display(&[0xf0, 0x80, 0x30, 0x00], "lock xor byte [bx + si * 1], 0x0"); test_display(&[0xf1], "int 0x1"); test_display(&[0xf2, 0x0f, 0x06], "clts"); test_display(&[0xf2, 0x0f, 0x07], "sysret"); test_display(&[0xf2, 0x0f, 0x12, 0x0f], "movddup xmm1, qword [bx]"); test_display(&[0xf2, 0x0f, 0x12, 0xcf], "movddup xmm1, xmm7"); test_display(&[0xf2, 0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0xf2, 0x0f, 0x2a, 0x00], "cvtsi2sd xmm0, dword [bx + si * 1]"); test_display(&[0xf2, 0x0f, 0x2a, 0x0f], "cvtsi2sd xmm1, dword [bx]"); test_display(&[0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_display(&[0xf2, 0x0f, 0x2a, 0xcf], "cvtsi2sd xmm1, edi"); test_display(&[0xf2, 0x0f, 0x2c, 0x0f], "cvttsd2si ecx, qword [bx]"); test_display(&[0xf2, 0x0f, 0x2c, 0xcf], "cvttsd2si ecx, xmm7"); test_display(&[0xf2, 0x0f, 0x2d, 0x0f], "cvtsd2si ecx, qword [bx]"); test_display(&[0xf2, 0x0f, 0x2d, 0xcf], "cvtsd2si ecx, xmm7"); test_display(&[0xf2, 0x0f, 0x38, 0xf0, 0xc1], "crc32 eax, cl"); test_display(&[0xf2, 0x0f, 0x38, 0xf0, 0xc6], "crc32 eax, dh"); test_display(&[0xf2, 0x0f, 0x38, 0xf1, 0xc1], "crc32 eax, cx"); test_display(&[0xf2, 0x0f, 0x38, 0xf1, 0xc6], "crc32 eax, si"); test_display(&[0xf2, 0x0f, 0x51, 0x01], "sqrtsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x58, 0x01], "addsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x59, 0x01], "mulsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x59, 0xc8], "mulsd xmm1, xmm0"); test_display(&[0xf2, 0x0f, 0x5a, 0x01], "cvtsd2ss xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x5c, 0x01], "subsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x5d, 0x01], "minsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x5e, 0x01], "divsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x5f, 0x01], "maxsd xmm0, qword [bx + di * 1]"); test_display(&[0xf2, 0x0f, 0x70, 0xc0, 0x4e], "pshuflw xmm0, xmm0, 0x4e"); test_display(&[0xf2, 0x0f, 0x78, 0xf1, 0x4e, 0x76], "insertq xmm6, xmm1, 0x4e, 0x76"); test_display(&[0xf2, 0x0f, 0x79, 0xcf], "insertq xmm1, xmm7"); test_display(&[0xf2, 0x0f, 0x7c, 0x0f], "haddps xmm1, xmmword [bx]"); test_display(&[0xf2, 0x0f, 0x7c, 0xcf], "haddps xmm1, xmm7"); test_display(&[0xf2, 0x0f, 0x7d, 0x0f], "hsubps xmm1, xmmword [bx]"); test_display(&[0xf2, 0x0f, 0x7d, 0xcf], "hsubps xmm1, xmm7"); test_display(&[0xf2, 0x0f, 0xae, 0xf1], "umwait ecx"); test_display(&[0xf2, 0x0f, 0xbc, 0xd3], "bsf dx, bx"); test_display(&[0xf2, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf2, 0x0f, 0xc1, 0xcc], "xadd sp, cx"); test_display(&[0xf2, 0x0f, 0xc2, 0x03, 0x08], "cmpsd xmm0, qword [bp + di * 1], 0x8"); test_display(&[0xf2, 0x0f, 0xc2, 0xc3, 0x08], "cmpsd xmm0, xmm3, 0x8"); test_display(&[0xf2, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [bx]"); test_display(&[0xf2, 0x0f, 0xd0, 0x0f], "addsubps xmm1, xmmword [bx]"); test_display(&[0xf2, 0x0f, 0xd0, 0xcf], "addsubps xmm1, xmm7"); test_display(&[0xf2, 0x0f, 0xd6, 0xc3], "movdq2q mm0, xmm3"); test_display(&[0xf2, 0x0f, 0xf0, 0x0f], "lddqu xmm1, xmmword [bx]"); test_display(&[0xf2, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_display(&[0xf2, 0x66, 0x66, 0x0f, 0x10, 0xc0], "movsd xmm0, xmm0"); test_display(&[0xf2, 0xf2, 0x2e, 0x36, 0x0f, 0x38, 0xf8, 0x83, 0x09, 0x1c], "enqcmd ax, zmmword ss:[bp + di * 1 + 0x1c09]"); test_display(&[0xf3, 0x0f, 0x01, 0x29], "rstorssp qword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0x0f, 0x12, 0x0f], "movsldup xmm1, xmmword [bx]"); test_display(&[0xf3, 0x0f, 0x12, 0xcf], "movsldup xmm1, xmm7"); test_display(&[0xf3, 0x0f, 0x16, 0x0f], "movshdup xmm1, xmmword [bx]"); test_display(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_display(&[0xf3, 0x0f, 0x16, 0xcf], "movshdup xmm1, xmm7"); test_display(&[0xf3, 0x0f, 0x1e, 0xfa], "endbr64"); test_display(&[0xf3, 0x0f, 0x1e, 0xfb], "endbr32"); test_display(&[0xf3, 0x0f, 0x1e, 0xfc], "nop sp, di"); test_display(&[0xf3, 0x0f, 0x21, 0xc8], "mov eax, dr1"); test_display(&[0xf3, 0x0f, 0x2a, 0x00], "cvtsi2ss xmm0, dword [bx + si * 1]"); test_display(&[0xf3, 0x0f, 0x2a, 0x01], "cvtsi2ss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x2a, 0xc1], "cvtsi2ss xmm0, ecx"); test_display(&[0xf3, 0x0f, 0x2a, 0xcf], "cvtsi2ss xmm1, edi"); test_display(&[0xf3, 0x0f, 0x2c, 0x01], "cvttss2si eax, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x2c, 0xc1], "cvttss2si eax, xmm1"); test_display(&[0xf3, 0x0f, 0x2d, 0x01], "cvtss2si eax, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x2d, 0xc1], "cvtss2si eax, xmm1"); test_display(&[0xf3, 0x0f, 0x38, 0xdd, 0x03], "aesdec128kl xmm0, m384b [bp + di * 1]"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0x01], "adox eax, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x38, 0xf6, 0xc1], "adox eax, ecx"); test_display(&[0xf3, 0x0f, 0x51, 0x01], "sqrtss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x52, 0x01], "rsqrtss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x53, 0x01], "rcpss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x53, 0xc1], "rcpss xmm0, xmm1"); test_display(&[0xf3, 0x0f, 0x58, 0x01], "addss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x59, 0x01], "mulss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x59, 0xc8], "mulss xmm1, xmm0"); test_display(&[0xf3, 0x0f, 0x5a, 0x01], "cvtss2sd xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x5b, 0x01], "cvttps2dq xmm0, xmmword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x5c, 0x01], "subss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x5d, 0x01], "minss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x5e, 0x01], "divss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x5f, 0x01], "maxss xmm0, dword [bx + di * 1]"); test_display(&[0xf3, 0x0f, 0x6f, 0x07], "movdqu xmm0, xmmword [bx]"); test_display(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_display(&[0xf3, 0x0f, 0x70, 0xc0, 0x4e], "pshufhw xmm0, xmm0, 0x4e"); test_display(&[0xf3, 0x0f, 0x7e, 0xc1], "movq xmm0, xmm1"); test_display(&[0xf3, 0x0f, 0x7f, 0x45, 0x00], "movdqu xmmword [di], xmm0"); test_display(&[0xf3, 0x0f, 0xae, 0x30], "clrssbsy qword [bx + si * 1]"); test_display(&[0xf3, 0x0f, 0xae, 0xe6], "ptwrite esi"); test_display(&[0xf3, 0x0f, 0xae, 0xe9], "incssp ecx"); test_display(&[0xf3, 0x0f, 0xae, 0xf1], "umonitor cx"); test_display(&[0x67, 0xf3, 0x0f, 0xae, 0xf1], "umonitor ecx"); test_display(&[0xf3, 0x0f, 0xb8, 0xc1], "popcnt ax, cx"); test_display(&[0xf3, 0x0f, 0xb8, 0xc1], "popcnt ax, cx"); test_display(&[0xf3, 0x0f, 0xbc, 0xd3], "tzcnt dx, bx"); test_display(&[0xf3, 0x0f, 0xbc, 0xd3], "tzcnt dx, bx"); test_display(&[0xf3, 0x0f, 0xbc, 0xd7], "tzcnt dx, di"); test_display(&[0xf3, 0x0f, 0xbd, 0xc1], "lzcnt ax, cx"); test_display(&[0xf3, 0x0f, 0xc0, 0xcc], "xadd ah, cl"); test_display(&[0xf3, 0x0f, 0xc1, 0xcc], "xadd sp, cx"); test_display(&[0xf3, 0x0f, 0xc2, 0x03, 0x08], "cmpss xmm0, dword [bp + di * 1], 0x8"); test_display(&[0xf3, 0x0f, 0xc2, 0xc3, 0x08], "cmpss xmm0, xmm3, 0x8"); test_display(&[0xf3, 0x0f, 0xc7, 0x0f], "cmpxchg8b qword [bx]"); test_display(&[0xf3, 0x0f, 0xc7, 0x33], "vmxon qword [bp + di * 1]"); test_display(&[0xf3, 0x0f, 0xc7, 0x37], "vmxon qword [bx]"); test_display(&[0xf3, 0x0f, 0xc7, 0xfd], "rdpid ebp"); test_display(&[0xf3, 0x0f, 0xd6, 0xc3], "movq2dq xmm0, mm3"); test_display(&[0xf3, 0x0f, 0xff, 0xc1], "ud0 eax, ecx"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0x29], "rstorssp qword [bx + di * 1]"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xe8], "setssbsy"); test_display(&[0xf3, 0x66, 0x0f, 0x01, 0xea], "saveprevssp"); test_display(&[0xf3, 0xa5], "rep movs word es:[di], word ds:[si]"); test_display(&[0x67, 0xf3, 0xa5], "rep movs word es:[edi], word ds:[esi]"); test_display(&[0x66, 0x67, 0xf3, 0xa5], "rep movs dword es:[edi], dword ds:[esi]"); test_display(&[0xf3, 0xab], "rep stos word es:[di], ax"); test_display(&[0xf5], "cmc"); test_display(&[0xf6, 0x28], "imul byte [bx + si * 1]"); test_display(&[0xf6, 0xc2, 0x18], "test dl, 0x18"); test_display(&[0xf6, 0xe8], "imul al"); test_display(&[0xfe, 0x00], "inc byte [bx + si * 1]"); test_display(&[0xfe, 0x08], "dec byte [bx + si * 1]"); test_display(&[0xff, 0x00], "inc word [bx + si * 1]"); test_display(&[0xff, 0x08], "dec word [bx + si * 1]"); test_display(&[0xff, 0x15], "call word [di]"); test_display(&[0x67, 0xff, 0x15, 0x12, 0x12, 0x12, 0x12], "call word [0x12121212]"); // note that this call only writes two bytes, and only moves sp by two. test_display(&[0x66, 0xff, 0x15], "call dword [di]"); test_display(&[0xff, 0x18], "callf dword [bx + si * 1]"); test_display(&[0xff, 0x24], "jmp word [si]"); test_display(&[0xff, 0x75, 0x08], "push word [di + 0x8]"); test_display(&[0xff, 0x75, 0xb8], "push word [di - 0x48]"); test_display(&[0xff, 0xe0], "jmp ax"); } #[test] fn test_invalid_sequences() { test_invalid(&[0x0f, 0x01, 0x69, 0xff]); test_invalid(&[0x0f, 0x01, 0xc6]); test_invalid(&[0x0f, 0x01, 0xc7]); test_invalid(&[0x0f, 0x01, 0xcc]); test_invalid(&[0x0f, 0x01, 0xcd]); test_invalid(&[0x0f, 0x01, 0xce]); test_invalid(&[0x0f, 0x01, 0xd2]); test_invalid(&[0x0f, 0x01, 0xd3]); test_invalid(&[0x0f, 0x01, 0xe8]); test_invalid(&[0x0f, 0x01, 0xe9]); test_invalid(&[0x0f, 0x01, 0xea]); test_invalid(&[0x0f, 0x01, 0xeb]); test_invalid(&[0x0f, 0x01, 0xf8]); test_invalid(&[0x0f, 0x13, 0xc0]); test_invalid(&[0x0f, 0x17, 0xc0]); test_invalid(&[0x0f, 0x20, 0xc8]); test_invalid(&[0x0f, 0x22, 0xc8]); test_invalid(&[0x0f, 0x36]); test_invalid(&[0x0f, 0x38, 0x10, 0x06]); test_invalid(&[0x0f, 0x38, 0x14, 0x06]); test_invalid(&[0x0f, 0x38, 0x15, 0x06]); test_invalid(&[0x0f, 0x38, 0x17, 0x06]); test_invalid(&[0x0f, 0x38, 0x20, 0x06]); test_invalid(&[0x0f, 0x38, 0x21, 0x06]); test_invalid(&[0x0f, 0x38, 0x22, 0x06]); test_invalid(&[0x0f, 0x38, 0x23, 0x06]); test_invalid(&[0x0f, 0x38, 0x24, 0x06]); test_invalid(&[0x0f, 0x38, 0x25, 0x06]); test_invalid(&[0x0f, 0x38, 0x28, 0x06]); test_invalid(&[0x0f, 0x38, 0x29, 0x06]); test_invalid(&[0x0f, 0x38, 0x2a, 0x06]); test_invalid(&[0x0f, 0x38, 0x2b, 0x06]); test_invalid(&[0x0f, 0x38, 0x30, 0x06]); test_invalid(&[0x0f, 0x38, 0x31, 0x06]); test_invalid(&[0x0f, 0x38, 0x32, 0x06]); test_invalid(&[0x0f, 0x38, 0x33, 0x06]); test_invalid(&[0x0f, 0x38, 0x34, 0x06]); test_invalid(&[0x0f, 0x38, 0x35, 0x06]); test_invalid(&[0x0f, 0x38, 0x38, 0x06]); test_invalid(&[0x0f, 0x38, 0x39, 0x06]); test_invalid(&[0x0f, 0x38, 0x3a, 0x06]); test_invalid(&[0x0f, 0x38, 0x3b, 0x06]); test_invalid(&[0x0f, 0x38, 0x3c, 0x06]); test_invalid(&[0x0f, 0x38, 0x3d, 0x06]); test_invalid(&[0x0f, 0x38, 0x3e, 0x06]); test_invalid(&[0x0f, 0x38, 0x3f, 0x06]); test_invalid(&[0x0f, 0x38, 0x40, 0x06]); test_invalid(&[0x0f, 0x38, 0x41, 0x06]); test_invalid(&[0x0f, 0x38, 0x80, 0x2f]); test_invalid(&[0x0f, 0x38, 0x81, 0x2f]); test_invalid(&[0x0f, 0x38, 0x82, 0x2f]); test_invalid(&[0x0f, 0x38, 0xf0, 0xc6]); test_invalid(&[0x0f, 0x38, 0xf5, 0x47, 0xe9]); test_invalid(&[0x0f, 0x3a, 0x08, 0x06]); test_invalid(&[0x0f, 0x3a, 0x09, 0x06]); test_invalid(&[0x0f, 0x3a, 0x0a, 0x06]); test_invalid(&[0x0f, 0x3a, 0x0b, 0x06]); test_invalid(&[0x0f, 0x3a, 0x0e, 0x06]); test_invalid(&[0x0f, 0x3a, 0x14, 0x06]); test_invalid(&[0x0f, 0x3a, 0x15, 0x06]); test_invalid(&[0x0f, 0x3a, 0x16, 0x06]); test_invalid(&[0x0f, 0x3a, 0x17, 0x06]); test_invalid(&[0x0f, 0x3a, 0x20, 0x06]); test_invalid(&[0x0f, 0x3a, 0x21, 0x06]); test_invalid(&[0x0f, 0x3a, 0x22, 0x06]); test_invalid(&[0x0f, 0x3a, 0x40, 0x06]); test_invalid(&[0x0f, 0x3a, 0x41, 0x06]); test_invalid(&[0x0f, 0x3a, 0x42, 0x06]); test_invalid(&[0x0f, 0x50, 0x00]); test_invalid(&[0x0f, 0x6c]); test_invalid(&[0x0f, 0x6d]); test_invalid(&[0x0f, 0x71, 0x00, 0x7f]); test_invalid(&[0x0f, 0x71, 0xc0, 0x7f]); test_invalid(&[0x0f, 0x72, 0x00, 0x7f]); test_invalid(&[0x0f, 0x72, 0xc0, 0x7f]); test_invalid(&[0x0f, 0x73, 0x00, 0x7f]); test_invalid(&[0x0f, 0x73, 0xc0, 0x7f]); test_invalid(&[0x0f, 0x73, 0xe0, 0x7f]); test_invalid(&[0x0f, 0xc3, 0xc3]); test_invalid(&[0x0f, 0xc5, 0x01, 0x00]); test_invalid(&[0x0f, 0xd7, 0x00]); test_invalid(&[0x0f, 0xe7, 0xc3]); test_invalid(&[0x0f, 0xf0, 0xc2]); test_invalid(&[0x0f, 0xf7, 0x01]); test_invalid(&[0x2e, 0x2e, 0xf2, 0x36, 0x0f, 0xb2, 0xdb, 0x42, 0xd6, 0xa3, 0x16]); test_invalid(&[0x66, 0x0f, 0x01, 0xc8]); test_invalid(&[0x66, 0x0f, 0x01, 0xc9]); test_invalid(&[0x66, 0x0f, 0x13, 0xc3]); test_invalid(&[0x66, 0x0f, 0x16, 0xc3]); test_invalid(&[0x66, 0x0f, 0x17, 0xc3]); test_invalid(&[0x66, 0x0f, 0x37]); test_invalid(&[0x66, 0x0f, 0x38, 0x2a, 0xc6]); test_invalid(&[0x66, 0x0f, 0x38, 0xf1, 0xc6]); test_invalid(&[0x66, 0x0f, 0x50, 0x01]); test_invalid(&[0x66, 0x0f, 0x52, 0x01]); test_invalid(&[0x66, 0x0f, 0x53, 0x01]); test_invalid(&[0x66, 0x0f, 0x71, 0x10, 0x8f]); test_invalid(&[0x66, 0x0f, 0x71, 0x20, 0x8f]); test_invalid(&[0x66, 0x0f, 0x71, 0x30, 0x8f]); test_invalid(&[0x66, 0x0f, 0x72, 0x10, 0x8f]); test_invalid(&[0x66, 0x0f, 0x72, 0x20, 0x8f]); test_invalid(&[0x66, 0x0f, 0x72, 0x30, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x10, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x18, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x30, 0x8f]); test_invalid(&[0x66, 0x0f, 0x73, 0x38, 0x8f]); test_invalid(&[0x66, 0x0f, 0x78, 0x03]); test_invalid(&[0x66, 0x0f, 0x78, 0xc9, 0x4e, 0x76]); test_invalid(&[0x66, 0x0f, 0x79, 0x03]); test_invalid(&[0x66, 0x0f, 0x79, 0x0f]); test_invalid(&[0x66, 0x0f, 0xae, 0xff]); test_invalid(&[0x66, 0x0f, 0xc3, 0x03]); test_invalid(&[0x66, 0x0f, 0xc5, 0x08, 0xff]); test_invalid(&[0x66, 0x0f, 0xd7, 0x01]); test_invalid(&[0x66, 0x0f, 0xe7, 0xc1]); test_invalid(&[0x66, 0x0f, 0xf0, 0x01]); test_invalid(&[0x66, 0x0f, 0xf0, 0xc1]); test_invalid(&[0x66, 0x0f, 0xf7, 0x01]); test_invalid(&[0x66, 0x2e, 0x64, 0x66, 0x0f, 0x38, 0xf8, 0xe2]); test_invalid(&[0x66, 0x3e, 0x65, 0x3e, 0x0f, 0x38, 0xf5, 0xf0]); test_invalid(&[0x66, 0xf2, 0x0f, 0x79, 0x0f]); test_invalid(&[0x66, 0xf2, 0x66, 0x0f, 0x16, 0xcf]); test_invalid(&[0x66, 0xf3, 0x0f, 0xae, 0xe6]); test_invalid(&[0x8d, 0xdd]); test_invalid(&[0x8e, 0x08]); test_invalid(&[0x8e, 0x30]); test_invalid(&[0x8e, 0x38]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_001, 0x2f, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_011, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2e, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2f, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_101, 0x2f, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_0111_111, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b11_010_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_000, 0xae, 0b11_011_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0xc5, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_001, 0xd7, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_100, 0xae, 0b00_010_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_100, 0xae, 0b00_011_001]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_101, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b0_1111_101, 0x7e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_000, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_000, 0x51, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x13, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_001, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_010, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_010, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0x11, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x12, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x16, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_100, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x12, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x13, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x16, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_101, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_110, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_110, 0x16, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x10, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x11, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0x12, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_0111_111, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_000, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b00_011_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x71, 0b11_101_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_000_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_100_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_101_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_110_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x72, 0b00_111_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_000_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_100_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0x73, 0b11_101_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xc5, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xe7, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_001, 0xf7, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_011, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_100, 0x50, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x17, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x2b, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x6e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x72, 0b11_011_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0x7e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xc4, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xc5, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xe7, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_101, 0xf7, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00001, 0b1_1111_111, 0xf0, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x17, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x18, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1c, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1d, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x1e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x2a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x2a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x36, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_001, 0x41, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x17, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x19, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x20, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x21, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x22, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x23, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x24, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x25, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x30, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x31, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x32, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x33, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x34, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x35, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0x41, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_0111_101, 0xdb, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x16, 0b00_011_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x5a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8c, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_001, 0x8e, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b0_1111_101, 0x5a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x18, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x1a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_001, 0x1a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x18, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x19, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x1a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0x1a, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_0111_101, 0xdb, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_001, 0x18, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_001, 0x46, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x16, 0b00_011_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x19, 0b11_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x46, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00010, 0b1_1111_101, 0x5a, 0b00_001_010]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x08, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x09, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x14, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x15, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_001, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x08, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x09, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x20, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x21, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x22, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x41, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_0111_101, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x06, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_001, 0x46, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x00, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x01, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x14, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x15, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x17, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x60, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x61, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x62, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b0_1111_101, 0x63, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x16, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x18, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0x4c, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_001, 0xdf, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x18, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x22, 0b00_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0x4c, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_0111_101, 0xdf, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x00, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x01, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_001, 0x02, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x02, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x19, 0b11_001_010, 0x77]); test_invalid(&[0xc4, 0b110_00011, 0b1_1111_101, 0x46, 0b11_001_010, 0x77]); test_invalid(&[0xc5, 0b1_1111_111, 0x2f, 0b11_001_010]); test_invalid(&[0xc5, 0x8c, 0x77]); test_invalid(&[0xd9, 0x08]); test_invalid(&[0xd9, 0x09]); test_invalid(&[0xd9, 0x0a]); test_invalid(&[0xd9, 0x0b]); test_invalid(&[0xd9, 0x0c]); test_invalid(&[0xd9, 0x0d]); test_invalid(&[0xd9, 0x0e]); test_invalid(&[0xd9, 0x0f]); test_invalid(&[0xd9, 0xd1]); test_invalid(&[0xd9, 0xd2]); test_invalid(&[0xd9, 0xd3]); test_invalid(&[0xd9, 0xd4]); test_invalid(&[0xd9, 0xd5]); test_invalid(&[0xd9, 0xd6]); test_invalid(&[0xd9, 0xd7]); test_invalid(&[0xd9, 0xe2]); test_invalid(&[0xd9, 0xe3]); test_invalid(&[0xd9, 0xe6]); test_invalid(&[0xd9, 0xe7]); test_invalid(&[0xd9, 0xef]); test_invalid(&[0xda, 0xe0]); test_invalid(&[0xda, 0xe1]); test_invalid(&[0xda, 0xe2]); test_invalid(&[0xda, 0xe3]); test_invalid(&[0xda, 0xe4]); test_invalid(&[0xda, 0xe5]); test_invalid(&[0xda, 0xe6]); test_invalid(&[0xda, 0xe7]); test_invalid(&[0xda, 0xe8]); test_invalid(&[0xda, 0xea]); test_invalid(&[0xda, 0xeb]); test_invalid(&[0xda, 0xec]); test_invalid(&[0xda, 0xed]); test_invalid(&[0xda, 0xee]); test_invalid(&[0xda, 0xef]); test_invalid(&[0xda, 0xf0]); test_invalid(&[0xda, 0xf1]); test_invalid(&[0xda, 0xf2]); test_invalid(&[0xda, 0xf3]); test_invalid(&[0xda, 0xf4]); test_invalid(&[0xda, 0xf5]); test_invalid(&[0xda, 0xf6]); test_invalid(&[0xda, 0xf7]); test_invalid(&[0xda, 0xf8]); test_invalid(&[0xda, 0xf9]); test_invalid(&[0xda, 0xfa]); test_invalid(&[0xda, 0xfb]); test_invalid(&[0xda, 0xfc]); test_invalid(&[0xda, 0xfd]); test_invalid(&[0xda, 0xfe]); test_invalid(&[0xda, 0xff]); test_invalid(&[0xdb, 0x20]); test_invalid(&[0xdb, 0x21]); test_invalid(&[0xdb, 0x22]); test_invalid(&[0xdb, 0x23]); test_invalid(&[0xdb, 0x24]); test_invalid(&[0xdb, 0x25]); test_invalid(&[0xdb, 0x26]); test_invalid(&[0xdb, 0x27]); test_invalid(&[0xdb, 0x30]); test_invalid(&[0xdb, 0x31]); test_invalid(&[0xdb, 0x32]); test_invalid(&[0xdb, 0x33]); test_invalid(&[0xdb, 0x34]); test_invalid(&[0xdb, 0x35]); test_invalid(&[0xdb, 0x36]); test_invalid(&[0xdb, 0x37]); test_invalid(&[0xdb, 0xe5]); test_invalid(&[0xdb, 0xe6]); test_invalid(&[0xdb, 0xe7]); test_invalid(&[0xdb, 0xf8]); test_invalid(&[0xdb, 0xf9]); test_invalid(&[0xdb, 0xfa]); test_invalid(&[0xdb, 0xfb]); test_invalid(&[0xdb, 0xfc]); test_invalid(&[0xdb, 0xfd]); test_invalid(&[0xdb, 0xfe]); test_invalid(&[0xdb, 0xff]); test_invalid(&[0xdd, 0x28]); test_invalid(&[0xdd, 0x29]); test_invalid(&[0xdd, 0x2a]); test_invalid(&[0xdd, 0x2b]); test_invalid(&[0xdd, 0x2c]); test_invalid(&[0xdd, 0x2d]); test_invalid(&[0xdd, 0x2e]); test_invalid(&[0xdd, 0x2f]); test_invalid(&[0xdd, 0xf0]); test_invalid(&[0xdd, 0xf1]); test_invalid(&[0xdd, 0xf2]); test_invalid(&[0xdd, 0xf3]); test_invalid(&[0xdd, 0xf4]); test_invalid(&[0xdd, 0xf5]); test_invalid(&[0xdd, 0xf6]); test_invalid(&[0xdd, 0xf7]); test_invalid(&[0xdd, 0xf8]); test_invalid(&[0xdd, 0xf9]); test_invalid(&[0xdd, 0xfa]); test_invalid(&[0xdd, 0xfb]); test_invalid(&[0xdd, 0xfc]); test_invalid(&[0xdd, 0xfd]); test_invalid(&[0xdd, 0xfe]); test_invalid(&[0xdd, 0xff]); test_invalid(&[0xde, 0xd8]); test_invalid(&[0xde, 0xda]); test_invalid(&[0xde, 0xdb]); test_invalid(&[0xde, 0xdc]); test_invalid(&[0xde, 0xdd]); test_invalid(&[0xde, 0xde]); test_invalid(&[0xde, 0xdf]); test_invalid(&[0xdf, 0xe1]); test_invalid(&[0xdf, 0xe2]); test_invalid(&[0xdf, 0xe3]); test_invalid(&[0xdf, 0xe4]); test_invalid(&[0xdf, 0xe5]); test_invalid(&[0xdf, 0xe6]); test_invalid(&[0xdf, 0xe7]); test_invalid(&[0xdf, 0xf8]); test_invalid(&[0xdf, 0xf9]); test_invalid(&[0xdf, 0xfa]); test_invalid(&[0xdf, 0xfb]); test_invalid(&[0xdf, 0xfc]); test_invalid(&[0xdf, 0xfd]); test_invalid(&[0xdf, 0xfe]); test_invalid(&[0xdf, 0xff]); test_invalid(&[0xf0, 0x33, 0xc0]); test_invalid(&[0xf0, 0xc7, 0x00, 0x00, 0x00, 0x00]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf2, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf2, 0x0f, 0x01, 0xee]); test_invalid(&[0xf2, 0x0f, 0x01, 0xef]); test_invalid(&[0xf2, 0x0f, 0x16, 0xcf]); test_invalid(&[0xf2, 0x0f, 0x2b, 0xc6]); test_invalid(&[0xf2, 0x0f, 0x37]); test_invalid(&[0xf2, 0x0f, 0x79, 0x0f]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc8]); test_invalid(&[0xf3, 0x0f, 0x01, 0xc9]); test_invalid(&[0xf3, 0x0f, 0x37]); test_invalid(&[0xf3, 0x0f, 0x38, 0xf8, 0xf3]); test_invalid(&[0xf3, 0x0f, 0xae, 0x04, 0x4f]); test_invalid(&[0xf3, 0x0f, 0xae, 0x87]); test_invalid(&[0xf3, 0x0f, 0xba, 0xc6]); test_invalid(&[0xf3, 0x0f, 0xd0, 0x0f]); test_invalid(&[0xf3, 0x0f, 0xd6, 0x03]); test_invalid(&[0xf3, 0x2e, 0x0f, 0x6a, 0x18]); test_invalid(&[0xf3, 0x67, 0x0f, 0x3a, 0xf0, 0xfb, 0xb4]); test_invalid(&[0xf3, 0xf2, 0x0f, 0xae, 0x8f, 0x54, 0x3c, 0x58, 0xb7]); test_invalid(&[0xff, 0xd8]); // vpbroadcastmw2d. similar to `vpmovm2*`, out-of-range `k` are just masked down. test_display(&[0x62, 0xd2, 0x7e, 0x28, 0x3a, 0xca], "vpbroadcastmw2d ymm1, k2"); // vpmovm2b (and larger forms). for some reason the source operand is a mask register but uses // modrm bits as a register selector. out-of-range `k` seem to just get masked down.. test_display(&[0x62, 0xd2, 0x7e, 0x08, 0x28, 0xc2], "vpmovm2b xmm0, k2"); test_display(&[0x62, 0xf2, 0x7e, 0x08, 0x28, 0xc1], "vpmovm2b xmm0, k1"); // vpmovb2m (and larger forms). out-of-range `k` are invalid in 64-bit mode, are part of the // `bound` instruction for 32- and 16-bit modes. test_display(&[0x62, 0x72, 0x7e /* , 0x28, 0x29, 0xfd */], "bound si, dword [bp + si * 1 + 0x7e]"); test_display(&[0x62, 0xf2, 0x7e, 0x28, 0x29, 0xfd], "vpmovb2m k7, ymm5"); } // some test cases are best just lifted from llvm or gcc. #[test] fn from_llvm() { test_display(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01], "hreset 0x1"); let mut reader = yaxpeax_arch::U8Reader::new(&[0xf3, 0x0f, 0x3a, 0xf0, 0xc0, 0x01]); let hreset = InstDecoder::default().decode(&mut reader).expect("can disassemble test instruction"); assert_eq!(hreset.operand_count(), 1); } #[test] fn from_reports() { // negative compressed evex displacements should not overflow and panic test_display(&[0x62, 0xf2, 0x6d, 0xac, 0x00, 0x59, 0xa7], "vpshufb ymm3{k4}{z}, ymm2, ymmword [bx + di * 1 - 0xb20]"); test_display(&[0x62, 0xf2, 0xfd, 0x0f, 0x8a, 0x62, 0xf2], "vcompresspd xmmword [bp + si * 1 - 0x70]{k7}, xmm4"); test_display(&[0xf3, 0x0f, 0x1e, 0x0f], "nop word [bx], cx"); } mod reg_specs { use yaxpeax_x86::real_mode::RegSpec; #[test] fn reg_specs_are_correct() { #[cfg(feature = "fmt")] { let cases: Vec<(RegSpec, &'static str)> = vec![ (RegSpec::d(0), "eax"), (RegSpec::eax(), "eax"), (RegSpec::d(1), "ecx"), (RegSpec::ecx(), "ecx"), (RegSpec::d(2), "edx"), (RegSpec::edx(), "edx"), (RegSpec::d(3), "ebx"), (RegSpec::ebx(), "ebx"), (RegSpec::d(4), "esp"), (RegSpec::esp(), "esp"), (RegSpec::d(5), "ebp"), (RegSpec::ebp(), "ebp"), (RegSpec::d(6), "esi"), (RegSpec::esi(), "esi"), (RegSpec::d(7), "edi"), (RegSpec::edi(), "edi"), (RegSpec::w(0), "ax"), (RegSpec::ax(), "ax"), (RegSpec::w(1), "cx"), (RegSpec::cx(), "cx"), (RegSpec::w(2), "dx"), (RegSpec::dx(), "dx"), (RegSpec::w(3), "bx"), (RegSpec::bx(), "bx"), (RegSpec::w(4), "sp"), (RegSpec::sp(), "sp"), (RegSpec::w(5), "bp"), (RegSpec::bp(), "bp"), (RegSpec::w(6), "si"), (RegSpec::si(), "si"), (RegSpec::w(7), "di"), (RegSpec::di(), "di"), (RegSpec::b(0), "al"), (RegSpec::al(), "al"), (RegSpec::b(1), "cl"), (RegSpec::cl(), "cl"), (RegSpec::b(2), "dl"), (RegSpec::dl(), "dl"), (RegSpec::b(3), "bl"), (RegSpec::bl(), "bl"), (RegSpec::b(4), "ah"), (RegSpec::ah(), "ah"), (RegSpec::b(5), "ch"), (RegSpec::ch(), "ch"), (RegSpec::b(6), "dh"), (RegSpec::dh(), "dh"), (RegSpec::b(7), "bh"), (RegSpec::bh(), "bh"), (RegSpec::eip(), "eip"), (RegSpec::eflags(), "eflags"), (RegSpec::es(), "es"), (RegSpec::cs(), "cs"), (RegSpec::ss(), "ss"), (RegSpec::ds(), "ds"), (RegSpec::fs(), "fs"), (RegSpec::gs(), "gs"), (RegSpec::mask(0), "k0"), (RegSpec::mask(1), "k1"), (RegSpec::mask(2), "k2"), (RegSpec::mask(3), "k3"), (RegSpec::mask(4), "k4"), (RegSpec::mask(5), "k5"), (RegSpec::mask(6), "k6"), (RegSpec::mask(7), "k7"), ]; for (reg, name) in cases.iter() { assert_eq!(reg.name(), *name); } } let cases: Vec<(RegSpec, RegSpec)> = vec![ (RegSpec::d(0), RegSpec::eax()), (RegSpec::d(1), RegSpec::ecx()), (RegSpec::d(2), RegSpec::edx()), (RegSpec::d(3), RegSpec::ebx()), (RegSpec::d(4), RegSpec::esp()), (RegSpec::d(5), RegSpec::ebp()), (RegSpec::d(6), RegSpec::esi()), (RegSpec::d(7), RegSpec::edi()), (RegSpec::w(0), RegSpec::ax()), (RegSpec::w(1), RegSpec::cx()), (RegSpec::w(2), RegSpec::dx()), (RegSpec::w(3), RegSpec::bx()), (RegSpec::w(4), RegSpec::sp()), (RegSpec::w(5), RegSpec::bp()), (RegSpec::w(6), RegSpec::si()), (RegSpec::w(7), RegSpec::di()), (RegSpec::b(0), RegSpec::al()), (RegSpec::b(1), RegSpec::cl()), (RegSpec::b(2), RegSpec::dl()), (RegSpec::b(3), RegSpec::bl()), (RegSpec::b(4), RegSpec::ah()), (RegSpec::b(5), RegSpec::ch()), (RegSpec::b(6), RegSpec::dh()), (RegSpec::b(7), RegSpec::bh()), ]; for (reg1, reg2) in cases.iter() { assert_eq!(reg1, reg2); } } #[test] #[should_panic] fn invalid_mask_reg_panics() { RegSpec::mask(8); } #[test] #[should_panic] fn invalid_dword_reg_panics() { RegSpec::d(8); } #[test] #[should_panic] fn invalid_word_reg_panics() { RegSpec::w(8); } #[test] #[should_panic] fn invalid_byte_reg_panics() { RegSpec::b(8); } #[test] #[should_panic] fn invalid_x87_reg_panics() { RegSpec::st(8); } #[test] #[should_panic] fn invalid_xmm_reg_panics() { RegSpec::xmm(32); } #[test] #[should_panic] fn invalid_ymm_reg_panics() { RegSpec::ymm(32); } #[test] #[should_panic] fn invalid_zmm_reg_panics() { RegSpec::zmm(32); } } yaxpeax-x86-1.2.2/test/real_mode/opcode.rs000064400000000000000000000055621046102023000164650ustar 00000000000000use yaxpeax_x86::real_mode::{ConditionCode, Opcode}; #[test] fn conditional_instructions() { const JCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::JO, ConditionCode::O), (Opcode::JNO, ConditionCode::NO), (Opcode::JB, ConditionCode::B), (Opcode::JNB, ConditionCode::AE), (Opcode::JZ, ConditionCode::Z), (Opcode::JNZ, ConditionCode::NZ), (Opcode::JA, ConditionCode::A), (Opcode::JNA, ConditionCode::BE), (Opcode::JS, ConditionCode::S), (Opcode::JNS, ConditionCode::NS), (Opcode::JP, ConditionCode::P), (Opcode::JNP, ConditionCode::NP), (Opcode::JL, ConditionCode::L), (Opcode::JGE, ConditionCode::GE), (Opcode::JG, ConditionCode::G), (Opcode::JLE, ConditionCode::LE), ]; for (opc, cond) in JCC.iter() { assert!(opc.is_jcc()); assert!(!opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const SETCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::SETO, ConditionCode::O), (Opcode::SETNO, ConditionCode::NO), (Opcode::SETB, ConditionCode::B), (Opcode::SETAE, ConditionCode::AE), (Opcode::SETZ, ConditionCode::Z), (Opcode::SETNZ, ConditionCode::NZ), (Opcode::SETA, ConditionCode::A), (Opcode::SETBE, ConditionCode::BE), (Opcode::SETS, ConditionCode::S), (Opcode::SETNS, ConditionCode::NS), (Opcode::SETP, ConditionCode::P), (Opcode::SETNP, ConditionCode::NP), (Opcode::SETL, ConditionCode::L), (Opcode::SETGE, ConditionCode::GE), (Opcode::SETG, ConditionCode::G), (Opcode::SETLE, ConditionCode::LE), ]; for (opc, cond) in SETCC.iter() { assert!(!opc.is_jcc()); assert!(opc.is_setcc()); assert!(!opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } const CMOVCC: &'static [(Opcode, ConditionCode); 16] = &[ (Opcode::CMOVO, ConditionCode::O), (Opcode::CMOVNO, ConditionCode::NO), (Opcode::CMOVB, ConditionCode::B), (Opcode::CMOVNB, ConditionCode::AE), (Opcode::CMOVZ, ConditionCode::Z), (Opcode::CMOVNZ, ConditionCode::NZ), (Opcode::CMOVA, ConditionCode::A), (Opcode::CMOVNA, ConditionCode::BE), (Opcode::CMOVS, ConditionCode::S), (Opcode::CMOVNS, ConditionCode::NS), (Opcode::CMOVP, ConditionCode::P), (Opcode::CMOVNP, ConditionCode::NP), (Opcode::CMOVL, ConditionCode::L), (Opcode::CMOVGE, ConditionCode::GE), (Opcode::CMOVG, ConditionCode::G), (Opcode::CMOVLE, ConditionCode::LE), ]; for (opc, cond) in CMOVCC.iter() { assert!(!opc.is_jcc()); assert!(!opc.is_setcc()); assert!(opc.is_cmovcc()); assert_eq!(opc.condition(), Some(*cond)); } } yaxpeax-x86-1.2.2/test/real_mode/operand.rs000064400000000000000000000017101046102023000166330ustar 00000000000000use yaxpeax_x86::real_mode::{InstDecoder}; #[test] fn test_implied_memory_width() { fn mem_size_of(data: &[u8]) -> Option { let decoder = InstDecoder::default(); decoder.decode_slice(data).unwrap().mem_size().unwrap().bytes_size() } // test push, pop, call, and ret assert_eq!(mem_size_of(&[0xc3]), Some(2)); assert_eq!(mem_size_of(&[0xe8, 0x11, 0x22, 0x33, 0x44]), Some(2)); assert_eq!(mem_size_of(&[0x50]), Some(2)); assert_eq!(mem_size_of(&[0x58]), Some(2)); assert_eq!(mem_size_of(&[0x66, 0x50]), Some(2)); assert_eq!(mem_size_of(&[0x66, 0x58]), Some(2)); assert_eq!(mem_size_of(&[0xff, 0xf0]), Some(2)); assert_eq!(mem_size_of(&[0x66, 0xff, 0xf0]), Some(4)); // unlike 64-bit mode, operand-size prefixed call and jump do have a different size: they read // four bytes. assert_eq!(mem_size_of(&[0x66, 0xff, 0x10]), Some(4)); assert_eq!(mem_size_of(&[0x66, 0xff, 0x20]), Some(4)); } yaxpeax-x86-1.2.2/test/test.rs000064400000000000000000000001501046102023000142300ustar 00000000000000extern crate yaxpeax_arch; extern crate yaxpeax_x86; mod long_mode; mod protected_mode; mod real_mode;